drivers/gpu/drm/i915/intel_fbc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Frame Buffer Compression (FBC)
  26  *
  27  * FBC tries to save memory bandwidth (and so power consumption) by
  28  * compressing the amount of memory used by the display. It is total
  29  * transparent to user space and completely handled in the kernel.
  30  *
  31  * The benefits of FBC are mostly visible with solid backgrounds and
  32  * variation-less patterns. It comes from keeping the memory footprint small
  33  * and having fewer memory pages opened and accessed for refreshing the display.
  34  *
  35  * i915 is responsible to reserve stolen memory for FBC and configure its
  36  * offset on proper registers. The hardware takes care of all
  37  * compress/decompress. However there are many known cases where we have to
  38  * forcibly disable it to allow proper screen updates.
  39  */
  40
  41 #include "intel_drv.h"
  42 #include "i915_drv.h"
  43
  44 static inline bool fbc_supported(struct drm_i915_private *dev_priv)
  45 {
  46         return HAS_FBC(dev_priv);
  47 }
  48
  49 static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv)
  50 {
  51         return IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8;
  52 }
  53
  54 static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv)
  55 {
  56         return INTEL_INFO(dev_priv)->gen < 4;
  57 }
  58
  59 static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
  60 {
  61         return INTEL_INFO(dev_priv)->gen <= 3;
  62 }
  63
  64 /*
  65  * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
  66  * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
  67  * origin so the x and y offsets can actually fit the registers. As a
  68  * consequence, the fence doesn't really start exactly at the display plane
  69  * address we program because it starts at the real start of the buffer, so we
  70  * have to take this into consideration here.
  71  */
  72 static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc)
  73 {
  74         return crtc->base.y - crtc->adjusted_y;
  75 }
  76
  77 /*
  78  * For SKL+, the plane source size used by the hardware is based on the value we
  79  * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
  80  * we wrote to PIPESRC.
  81  */
  82 static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache *cache,
  83                                             int *width, int *height)
  84 {
  85         int w, h;
  86
  87         if (intel_rotation_90_or_270(cache->plane.rotation)) {
  88                 w = cache->plane.src_h;
  89                 h = cache->plane.src_w;
  90         } else {
  91                 w = cache->plane.src_w;
  92                 h = cache->plane.src_h;
  93         }
  94
  95         if (width)
  96                 *width = w;
  97         if (height)
  98                 *height = h;
  99 }
 100
 101 static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
 102                                         struct intel_fbc_state_cache *cache)
 103 {
 104         int lines;
 105
 106         intel_fbc_get_plane_source_size(cache, NULL, &lines);
 107         if (INTEL_GEN(dev_priv) == 7)
 108                 lines = min(lines, 2048);
 109         else if (INTEL_GEN(dev_priv) >= 8)
 110                 lines = min(lines, 2560);
 111
 112         /* Hardware needs the full buffer stride, not just the active area. */
 113         return lines * cache->fb.stride;
 114 }
 115
 116 static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
 117 {
 118         u32 fbc_ctl;
 119
 120         /* Disable compression */
 121         fbc_ctl = I915_READ(FBC_CONTROL);
 122         if ((fbc_ctl & FBC_CTL_EN) == 0)
 123                 return;
 124
 125         fbc_ctl &= ~FBC_CTL_EN;
 126         I915_WRITE(FBC_CONTROL, fbc_ctl);
 127
 128         /* Wait for compressing bit to clear */
 129         if (intel_wait_for_register(dev_priv,
 130                                     FBC_STATUS, FBC_STAT_COMPRESSING, 0,
 131                                     10)) {
 132                 DRM_DEBUG_KMS("FBC idle timed out\n");
 133                 return;
 134         }
 135 }
 136
 137 static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
 138 {
 139         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 140         int cfb_pitch;
 141         int i;
 142         u32 fbc_ctl;
 143
 144         /* Note: fbc.threshold == 1 for i8xx */
 145         cfb_pitch = params->cfb_size / FBC_LL_SIZE;
 146         if (params->fb.stride < cfb_pitch)
 147                 cfb_pitch = params->fb.stride;
 148
 149         /* FBC_CTL wants 32B or 64B units */
 150         if (IS_GEN2(dev_priv))
 151                 cfb_pitch = (cfb_pitch / 32) - 1;
 152         else
 153                 cfb_pitch = (cfb_pitch / 64) - 1;
 154
 155         /* Clear old tags */
 156         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 157                 I915_WRITE(FBC_TAG(i), 0);
 158
 159         if (IS_GEN4(dev_priv)) {
 160                 u32 fbc_ctl2;
 161
 162                 /* Set it up... */
 163                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 164                 fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.plane);
 165                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 166                 I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset);
 167         }
 168
 169         /* enable it... */
 170         fbc_ctl = I915_READ(FBC_CONTROL);
 171         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 172         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 173         if (IS_I945GM(dev_priv))
 174                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 175         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 176         fbc_ctl |= params->fb.fence_reg;
 177         I915_WRITE(FBC_CONTROL, fbc_ctl);
 178 }
 179
 180 static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
 181 {
 182         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 183 }
 184
 185 static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
 186 {
 187         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 188         u32 dpfc_ctl;
 189
 190         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane) | DPFC_SR_EN;
 191         if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2)
 192                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 193         else
 194                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 195
 196         if (params->fb.fence_reg != I915_FENCE_REG_NONE) {
 197                 dpfc_ctl |= DPFC_CTL_FENCE_EN | params->fb.fence_reg;
 198                 I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
 199         } else {
 200                 I915_WRITE(DPFC_FENCE_YOFF, 0);
 201         }
 202
 203         /* enable it... */
 204         I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 205 }
 206
 207 static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv)
 208 {
 209         u32 dpfc_ctl;
 210
 211         /* Disable compression */
 212         dpfc_ctl = I915_READ(DPFC_CONTROL);
 213         if (dpfc_ctl & DPFC_CTL_EN) {
 214                 dpfc_ctl &= ~DPFC_CTL_EN;
 215                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 216         }
 217 }
 218
 219 static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
 220 {
 221         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 222 }
 223
 224 /* This function forces a CFB recompression through the nuke operation. */
 225 static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
 226 {
 227         I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE);
 228         POSTING_READ(MSG_FBC_REND_STATE);
 229 }
 230
 231 static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
 232 {
 233         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 234         u32 dpfc_ctl;
 235         int threshold = dev_priv->fbc.threshold;
 236
 237         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane);
 238         if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2)
 239                 threshold++;
 240
 241         switch (threshold) {
 242         case 4:
 243         case 3:
 244                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 245                 break;
 246         case 2:
 247                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 248                 break;
 249         case 1:
 250                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 251                 break;
 252         }
 253
 254         if (params->fb.fence_reg != I915_FENCE_REG_NONE) {
 255                 dpfc_ctl |= DPFC_CTL_FENCE_EN;
 256                 if (IS_GEN5(dev_priv))
 257                         dpfc_ctl |= params->fb.fence_reg;
 258                 if (IS_GEN6(dev_priv)) {
 259                         I915_WRITE(SNB_DPFC_CTL_SA,
 260                                    SNB_CPU_FENCE_ENABLE | params->fb.fence_reg);
 261                         I915_WRITE(DPFC_CPU_FENCE_OFFSET,
 262                                    params->crtc.fence_y_offset);
 263                 }
 264         } else {
 265                 if (IS_GEN6(dev_priv)) {
 266                         I915_WRITE(SNB_DPFC_CTL_SA, 0);
 267                         I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
 268                 }
 269         }
 270
 271         I915_WRITE(ILK_DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
 272         I915_WRITE(ILK_FBC_RT_BASE, params->fb.ggtt_offset | ILK_FBC_RT_VALID);
 273         /* enable it... */
 274         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 275
 276         intel_fbc_recompress(dev_priv);
 277 }
 278
 279 static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
 280 {
 281         u32 dpfc_ctl;
 282
 283         /* Disable compression */
 284         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 285         if (dpfc_ctl & DPFC_CTL_EN) {
 286                 dpfc_ctl &= ~DPFC_CTL_EN;
 287                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 288         }
 289 }
 290
 291 static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
 292 {
 293         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 294 }
 295
 296 static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 297 {
 298         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 299         u32 dpfc_ctl;
 300         int threshold = dev_priv->fbc.threshold;
 301
 302         dpfc_ctl = 0;
 303         if (IS_IVYBRIDGE(dev_priv))
 304                 dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
 305
 306         if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2)
 307                 threshold++;
 308
 309         switch (threshold) {
 310         case 4:
 311         case 3:
 312                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 313                 break;
 314         case 2:
 315                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 316                 break;
 317         case 1:
 318                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 319                 break;
 320         }
 321
 322         if (params->fb.fence_reg != I915_FENCE_REG_NONE) {
 323                 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 324                 I915_WRITE(SNB_DPFC_CTL_SA,
 325                            SNB_CPU_FENCE_ENABLE | params->fb.fence_reg);
 326                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset);
 327         } else {
 328                 I915_WRITE(SNB_DPFC_CTL_SA,0);
 329                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
 330         }
 331
 332         if (dev_priv->fbc.false_color)
 333                 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
 334
 335         if (IS_IVYBRIDGE(dev_priv)) {
 336                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 337                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
 338                            I915_READ(ILK_DISPLAY_CHICKEN1) |
 339                            ILK_FBCQ_DIS);
 340         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 341                 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
 342                 I915_WRITE(CHICKEN_PIPESL_1(params->crtc.pipe),
 343                            I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) |
 344                            HSW_FBCQ_DIS);
 345         }
 346
 347         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 348
 349         intel_fbc_recompress(dev_priv);
 350 }
 351
 352 static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
 353 {
 354         if (INTEL_INFO(dev_priv)->gen >= 5)
 355                 return ilk_fbc_is_active(dev_priv);
 356         else if (IS_GM45(dev_priv))
 357                 return g4x_fbc_is_active(dev_priv);
 358         else
 359                 return i8xx_fbc_is_active(dev_priv);
 360 }
 361
 362 static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
 363 {
 364         struct intel_fbc *fbc = &dev_priv->fbc;
 365
 366         fbc->active = true;
 367
 368         if (INTEL_INFO(dev_priv)->gen >= 7)
 369                 gen7_fbc_activate(dev_priv);
 370         else if (INTEL_INFO(dev_priv)->gen >= 5)
 371                 ilk_fbc_activate(dev_priv);
 372         else if (IS_GM45(dev_priv))
 373                 g4x_fbc_activate(dev_priv);
 374         else
 375                 i8xx_fbc_activate(dev_priv);
 376 }
 377
 378 static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
 379 {
 380         struct intel_fbc *fbc = &dev_priv->fbc;
 381
 382         fbc->active = false;
 383
 384         if (INTEL_INFO(dev_priv)->gen >= 5)
 385                 ilk_fbc_deactivate(dev_priv);
 386         else if (IS_GM45(dev_priv))
 387                 g4x_fbc_deactivate(dev_priv);
 388         else
 389                 i8xx_fbc_deactivate(dev_priv);
 390 }
 391
 392 /**
 393  * intel_fbc_is_active - Is FBC active?
 394  * @dev_priv: i915 device instance
 395  *
 396  * This function is used to verify the current state of FBC.
 397  *
 398  * FIXME: This should be tracked in the plane config eventually
 399  * instead of queried at runtime for most callers.
 400  */
 401 bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
 402 {
 403         return dev_priv->fbc.active;
 404 }
 405
 406 static void intel_fbc_work_fn(struct work_struct *__work)
 407 {
 408         struct drm_i915_private *dev_priv =
 409                 container_of(__work, struct drm_i915_private, fbc.work.work);
 410         struct intel_fbc *fbc = &dev_priv->fbc;
 411         struct intel_fbc_work *work = &fbc->work;
 412         struct intel_crtc *crtc = fbc->crtc;
 413         struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[crtc->pipe];
 414
 415         if (drm_crtc_vblank_get(&crtc->base)) {
 416                 DRM_ERROR("vblank not available for FBC on pipe %c\n",
 417                           pipe_name(crtc->pipe));
 418
 419                 mutex_lock(&fbc->lock);
 420                 work->scheduled = false;
 421                 mutex_unlock(&fbc->lock);
 422                 return;
 423         }
 424
 425 retry:
 426         /* Delay the actual enabling to let pageflipping cease and the
 427          * display to settle before starting the compression. Note that
 428          * this delay also serves a second purpose: it allows for a
 429          * vblank to pass after disabling the FBC before we attempt
 430          * to modify the control registers.
 431          *
 432          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 433          *
 434          * It is also worth mentioning that since work->scheduled_vblank can be
 435          * updated multiple times by the other threads, hitting the timeout is
 436          * not an error condition. We'll just end up hitting the "goto retry"
 437          * case below.
 438          */
 439         wait_event_timeout(vblank->queue,
 440                 drm_crtc_vblank_count(&crtc->base) != work->scheduled_vblank,
 441                 msecs_to_jiffies(50));
 442
 443         mutex_lock(&fbc->lock);
 444
 445         /* Were we cancelled? */
 446         if (!work->scheduled)
 447                 goto out;
 448
 449         /* Were we delayed again while this function was sleeping? */
 450         if (drm_crtc_vblank_count(&crtc->base) == work->scheduled_vblank) {
 451                 mutex_unlock(&fbc->lock);
 452                 goto retry;
 453         }
 454
 455         intel_fbc_hw_activate(dev_priv);
 456
 457         work->scheduled = false;
 458
 459 out:
 460         mutex_unlock(&fbc->lock);
 461         drm_crtc_vblank_put(&crtc->base);
 462 }
 463
 464 static void intel_fbc_schedule_activation(struct intel_crtc *crtc)
 465 {
 466         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 467         struct intel_fbc *fbc = &dev_priv->fbc;
 468         struct intel_fbc_work *work = &fbc->work;
 469
 470         WARN_ON(!mutex_is_locked(&fbc->lock));
 471
 472         if (drm_crtc_vblank_get(&crtc->base)) {
 473                 DRM_ERROR("vblank not available for FBC on pipe %c\n",
 474                           pipe_name(crtc->pipe));
 475                 return;
 476         }
 477
 478         /* It is useless to call intel_fbc_cancel_work() or cancel_work() in
 479          * this function since we're not releasing fbc.lock, so it won't have an
 480          * opportunity to grab it to discover that it was cancelled. So we just
 481          * update the expected jiffy count. */
 482         work->scheduled = true;
 483         work->scheduled_vblank = drm_crtc_vblank_count(&crtc->base);
 484         drm_crtc_vblank_put(&crtc->base);
 485
 486         schedule_work(&work->work);
 487 }
 488
 489 static void intel_fbc_deactivate(struct drm_i915_private *dev_priv)
 490 {
 491         struct intel_fbc *fbc = &dev_priv->fbc;
 492
 493         WARN_ON(!mutex_is_locked(&fbc->lock));
 494
 495         /* Calling cancel_work() here won't help due to the fact that the work
 496          * function grabs fbc->lock. Just set scheduled to false so the work
 497          * function can know it was cancelled. */
 498         fbc->work.scheduled = false;
 499
 500         if (fbc->active)
 501                 intel_fbc_hw_deactivate(dev_priv);
 502 }
 503
 504 static bool multiple_pipes_ok(struct intel_crtc *crtc,
 505                               struct intel_plane_state *plane_state)
 506 {
 507         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 508         struct intel_fbc *fbc = &dev_priv->fbc;
 509         enum pipe pipe = crtc->pipe;
 510
 511         /* Don't even bother tracking anything we don't need. */
 512         if (!no_fbc_on_multiple_pipes(dev_priv))
 513                 return true;
 514
 515         if (plane_state->base.visible)
 516                 fbc->visible_pipes_mask |= (1 << pipe);
 517         else
 518                 fbc->visible_pipes_mask &= ~(1 << pipe);
 519
 520         return (fbc->visible_pipes_mask & ~(1 << pipe)) != 0;
 521 }
 522
 523 static int find_compression_threshold(struct drm_i915_private *dev_priv,
 524                                       struct drm_mm_node *node,
 525                                       int size,
 526                                       int fb_cpp)
 527 {
 528         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 529         int compression_threshold = 1;
 530         int ret;
 531         u64 end;
 532
 533         /* The FBC hardware for BDW/SKL doesn't have access to the stolen
 534          * reserved range size, so it always assumes the maximum (8mb) is used.
 535          * If we enable FBC using a CFB on that memory range we'll get FIFO
 536          * underruns, even if that range is not reserved by the BIOS. */
 537         if (IS_BROADWELL(dev_priv) ||
 538             IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 539                 end = ggtt->stolen_size - 8 * 1024 * 1024;
 540         else
 541                 end = ggtt->stolen_usable_size;
 542
 543         /* HACK: This code depends on what we will do in *_enable_fbc. If that
 544          * code changes, this code needs to change as well.
 545          *
 546          * The enable_fbc code will attempt to use one of our 2 compression
 547          * thresholds, therefore, in that case, we only have 1 resort.
 548          */
 549
 550         /* Try to over-allocate to reduce reallocations and fragmentation. */
 551         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
 552                                                    4096, 0, end);
 553         if (ret == 0)
 554                 return compression_threshold;
 555
 556 again:
 557         /* HW's ability to limit the CFB is 1:4 */
 558         if (compression_threshold > 4 ||
 559             (fb_cpp == 2 && compression_threshold == 2))
 560                 return 0;
 561
 562         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
 563                                                    4096, 0, end);
 564         if (ret && INTEL_INFO(dev_priv)->gen <= 4) {
 565                 return 0;
 566         } else if (ret) {
 567                 compression_threshold <<= 1;
 568                 goto again;
 569         } else {
 570                 return compression_threshold;
 571         }
 572 }
 573
 574 static int intel_fbc_alloc_cfb(struct intel_crtc *crtc)
 575 {
 576         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 577         struct intel_fbc *fbc = &dev_priv->fbc;
 578         struct drm_mm_node *uninitialized_var(compressed_llb);
 579         int size, fb_cpp, ret;
 580
 581         WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb));
 582
 583         size = intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache);
 584         fb_cpp = drm_format_plane_cpp(fbc->state_cache.fb.pixel_format, 0);
 585
 586         ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
 587                                          size, fb_cpp);
 588         if (!ret)
 589                 goto err_llb;
 590         else if (ret > 1) {
 591                 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
 592
 593         }
 594
 595         fbc->threshold = ret;
 596
 597         if (INTEL_INFO(dev_priv)->gen >= 5)
 598                 I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
 599         else if (IS_GM45(dev_priv)) {
 600                 I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start);
 601         } else {
 602                 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
 603                 if (!compressed_llb)
 604                         goto err_fb;
 605
 606                 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
 607                                                   4096, 4096);
 608                 if (ret)
 609                         goto err_fb;
 610
 611                 fbc->compressed_llb = compressed_llb;
 612
 613                 I915_WRITE(FBC_CFB_BASE,
 614                            dev_priv->mm.stolen_base + fbc->compressed_fb.start);
 615                 I915_WRITE(FBC_LL_BASE,
 616                            dev_priv->mm.stolen_base + compressed_llb->start);
 617         }
 618
 619         DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
 620                       fbc->compressed_fb.size, fbc->threshold);
 621
 622         return 0;
 623
 624 err_fb:
 625         kfree(compressed_llb);
 626         i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 627 err_llb:
 628         pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
 629         return -ENOSPC;
 630 }
 631
 632 static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 633 {
 634         struct intel_fbc *fbc = &dev_priv->fbc;
 635
 636         if (drm_mm_node_allocated(&fbc->compressed_fb))
 637                 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 638
 639         if (fbc->compressed_llb) {
 640                 i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
 641                 kfree(fbc->compressed_llb);
 642         }
 643 }
 644
 645 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 646 {
 647         struct intel_fbc *fbc = &dev_priv->fbc;
 648
 649         if (!fbc_supported(dev_priv))
 650                 return;
 651
 652         mutex_lock(&fbc->lock);
 653         __intel_fbc_cleanup_cfb(dev_priv);
 654         mutex_unlock(&fbc->lock);
 655 }
 656
 657 static bool stride_is_valid(struct drm_i915_private *dev_priv,
 658                             unsigned int stride)
 659 {
 660         /* These should have been caught earlier. */
 661         WARN_ON(stride < 512);
 662         WARN_ON((stride & (64 - 1)) != 0);
 663
 664         /* Below are the additional FBC restrictions. */
 665
 666         if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
 667                 return stride == 4096 || stride == 8192;
 668
 669         if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048)
 670                 return false;
 671
 672         if (stride > 16384)
 673                 return false;
 674
 675         return true;
 676 }
 677
 678 static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
 679                                   uint32_t pixel_format)
 680 {
 681         switch (pixel_format) {
 682         case DRM_FORMAT_XRGB8888:
 683         case DRM_FORMAT_XBGR8888:
 684                 return true;
 685         case DRM_FORMAT_XRGB1555:
 686         case DRM_FORMAT_RGB565:
 687                 /* 16bpp not supported on gen2 */
 688                 if (IS_GEN2(dev_priv))
 689                         return false;
 690                 /* WaFbcOnly1to1Ratio:ctg */
 691                 if (IS_G4X(dev_priv))
 692                         return false;
 693                 return true;
 694         default:
 695                 return false;
 696         }
 697 }
 698
 699 /*
 700  * For some reason, the hardware tracking starts looking at whatever we
 701  * programmed as the display plane base address register. It does not look at
 702  * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
 703  * variables instead of just looking at the pipe/plane size.
 704  */
 705 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 706 {
 707         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 708         struct intel_fbc *fbc = &dev_priv->fbc;
 709         unsigned int effective_w, effective_h, max_w, max_h;
 710
 711         if (INTEL_INFO(dev_priv)->gen >= 8 || IS_HASWELL(dev_priv)) {
 712                 max_w = 4096;
 713                 max_h = 4096;
 714         } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
 715                 max_w = 4096;
 716                 max_h = 2048;
 717         } else {
 718                 max_w = 2048;
 719                 max_h = 1536;
 720         }
 721
 722         intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
 723                                         &effective_h);
 724         effective_w += crtc->adjusted_x;
 725         effective_h += crtc->adjusted_y;
 726
 727         return effective_w <= max_w && effective_h <= max_h;
 728 }
 729
 730 /* XXX replace me when we have VMA tracking for intel_plane_state */
 731 static int get_fence_id(struct drm_framebuffer *fb)
 732 {
 733         struct i915_vma *vma = i915_gem_object_to_ggtt(intel_fb_obj(fb), NULL);
 734
 735         return vma && vma->fence ? vma->fence->id : I915_FENCE_REG_NONE;
 736 }
 737
 738 static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 739                                          struct intel_crtc_state *crtc_state,
 740                                          struct intel_plane_state *plane_state)
 741 {
 742         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 743         struct intel_fbc *fbc = &dev_priv->fbc;
 744         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 745         struct drm_framebuffer *fb = plane_state->base.fb;
 746         struct drm_i915_gem_object *obj;
 747
 748         cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;
 749         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 750                 cache->crtc.hsw_bdw_pixel_rate =
 751                         ilk_pipe_pixel_rate(crtc_state);
 752
 753         cache->plane.rotation = plane_state->base.rotation;
 754         cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;
 755         cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;
 756         cache->plane.visible = plane_state->base.visible;
 757
 758         if (!cache->plane.visible)
 759                 return;
 760
 761         obj = intel_fb_obj(fb);
 762
 763         /* FIXME: We lack the proper locking here, so only run this on the
 764          * platforms that need. */
 765         if (IS_GEN(dev_priv, 5, 6))
 766                 cache->fb.ilk_ggtt_offset = i915_gem_object_ggtt_offset(obj, NULL);
 767         cache->fb.pixel_format = fb->pixel_format;
 768         cache->fb.stride = fb->pitches[0];
 769         cache->fb.fence_reg = get_fence_id(fb);
 770         cache->fb.tiling_mode = i915_gem_object_get_tiling(obj);
 771 }
 772
 773 static bool intel_fbc_can_activate(struct intel_crtc *crtc)
 774 {
 775         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 776         struct intel_fbc *fbc = &dev_priv->fbc;
 777         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 778
 779         if (!cache->plane.visible) {
 780                 fbc->no_fbc_reason = "primary plane not visible";
 781                 return false;
 782         }
 783
 784         if ((cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) ||
 785             (cache->crtc.mode_flags & DRM_MODE_FLAG_DBLSCAN)) {
 786                 fbc->no_fbc_reason = "incompatible mode";
 787                 return false;
 788         }
 789
 790         if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
 791                 fbc->no_fbc_reason = "mode too large for compression";
 792                 return false;
 793         }
 794
 795         /* The use of a CPU fence is mandatory in order to detect writes
 796          * by the CPU to the scanout and trigger updates to the FBC.
 797          *
 798          * Note that is possible for a tiled surface to be unmappable (and
 799          * so have no fence associated with it) due to aperture constaints
 800          * at the time of pinning.
 801          */
 802         if (cache->fb.tiling_mode != I915_TILING_X ||
 803             cache->fb.fence_reg == I915_FENCE_REG_NONE) {
 804                 fbc->no_fbc_reason = "framebuffer not tiled or fenced";
 805                 return false;
 806         }
 807         if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) &&
 808             cache->plane.rotation != DRM_ROTATE_0) {
 809                 fbc->no_fbc_reason = "rotation unsupported";
 810                 return false;
 811         }
 812
 813         if (!stride_is_valid(dev_priv, cache->fb.stride)) {
 814                 fbc->no_fbc_reason = "framebuffer stride not supported";
 815                 return false;
 816         }
 817
 818         if (!pixel_format_is_valid(dev_priv, cache->fb.pixel_format)) {
 819                 fbc->no_fbc_reason = "pixel format is invalid";
 820                 return false;
 821         }
 822
 823         /* WaFbcExceedCdClockThreshold:hsw,bdw */
 824         if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
 825             cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk_freq * 95 / 100) {
 826                 fbc->no_fbc_reason = "pixel rate is too big";
 827                 return false;
 828         }
 829
 830         /* It is possible for the required CFB size change without a
 831          * crtc->disable + crtc->enable since it is possible to change the
 832          * stride without triggering a full modeset. Since we try to
 833          * over-allocate the CFB, there's a chance we may keep FBC enabled even
 834          * if this happens, but if we exceed the current CFB size we'll have to
 835          * disable FBC. Notice that it would be possible to disable FBC, wait
 836          * for a frame, free the stolen node, then try to reenable FBC in case
 837          * we didn't get any invalidate/deactivate calls, but this would require
 838          * a lot of tracking just for a specific case. If we conclude it's an
 839          * important case, we can implement it later. */
 840         if (intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
 841             fbc->compressed_fb.size * fbc->threshold) {
 842                 fbc->no_fbc_reason = "CFB requirements changed";
 843                 return false;
 844         }
 845
 846         return true;
 847 }
 848
 849 static bool intel_fbc_can_choose(struct intel_crtc *crtc)
 850 {
 851         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 852         struct intel_fbc *fbc = &dev_priv->fbc;
 853
 854         if (intel_vgpu_active(dev_priv)) {
 855                 fbc->no_fbc_reason = "VGPU is active";
 856                 return false;
 857         }
 858
 859         if (!i915.enable_fbc) {
 860                 fbc->no_fbc_reason = "disabled per module param or by default";
 861                 return false;
 862         }
 863
 864         if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A) {
 865                 fbc->no_fbc_reason = "no enabled pipes can have FBC";
 866                 return false;
 867         }
 868
 869         if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A) {
 870                 fbc->no_fbc_reason = "no enabled planes can have FBC";
 871                 return false;
 872         }
 873
 874         return true;
 875 }
 876
 877 static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
 878                                      struct intel_fbc_reg_params *params)
 879 {
 880         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 881         struct intel_fbc *fbc = &dev_priv->fbc;
 882         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 883
 884         /* Since all our fields are integer types, use memset here so the
 885          * comparison function can rely on memcmp because the padding will be
 886          * zero. */
 887         memset(params, 0, sizeof(*params));
 888
 889         params->crtc.pipe = crtc->pipe;
 890         params->crtc.plane = crtc->plane;
 891         params->crtc.fence_y_offset = get_crtc_fence_y_offset(crtc);
 892
 893         params->fb.pixel_format = cache->fb.pixel_format;
 894         params->fb.stride = cache->fb.stride;
 895         params->fb.fence_reg = cache->fb.fence_reg;
 896
 897         params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
 898
 899         params->fb.ggtt_offset = cache->fb.ilk_ggtt_offset;
 900 }
 901
 902 static bool intel_fbc_reg_params_equal(struct intel_fbc_reg_params *params1,
 903                                        struct intel_fbc_reg_params *params2)
 904 {
 905         /* We can use this since intel_fbc_get_reg_params() does a memset. */
 906         return memcmp(params1, params2, sizeof(*params1)) == 0;
 907 }
 908
 909 void intel_fbc_pre_update(struct intel_crtc *crtc,
 910                           struct intel_crtc_state *crtc_state,
 911                           struct intel_plane_state *plane_state)
 912 {
 913         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 914         struct intel_fbc *fbc = &dev_priv->fbc;
 915
 916         if (!fbc_supported(dev_priv))
 917                 return;
 918
 919         mutex_lock(&fbc->lock);
 920
 921         if (!multiple_pipes_ok(crtc, plane_state)) {
 922                 fbc->no_fbc_reason = "more than one pipe active";
 923                 goto deactivate;
 924         }
 925
 926         if (!fbc->enabled || fbc->crtc != crtc)
 927                 goto unlock;
 928
 929         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
 930
 931 deactivate:
 932         intel_fbc_deactivate(dev_priv);
 933 unlock:
 934         mutex_unlock(&fbc->lock);
 935 }
 936
 937 static void __intel_fbc_post_update(struct intel_crtc *crtc)
 938 {
 939         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 940         struct intel_fbc *fbc = &dev_priv->fbc;
 941         struct intel_fbc_reg_params old_params;
 942
 943         WARN_ON(!mutex_is_locked(&fbc->lock));
 944
 945         if (!fbc->enabled || fbc->crtc != crtc)
 946                 return;
 947
 948         if (!intel_fbc_can_activate(crtc)) {
 949                 WARN_ON(fbc->active);
 950                 return;
 951         }
 952
 953         old_params = fbc->params;
 954         intel_fbc_get_reg_params(crtc, &fbc->params);
 955
 956         /* If the scanout has not changed, don't modify the FBC settings.
 957          * Note that we make the fundamental assumption that the fb->obj
 958          * cannot be unpinned (and have its GTT offset and fence revoked)
 959          * without first being decoupled from the scanout and FBC disabled.
 960          */
 961         if (fbc->active &&
 962             intel_fbc_reg_params_equal(&old_params, &fbc->params))
 963                 return;
 964
 965         intel_fbc_deactivate(dev_priv);
 966         intel_fbc_schedule_activation(crtc);
 967         fbc->no_fbc_reason = "FBC enabled (active or scheduled)";
 968 }
 969
 970 void intel_fbc_post_update(struct intel_crtc *crtc)
 971 {
 972         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 973         struct intel_fbc *fbc = &dev_priv->fbc;
 974
 975         if (!fbc_supported(dev_priv))
 976                 return;
 977
 978         mutex_lock(&fbc->lock);
 979         __intel_fbc_post_update(crtc);
 980         mutex_unlock(&fbc->lock);
 981 }
 982
 983 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
 984 {
 985         if (fbc->enabled)
 986                 return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
 987         else
 988                 return fbc->possible_framebuffer_bits;
 989 }
 990
 991 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
 992                           unsigned int frontbuffer_bits,
 993                           enum fb_op_origin origin)
 994 {
 995         struct intel_fbc *fbc = &dev_priv->fbc;
 996
 997         if (!fbc_supported(dev_priv))
 998                 return;
 999
1000         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1001                 return;
1002
1003         mutex_lock(&fbc->lock);
1004
1005         fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
1006
1007         if (fbc->enabled && fbc->busy_bits)
1008                 intel_fbc_deactivate(dev_priv);
1009
1010         mutex_unlock(&fbc->lock);
1011 }
1012
1013 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1014                      unsigned int frontbuffer_bits, enum fb_op_origin origin)
1015 {
1016         struct intel_fbc *fbc = &dev_priv->fbc;
1017
1018         if (!fbc_supported(dev_priv))
1019                 return;
1020
1021         mutex_lock(&fbc->lock);
1022
1023         fbc->busy_bits &= ~frontbuffer_bits;
1024
1025         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1026                 goto out;
1027
1028         if (!fbc->busy_bits && fbc->enabled &&
1029             (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
1030                 if (fbc->active)
1031                         intel_fbc_recompress(dev_priv);
1032                 else
1033                         __intel_fbc_post_update(fbc->crtc);
1034         }
1035
1036 out:
1037         mutex_unlock(&fbc->lock);
1038 }
1039
1040 /**
1041  * intel_fbc_choose_crtc - select a CRTC to enable FBC on
1042  * @dev_priv: i915 device instance
1043  * @state: the atomic state structure
1044  *
1045  * This function looks at the proposed state for CRTCs and planes, then chooses
1046  * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
1047  * true.
1048  *
1049  * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
1050  * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
1051  */
1052 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1053                            struct drm_atomic_state *state)
1054 {
1055         struct intel_fbc *fbc = &dev_priv->fbc;
1056         struct drm_crtc *crtc;
1057         struct drm_crtc_state *crtc_state;
1058         struct drm_plane *plane;
1059         struct drm_plane_state *plane_state;
1060         bool fbc_crtc_present = false;
1061         int i, j;
1062
1063         mutex_lock(&fbc->lock);
1064
1065         for_each_crtc_in_state(state, crtc, crtc_state, i) {
1066                 if (fbc->crtc == to_intel_crtc(crtc)) {
1067                         fbc_crtc_present = true;
1068                         break;
1069                 }
1070         }
1071         /* This atomic commit doesn't involve the CRTC currently tied to FBC. */
1072         if (!fbc_crtc_present && fbc->crtc != NULL)
1073                 goto out;
1074
1075         /* Simply choose the first CRTC that is compatible and has a visible
1076          * plane. We could go for fancier schemes such as checking the plane
1077          * size, but this would just affect the few platforms that don't tie FBC
1078          * to pipe or plane A. */
1079         for_each_plane_in_state(state, plane, plane_state, i) {
1080                 struct intel_plane_state *intel_plane_state =
1081                         to_intel_plane_state(plane_state);
1082
1083                 if (!intel_plane_state->base.visible)
1084                         continue;
1085
1086                 for_each_crtc_in_state(state, crtc, crtc_state, j) {
1087                         struct intel_crtc_state *intel_crtc_state =
1088                                 to_intel_crtc_state(crtc_state);
1089
1090                         if (plane_state->crtc != crtc)
1091                                 continue;
1092
1093                         if (!intel_fbc_can_choose(to_intel_crtc(crtc)))
1094                                 break;
1095
1096                         intel_crtc_state->enable_fbc = true;
1097                         goto out;
1098                 }
1099         }
1100
1101 out:
1102         mutex_unlock(&fbc->lock);
1103 }
1104
1105 /**
1106  * intel_fbc_enable: tries to enable FBC on the CRTC
1107  * @crtc: the CRTC
1108  * @crtc_state: corresponding &drm_crtc_state for @crtc
1109  * @plane_state: corresponding &drm_plane_state for the primary plane of @crtc
1110  *
1111  * This function checks if the given CRTC was chosen for FBC, then enables it if
1112  * possible. Notice that it doesn't activate FBC. It is valid to call
1113  * intel_fbc_enable multiple times for the same pipe without an
1114  * intel_fbc_disable in the middle, as long as it is deactivated.
1115  */
1116 void intel_fbc_enable(struct intel_crtc *crtc,
1117                       struct intel_crtc_state *crtc_state,
1118                       struct intel_plane_state *plane_state)
1119 {
1120         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1121         struct intel_fbc *fbc = &dev_priv->fbc;
1122
1123         if (!fbc_supported(dev_priv))
1124                 return;
1125
1126         mutex_lock(&fbc->lock);
1127
1128         if (fbc->enabled) {
1129                 WARN_ON(fbc->crtc == NULL);
1130                 if (fbc->crtc == crtc) {
1131                         WARN_ON(!crtc_state->enable_fbc);
1132                         WARN_ON(fbc->active);
1133                 }
1134                 goto out;
1135         }
1136
1137         if (!crtc_state->enable_fbc)
1138                 goto out;
1139
1140         WARN_ON(fbc->active);
1141         WARN_ON(fbc->crtc != NULL);
1142
1143         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1144         if (intel_fbc_alloc_cfb(crtc)) {
1145                 fbc->no_fbc_reason = "not enough stolen memory";
1146                 goto out;
1147         }
1148
1149         DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1150         fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1151
1152         fbc->enabled = true;
1153         fbc->crtc = crtc;
1154 out:
1155         mutex_unlock(&fbc->lock);
1156 }
1157
1158 /**
1159  * __intel_fbc_disable - disable FBC
1160  * @dev_priv: i915 device instance
1161  *
1162  * This is the low level function that actually disables FBC. Callers should
1163  * grab the FBC lock.
1164  */
1165 static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
1166 {
1167         struct intel_fbc *fbc = &dev_priv->fbc;
1168         struct intel_crtc *crtc = fbc->crtc;
1169
1170         WARN_ON(!mutex_is_locked(&fbc->lock));
1171         WARN_ON(!fbc->enabled);
1172         WARN_ON(fbc->active);
1173         WARN_ON(crtc->active);
1174
1175         DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1176
1177         __intel_fbc_cleanup_cfb(dev_priv);
1178
1179         fbc->enabled = false;
1180         fbc->crtc = NULL;
1181 }
1182
1183 /**
1184  * intel_fbc_disable - disable FBC if it's associated with crtc
1185  * @crtc: the CRTC
1186  *
1187  * This function disables FBC if it's associated with the provided CRTC.
1188  */
1189 void intel_fbc_disable(struct intel_crtc *crtc)
1190 {
1191         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1192         struct intel_fbc *fbc = &dev_priv->fbc;
1193
1194         if (!fbc_supported(dev_priv))
1195                 return;
1196
1197         mutex_lock(&fbc->lock);
1198         if (fbc->crtc == crtc)
1199                 __intel_fbc_disable(dev_priv);
1200         mutex_unlock(&fbc->lock);
1201
1202         cancel_work_sync(&fbc->work.work);
1203 }
1204
1205 /**
1206  * intel_fbc_global_disable - globally disable FBC
1207  * @dev_priv: i915 device instance
1208  *
1209  * This function disables FBC regardless of which CRTC is associated with it.
1210  */
1211 void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
1212 {
1213         struct intel_fbc *fbc = &dev_priv->fbc;
1214
1215         if (!fbc_supported(dev_priv))
1216                 return;
1217
1218         mutex_lock(&fbc->lock);
1219         if (fbc->enabled)
1220                 __intel_fbc_disable(dev_priv);
1221         mutex_unlock(&fbc->lock);
1222
1223         cancel_work_sync(&fbc->work.work);
1224 }
1225
1226 /**
1227  * intel_fbc_init_pipe_state - initialize FBC's CRTC visibility tracking
1228  * @dev_priv: i915 device instance
1229  *
1230  * The FBC code needs to track CRTC visibility since the older platforms can't
1231  * have FBC enabled while multiple pipes are used. This function does the
1232  * initial setup at driver load to make sure FBC is matching the real hardware.
1233  */
1234 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv)
1235 {
1236         struct intel_crtc *crtc;
1237
1238         /* Don't even bother tracking anything if we don't need. */
1239         if (!no_fbc_on_multiple_pipes(dev_priv))
1240                 return;
1241
1242         for_each_intel_crtc(&dev_priv->drm, crtc)
1243                 if (intel_crtc_active(&crtc->base) &&
1244                     to_intel_plane_state(crtc->base.primary->state)->base.visible)
1245                         dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe);
1246 }
1247
1248 /*
1249  * The DDX driver changes its behavior depending on the value it reads from
1250  * i915.enable_fbc, so sanitize it by translating the default value into either
1251  * 0 or 1 in order to allow it to know what's going on.
1252  *
1253  * Notice that this is done at driver initialization and we still allow user
1254  * space to change the value during runtime without sanitizing it again. IGT
1255  * relies on being able to change i915.enable_fbc at runtime.
1256  */
1257 static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
1258 {
1259         if (i915.enable_fbc >= 0)
1260                 return !!i915.enable_fbc;
1261
1262         if (!HAS_FBC(dev_priv))
1263                 return 0;
1264
1265         if (IS_BROADWELL(dev_priv))
1266                 return 1;
1267
1268         return 0;
1269 }
1270
1271 static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
1272 {
1273 #ifdef CONFIG_INTEL_IOMMU
1274         /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1275         if (intel_iommu_gfx_mapped &&
1276             (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
1277                 DRM_INFO("Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1278                 return true;
1279         }
1280 #endif
1281
1282         return false;
1283 }
1284
1285 /**
1286  * intel_fbc_init - Initialize FBC
1287  * @dev_priv: the i915 device
1288  *
1289  * This function might be called during PM init process.
1290  */
1291 void intel_fbc_init(struct drm_i915_private *dev_priv)
1292 {
1293         struct intel_fbc *fbc = &dev_priv->fbc;
1294         enum pipe pipe;
1295
1296         INIT_WORK(&fbc->work.work, intel_fbc_work_fn);
1297         mutex_init(&fbc->lock);
1298         fbc->enabled = false;
1299         fbc->active = false;
1300         fbc->work.scheduled = false;
1301
1302         if (need_fbc_vtd_wa(dev_priv))
1303                 mkwrite_device_info(dev_priv)->has_fbc = false;
1304
1305         i915.enable_fbc = intel_sanitize_fbc_option(dev_priv);
1306         DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n", i915.enable_fbc);
1307
1308         if (!HAS_FBC(dev_priv)) {
1309                 fbc->no_fbc_reason = "unsupported by this chipset";
1310                 return;
1311         }
1312
1313         for_each_pipe(dev_priv, pipe) {
1314                 fbc->possible_framebuffer_bits |=
1315                                 INTEL_FRONTBUFFER_PRIMARY(pipe);
1316
1317                 if (fbc_on_pipe_a_only(dev_priv))
1318                         break;
1319         }
1320
1321         /* This value was pulled out of someone's hat */
1322         if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_GM45(dev_priv))
1323                 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1324
1325         /* We still don't have any sort of hardware state readout for FBC, so
1326          * deactivate it in case the BIOS activated it to make sure software
1327          * matches the hardware state. */
1328         if (intel_fbc_hw_is_active(dev_priv))
1329                 intel_fbc_hw_deactivate(dev_priv);
1330 }