drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/i915_powerwell.h>
  35 #include <linux/pm_runtime.h>
  36
  37 /**
  38  * RC6 is a special power stage which allows the GPU to enter an very
  39  * low-voltage mode when idle, using down to 0V while at this stage.  This
  40  * stage is entered automatically when the GPU is idle when RC6 support is
  41  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  42  *
  43  * There are different RC6 modes available in Intel GPU, which differentiate
  44  * among each other with the latency required to enter and leave RC6 and
  45  * voltage consumed by the GPU in different states.
  46  *
  47  * The combination of the following flags define which states GPU is allowed
  48  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  49  * RC6pp is deepest RC6. Their support by hardware varies according to the
  50  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  51  * which brings the most power savings; deeper states save more power, but
  52  * require higher latency to switch to and wake up.
  53  */
  54 #define INTEL_RC6_ENABLE                        (1<<0)
  55 #define INTEL_RC6p_ENABLE                       (1<<1)
  56 #define INTEL_RC6pp_ENABLE                      (1<<2)
  57
  58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  59  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  60  * during in-memory transfers and, therefore, reduce the power packet.
  61  *
  62  * The benefits of FBC are mostly visible with solid backgrounds and
  63  * variation-less patterns.
  64  *
  65  * FBC-related functionality can be enabled by the means of the
  66  * i915.i915_enable_fbc parameter
  67  */
  68
  69 static void i8xx_disable_fbc(struct drm_device *dev)
  70 {
  71         struct drm_i915_private *dev_priv = dev->dev_private;
  72         u32 fbc_ctl;
  73
  74         /* Disable compression */
  75         fbc_ctl = I915_READ(FBC_CONTROL);
  76         if ((fbc_ctl & FBC_CTL_EN) == 0)
  77                 return;
  78
  79         fbc_ctl &= ~FBC_CTL_EN;
  80         I915_WRITE(FBC_CONTROL, fbc_ctl);
  81
  82         /* Wait for compressing bit to clear */
  83         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  84                 DRM_DEBUG_KMS("FBC idle timed out\n");
  85                 return;
  86         }
  87
  88         DRM_DEBUG_KMS("disabled FBC\n");
  89 }
  90
  91 static void i8xx_enable_fbc(struct drm_crtc *crtc)
  92 {
  93         struct drm_device *dev = crtc->dev;
  94         struct drm_i915_private *dev_priv = dev->dev_private;
  95         struct drm_framebuffer *fb = crtc->primary->fb;
  96         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  97         struct drm_i915_gem_object *obj = intel_fb->obj;
  98         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  99         int cfb_pitch;
 100         int i;
 101         u32 fbc_ctl;
 102
 103         cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
 104         if (fb->pitches[0] < cfb_pitch)
 105                 cfb_pitch = fb->pitches[0];
 106
 107         /* FBC_CTL wants 32B or 64B units */
 108         if (IS_GEN2(dev))
 109                 cfb_pitch = (cfb_pitch / 32) - 1;
 110         else
 111                 cfb_pitch = (cfb_pitch / 64) - 1;
 112
 113         /* Clear old tags */
 114         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 115                 I915_WRITE(FBC_TAG + (i * 4), 0);
 116
 117         if (IS_GEN4(dev)) {
 118                 u32 fbc_ctl2;
 119
 120                 /* Set it up... */
 121                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 122                 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
 123                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 124                 I915_WRITE(FBC_FENCE_OFF, crtc->y);
 125         }
 126
 127         /* enable it... */
 128         fbc_ctl = I915_READ(FBC_CONTROL);
 129         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 130         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 131         if (IS_I945GM(dev))
 132                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 133         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 134         fbc_ctl |= obj->fence_reg;
 135         I915_WRITE(FBC_CONTROL, fbc_ctl);
 136
 137         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
 138                       cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
 139 }
 140
 141 static bool i8xx_fbc_enabled(struct drm_device *dev)
 142 {
 143         struct drm_i915_private *dev_priv = dev->dev_private;
 144
 145         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 146 }
 147
 148 static void g4x_enable_fbc(struct drm_crtc *crtc)
 149 {
 150         struct drm_device *dev = crtc->dev;
 151         struct drm_i915_private *dev_priv = dev->dev_private;
 152         struct drm_framebuffer *fb = crtc->primary->fb;
 153         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 154         struct drm_i915_gem_object *obj = intel_fb->obj;
 155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 156         u32 dpfc_ctl;
 157
 158         dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
 159         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 160                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 161         else
 162                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 163         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 164
 165         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 166
 167         /* enable it... */
 168         I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 169
 170         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 171 }
 172
 173 static void g4x_disable_fbc(struct drm_device *dev)
 174 {
 175         struct drm_i915_private *dev_priv = dev->dev_private;
 176         u32 dpfc_ctl;
 177
 178         /* Disable compression */
 179         dpfc_ctl = I915_READ(DPFC_CONTROL);
 180         if (dpfc_ctl & DPFC_CTL_EN) {
 181                 dpfc_ctl &= ~DPFC_CTL_EN;
 182                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 183
 184                 DRM_DEBUG_KMS("disabled FBC\n");
 185         }
 186 }
 187
 188 static bool g4x_fbc_enabled(struct drm_device *dev)
 189 {
 190         struct drm_i915_private *dev_priv = dev->dev_private;
 191
 192         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 193 }
 194
 195 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 196 {
 197         struct drm_i915_private *dev_priv = dev->dev_private;
 198         u32 blt_ecoskpd;
 199
 200         /* Make sure blitter notifies FBC of writes */
 201
 202         /* Blitter is part of Media powerwell on VLV. No impact of
 203          * his param in other platforms for now */
 204         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
 205
 206         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 207         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 208                 GEN6_BLITTER_LOCK_SHIFT;
 209         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 210         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 211         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 212         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 213                          GEN6_BLITTER_LOCK_SHIFT);
 214         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 215         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 216
 217         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
 218 }
 219
 220 static void ironlake_enable_fbc(struct drm_crtc *crtc)
 221 {
 222         struct drm_device *dev = crtc->dev;
 223         struct drm_i915_private *dev_priv = dev->dev_private;
 224         struct drm_framebuffer *fb = crtc->primary->fb;
 225         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 226         struct drm_i915_gem_object *obj = intel_fb->obj;
 227         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 228         u32 dpfc_ctl;
 229
 230         dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
 231         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 232                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 233         else
 234                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 235         dpfc_ctl |= DPFC_CTL_FENCE_EN;
 236         if (IS_GEN5(dev))
 237                 dpfc_ctl |= obj->fence_reg;
 238
 239         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 240         I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
 241         /* enable it... */
 242         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 243
 244         if (IS_GEN6(dev)) {
 245                 I915_WRITE(SNB_DPFC_CTL_SA,
 246                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 247                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 248                 sandybridge_blit_fbc_update(dev);
 249         }
 250
 251         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 252 }
 253
 254 static void ironlake_disable_fbc(struct drm_device *dev)
 255 {
 256         struct drm_i915_private *dev_priv = dev->dev_private;
 257         u32 dpfc_ctl;
 258
 259         /* Disable compression */
 260         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 261         if (dpfc_ctl & DPFC_CTL_EN) {
 262                 dpfc_ctl &= ~DPFC_CTL_EN;
 263                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 264
 265                 DRM_DEBUG_KMS("disabled FBC\n");
 266         }
 267 }
 268
 269 static bool ironlake_fbc_enabled(struct drm_device *dev)
 270 {
 271         struct drm_i915_private *dev_priv = dev->dev_private;
 272
 273         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 274 }
 275
 276 static void gen7_enable_fbc(struct drm_crtc *crtc)
 277 {
 278         struct drm_device *dev = crtc->dev;
 279         struct drm_i915_private *dev_priv = dev->dev_private;
 280         struct drm_framebuffer *fb = crtc->primary->fb;
 281         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 282         struct drm_i915_gem_object *obj = intel_fb->obj;
 283         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 284         u32 dpfc_ctl;
 285
 286         dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
 287         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 288                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 289         else
 290                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 291         dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 292
 293         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 294
 295         if (IS_IVYBRIDGE(dev)) {
 296                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 297                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
 298                            I915_READ(ILK_DISPLAY_CHICKEN1) |
 299                            ILK_FBCQ_DIS);
 300         } else {
 301                 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
 302                 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
 303                            I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
 304                            HSW_FBCQ_DIS);
 305         }
 306
 307         I915_WRITE(SNB_DPFC_CTL_SA,
 308                    SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 309         I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 310
 311         sandybridge_blit_fbc_update(dev);
 312
 313         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 314 }
 315
 316 bool intel_fbc_enabled(struct drm_device *dev)
 317 {
 318         struct drm_i915_private *dev_priv = dev->dev_private;
 319
 320         if (!dev_priv->display.fbc_enabled)
 321                 return false;
 322
 323         return dev_priv->display.fbc_enabled(dev);
 324 }
 325
 326 static void intel_fbc_work_fn(struct work_struct *__work)
 327 {
 328         struct intel_fbc_work *work =
 329                 container_of(to_delayed_work(__work),
 330                              struct intel_fbc_work, work);
 331         struct drm_device *dev = work->crtc->dev;
 332         struct drm_i915_private *dev_priv = dev->dev_private;
 333
 334         mutex_lock(&dev->struct_mutex);
 335         if (work == dev_priv->fbc.fbc_work) {
 336                 /* Double check that we haven't switched fb without cancelling
 337                  * the prior work.
 338                  */
 339                 if (work->crtc->primary->fb == work->fb) {
 340                         dev_priv->display.enable_fbc(work->crtc);
 341
 342                         dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
 343                         dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
 344                         dev_priv->fbc.y = work->crtc->y;
 345                 }
 346
 347                 dev_priv->fbc.fbc_work = NULL;
 348         }
 349         mutex_unlock(&dev->struct_mutex);
 350
 351         kfree(work);
 352 }
 353
 354 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 355 {
 356         if (dev_priv->fbc.fbc_work == NULL)
 357                 return;
 358
 359         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 360
 361         /* Synchronisation is provided by struct_mutex and checking of
 362          * dev_priv->fbc.fbc_work, so we can perform the cancellation
 363          * entirely asynchronously.
 364          */
 365         if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
 366                 /* tasklet was killed before being run, clean up */
 367                 kfree(dev_priv->fbc.fbc_work);
 368
 369         /* Mark the work as no longer wanted so that if it does
 370          * wake-up (because the work was already running and waiting
 371          * for our mutex), it will discover that is no longer
 372          * necessary to run.
 373          */
 374         dev_priv->fbc.fbc_work = NULL;
 375 }
 376
 377 static void intel_enable_fbc(struct drm_crtc *crtc)
 378 {
 379         struct intel_fbc_work *work;
 380         struct drm_device *dev = crtc->dev;
 381         struct drm_i915_private *dev_priv = dev->dev_private;
 382
 383         if (!dev_priv->display.enable_fbc)
 384                 return;
 385
 386         intel_cancel_fbc_work(dev_priv);
 387
 388         work = kzalloc(sizeof(*work), GFP_KERNEL);
 389         if (work == NULL) {
 390                 DRM_ERROR("Failed to allocate FBC work structure\n");
 391                 dev_priv->display.enable_fbc(crtc);
 392                 return;
 393         }
 394
 395         work->crtc = crtc;
 396         work->fb = crtc->primary->fb;
 397         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 398
 399         dev_priv->fbc.fbc_work = work;
 400
 401         /* Delay the actual enabling to let pageflipping cease and the
 402          * display to settle before starting the compression. Note that
 403          * this delay also serves a second purpose: it allows for a
 404          * vblank to pass after disabling the FBC before we attempt
 405          * to modify the control registers.
 406          *
 407          * A more complicated solution would involve tracking vblanks
 408          * following the termination of the page-flipping sequence
 409          * and indeed performing the enable as a co-routine and not
 410          * waiting synchronously upon the vblank.
 411          *
 412          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 413          */
 414         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 415 }
 416
 417 void intel_disable_fbc(struct drm_device *dev)
 418 {
 419         struct drm_i915_private *dev_priv = dev->dev_private;
 420
 421         intel_cancel_fbc_work(dev_priv);
 422
 423         if (!dev_priv->display.disable_fbc)
 424                 return;
 425
 426         dev_priv->display.disable_fbc(dev);
 427         dev_priv->fbc.plane = -1;
 428 }
 429
 430 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
 431                               enum no_fbc_reason reason)
 432 {
 433         if (dev_priv->fbc.no_fbc_reason == reason)
 434                 return false;
 435
 436         dev_priv->fbc.no_fbc_reason = reason;
 437         return true;
 438 }
 439
 440 /**
 441  * intel_update_fbc - enable/disable FBC as needed
 442  * @dev: the drm_device
 443  *
 444  * Set up the framebuffer compression hardware at mode set time.  We
 445  * enable it if possible:
 446  *   - plane A only (on pre-965)
 447  *   - no pixel mulitply/line duplication
 448  *   - no alpha buffer discard
 449  *   - no dual wide
 450  *   - framebuffer <= max_hdisplay in width, max_vdisplay in height
 451  *
 452  * We can't assume that any compression will take place (worst case),
 453  * so the compressed buffer has to be the same size as the uncompressed
 454  * one.  It also must reside (along with the line length buffer) in
 455  * stolen memory.
 456  *
 457  * We need to enable/disable FBC on a global basis.
 458  */
 459 void intel_update_fbc(struct drm_device *dev)
 460 {
 461         struct drm_i915_private *dev_priv = dev->dev_private;
 462         struct drm_crtc *crtc = NULL, *tmp_crtc;
 463         struct intel_crtc *intel_crtc;
 464         struct drm_framebuffer *fb;
 465         struct intel_framebuffer *intel_fb;
 466         struct drm_i915_gem_object *obj;
 467         const struct drm_display_mode *adjusted_mode;
 468         unsigned int max_width, max_height;
 469
 470         if (!HAS_FBC(dev)) {
 471                 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
 472                 return;
 473         }
 474
 475         if (!i915.powersave) {
 476                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 477                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 478                 return;
 479         }
 480
 481         /*
 482          * If FBC is already on, we just have to verify that we can
 483          * keep it that way...
 484          * Need to disable if:
 485          *   - more than one pipe is active
 486          *   - changing FBC params (stride, fence, mode)
 487          *   - new fb is too large to fit in compressed buffer
 488          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 489          */
 490         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
 491                 if (intel_crtc_active(tmp_crtc) &&
 492                     to_intel_crtc(tmp_crtc)->primary_enabled) {
 493                         if (crtc) {
 494                                 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
 495                                         DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 496                                 goto out_disable;
 497                         }
 498                         crtc = tmp_crtc;
 499                 }
 500         }
 501
 502         if (!crtc || crtc->primary->fb == NULL) {
 503                 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
 504                         DRM_DEBUG_KMS("no output, disabling\n");
 505                 goto out_disable;
 506         }
 507
 508         intel_crtc = to_intel_crtc(crtc);
 509         fb = crtc->primary->fb;
 510         intel_fb = to_intel_framebuffer(fb);
 511         obj = intel_fb->obj;
 512         adjusted_mode = &intel_crtc->config.adjusted_mode;
 513
 514         if (i915.enable_fbc < 0 &&
 515             INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
 516                 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
 517                         DRM_DEBUG_KMS("disabled per chip default\n");
 518                 goto out_disable;
 519         }
 520         if (!i915.enable_fbc) {
 521                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 522                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 523                 goto out_disable;
 524         }
 525         if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
 526             (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
 527                 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
 528                         DRM_DEBUG_KMS("mode incompatible with compression, "
 529                                       "disabling\n");
 530                 goto out_disable;
 531         }
 532
 533         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 534                 max_width = 4096;
 535                 max_height = 2048;
 536         } else {
 537                 max_width = 2048;
 538                 max_height = 1536;
 539         }
 540         if (intel_crtc->config.pipe_src_w > max_width ||
 541             intel_crtc->config.pipe_src_h > max_height) {
 542                 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
 543                         DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 544                 goto out_disable;
 545         }
 546         if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
 547             intel_crtc->plane != PLANE_A) {
 548                 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
 549                         DRM_DEBUG_KMS("plane not A, disabling compression\n");
 550                 goto out_disable;
 551         }
 552
 553         /* The use of a CPU fence is mandatory in order to detect writes
 554          * by the CPU to the scanout and trigger updates to the FBC.
 555          */
 556         if (obj->tiling_mode != I915_TILING_X ||
 557             obj->fence_reg == I915_FENCE_REG_NONE) {
 558                 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
 559                         DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 560                 goto out_disable;
 561         }
 562
 563         /* If the kernel debugger is active, always disable compression */
 564         if (in_dbg_master())
 565                 goto out_disable;
 566
 567         if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
 568                 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
 569                         DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
 570                 goto out_disable;
 571         }
 572
 573         /* If the scanout has not changed, don't modify the FBC settings.
 574          * Note that we make the fundamental assumption that the fb->obj
 575          * cannot be unpinned (and have its GTT offset and fence revoked)
 576          * without first being decoupled from the scanout and FBC disabled.
 577          */
 578         if (dev_priv->fbc.plane == intel_crtc->plane &&
 579             dev_priv->fbc.fb_id == fb->base.id &&
 580             dev_priv->fbc.y == crtc->y)
 581                 return;
 582
 583         if (intel_fbc_enabled(dev)) {
 584                 /* We update FBC along two paths, after changing fb/crtc
 585                  * configuration (modeswitching) and after page-flipping
 586                  * finishes. For the latter, we know that not only did
 587                  * we disable the FBC at the start of the page-flip
 588                  * sequence, but also more than one vblank has passed.
 589                  *
 590                  * For the former case of modeswitching, it is possible
 591                  * to switch between two FBC valid configurations
 592                  * instantaneously so we do need to disable the FBC
 593                  * before we can modify its control registers. We also
 594                  * have to wait for the next vblank for that to take
 595                  * effect. However, since we delay enabling FBC we can
 596                  * assume that a vblank has passed since disabling and
 597                  * that we can safely alter the registers in the deferred
 598                  * callback.
 599                  *
 600                  * In the scenario that we go from a valid to invalid
 601                  * and then back to valid FBC configuration we have
 602                  * no strict enforcement that a vblank occurred since
 603                  * disabling the FBC. However, along all current pipe
 604                  * disabling paths we do need to wait for a vblank at
 605                  * some point. And we wait before enabling FBC anyway.
 606                  */
 607                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 608                 intel_disable_fbc(dev);
 609         }
 610
 611         intel_enable_fbc(crtc);
 612         dev_priv->fbc.no_fbc_reason = FBC_OK;
 613         return;
 614
 615 out_disable:
 616         /* Multiple disables should be harmless */
 617         if (intel_fbc_enabled(dev)) {
 618                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 619                 intel_disable_fbc(dev);
 620         }
 621         i915_gem_stolen_cleanup_compression(dev);
 622 }
 623
 624 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 625 {
 626         struct drm_i915_private *dev_priv = dev->dev_private;
 627         u32 tmp;
 628
 629         tmp = I915_READ(CLKCFG);
 630
 631         switch (tmp & CLKCFG_FSB_MASK) {
 632         case CLKCFG_FSB_533:
 633                 dev_priv->fsb_freq = 533; /* 133*4 */
 634                 break;
 635         case CLKCFG_FSB_800:
 636                 dev_priv->fsb_freq = 800; /* 200*4 */
 637                 break;
 638         case CLKCFG_FSB_667:
 639                 dev_priv->fsb_freq =  667; /* 167*4 */
 640                 break;
 641         case CLKCFG_FSB_400:
 642                 dev_priv->fsb_freq = 400; /* 100*4 */
 643                 break;
 644         }
 645
 646         switch (tmp & CLKCFG_MEM_MASK) {
 647         case CLKCFG_MEM_533:
 648                 dev_priv->mem_freq = 533;
 649                 break;
 650         case CLKCFG_MEM_667:
 651                 dev_priv->mem_freq = 667;
 652                 break;
 653         case CLKCFG_MEM_800:
 654                 dev_priv->mem_freq = 800;
 655                 break;
 656         }
 657
 658         /* detect pineview DDR3 setting */
 659         tmp = I915_READ(CSHRDDR3CTL);
 660         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 661 }
 662
 663 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 664 {
 665         struct drm_i915_private *dev_priv = dev->dev_private;
 666         u16 ddrpll, csipll;
 667
 668         ddrpll = I915_READ16(DDRMPLL1);
 669         csipll = I915_READ16(CSIPLL0);
 670
 671         switch (ddrpll & 0xff) {
 672         case 0xc:
 673                 dev_priv->mem_freq = 800;
 674                 break;
 675         case 0x10:
 676                 dev_priv->mem_freq = 1066;
 677                 break;
 678         case 0x14:
 679                 dev_priv->mem_freq = 1333;
 680                 break;
 681         case 0x18:
 682                 dev_priv->mem_freq = 1600;
 683                 break;
 684         default:
 685                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 686                                  ddrpll & 0xff);
 687                 dev_priv->mem_freq = 0;
 688                 break;
 689         }
 690
 691         dev_priv->ips.r_t = dev_priv->mem_freq;
 692
 693         switch (csipll & 0x3ff) {
 694         case 0x00c:
 695                 dev_priv->fsb_freq = 3200;
 696                 break;
 697         case 0x00e:
 698                 dev_priv->fsb_freq = 3733;
 699                 break;
 700         case 0x010:
 701                 dev_priv->fsb_freq = 4266;
 702                 break;
 703         case 0x012:
 704                 dev_priv->fsb_freq = 4800;
 705                 break;
 706         case 0x014:
 707                 dev_priv->fsb_freq = 5333;
 708                 break;
 709         case 0x016:
 710                 dev_priv->fsb_freq = 5866;
 711                 break;
 712         case 0x018:
 713                 dev_priv->fsb_freq = 6400;
 714                 break;
 715         default:
 716                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 717                                  csipll & 0x3ff);
 718                 dev_priv->fsb_freq = 0;
 719                 break;
 720         }
 721
 722         if (dev_priv->fsb_freq == 3200) {
 723                 dev_priv->ips.c_m = 0;
 724         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 725                 dev_priv->ips.c_m = 1;
 726         } else {
 727                 dev_priv->ips.c_m = 2;
 728         }
 729 }
 730
 731 static const struct cxsr_latency cxsr_latency_table[] = {
 732         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 733         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 734         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 735         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 736         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 737
 738         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 739         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 740         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 741         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 742         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 743
 744         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 745         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 746         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 747         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 748         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 749
 750         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 751         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 752         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 753         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 754         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 755
 756         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 757         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 758         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 759         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 760         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 761
 762         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 763         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 764         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 765         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 766         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 767 };
 768
 769 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 770                                                          int is_ddr3,
 771                                                          int fsb,
 772                                                          int mem)
 773 {
 774         const struct cxsr_latency *latency;
 775         int i;
 776
 777         if (fsb == 0 || mem == 0)
 778                 return NULL;
 779
 780         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 781                 latency = &cxsr_latency_table[i];
 782                 if (is_desktop == latency->is_desktop &&
 783                     is_ddr3 == latency->is_ddr3 &&
 784                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 785                         return latency;
 786         }
 787
 788         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 789
 790         return NULL;
 791 }
 792
 793 static void pineview_disable_cxsr(struct drm_device *dev)
 794 {
 795         struct drm_i915_private *dev_priv = dev->dev_private;
 796
 797         /* deactivate cxsr */
 798         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
 799 }
 800
 801 /*
 802  * Latency for FIFO fetches is dependent on several factors:
 803  *   - memory configuration (speed, channels)
 804  *   - chipset
 805  *   - current MCH state
 806  * It can be fairly high in some situations, so here we assume a fairly
 807  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 808  * set this value too high, the FIFO will fetch frequently to stay full)
 809  * and power consumption (set it too low to save power and we might see
 810  * FIFO underruns and display "flicker").
 811  *
 812  * A value of 5us seems to be a good balance; safe for very low end
 813  * platforms but not overly aggressive on lower latency configs.
 814  */
 815 static const int latency_ns = 5000;
 816
 817 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 818 {
 819         struct drm_i915_private *dev_priv = dev->dev_private;
 820         uint32_t dsparb = I915_READ(DSPARB);
 821         int size;
 822
 823         size = dsparb & 0x7f;
 824         if (plane)
 825                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 826
 827         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 828                       plane ? "B" : "A", size);
 829
 830         return size;
 831 }
 832
 833 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 834 {
 835         struct drm_i915_private *dev_priv = dev->dev_private;
 836         uint32_t dsparb = I915_READ(DSPARB);
 837         int size;
 838
 839         size = dsparb & 0x1ff;
 840         if (plane)
 841                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 842         size >>= 1; /* Convert to cachelines */
 843
 844         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 845                       plane ? "B" : "A", size);
 846
 847         return size;
 848 }
 849
 850 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 851 {
 852         struct drm_i915_private *dev_priv = dev->dev_private;
 853         uint32_t dsparb = I915_READ(DSPARB);
 854         int size;
 855
 856         size = dsparb & 0x7f;
 857         size >>= 2; /* Convert to cachelines */
 858
 859         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 860                       plane ? "B" : "A",
 861                       size);
 862
 863         return size;
 864 }
 865
 866 /* Pineview has different values for various configs */
 867 static const struct intel_watermark_params pineview_display_wm = {
 868         PINEVIEW_DISPLAY_FIFO,
 869         PINEVIEW_MAX_WM,
 870         PINEVIEW_DFT_WM,
 871         PINEVIEW_GUARD_WM,
 872         PINEVIEW_FIFO_LINE_SIZE
 873 };
 874 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 875         PINEVIEW_DISPLAY_FIFO,
 876         PINEVIEW_MAX_WM,
 877         PINEVIEW_DFT_HPLLOFF_WM,
 878         PINEVIEW_GUARD_WM,
 879         PINEVIEW_FIFO_LINE_SIZE
 880 };
 881 static const struct intel_watermark_params pineview_cursor_wm = {
 882         PINEVIEW_CURSOR_FIFO,
 883         PINEVIEW_CURSOR_MAX_WM,
 884         PINEVIEW_CURSOR_DFT_WM,
 885         PINEVIEW_CURSOR_GUARD_WM,
 886         PINEVIEW_FIFO_LINE_SIZE,
 887 };
 888 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 889         PINEVIEW_CURSOR_FIFO,
 890         PINEVIEW_CURSOR_MAX_WM,
 891         PINEVIEW_CURSOR_DFT_WM,
 892         PINEVIEW_CURSOR_GUARD_WM,
 893         PINEVIEW_FIFO_LINE_SIZE
 894 };
 895 static const struct intel_watermark_params g4x_wm_info = {
 896         G4X_FIFO_SIZE,
 897         G4X_MAX_WM,
 898         G4X_MAX_WM,
 899         2,
 900         G4X_FIFO_LINE_SIZE,
 901 };
 902 static const struct intel_watermark_params g4x_cursor_wm_info = {
 903         I965_CURSOR_FIFO,
 904         I965_CURSOR_MAX_WM,
 905         I965_CURSOR_DFT_WM,
 906         2,
 907         G4X_FIFO_LINE_SIZE,
 908 };
 909 static const struct intel_watermark_params valleyview_wm_info = {
 910         VALLEYVIEW_FIFO_SIZE,
 911         VALLEYVIEW_MAX_WM,
 912         VALLEYVIEW_MAX_WM,
 913         2,
 914         G4X_FIFO_LINE_SIZE,
 915 };
 916 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 917         I965_CURSOR_FIFO,
 918         VALLEYVIEW_CURSOR_MAX_WM,
 919         I965_CURSOR_DFT_WM,
 920         2,
 921         G4X_FIFO_LINE_SIZE,
 922 };
 923 static const struct intel_watermark_params i965_cursor_wm_info = {
 924         I965_CURSOR_FIFO,
 925         I965_CURSOR_MAX_WM,
 926         I965_CURSOR_DFT_WM,
 927         2,
 928         I915_FIFO_LINE_SIZE,
 929 };
 930 static const struct intel_watermark_params i945_wm_info = {
 931         I945_FIFO_SIZE,
 932         I915_MAX_WM,
 933         1,
 934         2,
 935         I915_FIFO_LINE_SIZE
 936 };
 937 static const struct intel_watermark_params i915_wm_info = {
 938         I915_FIFO_SIZE,
 939         I915_MAX_WM,
 940         1,
 941         2,
 942         I915_FIFO_LINE_SIZE
 943 };
 944 static const struct intel_watermark_params i830_wm_info = {
 945         I855GM_FIFO_SIZE,
 946         I915_MAX_WM,
 947         1,
 948         2,
 949         I830_FIFO_LINE_SIZE
 950 };
 951 static const struct intel_watermark_params i845_wm_info = {
 952         I830_FIFO_SIZE,
 953         I915_MAX_WM,
 954         1,
 955         2,
 956         I830_FIFO_LINE_SIZE
 957 };
 958
 959 /**
 960  * intel_calculate_wm - calculate watermark level
 961  * @clock_in_khz: pixel clock
 962  * @wm: chip FIFO params
 963  * @pixel_size: display pixel size
 964  * @latency_ns: memory latency for the platform
 965  *
 966  * Calculate the watermark level (the level at which the display plane will
 967  * start fetching from memory again).  Each chip has a different display
 968  * FIFO size and allocation, so the caller needs to figure that out and pass
 969  * in the correct intel_watermark_params structure.
 970  *
 971  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 972  * on the pixel size.  When it reaches the watermark level, it'll start
 973  * fetching FIFO line sized based chunks from memory until the FIFO fills
 974  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 975  * will occur, and a display engine hang could result.
 976  */
 977 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 978                                         const struct intel_watermark_params *wm,
 979                                         int fifo_size,
 980                                         int pixel_size,
 981                                         unsigned long latency_ns)
 982 {
 983         long entries_required, wm_size;
 984
 985         /*
 986          * Note: we need to make sure we don't overflow for various clock &
 987          * latency values.
 988          * clocks go from a few thousand to several hundred thousand.
 989          * latency is usually a few thousand
 990          */
 991         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 992                 1000;
 993         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 994
 995         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 996
 997         wm_size = fifo_size - (entries_required + wm->guard_size);
 998
 999         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1000
1001         /* Don't promote wm_size to unsigned... */
1002         if (wm_size > (long)wm->max_wm)
1003                 wm_size = wm->max_wm;
1004         if (wm_size <= 0)
1005                 wm_size = wm->default_wm;
1006         return wm_size;
1007 }
1008
1009 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1010 {
1011         struct drm_crtc *crtc, *enabled = NULL;
1012
1013         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1014                 if (intel_crtc_active(crtc)) {
1015                         if (enabled)
1016                                 return NULL;
1017                         enabled = crtc;
1018                 }
1019         }
1020
1021         return enabled;
1022 }
1023
1024 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1025 {
1026         struct drm_device *dev = unused_crtc->dev;
1027         struct drm_i915_private *dev_priv = dev->dev_private;
1028         struct drm_crtc *crtc;
1029         const struct cxsr_latency *latency;
1030         u32 reg;
1031         unsigned long wm;
1032
1033         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1034                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1035         if (!latency) {
1036                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1037                 pineview_disable_cxsr(dev);
1038                 return;
1039         }
1040
1041         crtc = single_enabled_crtc(dev);
1042         if (crtc) {
1043                 const struct drm_display_mode *adjusted_mode;
1044                 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1045                 int clock;
1046
1047                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1048                 clock = adjusted_mode->crtc_clock;
1049
1050                 /* Display SR */
1051                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1052                                         pineview_display_wm.fifo_size,
1053                                         pixel_size, latency->display_sr);
1054                 reg = I915_READ(DSPFW1);
1055                 reg &= ~DSPFW_SR_MASK;
1056                 reg |= wm << DSPFW_SR_SHIFT;
1057                 I915_WRITE(DSPFW1, reg);
1058                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1059
1060                 /* cursor SR */
1061                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1062                                         pineview_display_wm.fifo_size,
1063                                         pixel_size, latency->cursor_sr);
1064                 reg = I915_READ(DSPFW3);
1065                 reg &= ~DSPFW_CURSOR_SR_MASK;
1066                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1067                 I915_WRITE(DSPFW3, reg);
1068
1069                 /* Display HPLL off SR */
1070                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1071                                         pineview_display_hplloff_wm.fifo_size,
1072                                         pixel_size, latency->display_hpll_disable);
1073                 reg = I915_READ(DSPFW3);
1074                 reg &= ~DSPFW_HPLL_SR_MASK;
1075                 reg |= wm & DSPFW_HPLL_SR_MASK;
1076                 I915_WRITE(DSPFW3, reg);
1077
1078                 /* cursor HPLL off SR */
1079                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1080                                         pineview_display_hplloff_wm.fifo_size,
1081                                         pixel_size, latency->cursor_hpll_disable);
1082                 reg = I915_READ(DSPFW3);
1083                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1084                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1085                 I915_WRITE(DSPFW3, reg);
1086                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1087
1088                 /* activate cxsr */
1089                 I915_WRITE(DSPFW3,
1090                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1091                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1092         } else {
1093                 pineview_disable_cxsr(dev);
1094                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1095         }
1096 }
1097
1098 static bool g4x_compute_wm0(struct drm_device *dev,
1099                             int plane,
1100                             const struct intel_watermark_params *display,
1101                             int display_latency_ns,
1102                             const struct intel_watermark_params *cursor,
1103                             int cursor_latency_ns,
1104                             int *plane_wm,
1105                             int *cursor_wm)
1106 {
1107         struct drm_crtc *crtc;
1108         const struct drm_display_mode *adjusted_mode;
1109         int htotal, hdisplay, clock, pixel_size;
1110         int line_time_us, line_count;
1111         int entries, tlb_miss;
1112
1113         crtc = intel_get_crtc_for_plane(dev, plane);
1114         if (!intel_crtc_active(crtc)) {
1115                 *cursor_wm = cursor->guard_size;
1116                 *plane_wm = display->guard_size;
1117                 return false;
1118         }
1119
1120         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1121         clock = adjusted_mode->crtc_clock;
1122         htotal = adjusted_mode->crtc_htotal;
1123         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1124         pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1125
1126         /* Use the small buffer method to calculate plane watermark */
1127         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1128         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1129         if (tlb_miss > 0)
1130                 entries += tlb_miss;
1131         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1132         *plane_wm = entries + display->guard_size;
1133         if (*plane_wm > (int)display->max_wm)
1134                 *plane_wm = display->max_wm;
1135
1136         /* Use the large buffer method to calculate cursor watermark */
1137         line_time_us = max(htotal * 1000 / clock, 1);
1138         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1139         entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
1140         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1141         if (tlb_miss > 0)
1142                 entries += tlb_miss;
1143         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1144         *cursor_wm = entries + cursor->guard_size;
1145         if (*cursor_wm > (int)cursor->max_wm)
1146                 *cursor_wm = (int)cursor->max_wm;
1147
1148         return true;
1149 }
1150
1151 /*
1152  * Check the wm result.
1153  *
1154  * If any calculated watermark values is larger than the maximum value that
1155  * can be programmed into the associated watermark register, that watermark
1156  * must be disabled.
1157  */
1158 static bool g4x_check_srwm(struct drm_device *dev,
1159                            int display_wm, int cursor_wm,
1160                            const struct intel_watermark_params *display,
1161                            const struct intel_watermark_params *cursor)
1162 {
1163         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1164                       display_wm, cursor_wm);
1165
1166         if (display_wm > display->max_wm) {
1167                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1168                               display_wm, display->max_wm);
1169                 return false;
1170         }
1171
1172         if (cursor_wm > cursor->max_wm) {
1173                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1174                               cursor_wm, cursor->max_wm);
1175                 return false;
1176         }
1177
1178         if (!(display_wm || cursor_wm)) {
1179                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1180                 return false;
1181         }
1182
1183         return true;
1184 }
1185
1186 static bool g4x_compute_srwm(struct drm_device *dev,
1187                              int plane,
1188                              int latency_ns,
1189                              const struct intel_watermark_params *display,
1190                              const struct intel_watermark_params *cursor,
1191                              int *display_wm, int *cursor_wm)
1192 {
1193         struct drm_crtc *crtc;
1194         const struct drm_display_mode *adjusted_mode;
1195         int hdisplay, htotal, pixel_size, clock;
1196         unsigned long line_time_us;
1197         int line_count, line_size;
1198         int small, large;
1199         int entries;
1200
1201         if (!latency_ns) {
1202                 *display_wm = *cursor_wm = 0;
1203                 return false;
1204         }
1205
1206         crtc = intel_get_crtc_for_plane(dev, plane);
1207         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1208         clock = adjusted_mode->crtc_clock;
1209         htotal = adjusted_mode->crtc_htotal;
1210         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1211         pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1212
1213         line_time_us = max(htotal * 1000 / clock, 1);
1214         line_count = (latency_ns / line_time_us + 1000) / 1000;
1215         line_size = hdisplay * pixel_size;
1216
1217         /* Use the minimum of the small and large buffer method for primary */
1218         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1219         large = line_count * line_size;
1220
1221         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1222         *display_wm = entries + display->guard_size;
1223
1224         /* calculate the self-refresh watermark for display cursor */
1225         entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
1226         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1227         *cursor_wm = entries + cursor->guard_size;
1228
1229         return g4x_check_srwm(dev,
1230                               *display_wm, *cursor_wm,
1231                               display, cursor);
1232 }
1233
1234 static bool vlv_compute_drain_latency(struct drm_device *dev,
1235                                      int plane,
1236                                      int *plane_prec_mult,
1237                                      int *plane_dl,
1238                                      int *cursor_prec_mult,
1239                                      int *cursor_dl)
1240 {
1241         struct drm_crtc *crtc;
1242         int clock, pixel_size;
1243         int entries;
1244
1245         crtc = intel_get_crtc_for_plane(dev, plane);
1246         if (!intel_crtc_active(crtc))
1247                 return false;
1248
1249         clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1250         pixel_size = crtc->primary->fb->bits_per_pixel / 8;     /* BPP */
1251
1252         entries = (clock / 1000) * pixel_size;
1253         *plane_prec_mult = (entries > 256) ?
1254                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1255         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1256                                                      pixel_size);
1257
1258         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
1259         *cursor_prec_mult = (entries > 256) ?
1260                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1261         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1262
1263         return true;
1264 }
1265
1266 /*
1267  * Update drain latency registers of memory arbiter
1268  *
1269  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1270  * to be programmed. Each plane has a drain latency multiplier and a drain
1271  * latency value.
1272  */
1273
1274 static void vlv_update_drain_latency(struct drm_device *dev)
1275 {
1276         struct drm_i915_private *dev_priv = dev->dev_private;
1277         int planea_prec, planea_dl, planeb_prec, planeb_dl;
1278         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1279         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1280                                                         either 16 or 32 */
1281
1282         /* For plane A, Cursor A */
1283         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1284                                       &cursor_prec_mult, &cursora_dl)) {
1285                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1286                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1287                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1288                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1289
1290                 I915_WRITE(VLV_DDL1, cursora_prec |
1291                                 (cursora_dl << DDL_CURSORA_SHIFT) |
1292                                 planea_prec | planea_dl);
1293         }
1294
1295         /* For plane B, Cursor B */
1296         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1297                                       &cursor_prec_mult, &cursorb_dl)) {
1298                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1299                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1300                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1301                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1302
1303                 I915_WRITE(VLV_DDL2, cursorb_prec |
1304                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
1305                                 planeb_prec | planeb_dl);
1306         }
1307 }
1308
1309 #define single_plane_enabled(mask) is_power_of_2(mask)
1310
1311 static void valleyview_update_wm(struct drm_crtc *crtc)
1312 {
1313         struct drm_device *dev = crtc->dev;
1314         static const int sr_latency_ns = 12000;
1315         struct drm_i915_private *dev_priv = dev->dev_private;
1316         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1317         int plane_sr, cursor_sr;
1318         int ignore_plane_sr, ignore_cursor_sr;
1319         unsigned int enabled = 0;
1320
1321         vlv_update_drain_latency(dev);
1322
1323         if (g4x_compute_wm0(dev, PIPE_A,
1324                             &valleyview_wm_info, latency_ns,
1325                             &valleyview_cursor_wm_info, latency_ns,
1326                             &planea_wm, &cursora_wm))
1327                 enabled |= 1 << PIPE_A;
1328
1329         if (g4x_compute_wm0(dev, PIPE_B,
1330                             &valleyview_wm_info, latency_ns,
1331                             &valleyview_cursor_wm_info, latency_ns,
1332                             &planeb_wm, &cursorb_wm))
1333                 enabled |= 1 << PIPE_B;
1334
1335         if (single_plane_enabled(enabled) &&
1336             g4x_compute_srwm(dev, ffs(enabled) - 1,
1337                              sr_latency_ns,
1338                              &valleyview_wm_info,
1339                              &valleyview_cursor_wm_info,
1340                              &plane_sr, &ignore_cursor_sr) &&
1341             g4x_compute_srwm(dev, ffs(enabled) - 1,
1342                              2*sr_latency_ns,
1343                              &valleyview_wm_info,
1344                              &valleyview_cursor_wm_info,
1345                              &ignore_plane_sr, &cursor_sr)) {
1346                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1347         } else {
1348                 I915_WRITE(FW_BLC_SELF_VLV,
1349                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1350                 plane_sr = cursor_sr = 0;
1351         }
1352
1353         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1354                       planea_wm, cursora_wm,
1355                       planeb_wm, cursorb_wm,
1356                       plane_sr, cursor_sr);
1357
1358         I915_WRITE(DSPFW1,
1359                    (plane_sr << DSPFW_SR_SHIFT) |
1360                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1361                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1362                    planea_wm);
1363         I915_WRITE(DSPFW2,
1364                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1365                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1366         I915_WRITE(DSPFW3,
1367                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1368                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1369 }
1370
1371 static void g4x_update_wm(struct drm_crtc *crtc)
1372 {
1373         struct drm_device *dev = crtc->dev;
1374         static const int sr_latency_ns = 12000;
1375         struct drm_i915_private *dev_priv = dev->dev_private;
1376         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1377         int plane_sr, cursor_sr;
1378         unsigned int enabled = 0;
1379
1380         if (g4x_compute_wm0(dev, PIPE_A,
1381                             &g4x_wm_info, latency_ns,
1382                             &g4x_cursor_wm_info, latency_ns,
1383                             &planea_wm, &cursora_wm))
1384                 enabled |= 1 << PIPE_A;
1385
1386         if (g4x_compute_wm0(dev, PIPE_B,
1387                             &g4x_wm_info, latency_ns,
1388                             &g4x_cursor_wm_info, latency_ns,
1389                             &planeb_wm, &cursorb_wm))
1390                 enabled |= 1 << PIPE_B;
1391
1392         if (single_plane_enabled(enabled) &&
1393             g4x_compute_srwm(dev, ffs(enabled) - 1,
1394                              sr_latency_ns,
1395                              &g4x_wm_info,
1396                              &g4x_cursor_wm_info,
1397                              &plane_sr, &cursor_sr)) {
1398                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1399         } else {
1400                 I915_WRITE(FW_BLC_SELF,
1401                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1402                 plane_sr = cursor_sr = 0;
1403         }
1404
1405         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1406                       planea_wm, cursora_wm,
1407                       planeb_wm, cursorb_wm,
1408                       plane_sr, cursor_sr);
1409
1410         I915_WRITE(DSPFW1,
1411                    (plane_sr << DSPFW_SR_SHIFT) |
1412                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1413                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1414                    planea_wm);
1415         I915_WRITE(DSPFW2,
1416                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1417                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1418         /* HPLL off in SR has some issues on G4x... disable it */
1419         I915_WRITE(DSPFW3,
1420                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1421                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1422 }
1423
1424 static void i965_update_wm(struct drm_crtc *unused_crtc)
1425 {
1426         struct drm_device *dev = unused_crtc->dev;
1427         struct drm_i915_private *dev_priv = dev->dev_private;
1428         struct drm_crtc *crtc;
1429         int srwm = 1;
1430         int cursor_sr = 16;
1431
1432         /* Calc sr entries for one plane configs */
1433         crtc = single_enabled_crtc(dev);
1434         if (crtc) {
1435                 /* self-refresh has much higher latency */
1436                 static const int sr_latency_ns = 12000;
1437                 const struct drm_display_mode *adjusted_mode =
1438                         &to_intel_crtc(crtc)->config.adjusted_mode;
1439                 int clock = adjusted_mode->crtc_clock;
1440                 int htotal = adjusted_mode->crtc_htotal;
1441                 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1442                 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1443                 unsigned long line_time_us;
1444                 int entries;
1445
1446                 line_time_us = max(htotal * 1000 / clock, 1);
1447
1448                 /* Use ns/us then divide to preserve precision */
1449                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1450                         pixel_size * hdisplay;
1451                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1452                 srwm = I965_FIFO_SIZE - entries;
1453                 if (srwm < 0)
1454                         srwm = 1;
1455                 srwm &= 0x1ff;
1456                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1457                               entries, srwm);
1458
1459                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1460                         pixel_size * to_intel_crtc(crtc)->cursor_width;
1461                 entries = DIV_ROUND_UP(entries,
1462                                           i965_cursor_wm_info.cacheline_size);
1463                 cursor_sr = i965_cursor_wm_info.fifo_size -
1464                         (entries + i965_cursor_wm_info.guard_size);
1465
1466                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1467                         cursor_sr = i965_cursor_wm_info.max_wm;
1468
1469                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1470                               "cursor %d\n", srwm, cursor_sr);
1471
1472                 if (IS_CRESTLINE(dev))
1473                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1474         } else {
1475                 /* Turn off self refresh if both pipes are enabled */
1476                 if (IS_CRESTLINE(dev))
1477                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1478                                    & ~FW_BLC_SELF_EN);
1479         }
1480
1481         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1482                       srwm);
1483
1484         /* 965 has limitations... */
1485         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1486                    (8 << 16) | (8 << 8) | (8 << 0));
1487         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1488         /* update cursor SR watermark */
1489         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1490 }
1491
1492 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1493 {
1494         struct drm_device *dev = unused_crtc->dev;
1495         struct drm_i915_private *dev_priv = dev->dev_private;
1496         const struct intel_watermark_params *wm_info;
1497         uint32_t fwater_lo;
1498         uint32_t fwater_hi;
1499         int cwm, srwm = 1;
1500         int fifo_size;
1501         int planea_wm, planeb_wm;
1502         struct drm_crtc *crtc, *enabled = NULL;
1503
1504         if (IS_I945GM(dev))
1505                 wm_info = &i945_wm_info;
1506         else if (!IS_GEN2(dev))
1507                 wm_info = &i915_wm_info;
1508         else
1509                 wm_info = &i830_wm_info;
1510
1511         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1512         crtc = intel_get_crtc_for_plane(dev, 0);
1513         if (intel_crtc_active(crtc)) {
1514                 const struct drm_display_mode *adjusted_mode;
1515                 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1516                 if (IS_GEN2(dev))
1517                         cpp = 4;
1518
1519                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1520                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1521                                                wm_info, fifo_size, cpp,
1522                                                latency_ns);
1523                 enabled = crtc;
1524         } else
1525                 planea_wm = fifo_size - wm_info->guard_size;
1526
1527         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1528         crtc = intel_get_crtc_for_plane(dev, 1);
1529         if (intel_crtc_active(crtc)) {
1530                 const struct drm_display_mode *adjusted_mode;
1531                 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1532                 if (IS_GEN2(dev))
1533                         cpp = 4;
1534
1535                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1536                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1537                                                wm_info, fifo_size, cpp,
1538                                                latency_ns);
1539                 if (enabled == NULL)
1540                         enabled = crtc;
1541                 else
1542                         enabled = NULL;
1543         } else
1544                 planeb_wm = fifo_size - wm_info->guard_size;
1545
1546         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1547
1548         if (IS_I915GM(dev) && enabled) {
1549                 struct intel_framebuffer *fb;
1550
1551                 fb = to_intel_framebuffer(enabled->primary->fb);
1552
1553                 /* self-refresh seems busted with untiled */
1554                 if (fb->obj->tiling_mode == I915_TILING_NONE)
1555                         enabled = NULL;
1556         }
1557
1558         /*
1559          * Overlay gets an aggressive default since video jitter is bad.
1560          */
1561         cwm = 2;
1562
1563         /* Play safe and disable self-refresh before adjusting watermarks. */
1564         if (IS_I945G(dev) || IS_I945GM(dev))
1565                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1566         else if (IS_I915GM(dev))
1567                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_SELF_EN));
1568
1569         /* Calc sr entries for one plane configs */
1570         if (HAS_FW_BLC(dev) && enabled) {
1571                 /* self-refresh has much higher latency */
1572                 static const int sr_latency_ns = 6000;
1573                 const struct drm_display_mode *adjusted_mode =
1574                         &to_intel_crtc(enabled)->config.adjusted_mode;
1575                 int clock = adjusted_mode->crtc_clock;
1576                 int htotal = adjusted_mode->crtc_htotal;
1577                 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1578                 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
1579                 unsigned long line_time_us;
1580                 int entries;
1581
1582                 line_time_us = max(htotal * 1000 / clock, 1);
1583
1584                 /* Use ns/us then divide to preserve precision */
1585                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1586                         pixel_size * hdisplay;
1587                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1588                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1589                 srwm = wm_info->fifo_size - entries;
1590                 if (srwm < 0)
1591                         srwm = 1;
1592
1593                 if (IS_I945G(dev) || IS_I945GM(dev))
1594                         I915_WRITE(FW_BLC_SELF,
1595                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1596                 else if (IS_I915GM(dev))
1597                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1598         }
1599
1600         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1601                       planea_wm, planeb_wm, cwm, srwm);
1602
1603         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1604         fwater_hi = (cwm & 0x1f);
1605
1606         /* Set request length to 8 cachelines per fetch */
1607         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1608         fwater_hi = fwater_hi | (1 << 8);
1609
1610         I915_WRITE(FW_BLC, fwater_lo);
1611         I915_WRITE(FW_BLC2, fwater_hi);
1612
1613         if (HAS_FW_BLC(dev)) {
1614                 if (enabled) {
1615                         if (IS_I945G(dev) || IS_I945GM(dev))
1616                                 I915_WRITE(FW_BLC_SELF,
1617                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1618                         else if (IS_I915GM(dev))
1619                                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_SELF_EN));
1620                         DRM_DEBUG_KMS("memory self refresh enabled\n");
1621                 } else
1622                         DRM_DEBUG_KMS("memory self refresh disabled\n");
1623         }
1624 }
1625
1626 static void i845_update_wm(struct drm_crtc *unused_crtc)
1627 {
1628         struct drm_device *dev = unused_crtc->dev;
1629         struct drm_i915_private *dev_priv = dev->dev_private;
1630         struct drm_crtc *crtc;
1631         const struct drm_display_mode *adjusted_mode;
1632         uint32_t fwater_lo;
1633         int planea_wm;
1634
1635         crtc = single_enabled_crtc(dev);
1636         if (crtc == NULL)
1637                 return;
1638
1639         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1640         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1641                                        &i845_wm_info,
1642                                        dev_priv->display.get_fifo_size(dev, 0),
1643                                        4, latency_ns);
1644         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1645         fwater_lo |= (3<<8) | planea_wm;
1646
1647         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1648
1649         I915_WRITE(FW_BLC, fwater_lo);
1650 }
1651
1652 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1653                                     struct drm_crtc *crtc)
1654 {
1655         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1656         uint32_t pixel_rate;
1657
1658         pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
1659
1660         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1661          * adjust the pixel_rate here. */
1662
1663         if (intel_crtc->config.pch_pfit.enabled) {
1664                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1665                 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
1666
1667                 pipe_w = intel_crtc->config.pipe_src_w;
1668                 pipe_h = intel_crtc->config.pipe_src_h;
1669                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1670                 pfit_h = pfit_size & 0xFFFF;
1671                 if (pipe_w < pfit_w)
1672                         pipe_w = pfit_w;
1673                 if (pipe_h < pfit_h)
1674                         pipe_h = pfit_h;
1675
1676                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1677                                      pfit_w * pfit_h);
1678         }
1679
1680         return pixel_rate;
1681 }
1682
1683 /* latency must be in 0.1us units. */
1684 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1685                                uint32_t latency)
1686 {
1687         uint64_t ret;
1688
1689         if (WARN(latency == 0, "Latency value missing\n"))
1690                 return UINT_MAX;
1691
1692         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1693         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1694
1695         return ret;
1696 }
1697
1698 /* latency must be in 0.1us units. */
1699 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1700                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1701                                uint32_t latency)
1702 {
1703         uint32_t ret;
1704
1705         if (WARN(latency == 0, "Latency value missing\n"))
1706                 return UINT_MAX;
1707
1708         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1709         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1710         ret = DIV_ROUND_UP(ret, 64) + 2;
1711         return ret;
1712 }
1713
1714 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1715                            uint8_t bytes_per_pixel)
1716 {
1717         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1718 }
1719
1720 struct ilk_pipe_wm_parameters {
1721         bool active;
1722         uint32_t pipe_htotal;
1723         uint32_t pixel_rate;
1724         struct intel_plane_wm_parameters pri;
1725         struct intel_plane_wm_parameters spr;
1726         struct intel_plane_wm_parameters cur;
1727 };
1728
1729 struct ilk_wm_maximums {
1730         uint16_t pri;
1731         uint16_t spr;
1732         uint16_t cur;
1733         uint16_t fbc;
1734 };
1735
1736 /* used in computing the new watermarks state */
1737 struct intel_wm_config {
1738         unsigned int num_pipes_active;
1739         bool sprites_enabled;
1740         bool sprites_scaled;
1741 };
1742
1743 /*
1744  * For both WM_PIPE and WM_LP.
1745  * mem_value must be in 0.1us units.
1746  */
1747 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1748                                    uint32_t mem_value,
1749                                    bool is_lp)
1750 {
1751         uint32_t method1, method2;
1752
1753         if (!params->active || !params->pri.enabled)
1754                 return 0;
1755
1756         method1 = ilk_wm_method1(params->pixel_rate,
1757                                  params->pri.bytes_per_pixel,
1758                                  mem_value);
1759
1760         if (!is_lp)
1761                 return method1;
1762
1763         method2 = ilk_wm_method2(params->pixel_rate,
1764                                  params->pipe_htotal,
1765                                  params->pri.horiz_pixels,
1766                                  params->pri.bytes_per_pixel,
1767                                  mem_value);
1768
1769         return min(method1, method2);
1770 }
1771
1772 /*
1773  * For both WM_PIPE and WM_LP.
1774  * mem_value must be in 0.1us units.
1775  */
1776 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1777                                    uint32_t mem_value)
1778 {
1779         uint32_t method1, method2;
1780
1781         if (!params->active || !params->spr.enabled)
1782                 return 0;
1783
1784         method1 = ilk_wm_method1(params->pixel_rate,
1785                                  params->spr.bytes_per_pixel,
1786                                  mem_value);
1787         method2 = ilk_wm_method2(params->pixel_rate,
1788                                  params->pipe_htotal,
1789                                  params->spr.horiz_pixels,
1790                                  params->spr.bytes_per_pixel,
1791                                  mem_value);
1792         return min(method1, method2);
1793 }
1794
1795 /*
1796  * For both WM_PIPE and WM_LP.
1797  * mem_value must be in 0.1us units.
1798  */
1799 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1800                                    uint32_t mem_value)
1801 {
1802         if (!params->active || !params->cur.enabled)
1803                 return 0;
1804
1805         return ilk_wm_method2(params->pixel_rate,
1806                               params->pipe_htotal,
1807                               params->cur.horiz_pixels,
1808                               params->cur.bytes_per_pixel,
1809                               mem_value);
1810 }
1811
1812 /* Only for WM_LP. */
1813 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1814                                    uint32_t pri_val)
1815 {
1816         if (!params->active || !params->pri.enabled)
1817                 return 0;
1818
1819         return ilk_wm_fbc(pri_val,
1820                           params->pri.horiz_pixels,
1821                           params->pri.bytes_per_pixel);
1822 }
1823
1824 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1825 {
1826         if (INTEL_INFO(dev)->gen >= 8)
1827                 return 3072;
1828         else if (INTEL_INFO(dev)->gen >= 7)
1829                 return 768;
1830         else
1831                 return 512;
1832 }
1833
1834 /* Calculate the maximum primary/sprite plane watermark */
1835 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1836                                      int level,
1837                                      const struct intel_wm_config *config,
1838                                      enum intel_ddb_partitioning ddb_partitioning,
1839                                      bool is_sprite)
1840 {
1841         unsigned int fifo_size = ilk_display_fifo_size(dev);
1842         unsigned int max;
1843
1844         /* if sprites aren't enabled, sprites get nothing */
1845         if (is_sprite && !config->sprites_enabled)
1846                 return 0;
1847
1848         /* HSW allows LP1+ watermarks even with multiple pipes */
1849         if (level == 0 || config->num_pipes_active > 1) {
1850                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1851
1852                 /*
1853                  * For some reason the non self refresh
1854                  * FIFO size is only half of the self
1855                  * refresh FIFO size on ILK/SNB.
1856                  */
1857                 if (INTEL_INFO(dev)->gen <= 6)
1858                         fifo_size /= 2;
1859         }
1860
1861         if (config->sprites_enabled) {
1862                 /* level 0 is always calculated with 1:1 split */
1863                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1864                         if (is_sprite)
1865                                 fifo_size *= 5;
1866                         fifo_size /= 6;
1867                 } else {
1868                         fifo_size /= 2;
1869                 }
1870         }
1871
1872         /* clamp to max that the registers can hold */
1873         if (INTEL_INFO(dev)->gen >= 8)
1874                 max = level == 0 ? 255 : 2047;
1875         else if (INTEL_INFO(dev)->gen >= 7)
1876                 /* IVB/HSW primary/sprite plane watermarks */
1877                 max = level == 0 ? 127 : 1023;
1878         else if (!is_sprite)
1879                 /* ILK/SNB primary plane watermarks */
1880                 max = level == 0 ? 127 : 511;
1881         else
1882                 /* ILK/SNB sprite plane watermarks */
1883                 max = level == 0 ? 63 : 255;
1884
1885         return min(fifo_size, max);
1886 }
1887
1888 /* Calculate the maximum cursor plane watermark */
1889 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1890                                       int level,
1891                                       const struct intel_wm_config *config)
1892 {
1893         /* HSW LP1+ watermarks w/ multiple pipes */
1894         if (level > 0 && config->num_pipes_active > 1)
1895                 return 64;
1896
1897         /* otherwise just report max that registers can hold */
1898         if (INTEL_INFO(dev)->gen >= 7)
1899                 return level == 0 ? 63 : 255;
1900         else
1901                 return level == 0 ? 31 : 63;
1902 }
1903
1904 /* Calculate the maximum FBC watermark */
1905 static unsigned int ilk_fbc_wm_max(const struct drm_device *dev)
1906 {
1907         /* max that registers can hold */
1908         if (INTEL_INFO(dev)->gen >= 8)
1909                 return 31;
1910         else
1911                 return 15;
1912 }
1913
1914 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1915                                     int level,
1916                                     const struct intel_wm_config *config,
1917                                     enum intel_ddb_partitioning ddb_partitioning,
1918                                     struct ilk_wm_maximums *max)
1919 {
1920         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1921         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1922         max->cur = ilk_cursor_wm_max(dev, level, config);
1923         max->fbc = ilk_fbc_wm_max(dev);
1924 }
1925
1926 static bool ilk_validate_wm_level(int level,
1927                                   const struct ilk_wm_maximums *max,
1928                                   struct intel_wm_level *result)
1929 {
1930         bool ret;
1931
1932         /* already determined to be invalid? */
1933         if (!result->enable)
1934                 return false;
1935
1936         result->enable = result->pri_val <= max->pri &&
1937                          result->spr_val <= max->spr &&
1938                          result->cur_val <= max->cur;
1939
1940         ret = result->enable;
1941
1942         /*
1943          * HACK until we can pre-compute everything,
1944          * and thus fail gracefully if LP0 watermarks
1945          * are exceeded...
1946          */
1947         if (level == 0 && !result->enable) {
1948                 if (result->pri_val > max->pri)
1949                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1950                                       level, result->pri_val, max->pri);
1951                 if (result->spr_val > max->spr)
1952                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1953                                       level, result->spr_val, max->spr);
1954                 if (result->cur_val > max->cur)
1955                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1956                                       level, result->cur_val, max->cur);
1957
1958                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1959                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1960                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1961                 result->enable = true;
1962         }
1963
1964         return ret;
1965 }
1966
1967 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1968                                  int level,
1969                                  const struct ilk_pipe_wm_parameters *p,
1970                                  struct intel_wm_level *result)
1971 {
1972         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1973         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1974         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1975
1976         /* WM1+ latency values stored in 0.5us units */
1977         if (level > 0) {
1978                 pri_latency *= 5;
1979                 spr_latency *= 5;
1980                 cur_latency *= 5;
1981         }
1982
1983         result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
1984         result->spr_val = ilk_compute_spr_wm(p, spr_latency);
1985         result->cur_val = ilk_compute_cur_wm(p, cur_latency);
1986         result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
1987         result->enable = true;
1988 }
1989
1990 static uint32_t
1991 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1992 {
1993         struct drm_i915_private *dev_priv = dev->dev_private;
1994         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1995         struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
1996         u32 linetime, ips_linetime;
1997
1998         if (!intel_crtc_active(crtc))
1999                 return 0;
2000
2001         /* The WM are computed with base on how long it takes to fill a single
2002          * row at the given clock rate, multiplied by 8.
2003          * */
2004         linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2005                                      mode->crtc_clock);
2006         ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2007                                          intel_ddi_get_cdclk_freq(dev_priv));
2008
2009         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2010                PIPE_WM_LINETIME_TIME(linetime);
2011 }
2012
2013 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2014 {
2015         struct drm_i915_private *dev_priv = dev->dev_private;
2016
2017         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2018                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2019
2020                 wm[0] = (sskpd >> 56) & 0xFF;
2021                 if (wm[0] == 0)
2022                         wm[0] = sskpd & 0xF;
2023                 wm[1] = (sskpd >> 4) & 0xFF;
2024                 wm[2] = (sskpd >> 12) & 0xFF;
2025                 wm[3] = (sskpd >> 20) & 0x1FF;
2026                 wm[4] = (sskpd >> 32) & 0x1FF;
2027         } else if (INTEL_INFO(dev)->gen >= 6) {
2028                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2029
2030                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2031                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2032                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2033                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2034         } else if (INTEL_INFO(dev)->gen >= 5) {
2035                 uint32_t mltr = I915_READ(MLTR_ILK);
2036
2037                 /* ILK primary LP0 latency is 700 ns */
2038                 wm[0] = 7;
2039                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2040                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2041         }
2042 }
2043
2044 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2045 {
2046         /* ILK sprite LP0 latency is 1300 ns */
2047         if (INTEL_INFO(dev)->gen == 5)
2048                 wm[0] = 13;
2049 }
2050
2051 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2052 {
2053         /* ILK cursor LP0 latency is 1300 ns */
2054         if (INTEL_INFO(dev)->gen == 5)
2055                 wm[0] = 13;
2056
2057         /* WaDoubleCursorLP3Latency:ivb */
2058         if (IS_IVYBRIDGE(dev))
2059                 wm[3] *= 2;
2060 }
2061
2062 static int ilk_wm_max_level(const struct drm_device *dev)
2063 {
2064         /* how many WM levels are we expecting */
2065         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2066                 return 4;
2067         else if (INTEL_INFO(dev)->gen >= 6)
2068                 return 3;
2069         else
2070                 return 2;
2071 }
2072
2073 static void intel_print_wm_latency(struct drm_device *dev,
2074                                    const char *name,
2075                                    const uint16_t wm[5])
2076 {
2077         int level, max_level = ilk_wm_max_level(dev);
2078
2079         for (level = 0; level <= max_level; level++) {
2080                 unsigned int latency = wm[level];
2081
2082                 if (latency == 0) {
2083                         DRM_ERROR("%s WM%d latency not provided\n",
2084                                   name, level);
2085                         continue;
2086                 }
2087
2088                 /* WM1+ latency values in 0.5us units */
2089                 if (level > 0)
2090                         latency *= 5;
2091
2092                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2093                               name, level, wm[level],
2094                               latency / 10, latency % 10);
2095         }
2096 }
2097
2098 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2099                                     uint16_t wm[5], uint16_t min)
2100 {
2101         int level, max_level = ilk_wm_max_level(dev_priv->dev);
2102
2103         if (wm[0] >= min)
2104                 return false;
2105
2106         wm[0] = max(wm[0], min);
2107         for (level = 1; level <= max_level; level++)
2108                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2109
2110         return true;
2111 }
2112
2113 static void snb_wm_latency_quirk(struct drm_device *dev)
2114 {
2115         struct drm_i915_private *dev_priv = dev->dev_private;
2116         bool changed;
2117
2118         /*
2119          * The BIOS provided WM memory latency values are often
2120          * inadequate for high resolution displays. Adjust them.
2121          */
2122         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2123                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2124                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2125
2126         if (!changed)
2127                 return;
2128
2129         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2130         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2131         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2132         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2133 }
2134
2135 static void ilk_setup_wm_latency(struct drm_device *dev)
2136 {
2137         struct drm_i915_private *dev_priv = dev->dev_private;
2138
2139         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2140
2141         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2142                sizeof(dev_priv->wm.pri_latency));
2143         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2144                sizeof(dev_priv->wm.pri_latency));
2145
2146         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2147         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2148
2149         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2150         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2151         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2152
2153         if (IS_GEN6(dev))
2154                 snb_wm_latency_quirk(dev);
2155 }
2156
2157 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2158                                       struct ilk_pipe_wm_parameters *p,
2159                                       struct intel_wm_config *config)
2160 {
2161         struct drm_device *dev = crtc->dev;
2162         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2163         enum pipe pipe = intel_crtc->pipe;
2164         struct drm_plane *plane;
2165
2166         p->active = intel_crtc_active(crtc);
2167         if (p->active) {
2168                 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2169                 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2170                 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2171                 p->cur.bytes_per_pixel = 4;
2172                 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2173                 p->cur.horiz_pixels = intel_crtc->cursor_width;
2174                 /* TODO: for now, assume primary and cursor planes are always enabled. */
2175                 p->pri.enabled = true;
2176                 p->cur.enabled = true;
2177         }
2178
2179         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2180                 config->num_pipes_active += intel_crtc_active(crtc);
2181
2182         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
2183                 struct intel_plane *intel_plane = to_intel_plane(plane);
2184
2185                 if (intel_plane->pipe == pipe)
2186                         p->spr = intel_plane->wm;
2187
2188                 config->sprites_enabled |= intel_plane->wm.enabled;
2189                 config->sprites_scaled |= intel_plane->wm.scaled;
2190         }
2191 }
2192
2193 /* Compute new watermarks for the pipe */
2194 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2195                                   const struct ilk_pipe_wm_parameters *params,
2196                                   struct intel_pipe_wm *pipe_wm)
2197 {
2198         struct drm_device *dev = crtc->dev;
2199         const struct drm_i915_private *dev_priv = dev->dev_private;
2200         int level, max_level = ilk_wm_max_level(dev);
2201         /* LP0 watermark maximums depend on this pipe alone */
2202         struct intel_wm_config config = {
2203                 .num_pipes_active = 1,
2204                 .sprites_enabled = params->spr.enabled,
2205                 .sprites_scaled = params->spr.scaled,
2206         };
2207         struct ilk_wm_maximums max;
2208
2209         /* LP0 watermarks always use 1/2 DDB partitioning */
2210         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2211
2212         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2213         if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2214                 max_level = 1;
2215
2216         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2217         if (params->spr.scaled)
2218                 max_level = 0;
2219
2220         for (level = 0; level <= max_level; level++)
2221                 ilk_compute_wm_level(dev_priv, level, params,
2222                                      &pipe_wm->wm[level]);
2223
2224         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2225                 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2226
2227         /* At least LP0 must be valid */
2228         return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]);
2229 }
2230
2231 /*
2232  * Merge the watermarks from all active pipes for a specific level.
2233  */
2234 static void ilk_merge_wm_level(struct drm_device *dev,
2235                                int level,
2236                                struct intel_wm_level *ret_wm)
2237 {
2238         const struct intel_crtc *intel_crtc;
2239
2240         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2241                 const struct intel_wm_level *wm =
2242                         &intel_crtc->wm.active.wm[level];
2243
2244                 if (!wm->enable)
2245                         return;
2246
2247                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2248                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2249                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2250                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2251         }
2252
2253         ret_wm->enable = true;
2254 }
2255
2256 /*
2257  * Merge all low power watermarks for all active pipes.
2258  */
2259 static void ilk_wm_merge(struct drm_device *dev,
2260                          const struct intel_wm_config *config,
2261                          const struct ilk_wm_maximums *max,
2262                          struct intel_pipe_wm *merged)
2263 {
2264         int level, max_level = ilk_wm_max_level(dev);
2265
2266         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2267         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2268             config->num_pipes_active > 1)
2269                 return;
2270
2271         /* ILK: FBC WM must be disabled always */
2272         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2273
2274         /* merge each WM1+ level */
2275         for (level = 1; level <= max_level; level++) {
2276                 struct intel_wm_level *wm = &merged->wm[level];
2277
2278                 ilk_merge_wm_level(dev, level, wm);
2279
2280                 if (!ilk_validate_wm_level(level, max, wm))
2281                         break;
2282
2283                 /*
2284                  * The spec says it is preferred to disable
2285                  * FBC WMs instead of disabling a WM level.
2286                  */
2287                 if (wm->fbc_val > max->fbc) {
2288                         merged->fbc_wm_enabled = false;
2289                         wm->fbc_val = 0;
2290                 }
2291         }
2292
2293         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2294         /*
2295          * FIXME this is racy. FBC might get enabled later.
2296          * What we should check here is whether FBC can be
2297          * enabled sometime later.
2298          */
2299         if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2300                 for (level = 2; level <= max_level; level++) {
2301                         struct intel_wm_level *wm = &merged->wm[level];
2302
2303                         wm->enable = false;
2304                 }
2305         }
2306 }
2307
2308 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2309 {
2310         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2311         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2312 }
2313
2314 /* The value we need to program into the WM_LPx latency field */
2315 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2316 {
2317         struct drm_i915_private *dev_priv = dev->dev_private;
2318
2319         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2320                 return 2 * level;
2321         else
2322                 return dev_priv->wm.pri_latency[level];
2323 }
2324
2325 static void ilk_compute_wm_results(struct drm_device *dev,
2326                                    const struct intel_pipe_wm *merged,
2327                                    enum intel_ddb_partitioning partitioning,
2328                                    struct ilk_wm_values *results)
2329 {
2330         struct intel_crtc *intel_crtc;
2331         int level, wm_lp;
2332
2333         results->enable_fbc_wm = merged->fbc_wm_enabled;
2334         results->partitioning = partitioning;
2335
2336         /* LP1+ register values */
2337         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2338                 const struct intel_wm_level *r;
2339
2340                 level = ilk_wm_lp_to_level(wm_lp, merged);
2341
2342                 r = &merged->wm[level];
2343                 if (!r->enable)
2344                         break;
2345
2346                 results->wm_lp[wm_lp - 1] = WM3_LP_EN |
2347                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2348                         (r->pri_val << WM1_LP_SR_SHIFT) |
2349                         r->cur_val;
2350
2351                 if (INTEL_INFO(dev)->gen >= 8)
2352                         results->wm_lp[wm_lp - 1] |=
2353                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2354                 else
2355                         results->wm_lp[wm_lp - 1] |=
2356                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2357
2358                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2359                         WARN_ON(wm_lp != 1);
2360                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2361                 } else
2362                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2363         }
2364
2365         /* LP0 register values */
2366         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2367                 enum pipe pipe = intel_crtc->pipe;
2368                 const struct intel_wm_level *r =
2369                         &intel_crtc->wm.active.wm[0];
2370
2371                 if (WARN_ON(!r->enable))
2372                         continue;
2373
2374                 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2375
2376                 results->wm_pipe[pipe] =
2377                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2378                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2379                         r->cur_val;
2380         }
2381 }
2382
2383 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2384  * case both are at the same level. Prefer r1 in case they're the same. */
2385 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2386                                                   struct intel_pipe_wm *r1,
2387                                                   struct intel_pipe_wm *r2)
2388 {
2389         int level, max_level = ilk_wm_max_level(dev);
2390         int level1 = 0, level2 = 0;
2391
2392         for (level = 1; level <= max_level; level++) {
2393                 if (r1->wm[level].enable)
2394                         level1 = level;
2395                 if (r2->wm[level].enable)
2396                         level2 = level;
2397         }
2398
2399         if (level1 == level2) {
2400                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2401                         return r2;
2402                 else
2403                         return r1;
2404         } else if (level1 > level2) {
2405                 return r1;
2406         } else {
2407                 return r2;
2408         }
2409 }
2410
2411 /* dirty bits used to track which watermarks need changes */
2412 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2413 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2414 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2415 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2416 #define WM_DIRTY_FBC (1 << 24)
2417 #define WM_DIRTY_DDB (1 << 25)
2418
2419 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2420                                          const struct ilk_wm_values *old,
2421                                          const struct ilk_wm_values *new)
2422 {
2423         unsigned int dirty = 0;
2424         enum pipe pipe;
2425         int wm_lp;
2426
2427         for_each_pipe(pipe) {
2428                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2429                         dirty |= WM_DIRTY_LINETIME(pipe);
2430                         /* Must disable LP1+ watermarks too */
2431                         dirty |= WM_DIRTY_LP_ALL;
2432                 }
2433
2434                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2435                         dirty |= WM_DIRTY_PIPE(pipe);
2436                         /* Must disable LP1+ watermarks too */
2437                         dirty |= WM_DIRTY_LP_ALL;
2438                 }
2439         }
2440
2441         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2442                 dirty |= WM_DIRTY_FBC;
2443                 /* Must disable LP1+ watermarks too */
2444                 dirty |= WM_DIRTY_LP_ALL;
2445         }
2446
2447         if (old->partitioning != new->partitioning) {
2448                 dirty |= WM_DIRTY_DDB;
2449                 /* Must disable LP1+ watermarks too */
2450                 dirty |= WM_DIRTY_LP_ALL;
2451         }
2452
2453         /* LP1+ watermarks already deemed dirty, no need to continue */
2454         if (dirty & WM_DIRTY_LP_ALL)
2455                 return dirty;
2456
2457         /* Find the lowest numbered LP1+ watermark in need of an update... */
2458         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2459                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2460                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2461                         break;
2462         }
2463
2464         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2465         for (; wm_lp <= 3; wm_lp++)
2466                 dirty |= WM_DIRTY_LP(wm_lp);
2467
2468         return dirty;
2469 }
2470
2471 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2472                                unsigned int dirty)
2473 {
2474         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2475         bool changed = false;
2476
2477         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2478                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2479                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2480                 changed = true;
2481         }
2482         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2483                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2484                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2485                 changed = true;
2486         }
2487         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2488                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2489                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2490                 changed = true;
2491         }
2492
2493         /*
2494          * Don't touch WM1S_LP_EN here.
2495          * Doing so could cause underruns.
2496          */
2497
2498         return changed;
2499 }
2500
2501 /*
2502  * The spec says we shouldn't write when we don't need, because every write
2503  * causes WMs to be re-evaluated, expending some power.
2504  */
2505 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2506                                 struct ilk_wm_values *results)
2507 {
2508         struct drm_device *dev = dev_priv->dev;
2509         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2510         unsigned int dirty;
2511         uint32_t val;
2512
2513         dirty = ilk_compute_wm_dirty(dev, previous, results);
2514         if (!dirty)
2515                 return;
2516
2517         _ilk_disable_lp_wm(dev_priv, dirty);
2518
2519         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2520                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2521         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2522                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2523         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2524                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2525
2526         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2527                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2528         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2529                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2530         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2531                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2532
2533         if (dirty & WM_DIRTY_DDB) {
2534                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2535                         val = I915_READ(WM_MISC);
2536                         if (results->partitioning == INTEL_DDB_PART_1_2)
2537                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2538                         else
2539                                 val |= WM_MISC_DATA_PARTITION_5_6;
2540                         I915_WRITE(WM_MISC, val);
2541                 } else {
2542                         val = I915_READ(DISP_ARB_CTL2);
2543                         if (results->partitioning == INTEL_DDB_PART_1_2)
2544                                 val &= ~DISP_DATA_PARTITION_5_6;
2545                         else
2546                                 val |= DISP_DATA_PARTITION_5_6;
2547                         I915_WRITE(DISP_ARB_CTL2, val);
2548                 }
2549         }
2550
2551         if (dirty & WM_DIRTY_FBC) {
2552                 val = I915_READ(DISP_ARB_CTL);
2553                 if (results->enable_fbc_wm)
2554                         val &= ~DISP_FBC_WM_DIS;
2555                 else
2556                         val |= DISP_FBC_WM_DIS;
2557                 I915_WRITE(DISP_ARB_CTL, val);
2558         }
2559
2560         if (dirty & WM_DIRTY_LP(1) &&
2561             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2562                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2563
2564         if (INTEL_INFO(dev)->gen >= 7) {
2565                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2566                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2567                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2568                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2569         }
2570
2571         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2572                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2573         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2574                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2575         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2576                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2577
2578         dev_priv->wm.hw = *results;
2579 }
2580
2581 static bool ilk_disable_lp_wm(struct drm_device *dev)
2582 {
2583         struct drm_i915_private *dev_priv = dev->dev_private;
2584
2585         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2586 }
2587
2588 static void ilk_update_wm(struct drm_crtc *crtc)
2589 {
2590         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2591         struct drm_device *dev = crtc->dev;
2592         struct drm_i915_private *dev_priv = dev->dev_private;
2593         struct ilk_wm_maximums max;
2594         struct ilk_pipe_wm_parameters params = {};
2595         struct ilk_wm_values results = {};
2596         enum intel_ddb_partitioning partitioning;
2597         struct intel_pipe_wm pipe_wm = {};
2598         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2599         struct intel_wm_config config = {};
2600
2601         ilk_compute_wm_parameters(crtc, &params, &config);
2602
2603         intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2604
2605         if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2606                 return;
2607
2608         intel_crtc->wm.active = pipe_wm;
2609
2610         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2611         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
2612
2613         /* 5/6 split only in single pipe config on IVB+ */
2614         if (INTEL_INFO(dev)->gen >= 7 &&
2615             config.num_pipes_active == 1 && config.sprites_enabled) {
2616                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2617                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
2618
2619                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2620         } else {
2621                 best_lp_wm = &lp_wm_1_2;
2622         }
2623
2624         partitioning = (best_lp_wm == &lp_wm_1_2) ?
2625                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2626
2627         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2628
2629         ilk_write_wm_values(dev_priv, &results);
2630 }
2631
2632 static void ilk_update_sprite_wm(struct drm_plane *plane,
2633                                      struct drm_crtc *crtc,
2634                                      uint32_t sprite_width, int pixel_size,
2635                                      bool enabled, bool scaled)
2636 {
2637         struct drm_device *dev = plane->dev;
2638         struct intel_plane *intel_plane = to_intel_plane(plane);
2639
2640         intel_plane->wm.enabled = enabled;
2641         intel_plane->wm.scaled = scaled;
2642         intel_plane->wm.horiz_pixels = sprite_width;
2643         intel_plane->wm.bytes_per_pixel = pixel_size;
2644
2645         /*
2646          * IVB workaround: must disable low power watermarks for at least
2647          * one frame before enabling scaling.  LP watermarks can be re-enabled
2648          * when scaling is disabled.
2649          *
2650          * WaCxSRDisabledForSpriteScaling:ivb
2651          */
2652         if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2653                 intel_wait_for_vblank(dev, intel_plane->pipe);
2654
2655         ilk_update_wm(crtc);
2656 }
2657
2658 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2659 {
2660         struct drm_device *dev = crtc->dev;
2661         struct drm_i915_private *dev_priv = dev->dev_private;
2662         struct ilk_wm_values *hw = &dev_priv->wm.hw;
2663         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2664         struct intel_pipe_wm *active = &intel_crtc->wm.active;
2665         enum pipe pipe = intel_crtc->pipe;
2666         static const unsigned int wm0_pipe_reg[] = {
2667                 [PIPE_A] = WM0_PIPEA_ILK,
2668                 [PIPE_B] = WM0_PIPEB_ILK,
2669                 [PIPE_C] = WM0_PIPEC_IVB,
2670         };
2671
2672         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
2673         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2674                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
2675
2676         if (intel_crtc_active(crtc)) {
2677                 u32 tmp = hw->wm_pipe[pipe];
2678
2679                 /*
2680                  * For active pipes LP0 watermark is marked as
2681                  * enabled, and LP1+ watermaks as disabled since
2682                  * we can't really reverse compute them in case
2683                  * multiple pipes are active.
2684                  */
2685                 active->wm[0].enable = true;
2686                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2687                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2688                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2689                 active->linetime = hw->wm_linetime[pipe];
2690         } else {
2691                 int level, max_level = ilk_wm_max_level(dev);
2692
2693                 /*
2694                  * For inactive pipes, all watermark levels
2695                  * should be marked as enabled but zeroed,
2696                  * which is what we'd compute them to.
2697                  */
2698                 for (level = 0; level <= max_level; level++)
2699                         active->wm[level].enable = true;
2700         }
2701 }
2702
2703 void ilk_wm_get_hw_state(struct drm_device *dev)
2704 {
2705         struct drm_i915_private *dev_priv = dev->dev_private;
2706         struct ilk_wm_values *hw = &dev_priv->wm.hw;
2707         struct drm_crtc *crtc;
2708
2709         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2710                 ilk_pipe_wm_get_hw_state(crtc);
2711
2712         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2713         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2714         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2715
2716         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2717         hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2718         hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2719
2720         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2721                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2722                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2723         else if (IS_IVYBRIDGE(dev))
2724                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2725                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2726
2727         hw->enable_fbc_wm =
2728                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2729 }
2730
2731 /**
2732  * intel_update_watermarks - update FIFO watermark values based on current modes
2733  *
2734  * Calculate watermark values for the various WM regs based on current mode
2735  * and plane configuration.
2736  *
2737  * There are several cases to deal with here:
2738  *   - normal (i.e. non-self-refresh)
2739  *   - self-refresh (SR) mode
2740  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2741  *   - lines are small relative to FIFO size (buffer can hold more than 2
2742  *     lines), so need to account for TLB latency
2743  *
2744  *   The normal calculation is:
2745  *     watermark = dotclock * bytes per pixel * latency
2746  *   where latency is platform & configuration dependent (we assume pessimal
2747  *   values here).
2748  *
2749  *   The SR calculation is:
2750  *     watermark = (trunc(latency/line time)+1) * surface width *
2751  *       bytes per pixel
2752  *   where
2753  *     line time = htotal / dotclock
2754  *     surface width = hdisplay for normal plane and 64 for cursor
2755  *   and latency is assumed to be high, as above.
2756  *
2757  * The final value programmed to the register should always be rounded up,
2758  * and include an extra 2 entries to account for clock crossings.
2759  *
2760  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2761  * to set the non-SR watermarks to 8.
2762  */
2763 void intel_update_watermarks(struct drm_crtc *crtc)
2764 {
2765         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2766
2767         if (dev_priv->display.update_wm)
2768                 dev_priv->display.update_wm(crtc);
2769 }
2770
2771 void intel_update_sprite_watermarks(struct drm_plane *plane,
2772                                     struct drm_crtc *crtc,
2773                                     uint32_t sprite_width, int pixel_size,
2774                                     bool enabled, bool scaled)
2775 {
2776         struct drm_i915_private *dev_priv = plane->dev->dev_private;
2777
2778         if (dev_priv->display.update_sprite_wm)
2779                 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
2780                                                    pixel_size, enabled, scaled);
2781 }
2782
2783 static struct drm_i915_gem_object *
2784 intel_alloc_context_page(struct drm_device *dev)
2785 {
2786         struct drm_i915_gem_object *ctx;
2787         int ret;
2788
2789         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2790
2791         ctx = i915_gem_alloc_object(dev, 4096);
2792         if (!ctx) {
2793                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2794                 return NULL;
2795         }
2796
2797         ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2798         if (ret) {
2799                 DRM_ERROR("failed to pin power context: %d\n", ret);
2800                 goto err_unref;
2801         }
2802
2803         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2804         if (ret) {
2805                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2806                 goto err_unpin;
2807         }
2808
2809         return ctx;
2810
2811 err_unpin:
2812         i915_gem_object_ggtt_unpin(ctx);
2813 err_unref:
2814         drm_gem_object_unreference(&ctx->base);
2815         return NULL;
2816 }
2817
2818 /**
2819  * Lock protecting IPS related data structures
2820  */
2821 DEFINE_SPINLOCK(mchdev_lock);
2822
2823 /* Global for IPS driver to get at the current i915 device. Protected by
2824  * mchdev_lock. */
2825 static struct drm_i915_private *i915_mch_dev;
2826
2827 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2828 {
2829         struct drm_i915_private *dev_priv = dev->dev_private;
2830         u16 rgvswctl;
2831
2832         assert_spin_locked(&mchdev_lock);
2833
2834         rgvswctl = I915_READ16(MEMSWCTL);
2835         if (rgvswctl & MEMCTL_CMD_STS) {
2836                 DRM_DEBUG("gpu busy, RCS change rejected\n");
2837                 return false; /* still busy with another command */
2838         }
2839
2840         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2841                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2842         I915_WRITE16(MEMSWCTL, rgvswctl);
2843         POSTING_READ16(MEMSWCTL);
2844
2845         rgvswctl |= MEMCTL_CMD_STS;
2846         I915_WRITE16(MEMSWCTL, rgvswctl);
2847
2848         return true;
2849 }
2850
2851 static void ironlake_enable_drps(struct drm_device *dev)
2852 {
2853         struct drm_i915_private *dev_priv = dev->dev_private;
2854         u32 rgvmodectl = I915_READ(MEMMODECTL);
2855         u8 fmax, fmin, fstart, vstart;
2856
2857         spin_lock_irq(&mchdev_lock);
2858
2859         /* Enable temp reporting */
2860         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2861         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2862
2863         /* 100ms RC evaluation intervals */
2864         I915_WRITE(RCUPEI, 100000);
2865         I915_WRITE(RCDNEI, 100000);
2866
2867         /* Set max/min thresholds to 90ms and 80ms respectively */
2868         I915_WRITE(RCBMAXAVG, 90000);
2869         I915_WRITE(RCBMINAVG, 80000);
2870
2871         I915_WRITE(MEMIHYST, 1);
2872
2873         /* Set up min, max, and cur for interrupt handling */
2874         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2875         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2876         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2877                 MEMMODE_FSTART_SHIFT;
2878
2879         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2880                 PXVFREQ_PX_SHIFT;
2881
2882         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2883         dev_priv->ips.fstart = fstart;
2884
2885         dev_priv->ips.max_delay = fstart;
2886         dev_priv->ips.min_delay = fmin;
2887         dev_priv->ips.cur_delay = fstart;
2888
2889         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2890                          fmax, fmin, fstart);
2891
2892         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2893
2894         /*
2895          * Interrupts will be enabled in ironlake_irq_postinstall
2896          */
2897
2898         I915_WRITE(VIDSTART, vstart);
2899         POSTING_READ(VIDSTART);
2900
2901         rgvmodectl |= MEMMODE_SWMODE_EN;
2902         I915_WRITE(MEMMODECTL, rgvmodectl);
2903
2904         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2905                 DRM_ERROR("stuck trying to change perf mode\n");
2906         mdelay(1);
2907
2908         ironlake_set_drps(dev, fstart);
2909
2910         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2911                 I915_READ(0x112e0);
2912         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2913         dev_priv->ips.last_count2 = I915_READ(0x112f4);
2914         getrawmonotonic(&dev_priv->ips.last_time2);
2915
2916         spin_unlock_irq(&mchdev_lock);
2917 }
2918
2919 static void ironlake_disable_drps(struct drm_device *dev)
2920 {
2921         struct drm_i915_private *dev_priv = dev->dev_private;
2922         u16 rgvswctl;
2923
2924         spin_lock_irq(&mchdev_lock);
2925
2926         rgvswctl = I915_READ16(MEMSWCTL);
2927
2928         /* Ack interrupts, disable EFC interrupt */
2929         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2930         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2931         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2932         I915_WRITE(DEIIR, DE_PCU_EVENT);
2933         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2934
2935         /* Go back to the starting frequency */
2936         ironlake_set_drps(dev, dev_priv->ips.fstart);
2937         mdelay(1);
2938         rgvswctl |= MEMCTL_CMD_STS;
2939         I915_WRITE(MEMSWCTL, rgvswctl);
2940         mdelay(1);
2941
2942         spin_unlock_irq(&mchdev_lock);
2943 }
2944
2945 /* There's a funny hw issue where the hw returns all 0 when reading from
2946  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2947  * ourselves, instead of doing a rmw cycle (which might result in us clearing
2948  * all limits and the gpu stuck at whatever frequency it is at atm).
2949  */
2950 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2951 {
2952         u32 limits;
2953
2954         /* Only set the down limit when we've reached the lowest level to avoid
2955          * getting more interrupts, otherwise leave this clear. This prevents a
2956          * race in the hw when coming out of rc6: There's a tiny window where
2957          * the hw runs at the minimal clock before selecting the desired
2958          * frequency, if the down threshold expires in that window we will not
2959          * receive a down interrupt. */
2960         limits = dev_priv->rps.max_freq_softlimit << 24;
2961         if (val <= dev_priv->rps.min_freq_softlimit)
2962                 limits |= dev_priv->rps.min_freq_softlimit << 16;
2963
2964         return limits;
2965 }
2966
2967 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
2968 {
2969         int new_power;
2970
2971         new_power = dev_priv->rps.power;
2972         switch (dev_priv->rps.power) {
2973         case LOW_POWER:
2974                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
2975                         new_power = BETWEEN;
2976                 break;
2977
2978         case BETWEEN:
2979                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
2980                         new_power = LOW_POWER;
2981                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
2982                         new_power = HIGH_POWER;
2983                 break;
2984
2985         case HIGH_POWER:
2986                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
2987                         new_power = BETWEEN;
2988                 break;
2989         }
2990         /* Max/min bins are special */
2991         if (val == dev_priv->rps.min_freq_softlimit)
2992                 new_power = LOW_POWER;
2993         if (val == dev_priv->rps.max_freq_softlimit)
2994                 new_power = HIGH_POWER;
2995         if (new_power == dev_priv->rps.power)
2996                 return;
2997
2998         /* Note the units here are not exactly 1us, but 1280ns. */
2999         switch (new_power) {
3000         case LOW_POWER:
3001                 /* Upclock if more than 95% busy over 16ms */
3002                 I915_WRITE(GEN6_RP_UP_EI, 12500);
3003                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3004
3005                 /* Downclock if less than 85% busy over 32ms */
3006                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3007                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3008
3009                 I915_WRITE(GEN6_RP_CONTROL,
3010                            GEN6_RP_MEDIA_TURBO |
3011                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3012                            GEN6_RP_MEDIA_IS_GFX |
3013                            GEN6_RP_ENABLE |
3014                            GEN6_RP_UP_BUSY_AVG |
3015                            GEN6_RP_DOWN_IDLE_AVG);
3016                 break;
3017
3018         case BETWEEN:
3019                 /* Upclock if more than 90% busy over 13ms */
3020                 I915_WRITE(GEN6_RP_UP_EI, 10250);
3021                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3022
3023                 /* Downclock if less than 75% busy over 32ms */
3024                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3025                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3026
3027                 I915_WRITE(GEN6_RP_CONTROL,
3028                            GEN6_RP_MEDIA_TURBO |
3029                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3030                            GEN6_RP_MEDIA_IS_GFX |
3031                            GEN6_RP_ENABLE |
3032                            GEN6_RP_UP_BUSY_AVG |
3033                            GEN6_RP_DOWN_IDLE_AVG);
3034                 break;
3035
3036         case HIGH_POWER:
3037                 /* Upclock if more than 85% busy over 10ms */
3038                 I915_WRITE(GEN6_RP_UP_EI, 8000);
3039                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3040
3041                 /* Downclock if less than 60% busy over 32ms */
3042                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3043                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3044
3045                 I915_WRITE(GEN6_RP_CONTROL,
3046                            GEN6_RP_MEDIA_TURBO |
3047                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3048                            GEN6_RP_MEDIA_IS_GFX |
3049                            GEN6_RP_ENABLE |
3050                            GEN6_RP_UP_BUSY_AVG |
3051                            GEN6_RP_DOWN_IDLE_AVG);
3052                 break;
3053         }
3054
3055         dev_priv->rps.power = new_power;
3056         dev_priv->rps.last_adj = 0;
3057 }
3058
3059 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3060 {
3061         u32 mask = 0;
3062
3063         if (val > dev_priv->rps.min_freq_softlimit)
3064                 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3065         if (val < dev_priv->rps.max_freq_softlimit)
3066                 mask |= GEN6_PM_RP_UP_THRESHOLD;
3067
3068         /* IVB and SNB hard hangs on looping batchbuffer
3069          * if GEN6_PM_UP_EI_EXPIRED is masked.
3070          */
3071         if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3072                 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3073
3074         return ~mask;
3075 }
3076
3077 /* gen6_set_rps is called to update the frequency request, but should also be
3078  * called when the range (min_delay and max_delay) is modified so that we can
3079  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3080 void gen6_set_rps(struct drm_device *dev, u8 val)
3081 {
3082         struct drm_i915_private *dev_priv = dev->dev_private;
3083
3084         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3085         WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3086         WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3087
3088         /* min/max delay may still have been modified so be sure to
3089          * write the limits value.
3090          */
3091         if (val != dev_priv->rps.cur_freq) {
3092                 gen6_set_rps_thresholds(dev_priv, val);
3093
3094                 if (IS_HASWELL(dev))
3095                         I915_WRITE(GEN6_RPNSWREQ,
3096                                    HSW_FREQUENCY(val));
3097                 else
3098                         I915_WRITE(GEN6_RPNSWREQ,
3099                                    GEN6_FREQUENCY(val) |
3100                                    GEN6_OFFSET(0) |
3101                                    GEN6_AGGRESSIVE_TURBO);
3102         }
3103
3104         /* Make sure we continue to get interrupts
3105          * until we hit the minimum or maximum frequencies.
3106          */
3107         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
3108         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3109
3110         POSTING_READ(GEN6_RPNSWREQ);
3111
3112         dev_priv->rps.cur_freq = val;
3113         trace_intel_gpu_freq_change(val * 50);
3114 }
3115
3116 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3117  *
3118  * * If Gfx is Idle, then
3119  * 1. Mask Turbo interrupts
3120  * 2. Bring up Gfx clock
3121  * 3. Change the freq to Rpn and wait till P-Unit updates freq
3122  * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3123  * 5. Unmask Turbo interrupts
3124 */
3125 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3126 {
3127         /*
3128          * When we are idle.  Drop to min voltage state.
3129          */
3130
3131         if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
3132                 return;
3133
3134         /* Mask turbo interrupt so that they will not come in between */
3135         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3136
3137         /* Bring up the Gfx clock */
3138         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG,
3139                 I915_READ(VLV_GTLC_SURVIVABILITY_REG) |
3140                                 VLV_GFX_CLK_FORCE_ON_BIT);
3141
3142         if (wait_for(((VLV_GFX_CLK_STATUS_BIT &
3143                 I915_READ(VLV_GTLC_SURVIVABILITY_REG)) != 0), 5)) {
3144                         DRM_ERROR("GFX_CLK_ON request timed out\n");
3145                 return;
3146         }
3147
3148         dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
3149
3150         vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
3151                                         dev_priv->rps.min_freq_softlimit);
3152
3153         if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3154                                 & GENFREQSTATUS) == 0, 5))
3155                 DRM_ERROR("timed out waiting for Punit\n");
3156
3157         /* Release the Gfx clock */
3158         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG,
3159                 I915_READ(VLV_GTLC_SURVIVABILITY_REG) &
3160                                 ~VLV_GFX_CLK_FORCE_ON_BIT);
3161
3162         I915_WRITE(GEN6_PMINTRMSK,
3163                    gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
3164 }
3165
3166 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3167 {
3168         struct drm_device *dev = dev_priv->dev;
3169
3170         mutex_lock(&dev_priv->rps.hw_lock);
3171         if (dev_priv->rps.enabled) {
3172                 if (IS_VALLEYVIEW(dev))
3173                         vlv_set_rps_idle(dev_priv);
3174                 else
3175                         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3176                 dev_priv->rps.last_adj = 0;
3177         }
3178         mutex_unlock(&dev_priv->rps.hw_lock);
3179 }
3180
3181 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3182 {
3183         struct drm_device *dev = dev_priv->dev;
3184
3185         mutex_lock(&dev_priv->rps.hw_lock);
3186         if (dev_priv->rps.enabled) {
3187                 if (IS_VALLEYVIEW(dev))
3188                         valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3189                 else
3190                         gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3191                 dev_priv->rps.last_adj = 0;
3192         }
3193         mutex_unlock(&dev_priv->rps.hw_lock);
3194 }
3195
3196 void valleyview_set_rps(struct drm_device *dev, u8 val)
3197 {
3198         struct drm_i915_private *dev_priv = dev->dev_private;
3199
3200         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3201         WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3202         WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3203
3204         DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3205                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3206                          dev_priv->rps.cur_freq,
3207                          vlv_gpu_freq(dev_priv, val), val);
3208
3209         if (val != dev_priv->rps.cur_freq)
3210                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3211
3212         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3213
3214         dev_priv->rps.cur_freq = val;
3215         trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3216 }
3217
3218 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3219 {
3220         struct drm_i915_private *dev_priv = dev->dev_private;
3221
3222         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3223         I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3224                                 ~dev_priv->pm_rps_events);
3225         /* Complete PM interrupt masking here doesn't race with the rps work
3226          * item again unmasking PM interrupts because that is using a different
3227          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3228          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3229
3230         spin_lock_irq(&dev_priv->irq_lock);
3231         dev_priv->rps.pm_iir = 0;
3232         spin_unlock_irq(&dev_priv->irq_lock);
3233
3234         I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3235 }
3236
3237 static void gen6_disable_rps(struct drm_device *dev)
3238 {
3239         struct drm_i915_private *dev_priv = dev->dev_private;
3240
3241         I915_WRITE(GEN6_RC_CONTROL, 0);
3242         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3243
3244         gen6_disable_rps_interrupts(dev);
3245 }
3246
3247 static void valleyview_disable_rps(struct drm_device *dev)
3248 {
3249         struct drm_i915_private *dev_priv = dev->dev_private;
3250
3251         I915_WRITE(GEN6_RC_CONTROL, 0);
3252
3253         gen6_disable_rps_interrupts(dev);
3254 }
3255
3256 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3257 {
3258         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3259                  (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3260                  (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3261                  (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3262 }
3263
3264 int intel_enable_rc6(const struct drm_device *dev)
3265 {
3266         /* No RC6 before Ironlake */
3267         if (INTEL_INFO(dev)->gen < 5)
3268                 return 0;
3269
3270         /* Respect the kernel parameter if it is set */
3271         if (i915.enable_rc6 >= 0)
3272                 return i915.enable_rc6;
3273
3274         /* Disable RC6 on Ironlake */
3275         if (INTEL_INFO(dev)->gen == 5)
3276                 return 0;
3277
3278         if (IS_IVYBRIDGE(dev))
3279                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3280
3281         return INTEL_RC6_ENABLE;
3282 }
3283
3284 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3285 {
3286         struct drm_i915_private *dev_priv = dev->dev_private;
3287
3288         spin_lock_irq(&dev_priv->irq_lock);
3289         WARN_ON(dev_priv->rps.pm_iir);
3290         snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3291         I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3292         spin_unlock_irq(&dev_priv->irq_lock);
3293 }
3294
3295 static void gen8_enable_rps(struct drm_device *dev)
3296 {
3297         struct drm_i915_private *dev_priv = dev->dev_private;
3298         struct intel_ring_buffer *ring;
3299         uint32_t rc6_mask = 0, rp_state_cap;
3300         int unused;
3301
3302         /* 1a: Software RC state - RC0 */
3303         I915_WRITE(GEN6_RC_STATE, 0);
3304
3305         /* 1c & 1d: Get forcewake during program sequence. Although the driver
3306          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3307         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3308
3309         /* 2a: Disable RC states. */
3310         I915_WRITE(GEN6_RC_CONTROL, 0);
3311
3312         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3313
3314         /* 2b: Program RC6 thresholds.*/
3315         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3316         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3317         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3318         for_each_ring(ring, dev_priv, unused)
3319                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3320         I915_WRITE(GEN6_RC_SLEEP, 0);
3321         I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3322
3323         /* 3: Enable RC6 */
3324         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3325                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3326         intel_print_rc6_info(dev, rc6_mask);
3327         I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3328                                     GEN6_RC_CTL_EI_MODE(1) |
3329                                     rc6_mask);
3330
3331         /* 4 Program defaults and thresholds for RPS*/
3332         I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
3333         I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */
3334         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3335         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3336
3337         /* Docs recommend 900MHz, and 300 MHz respectively */
3338         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3339                    dev_priv->rps.max_freq_softlimit << 24 |
3340                    dev_priv->rps.min_freq_softlimit << 16);
3341
3342         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3343         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3344         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3345         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3346
3347         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3348
3349         /* 5: Enable RPS */
3350         I915_WRITE(GEN6_RP_CONTROL,
3351                    GEN6_RP_MEDIA_TURBO |
3352                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
3353                    GEN6_RP_MEDIA_IS_GFX |
3354                    GEN6_RP_ENABLE |
3355                    GEN6_RP_UP_BUSY_AVG |
3356                    GEN6_RP_DOWN_IDLE_AVG);
3357
3358         /* 6: Ring frequency + overclocking (our driver does this later */
3359
3360         gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3361
3362         gen6_enable_rps_interrupts(dev);
3363
3364         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3365 }
3366
3367 static void gen6_enable_rps(struct drm_device *dev)
3368 {
3369         struct drm_i915_private *dev_priv = dev->dev_private;
3370         struct intel_ring_buffer *ring;
3371         u32 rp_state_cap;
3372         u32 gt_perf_status;
3373         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
3374         u32 gtfifodbg;
3375         int rc6_mode;
3376         int i, ret;
3377
3378         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3379
3380         /* Here begins a magic sequence of register writes to enable
3381          * auto-downclocking.
3382          *
3383          * Perhaps there might be some value in exposing these to
3384          * userspace...
3385          */
3386         I915_WRITE(GEN6_RC_STATE, 0);
3387
3388         /* Clear the DBG now so we don't confuse earlier errors */
3389         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3390                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3391                 I915_WRITE(GTFIFODBG, gtfifodbg);
3392         }
3393
3394         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3395
3396         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3397         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3398
3399         /* All of these values are in units of 50MHz */
3400         dev_priv->rps.cur_freq          = 0;
3401         /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3402         dev_priv->rps.rp1_freq          = (rp_state_cap >>  8) & 0xff;
3403         dev_priv->rps.rp0_freq          = (rp_state_cap >>  0) & 0xff;
3404         dev_priv->rps.min_freq          = (rp_state_cap >> 16) & 0xff;
3405         /* XXX: only BYT has a special efficient freq */
3406         dev_priv->rps.efficient_freq    = dev_priv->rps.rp1_freq;
3407         /* hw_max = RP0 until we check for overclocking */
3408         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
3409
3410         /* Preserve min/max settings in case of re-init */
3411         if (dev_priv->rps.max_freq_softlimit == 0)
3412                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3413
3414         if (dev_priv->rps.min_freq_softlimit == 0)
3415                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3416
3417         /* disable the counters and set deterministic thresholds */
3418         I915_WRITE(GEN6_RC_CONTROL, 0);
3419
3420         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3421         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3422         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3423         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3424         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3425
3426         for_each_ring(ring, dev_priv, i)
3427                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3428
3429         I915_WRITE(GEN6_RC_SLEEP, 0);
3430         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3431         if (IS_IVYBRIDGE(dev))
3432                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3433         else
3434                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3435         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3436         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3437
3438         /* Check if we are enabling RC6 */
3439         rc6_mode = intel_enable_rc6(dev_priv->dev);
3440         if (rc6_mode & INTEL_RC6_ENABLE)
3441                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3442
3443         /* We don't use those on Haswell */
3444         if (!IS_HASWELL(dev)) {
3445                 if (rc6_mode & INTEL_RC6p_ENABLE)
3446                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3447
3448                 if (rc6_mode & INTEL_RC6pp_ENABLE)
3449                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3450         }
3451
3452         intel_print_rc6_info(dev, rc6_mask);
3453
3454         I915_WRITE(GEN6_RC_CONTROL,
3455                    rc6_mask |
3456                    GEN6_RC_CTL_EI_MODE(1) |
3457                    GEN6_RC_CTL_HW_ENABLE);
3458
3459         /* Power down if completely idle for over 50ms */
3460         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3461         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3462
3463         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3464         if (ret)
3465                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3466
3467         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3468         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3469                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3470                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
3471                                  (pcu_mbox & 0xff) * 50);
3472                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
3473         }
3474
3475         dev_priv->rps.power = HIGH_POWER; /* force a reset */
3476         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3477
3478         gen6_enable_rps_interrupts(dev);
3479
3480         rc6vids = 0;
3481         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3482         if (IS_GEN6(dev) && ret) {
3483                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3484         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3485                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3486                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3487                 rc6vids &= 0xffff00;
3488                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3489                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3490                 if (ret)
3491                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3492         }
3493
3494         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3495 }
3496
3497 void gen6_update_ring_freq(struct drm_device *dev)
3498 {
3499         struct drm_i915_private *dev_priv = dev->dev_private;
3500         int min_freq = 15;
3501         unsigned int gpu_freq;
3502         unsigned int max_ia_freq, min_ring_freq;
3503         int scaling_factor = 180;
3504         struct cpufreq_policy *policy;
3505
3506         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3507
3508         policy = cpufreq_cpu_get(0);
3509         if (policy) {
3510                 max_ia_freq = policy->cpuinfo.max_freq;
3511                 cpufreq_cpu_put(policy);
3512         } else {
3513                 /*
3514                  * Default to measured freq if none found, PCU will ensure we
3515                  * don't go over
3516                  */
3517                 max_ia_freq = tsc_khz;
3518         }
3519
3520         /* Convert from kHz to MHz */
3521         max_ia_freq /= 1000;
3522
3523         min_ring_freq = I915_READ(DCLK) & 0xf;
3524         /* convert DDR frequency from units of 266.6MHz to bandwidth */
3525         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3526
3527         /*
3528          * For each potential GPU frequency, load a ring frequency we'd like
3529          * to use for memory access.  We do this by specifying the IA frequency
3530          * the PCU should use as a reference to determine the ring frequency.
3531          */
3532         for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
3533              gpu_freq--) {
3534                 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3535                 unsigned int ia_freq = 0, ring_freq = 0;
3536
3537                 if (INTEL_INFO(dev)->gen >= 8) {
3538                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
3539                         ring_freq = max(min_ring_freq, gpu_freq);
3540                 } else if (IS_HASWELL(dev)) {
3541                         ring_freq = mult_frac(gpu_freq, 5, 4);
3542                         ring_freq = max(min_ring_freq, ring_freq);
3543                         /* leave ia_freq as the default, chosen by cpufreq */
3544                 } else {
3545                         /* On older processors, there is no separate ring
3546                          * clock domain, so in order to boost the bandwidth
3547                          * of the ring, we need to upclock the CPU (ia_freq).
3548                          *
3549                          * For GPU frequencies less than 750MHz,
3550                          * just use the lowest ring freq.
3551                          */
3552                         if (gpu_freq < min_freq)
3553                                 ia_freq = 800;
3554                         else
3555                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3556                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3557                 }
3558
3559                 sandybridge_pcode_write(dev_priv,
3560                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3561                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3562                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3563                                         gpu_freq);
3564         }
3565 }
3566
3567 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3568 {
3569         u32 val, rp0;
3570
3571         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3572
3573         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3574         /* Clamp to max */
3575         rp0 = min_t(u32, rp0, 0xea);
3576
3577         return rp0;
3578 }
3579
3580 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3581 {
3582         u32 val, rpe;
3583
3584         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3585         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3586         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3587         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3588
3589         return rpe;
3590 }
3591
3592 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3593 {
3594         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3595 }
3596
3597 /* Check that the pctx buffer wasn't move under us. */
3598 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
3599 {
3600         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3601
3602         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
3603                              dev_priv->vlv_pctx->stolen->start);
3604 }
3605
3606 static void valleyview_setup_pctx(struct drm_device *dev)
3607 {
3608         struct drm_i915_private *dev_priv = dev->dev_private;
3609         struct drm_i915_gem_object *pctx;
3610         unsigned long pctx_paddr;
3611         u32 pcbr;
3612         int pctx_size = 24*1024;
3613
3614         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3615
3616         pcbr = I915_READ(VLV_PCBR);
3617         if (pcbr) {
3618                 /* BIOS set it up already, grab the pre-alloc'd space */
3619                 int pcbr_offset;
3620
3621                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3622                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3623                                                                       pcbr_offset,
3624                                                                       I915_GTT_OFFSET_NONE,
3625                                                                       pctx_size);
3626                 goto out;
3627         }
3628
3629         /*
3630          * From the Gunit register HAS:
3631          * The Gfx driver is expected to program this register and ensure
3632          * proper allocation within Gfx stolen memory.  For example, this
3633          * register should be programmed such than the PCBR range does not
3634          * overlap with other ranges, such as the frame buffer, protected
3635          * memory, or any other relevant ranges.
3636          */
3637         pctx = i915_gem_object_create_stolen(dev, pctx_size);
3638         if (!pctx) {
3639                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3640                 return;
3641         }
3642
3643         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3644         I915_WRITE(VLV_PCBR, pctx_paddr);
3645
3646 out:
3647         dev_priv->vlv_pctx = pctx;
3648 }
3649
3650 static void valleyview_cleanup_pctx(struct drm_device *dev)
3651 {
3652         struct drm_i915_private *dev_priv = dev->dev_private;
3653
3654         if (WARN_ON(!dev_priv->vlv_pctx))
3655                 return;
3656
3657         drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3658         dev_priv->vlv_pctx = NULL;
3659 }
3660
3661 static void valleyview_enable_rps(struct drm_device *dev)
3662 {
3663         struct drm_i915_private *dev_priv = dev->dev_private;
3664         struct intel_ring_buffer *ring;
3665         u32 gtfifodbg, val, rc6_mode = 0;
3666         int i;
3667
3668         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3669
3670         valleyview_check_pctx(dev_priv);
3671
3672         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3673                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3674                                  gtfifodbg);
3675                 I915_WRITE(GTFIFODBG, gtfifodbg);
3676         }
3677
3678         /* If VLV, Forcewake all wells, else re-direct to regular path */
3679         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3680
3681         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3682         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3683         I915_WRITE(GEN6_RP_UP_EI, 66000);
3684         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3685
3686         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3687
3688         I915_WRITE(GEN6_RP_CONTROL,
3689                    GEN6_RP_MEDIA_TURBO |
3690                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
3691                    GEN6_RP_MEDIA_IS_GFX |
3692                    GEN6_RP_ENABLE |
3693                    GEN6_RP_UP_BUSY_AVG |
3694                    GEN6_RP_DOWN_IDLE_CONT);
3695
3696         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3697         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3698         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3699
3700         for_each_ring(ring, dev_priv, i)
3701                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3702
3703         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
3704
3705         /* allows RC6 residency counter to work */
3706         I915_WRITE(VLV_COUNTER_CONTROL,
3707                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
3708                                       VLV_MEDIA_RC6_COUNT_EN |
3709                                       VLV_RENDER_RC6_COUNT_EN));
3710         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3711                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
3712
3713         intel_print_rc6_info(dev, rc6_mode);
3714
3715         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
3716
3717         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3718
3719         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3720         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3721
3722         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
3723         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3724                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3725                          dev_priv->rps.cur_freq);
3726
3727         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
3728         dev_priv->rps.rp0_freq  = dev_priv->rps.max_freq;
3729         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3730                          vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
3731                          dev_priv->rps.max_freq);
3732
3733         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
3734         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3735                          vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3736                          dev_priv->rps.efficient_freq);
3737
3738         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
3739         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3740                          vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
3741                          dev_priv->rps.min_freq);
3742
3743         /* Preserve min/max settings in case of re-init */
3744         if (dev_priv->rps.max_freq_softlimit == 0)
3745                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3746
3747         if (dev_priv->rps.min_freq_softlimit == 0)
3748                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3749
3750         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3751                          vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3752                          dev_priv->rps.efficient_freq);
3753
3754         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
3755
3756         gen6_enable_rps_interrupts(dev);
3757
3758         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3759 }
3760
3761 void ironlake_teardown_rc6(struct drm_device *dev)
3762 {
3763         struct drm_i915_private *dev_priv = dev->dev_private;
3764
3765         if (dev_priv->ips.renderctx) {
3766                 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
3767                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3768                 dev_priv->ips.renderctx = NULL;
3769         }
3770
3771         if (dev_priv->ips.pwrctx) {
3772                 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
3773                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3774                 dev_priv->ips.pwrctx = NULL;
3775         }
3776 }
3777
3778 static void ironlake_disable_rc6(struct drm_device *dev)
3779 {
3780         struct drm_i915_private *dev_priv = dev->dev_private;
3781
3782         if (I915_READ(PWRCTXA)) {
3783                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3784                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3785                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3786                          50);
3787
3788                 I915_WRITE(PWRCTXA, 0);
3789                 POSTING_READ(PWRCTXA);
3790
3791                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3792                 POSTING_READ(RSTDBYCTL);
3793         }
3794 }
3795
3796 static int ironlake_setup_rc6(struct drm_device *dev)
3797 {
3798         struct drm_i915_private *dev_priv = dev->dev_private;
3799
3800         if (dev_priv->ips.renderctx == NULL)
3801                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3802         if (!dev_priv->ips.renderctx)
3803                 return -ENOMEM;
3804
3805         if (dev_priv->ips.pwrctx == NULL)
3806                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3807         if (!dev_priv->ips.pwrctx) {
3808                 ironlake_teardown_rc6(dev);
3809                 return -ENOMEM;
3810         }
3811
3812         return 0;
3813 }
3814
3815 static void ironlake_enable_rc6(struct drm_device *dev)
3816 {
3817         struct drm_i915_private *dev_priv = dev->dev_private;
3818         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3819         bool was_interruptible;
3820         int ret;
3821
3822         /* rc6 disabled by default due to repeated reports of hanging during
3823          * boot and resume.
3824          */
3825         if (!intel_enable_rc6(dev))
3826                 return;
3827
3828         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3829
3830         ret = ironlake_setup_rc6(dev);
3831         if (ret)
3832                 return;
3833
3834         was_interruptible = dev_priv->mm.interruptible;
3835         dev_priv->mm.interruptible = false;
3836
3837         /*
3838          * GPU can automatically power down the render unit if given a page
3839          * to save state.
3840          */
3841         ret = intel_ring_begin(ring, 6);
3842         if (ret) {
3843                 ironlake_teardown_rc6(dev);
3844                 dev_priv->mm.interruptible = was_interruptible;
3845                 return;
3846         }
3847
3848         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3849         intel_ring_emit(ring, MI_SET_CONTEXT);
3850         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
3851                         MI_MM_SPACE_GTT |
3852                         MI_SAVE_EXT_STATE_EN |
3853                         MI_RESTORE_EXT_STATE_EN |
3854                         MI_RESTORE_INHIBIT);
3855         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3856         intel_ring_emit(ring, MI_NOOP);
3857         intel_ring_emit(ring, MI_FLUSH);
3858         intel_ring_advance(ring);
3859
3860         /*
3861          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3862          * does an implicit flush, combined with MI_FLUSH above, it should be
3863          * safe to assume that renderctx is valid
3864          */
3865         ret = intel_ring_idle(ring);
3866         dev_priv->mm.interruptible = was_interruptible;
3867         if (ret) {
3868                 DRM_ERROR("failed to enable ironlake power savings\n");
3869                 ironlake_teardown_rc6(dev);
3870                 return;
3871         }
3872
3873         I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
3874         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3875
3876         intel_print_rc6_info(dev, INTEL_RC6_ENABLE);
3877 }
3878
3879 static unsigned long intel_pxfreq(u32 vidfreq)
3880 {
3881         unsigned long freq;
3882         int div = (vidfreq & 0x3f0000) >> 16;
3883         int post = (vidfreq & 0x3000) >> 12;
3884         int pre = (vidfreq & 0x7);
3885
3886         if (!pre)
3887                 return 0;
3888
3889         freq = ((div * 133333) / ((1<<post) * pre));
3890
3891         return freq;
3892 }
3893
3894 static const struct cparams {
3895         u16 i;
3896         u16 t;
3897         u16 m;
3898         u16 c;
3899 } cparams[] = {
3900         { 1, 1333, 301, 28664 },
3901         { 1, 1066, 294, 24460 },
3902         { 1, 800, 294, 25192 },
3903         { 0, 1333, 276, 27605 },
3904         { 0, 1066, 276, 27605 },
3905         { 0, 800, 231, 23784 },
3906 };
3907
3908 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
3909 {
3910         u64 total_count, diff, ret;
3911         u32 count1, count2, count3, m = 0, c = 0;
3912         unsigned long now = jiffies_to_msecs(jiffies), diff1;
3913         int i;
3914
3915         assert_spin_locked(&mchdev_lock);
3916
3917         diff1 = now - dev_priv->ips.last_time1;
3918
3919         /* Prevent division-by-zero if we are asking too fast.
3920          * Also, we don't get interesting results if we are polling
3921          * faster than once in 10ms, so just return the saved value
3922          * in such cases.
3923          */
3924         if (diff1 <= 10)
3925                 return dev_priv->ips.chipset_power;
3926
3927         count1 = I915_READ(DMIEC);
3928         count2 = I915_READ(DDREC);
3929         count3 = I915_READ(CSIEC);
3930
3931         total_count = count1 + count2 + count3;
3932
3933         /* FIXME: handle per-counter overflow */
3934         if (total_count < dev_priv->ips.last_count1) {
3935                 diff = ~0UL - dev_priv->ips.last_count1;
3936                 diff += total_count;
3937         } else {
3938                 diff = total_count - dev_priv->ips.last_count1;
3939         }
3940
3941         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
3942                 if (cparams[i].i == dev_priv->ips.c_m &&
3943                     cparams[i].t == dev_priv->ips.r_t) {
3944                         m = cparams[i].m;
3945                         c = cparams[i].c;
3946                         break;
3947                 }
3948         }
3949
3950         diff = div_u64(diff, diff1);
3951         ret = ((m * diff) + c);
3952         ret = div_u64(ret, 10);
3953
3954         dev_priv->ips.last_count1 = total_count;
3955         dev_priv->ips.last_time1 = now;
3956
3957         dev_priv->ips.chipset_power = ret;
3958
3959         return ret;
3960 }
3961
3962 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3963 {
3964         struct drm_device *dev = dev_priv->dev;
3965         unsigned long val;
3966
3967         if (INTEL_INFO(dev)->gen != 5)
3968                 return 0;
3969
3970         spin_lock_irq(&mchdev_lock);
3971
3972         val = __i915_chipset_val(dev_priv);
3973
3974         spin_unlock_irq(&mchdev_lock);
3975
3976         return val;
3977 }
3978
3979 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3980 {
3981         unsigned long m, x, b;
3982         u32 tsfs;
3983
3984         tsfs = I915_READ(TSFS);
3985
3986         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3987         x = I915_READ8(TR1);
3988
3989         b = tsfs & TSFS_INTR_MASK;
3990
3991         return ((m * x) / 127) - b;
3992 }
3993
3994 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3995 {
3996         struct drm_device *dev = dev_priv->dev;
3997         static const struct v_table {
3998                 u16 vd; /* in .1 mil */
3999                 u16 vm; /* in .1 mil */
4000         } v_table[] = {
4001                 { 0, 0, },
4002                 { 375, 0, },
4003                 { 500, 0, },
4004                 { 625, 0, },
4005                 { 750, 0, },
4006                 { 875, 0, },
4007                 { 1000, 0, },
4008                 { 1125, 0, },
4009                 { 4125, 3000, },
4010                 { 4125, 3000, },
4011                 { 4125, 3000, },
4012                 { 4125, 3000, },
4013                 { 4125, 3000, },
4014                 { 4125, 3000, },
4015                 { 4125, 3000, },
4016                 { 4125, 3000, },
4017                 { 4125, 3000, },
4018                 { 4125, 3000, },
4019                 { 4125, 3000, },
4020                 { 4125, 3000, },
4021                 { 4125, 3000, },
4022                 { 4125, 3000, },
4023                 { 4125, 3000, },
4024                 { 4125, 3000, },
4025                 { 4125, 3000, },
4026                 { 4125, 3000, },
4027                 { 4125, 3000, },
4028                 { 4125, 3000, },
4029                 { 4125, 3000, },
4030                 { 4125, 3000, },
4031                 { 4125, 3000, },
4032                 { 4125, 3000, },
4033                 { 4250, 3125, },
4034                 { 4375, 3250, },
4035                 { 4500, 3375, },
4036                 { 4625, 3500, },
4037                 { 4750, 3625, },
4038                 { 4875, 3750, },
4039                 { 5000, 3875, },
4040                 { 5125, 4000, },
4041                 { 5250, 4125, },
4042                 { 5375, 4250, },
4043                 { 5500, 4375, },
4044                 { 5625, 4500, },
4045                 { 5750, 4625, },
4046                 { 5875, 4750, },
4047                 { 6000, 4875, },
4048                 { 6125, 5000, },
4049                 { 6250, 5125, },
4050                 { 6375, 5250, },
4051                 { 6500, 5375, },
4052                 { 6625, 5500, },
4053                 { 6750, 5625, },
4054                 { 6875, 5750, },
4055                 { 7000, 5875, },
4056                 { 7125, 6000, },
4057                 { 7250, 6125, },
4058                 { 7375, 6250, },
4059                 { 7500, 6375, },
4060                 { 7625, 6500, },
4061                 { 7750, 6625, },
4062                 { 7875, 6750, },
4063                 { 8000, 6875, },
4064                 { 8125, 7000, },
4065                 { 8250, 7125, },
4066                 { 8375, 7250, },
4067                 { 8500, 7375, },
4068                 { 8625, 7500, },
4069                 { 8750, 7625, },
4070                 { 8875, 7750, },
4071                 { 9000, 7875, },
4072                 { 9125, 8000, },
4073                 { 9250, 8125, },
4074                 { 9375, 8250, },
4075                 { 9500, 8375, },
4076                 { 9625, 8500, },
4077                 { 9750, 8625, },
4078                 { 9875, 8750, },
4079                 { 10000, 8875, },
4080                 { 10125, 9000, },
4081                 { 10250, 9125, },
4082                 { 10375, 9250, },
4083                 { 10500, 9375, },
4084                 { 10625, 9500, },
4085                 { 10750, 9625, },
4086                 { 10875, 9750, },
4087                 { 11000, 9875, },
4088                 { 11125, 10000, },
4089                 { 11250, 10125, },
4090                 { 11375, 10250, },
4091                 { 11500, 10375, },
4092                 { 11625, 10500, },
4093                 { 11750, 10625, },
4094                 { 11875, 10750, },
4095                 { 12000, 10875, },
4096                 { 12125, 11000, },
4097                 { 12250, 11125, },
4098                 { 12375, 11250, },
4099                 { 12500, 11375, },
4100                 { 12625, 11500, },
4101                 { 12750, 11625, },
4102                 { 12875, 11750, },
4103                 { 13000, 11875, },
4104                 { 13125, 12000, },
4105                 { 13250, 12125, },
4106                 { 13375, 12250, },
4107                 { 13500, 12375, },
4108                 { 13625, 12500, },
4109                 { 13750, 12625, },
4110                 { 13875, 12750, },
4111                 { 14000, 12875, },
4112                 { 14125, 13000, },
4113                 { 14250, 13125, },
4114                 { 14375, 13250, },
4115                 { 14500, 13375, },
4116                 { 14625, 13500, },
4117                 { 14750, 13625, },
4118                 { 14875, 13750, },
4119                 { 15000, 13875, },
4120                 { 15125, 14000, },
4121                 { 15250, 14125, },
4122                 { 15375, 14250, },
4123                 { 15500, 14375, },
4124                 { 15625, 14500, },
4125                 { 15750, 14625, },
4126                 { 15875, 14750, },
4127                 { 16000, 14875, },
4128                 { 16125, 15000, },
4129         };
4130         if (INTEL_INFO(dev)->is_mobile)
4131                 return v_table[pxvid].vm;
4132         else
4133                 return v_table[pxvid].vd;
4134 }
4135
4136 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4137 {
4138         struct timespec now, diff1;
4139         u64 diff;
4140         unsigned long diffms;
4141         u32 count;
4142
4143         assert_spin_locked(&mchdev_lock);
4144
4145         getrawmonotonic(&now);
4146         diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4147
4148         /* Don't divide by 0 */
4149         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4150         if (!diffms)
4151                 return;
4152
4153         count = I915_READ(GFXEC);
4154
4155         if (count < dev_priv->ips.last_count2) {
4156                 diff = ~0UL - dev_priv->ips.last_count2;
4157                 diff += count;
4158         } else {
4159                 diff = count - dev_priv->ips.last_count2;
4160         }
4161
4162         dev_priv->ips.last_count2 = count;
4163         dev_priv->ips.last_time2 = now;
4164
4165         /* More magic constants... */
4166         diff = diff * 1181;
4167         diff = div_u64(diff, diffms * 10);
4168         dev_priv->ips.gfx_power = diff;
4169 }
4170
4171 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4172 {
4173         struct drm_device *dev = dev_priv->dev;
4174
4175         if (INTEL_INFO(dev)->gen != 5)
4176                 return;
4177
4178         spin_lock_irq(&mchdev_lock);
4179
4180         __i915_update_gfx_val(dev_priv);
4181
4182         spin_unlock_irq(&mchdev_lock);
4183 }
4184
4185 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4186 {
4187         unsigned long t, corr, state1, corr2, state2;
4188         u32 pxvid, ext_v;
4189
4190         assert_spin_locked(&mchdev_lock);
4191
4192         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
4193         pxvid = (pxvid >> 24) & 0x7f;
4194         ext_v = pvid_to_extvid(dev_priv, pxvid);
4195
4196         state1 = ext_v;
4197
4198         t = i915_mch_val(dev_priv);
4199
4200         /* Revel in the empirically derived constants */
4201
4202         /* Correction factor in 1/100000 units */
4203         if (t > 80)
4204                 corr = ((t * 2349) + 135940);
4205         else if (t >= 50)
4206                 corr = ((t * 964) + 29317);
4207         else /* < 50 */
4208                 corr = ((t * 301) + 1004);
4209
4210         corr = corr * ((150142 * state1) / 10000 - 78642);
4211         corr /= 100000;
4212         corr2 = (corr * dev_priv->ips.corr);
4213
4214         state2 = (corr2 * state1) / 10000;
4215         state2 /= 100; /* convert to mW */
4216
4217         __i915_update_gfx_val(dev_priv);
4218
4219         return dev_priv->ips.gfx_power + state2;
4220 }
4221
4222 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4223 {
4224         struct drm_device *dev = dev_priv->dev;
4225         unsigned long val;
4226
4227         if (INTEL_INFO(dev)->gen != 5)
4228                 return 0;
4229
4230         spin_lock_irq(&mchdev_lock);
4231
4232         val = __i915_gfx_val(dev_priv);
4233
4234         spin_unlock_irq(&mchdev_lock);
4235
4236         return val;
4237 }
4238
4239 /**
4240  * i915_read_mch_val - return value for IPS use
4241  *
4242  * Calculate and return a value for the IPS driver to use when deciding whether
4243  * we have thermal and power headroom to increase CPU or GPU power budget.
4244  */
4245 unsigned long i915_read_mch_val(void)
4246 {
4247         struct drm_i915_private *dev_priv;
4248         unsigned long chipset_val, graphics_val, ret = 0;
4249
4250         spin_lock_irq(&mchdev_lock);
4251         if (!i915_mch_dev)
4252                 goto out_unlock;
4253         dev_priv = i915_mch_dev;
4254
4255         chipset_val = __i915_chipset_val(dev_priv);
4256         graphics_val = __i915_gfx_val(dev_priv);
4257
4258         ret = chipset_val + graphics_val;
4259
4260 out_unlock:
4261         spin_unlock_irq(&mchdev_lock);
4262
4263         return ret;
4264 }
4265 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4266
4267 /**
4268  * i915_gpu_raise - raise GPU frequency limit
4269  *
4270  * Raise the limit; IPS indicates we have thermal headroom.
4271  */
4272 bool i915_gpu_raise(void)
4273 {
4274         struct drm_i915_private *dev_priv;
4275         bool ret = true;
4276
4277         spin_lock_irq(&mchdev_lock);
4278         if (!i915_mch_dev) {
4279                 ret = false;
4280                 goto out_unlock;
4281         }
4282         dev_priv = i915_mch_dev;
4283
4284         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4285                 dev_priv->ips.max_delay--;
4286
4287 out_unlock:
4288         spin_unlock_irq(&mchdev_lock);
4289
4290         return ret;
4291 }
4292 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4293
4294 /**
4295  * i915_gpu_lower - lower GPU frequency limit
4296  *
4297  * IPS indicates we're close to a thermal limit, so throttle back the GPU
4298  * frequency maximum.
4299  */
4300 bool i915_gpu_lower(void)
4301 {
4302         struct drm_i915_private *dev_priv;
4303         bool ret = true;
4304
4305         spin_lock_irq(&mchdev_lock);
4306         if (!i915_mch_dev) {
4307                 ret = false;
4308                 goto out_unlock;
4309         }
4310         dev_priv = i915_mch_dev;
4311
4312         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4313                 dev_priv->ips.max_delay++;
4314
4315 out_unlock:
4316         spin_unlock_irq(&mchdev_lock);
4317
4318         return ret;
4319 }
4320 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4321
4322 /**
4323  * i915_gpu_busy - indicate GPU business to IPS
4324  *
4325  * Tell the IPS driver whether or not the GPU is busy.
4326  */
4327 bool i915_gpu_busy(void)
4328 {
4329         struct drm_i915_private *dev_priv;
4330         struct intel_ring_buffer *ring;
4331         bool ret = false;
4332         int i;
4333
4334         spin_lock_irq(&mchdev_lock);
4335         if (!i915_mch_dev)
4336                 goto out_unlock;
4337         dev_priv = i915_mch_dev;
4338
4339         for_each_ring(ring, dev_priv, i)
4340                 ret |= !list_empty(&ring->request_list);
4341
4342 out_unlock:
4343         spin_unlock_irq(&mchdev_lock);
4344
4345         return ret;
4346 }
4347 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4348
4349 /**
4350  * i915_gpu_turbo_disable - disable graphics turbo
4351  *
4352  * Disable graphics turbo by resetting the max frequency and setting the
4353  * current frequency to the default.
4354  */
4355 bool i915_gpu_turbo_disable(void)
4356 {
4357         struct drm_i915_private *dev_priv;
4358         bool ret = true;
4359
4360         spin_lock_irq(&mchdev_lock);
4361         if (!i915_mch_dev) {
4362                 ret = false;
4363                 goto out_unlock;
4364         }
4365         dev_priv = i915_mch_dev;
4366
4367         dev_priv->ips.max_delay = dev_priv->ips.fstart;
4368
4369         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4370                 ret = false;
4371
4372 out_unlock:
4373         spin_unlock_irq(&mchdev_lock);
4374
4375         return ret;
4376 }
4377 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4378
4379 /**
4380  * Tells the intel_ips driver that the i915 driver is now loaded, if
4381  * IPS got loaded first.
4382  *
4383  * This awkward dance is so that neither module has to depend on the
4384  * other in order for IPS to do the appropriate communication of
4385  * GPU turbo limits to i915.
4386  */
4387 static void
4388 ips_ping_for_i915_load(void)
4389 {
4390         void (*link)(void);
4391
4392         link = symbol_get(ips_link_to_i915_driver);
4393         if (link) {
4394                 link();
4395                 symbol_put(ips_link_to_i915_driver);
4396         }
4397 }
4398
4399 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4400 {
4401         /* We only register the i915 ips part with intel-ips once everything is
4402          * set up, to avoid intel-ips sneaking in and reading bogus values. */
4403         spin_lock_irq(&mchdev_lock);
4404         i915_mch_dev = dev_priv;
4405         spin_unlock_irq(&mchdev_lock);
4406
4407         ips_ping_for_i915_load();
4408 }
4409
4410 void intel_gpu_ips_teardown(void)
4411 {
4412         spin_lock_irq(&mchdev_lock);
4413         i915_mch_dev = NULL;
4414         spin_unlock_irq(&mchdev_lock);
4415 }
4416
4417 static void intel_init_emon(struct drm_device *dev)
4418 {
4419         struct drm_i915_private *dev_priv = dev->dev_private;
4420         u32 lcfuse;
4421         u8 pxw[16];
4422         int i;
4423
4424         /* Disable to program */
4425         I915_WRITE(ECR, 0);
4426         POSTING_READ(ECR);
4427
4428         /* Program energy weights for various events */
4429         I915_WRITE(SDEW, 0x15040d00);
4430         I915_WRITE(CSIEW0, 0x007f0000);
4431         I915_WRITE(CSIEW1, 0x1e220004);
4432         I915_WRITE(CSIEW2, 0x04000004);
4433
4434         for (i = 0; i < 5; i++)
4435                 I915_WRITE(PEW + (i * 4), 0);
4436         for (i = 0; i < 3; i++)
4437                 I915_WRITE(DEW + (i * 4), 0);
4438
4439         /* Program P-state weights to account for frequency power adjustment */
4440         for (i = 0; i < 16; i++) {
4441                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4442                 unsigned long freq = intel_pxfreq(pxvidfreq);
4443                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4444                         PXVFREQ_PX_SHIFT;
4445                 unsigned long val;
4446
4447                 val = vid * vid;
4448                 val *= (freq / 1000);
4449                 val *= 255;
4450                 val /= (127*127*900);
4451                 if (val > 0xff)
4452                         DRM_ERROR("bad pxval: %ld\n", val);
4453                 pxw[i] = val;
4454         }
4455         /* Render standby states get 0 weight */
4456         pxw[14] = 0;
4457         pxw[15] = 0;
4458
4459         for (i = 0; i < 4; i++) {
4460                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4461                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4462                 I915_WRITE(PXW + (i * 4), val);
4463         }
4464
4465         /* Adjust magic regs to magic values (more experimental results) */
4466         I915_WRITE(OGW0, 0);
4467         I915_WRITE(OGW1, 0);
4468         I915_WRITE(EG0, 0x00007f00);
4469         I915_WRITE(EG1, 0x0000000e);
4470         I915_WRITE(EG2, 0x000e0000);
4471         I915_WRITE(EG3, 0x68000300);
4472         I915_WRITE(EG4, 0x42000000);
4473         I915_WRITE(EG5, 0x00140031);
4474         I915_WRITE(EG6, 0);
4475         I915_WRITE(EG7, 0);
4476
4477         for (i = 0; i < 8; i++)
4478                 I915_WRITE(PXWL + (i * 4), 0);
4479
4480         /* Enable PMON + select events */
4481         I915_WRITE(ECR, 0x80000019);
4482
4483         lcfuse = I915_READ(LCFUSE02);
4484
4485         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4486 }
4487
4488 void intel_init_gt_powersave(struct drm_device *dev)
4489 {
4490         if (IS_VALLEYVIEW(dev))
4491                 valleyview_setup_pctx(dev);
4492 }
4493
4494 void intel_cleanup_gt_powersave(struct drm_device *dev)
4495 {
4496         if (IS_VALLEYVIEW(dev))
4497                 valleyview_cleanup_pctx(dev);
4498 }
4499
4500 void intel_disable_gt_powersave(struct drm_device *dev)
4501 {
4502         struct drm_i915_private *dev_priv = dev->dev_private;
4503
4504         /* Interrupts should be disabled already to avoid re-arming. */
4505         WARN_ON(dev->irq_enabled);
4506
4507         if (IS_IRONLAKE_M(dev)) {
4508                 ironlake_disable_drps(dev);
4509                 ironlake_disable_rc6(dev);
4510         } else if (INTEL_INFO(dev)->gen >= 6) {
4511                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4512                 cancel_work_sync(&dev_priv->rps.work);
4513                 mutex_lock(&dev_priv->rps.hw_lock);
4514                 if (IS_VALLEYVIEW(dev))
4515                         valleyview_disable_rps(dev);
4516                 else
4517                         gen6_disable_rps(dev);
4518                 dev_priv->rps.enabled = false;
4519                 mutex_unlock(&dev_priv->rps.hw_lock);
4520         }
4521 }
4522
4523 static void intel_gen6_powersave_work(struct work_struct *work)
4524 {
4525         struct drm_i915_private *dev_priv =
4526                 container_of(work, struct drm_i915_private,
4527                              rps.delayed_resume_work.work);
4528         struct drm_device *dev = dev_priv->dev;
4529
4530         mutex_lock(&dev_priv->rps.hw_lock);
4531
4532         if (IS_VALLEYVIEW(dev)) {
4533                 valleyview_enable_rps(dev);
4534         } else if (IS_BROADWELL(dev)) {
4535                 gen8_enable_rps(dev);
4536                 gen6_update_ring_freq(dev);
4537         } else {
4538                 gen6_enable_rps(dev);
4539                 gen6_update_ring_freq(dev);
4540         }
4541         dev_priv->rps.enabled = true;
4542         mutex_unlock(&dev_priv->rps.hw_lock);
4543 }
4544
4545 void intel_enable_gt_powersave(struct drm_device *dev)
4546 {
4547         struct drm_i915_private *dev_priv = dev->dev_private;
4548
4549         if (IS_IRONLAKE_M(dev)) {
4550                 ironlake_enable_drps(dev);
4551                 ironlake_enable_rc6(dev);
4552                 intel_init_emon(dev);
4553         } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4554                 /*
4555                  * PCU communication is slow and this doesn't need to be
4556                  * done at any specific time, so do this out of our fast path
4557                  * to make resume and init faster.
4558                  */
4559                 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4560                                       round_jiffies_up_relative(HZ));
4561         }
4562 }
4563
4564 static void ibx_init_clock_gating(struct drm_device *dev)
4565 {
4566         struct drm_i915_private *dev_priv = dev->dev_private;
4567
4568         /*
4569          * On Ibex Peak and Cougar Point, we need to disable clock
4570          * gating for the panel power sequencer or it will fail to
4571          * start up when no ports are active.
4572          */
4573         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4574 }
4575
4576 static void g4x_disable_trickle_feed(struct drm_device *dev)
4577 {
4578         struct drm_i915_private *dev_priv = dev->dev_private;
4579         int pipe;
4580
4581         for_each_pipe(pipe) {
4582                 I915_WRITE(DSPCNTR(pipe),
4583                            I915_READ(DSPCNTR(pipe)) |
4584                            DISPPLANE_TRICKLE_FEED_DISABLE);
4585                 intel_flush_primary_plane(dev_priv, pipe);
4586         }
4587 }
4588
4589 static void ilk_init_lp_watermarks(struct drm_device *dev)
4590 {
4591         struct drm_i915_private *dev_priv = dev->dev_private;
4592
4593         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
4594         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
4595         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
4596
4597         /*
4598          * Don't touch WM1S_LP_EN here.
4599          * Doing so could cause underruns.
4600          */
4601 }
4602
4603 static void ironlake_init_clock_gating(struct drm_device *dev)
4604 {
4605         struct drm_i915_private *dev_priv = dev->dev_private;
4606         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4607
4608         /*
4609          * Required for FBC
4610          * WaFbcDisableDpfcClockGating:ilk
4611          */
4612         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4613                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4614                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4615
4616         I915_WRITE(PCH_3DCGDIS0,
4617                    MARIUNIT_CLOCK_GATE_DISABLE |
4618                    SVSMUNIT_CLOCK_GATE_DISABLE);
4619         I915_WRITE(PCH_3DCGDIS1,
4620                    VFMUNIT_CLOCK_GATE_DISABLE);
4621
4622         /*
4623          * According to the spec the following bits should be set in
4624          * order to enable memory self-refresh
4625          * The bit 22/21 of 0x42004
4626          * The bit 5 of 0x42020
4627          * The bit 15 of 0x45000
4628          */
4629         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4630                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
4631                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4632         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
4633         I915_WRITE(DISP_ARB_CTL,
4634                    (I915_READ(DISP_ARB_CTL) |
4635                     DISP_FBC_WM_DIS));
4636
4637         ilk_init_lp_watermarks(dev);
4638
4639         /*
4640          * Based on the document from hardware guys the following bits
4641          * should be set unconditionally in order to enable FBC.
4642          * The bit 22 of 0x42000
4643          * The bit 22 of 0x42004
4644          * The bit 7,8,9 of 0x42020.
4645          */
4646         if (IS_IRONLAKE_M(dev)) {
4647                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
4648                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4649                            I915_READ(ILK_DISPLAY_CHICKEN1) |
4650                            ILK_FBCQ_DIS);
4651                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4652                            I915_READ(ILK_DISPLAY_CHICKEN2) |
4653                            ILK_DPARB_GATE);
4654         }
4655
4656         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4657
4658         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4659                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4660                    ILK_ELPIN_409_SELECT);
4661         I915_WRITE(_3D_CHICKEN2,
4662                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4663                    _3D_CHICKEN2_WM_READ_PIPELINED);
4664
4665         /* WaDisableRenderCachePipelinedFlush:ilk */
4666         I915_WRITE(CACHE_MODE_0,
4667                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4668
4669         g4x_disable_trickle_feed(dev);
4670
4671         ibx_init_clock_gating(dev);
4672 }
4673
4674 static void cpt_init_clock_gating(struct drm_device *dev)
4675 {
4676         struct drm_i915_private *dev_priv = dev->dev_private;
4677         int pipe;
4678         uint32_t val;
4679
4680         /*
4681          * On Ibex Peak and Cougar Point, we need to disable clock
4682          * gating for the panel power sequencer or it will fail to
4683          * start up when no ports are active.
4684          */
4685         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
4686                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
4687                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
4688         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4689                    DPLS_EDP_PPS_FIX_DIS);
4690         /* The below fixes the weird display corruption, a few pixels shifted
4691          * downward, on (only) LVDS of some HP laptops with IVY.
4692          */
4693         for_each_pipe(pipe) {
4694                 val = I915_READ(TRANS_CHICKEN2(pipe));
4695                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4696                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4697                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
4698                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4699                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4700                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4701                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
4702                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4703         }
4704         /* WADP0ClockGatingDisable */
4705         for_each_pipe(pipe) {
4706                 I915_WRITE(TRANS_CHICKEN1(pipe),
4707                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4708         }
4709 }
4710
4711 static void gen6_check_mch_setup(struct drm_device *dev)
4712 {
4713         struct drm_i915_private *dev_priv = dev->dev_private;
4714         uint32_t tmp;
4715
4716         tmp = I915_READ(MCH_SSKPD);
4717         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4718                 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4719                 DRM_INFO("This can cause pipe underruns and display issues.\n");
4720                 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4721         }
4722 }
4723
4724 static void gen6_init_clock_gating(struct drm_device *dev)
4725 {
4726         struct drm_i915_private *dev_priv = dev->dev_private;
4727         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4728
4729         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4730
4731         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4732                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4733                    ILK_ELPIN_409_SELECT);
4734
4735         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4736         I915_WRITE(_3D_CHICKEN,
4737                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4738
4739         /* WaSetupGtModeTdRowDispatch:snb */
4740         if (IS_SNB_GT1(dev))
4741                 I915_WRITE(GEN6_GT_MODE,
4742                            _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4743
4744         /*
4745          * BSpec recoomends 8x4 when MSAA is used,
4746          * however in practice 16x4 seems fastest.
4747          *
4748          * Note that PS/WM thread counts depend on the WIZ hashing
4749          * disable bit, which we don't touch here, but it's good
4750          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
4751          */
4752         I915_WRITE(GEN6_GT_MODE,
4753                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
4754
4755         ilk_init_lp_watermarks(dev);
4756
4757         I915_WRITE(CACHE_MODE_0,
4758                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
4759
4760         I915_WRITE(GEN6_UCGCTL1,
4761                    I915_READ(GEN6_UCGCTL1) |
4762                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4763                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4764
4765         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4766          * gating disable must be set.  Failure to set it results in
4767          * flickering pixels due to Z write ordering failures after
4768          * some amount of runtime in the Mesa "fire" demo, and Unigine
4769          * Sanctuary and Tropics, and apparently anything else with
4770          * alpha test or pixel discard.
4771          *
4772          * According to the spec, bit 11 (RCCUNIT) must also be set,
4773          * but we didn't debug actual testcases to find it out.
4774          *
4775          * WaDisableRCCUnitClockGating:snb
4776          * WaDisableRCPBUnitClockGating:snb
4777          */
4778         I915_WRITE(GEN6_UCGCTL2,
4779                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4780                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4781
4782         /* WaStripsFansDisableFastClipPerformanceFix:snb */
4783         I915_WRITE(_3D_CHICKEN3,
4784                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
4785
4786         /*
4787          * Bspec says:
4788          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
4789          * 3DSTATE_SF number of SF output attributes is more than 16."
4790          */
4791         I915_WRITE(_3D_CHICKEN3,
4792                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
4793
4794         /*
4795          * According to the spec the following bits should be
4796          * set in order to enable memory self-refresh and fbc:
4797          * The bit21 and bit22 of 0x42000
4798          * The bit21 and bit22 of 0x42004
4799          * The bit5 and bit7 of 0x42020
4800          * The bit14 of 0x70180
4801          * The bit14 of 0x71180
4802          *
4803          * WaFbcAsynchFlipDisableFbcQueue:snb
4804          */
4805         I915_WRITE(ILK_DISPLAY_CHICKEN1,
4806                    I915_READ(ILK_DISPLAY_CHICKEN1) |
4807                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4808         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4809                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4810                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
4811         I915_WRITE(ILK_DSPCLK_GATE_D,
4812                    I915_READ(ILK_DSPCLK_GATE_D) |
4813                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
4814                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
4815
4816         g4x_disable_trickle_feed(dev);
4817
4818         cpt_init_clock_gating(dev);
4819
4820         gen6_check_mch_setup(dev);
4821 }
4822
4823 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4824 {
4825         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4826
4827         /*
4828          * WaVSThreadDispatchOverride:ivb,vlv
4829          *
4830          * This actually overrides the dispatch
4831          * mode for all thread types.
4832          */
4833         reg &= ~GEN7_FF_SCHED_MASK;
4834         reg |= GEN7_FF_TS_SCHED_HW;
4835         reg |= GEN7_FF_VS_SCHED_HW;
4836         reg |= GEN7_FF_DS_SCHED_HW;
4837
4838         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4839 }
4840
4841 static void lpt_init_clock_gating(struct drm_device *dev)
4842 {
4843         struct drm_i915_private *dev_priv = dev->dev_private;
4844
4845         /*
4846          * TODO: this bit should only be enabled when really needed, then
4847          * disabled when not needed anymore in order to save power.
4848          */
4849         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4850                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4851                            I915_READ(SOUTH_DSPCLK_GATE_D) |
4852                            PCH_LP_PARTITION_LEVEL_DISABLE);
4853
4854         /* WADPOClockGatingDisable:hsw */
4855         I915_WRITE(_TRANSA_CHICKEN1,
4856                    I915_READ(_TRANSA_CHICKEN1) |
4857                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4858 }
4859
4860 static void lpt_suspend_hw(struct drm_device *dev)
4861 {
4862         struct drm_i915_private *dev_priv = dev->dev_private;
4863
4864         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4865                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4866
4867                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4868                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4869         }
4870 }
4871
4872 static void gen8_init_clock_gating(struct drm_device *dev)
4873 {
4874         struct drm_i915_private *dev_priv = dev->dev_private;
4875         enum pipe pipe;
4876
4877         I915_WRITE(WM3_LP_ILK, 0);
4878         I915_WRITE(WM2_LP_ILK, 0);
4879         I915_WRITE(WM1_LP_ILK, 0);
4880
4881         /* FIXME(BDW): Check all the w/a, some might only apply to
4882          * pre-production hw. */
4883
4884         /* WaDisablePartialInstShootdown:bdw */
4885         I915_WRITE(GEN8_ROW_CHICKEN,
4886                    _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
4887
4888         /* WaDisableThreadStallDopClockGating:bdw */
4889         /* FIXME: Unclear whether we really need this on production bdw. */
4890         I915_WRITE(GEN8_ROW_CHICKEN,
4891                    _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
4892
4893         /*
4894          * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
4895          * pre-production hardware
4896          */
4897         I915_WRITE(HALF_SLICE_CHICKEN3,
4898                    _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
4899         I915_WRITE(HALF_SLICE_CHICKEN3,
4900                    _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
4901         I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
4902
4903         I915_WRITE(_3D_CHICKEN3,
4904                    _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
4905
4906         I915_WRITE(COMMON_SLICE_CHICKEN2,
4907                    _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
4908
4909         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4910                    _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
4911
4912         /* WaSwitchSolVfFArbitrationPriority:bdw */
4913         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4914
4915         /* WaPsrDPAMaskVBlankInSRD:bdw */
4916         I915_WRITE(CHICKEN_PAR1_1,
4917                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
4918
4919         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
4920         for_each_pipe(pipe) {
4921                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
4922                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
4923                            BDW_DPRS_MASK_VBLANK_SRD);
4924         }
4925
4926         /* Use Force Non-Coherent whenever executing a 3D context. This is a
4927          * workaround for for a possible hang in the unlikely event a TLB
4928          * invalidation occurs during a PSD flush.
4929          */
4930         I915_WRITE(HDC_CHICKEN0,
4931                    I915_READ(HDC_CHICKEN0) |
4932                    _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
4933
4934         /* WaVSRefCountFullforceMissDisable:bdw */
4935         /* WaDSRefCountFullforceMissDisable:bdw */
4936         I915_WRITE(GEN7_FF_THREAD_MODE,
4937                    I915_READ(GEN7_FF_THREAD_MODE) &
4938                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
4939
4940         /*
4941          * BSpec recommends 8x4 when MSAA is used,
4942          * however in practice 16x4 seems fastest.
4943          *
4944          * Note that PS/WM thread counts depend on the WIZ hashing
4945          * disable bit, which we don't touch here, but it's good
4946          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
4947          */
4948         I915_WRITE(GEN7_GT_MODE,
4949                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
4950
4951         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
4952                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4953
4954         /* WaDisableSDEUnitClockGating:bdw */
4955         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
4956                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
4957
4958         /* Wa4x4STCOptimizationDisable:bdw */
4959         I915_WRITE(CACHE_MODE_1,
4960                    _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
4961 }
4962
4963 static void haswell_init_clock_gating(struct drm_device *dev)
4964 {
4965         struct drm_i915_private *dev_priv = dev->dev_private;
4966
4967         ilk_init_lp_watermarks(dev);
4968
4969         /* L3 caching of data atomics doesn't work -- disable it. */
4970         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
4971         I915_WRITE(HSW_ROW_CHICKEN3,
4972                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
4973
4974         /* This is required by WaCatErrorRejectionIssue:hsw */
4975         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4976                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4977                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4978
4979         /* WaVSRefCountFullforceMissDisable:hsw */
4980         I915_WRITE(GEN7_FF_THREAD_MODE,
4981                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
4982
4983         /* enable HiZ Raw Stall Optimization */
4984         I915_WRITE(CACHE_MODE_0_GEN7,
4985                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
4986
4987         /* WaDisable4x2SubspanOptimization:hsw */
4988         I915_WRITE(CACHE_MODE_1,
4989                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4990
4991         /*
4992          * BSpec recommends 8x4 when MSAA is used,
4993          * however in practice 16x4 seems fastest.
4994          *
4995          * Note that PS/WM thread counts depend on the WIZ hashing
4996          * disable bit, which we don't touch here, but it's good
4997          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
4998          */
4999         I915_WRITE(GEN7_GT_MODE,
5000                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5001
5002         /* WaSwitchSolVfFArbitrationPriority:hsw */
5003         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5004
5005         /* WaRsPkgCStateDisplayPMReq:hsw */
5006         I915_WRITE(CHICKEN_PAR1_1,
5007                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5008
5009         lpt_init_clock_gating(dev);
5010 }
5011
5012 static void ivybridge_init_clock_gating(struct drm_device *dev)
5013 {
5014         struct drm_i915_private *dev_priv = dev->dev_private;
5015         uint32_t snpcr;
5016
5017         ilk_init_lp_watermarks(dev);
5018
5019         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5020
5021         /* WaDisableEarlyCull:ivb */
5022         I915_WRITE(_3D_CHICKEN3,
5023                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5024
5025         /* WaDisableBackToBackFlipFix:ivb */
5026         I915_WRITE(IVB_CHICKEN3,
5027                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5028                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5029
5030         /* WaDisablePSDDualDispatchEnable:ivb */
5031         if (IS_IVB_GT1(dev))
5032                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5033                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5034
5035         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5036         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5037                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5038
5039         /* WaApplyL3ControlAndL3ChickenMode:ivb */
5040         I915_WRITE(GEN7_L3CNTLREG1,
5041                         GEN7_WA_FOR_GEN7_L3_CONTROL);
5042         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5043                    GEN7_WA_L3_CHICKEN_MODE);
5044         if (IS_IVB_GT1(dev))
5045                 I915_WRITE(GEN7_ROW_CHICKEN2,
5046                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5047         else {
5048                 /* must write both registers */
5049                 I915_WRITE(GEN7_ROW_CHICKEN2,
5050                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5051                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5052                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5053         }
5054
5055         /* WaForceL3Serialization:ivb */
5056         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5057                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5058
5059         /*
5060          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5061          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5062          */
5063         I915_WRITE(GEN6_UCGCTL2,
5064                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5065
5066         /* This is required by WaCatErrorRejectionIssue:ivb */
5067         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5068                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5069                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5070
5071         g4x_disable_trickle_feed(dev);
5072
5073         gen7_setup_fixed_func_scheduler(dev_priv);
5074
5075         if (0) { /* causes HiZ corruption on ivb:gt1 */
5076                 /* enable HiZ Raw Stall Optimization */
5077                 I915_WRITE(CACHE_MODE_0_GEN7,
5078                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5079         }
5080
5081         /* WaDisable4x2SubspanOptimization:ivb */
5082         I915_WRITE(CACHE_MODE_1,
5083                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5084
5085         /*
5086          * BSpec recommends 8x4 when MSAA is used,
5087          * however in practice 16x4 seems fastest.
5088          *
5089          * Note that PS/WM thread counts depend on the WIZ hashing
5090          * disable bit, which we don't touch here, but it's good
5091          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5092          */
5093         I915_WRITE(GEN7_GT_MODE,
5094                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5095
5096         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5097         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5098         snpcr |= GEN6_MBC_SNPCR_MED;
5099         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5100
5101         if (!HAS_PCH_NOP(dev))
5102                 cpt_init_clock_gating(dev);
5103
5104         gen6_check_mch_setup(dev);
5105 }
5106
5107 static void valleyview_init_clock_gating(struct drm_device *dev)
5108 {
5109         struct drm_i915_private *dev_priv = dev->dev_private;
5110         u32 val;
5111
5112         mutex_lock(&dev_priv->rps.hw_lock);
5113         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5114         mutex_unlock(&dev_priv->rps.hw_lock);
5115         switch ((val >> 6) & 3) {
5116         case 0:
5117         case 1:
5118                 dev_priv->mem_freq = 800;
5119                 break;
5120         case 2:
5121                 dev_priv->mem_freq = 1066;
5122                 break;
5123         case 3:
5124                 dev_priv->mem_freq = 1333;
5125                 break;
5126         }
5127         DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5128
5129         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5130
5131         /* WaDisableEarlyCull:vlv */
5132         I915_WRITE(_3D_CHICKEN3,
5133                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5134
5135         /* WaDisableBackToBackFlipFix:vlv */
5136         I915_WRITE(IVB_CHICKEN3,
5137                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5138                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5139
5140         /* WaPsdDispatchEnable:vlv */
5141         /* WaDisablePSDDualDispatchEnable:vlv */
5142         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5143                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5144                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5145
5146         /* WaForceL3Serialization:vlv */
5147         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5148                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5149
5150         /* WaDisableDopClockGating:vlv */
5151         I915_WRITE(GEN7_ROW_CHICKEN2,
5152                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5153
5154         /* This is required by WaCatErrorRejectionIssue:vlv */
5155         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5156                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5157                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5158
5159         gen7_setup_fixed_func_scheduler(dev_priv);
5160
5161         /*
5162          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5163          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5164          */
5165         I915_WRITE(GEN6_UCGCTL2,
5166                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5167
5168         /* WaDisableL3Bank2xClockGate:vlv */
5169         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5170
5171         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5172
5173         /*
5174          * BSpec says this must be set, even though
5175          * WaDisable4x2SubspanOptimization isn't listed for VLV.
5176          */
5177         I915_WRITE(CACHE_MODE_1,
5178                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5179
5180         /*
5181          * WaIncreaseL3CreditsForVLVB0:vlv
5182          * This is the hardware default actually.
5183          */
5184         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5185
5186         /*
5187          * WaDisableVLVClockGating_VBIIssue:vlv
5188          * Disable clock gating on th GCFG unit to prevent a delay
5189          * in the reporting of vblank events.
5190          */
5191         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
5192 }
5193
5194 static void g4x_init_clock_gating(struct drm_device *dev)
5195 {
5196         struct drm_i915_private *dev_priv = dev->dev_private;
5197         uint32_t dspclk_gate;
5198
5199         I915_WRITE(RENCLK_GATE_D1, 0);
5200         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5201                    GS_UNIT_CLOCK_GATE_DISABLE |
5202                    CL_UNIT_CLOCK_GATE_DISABLE);
5203         I915_WRITE(RAMCLK_GATE_D, 0);
5204         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5205                 OVRUNIT_CLOCK_GATE_DISABLE |
5206                 OVCUNIT_CLOCK_GATE_DISABLE;
5207         if (IS_GM45(dev))
5208                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5209         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5210
5211         /* WaDisableRenderCachePipelinedFlush */
5212         I915_WRITE(CACHE_MODE_0,
5213                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5214
5215         g4x_disable_trickle_feed(dev);
5216 }
5217
5218 static void crestline_init_clock_gating(struct drm_device *dev)
5219 {
5220         struct drm_i915_private *dev_priv = dev->dev_private;
5221
5222         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5223         I915_WRITE(RENCLK_GATE_D2, 0);
5224         I915_WRITE(DSPCLK_GATE_D, 0);
5225         I915_WRITE(RAMCLK_GATE_D, 0);
5226         I915_WRITE16(DEUC, 0);
5227         I915_WRITE(MI_ARB_STATE,
5228                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5229 }
5230
5231 static void broadwater_init_clock_gating(struct drm_device *dev)
5232 {
5233         struct drm_i915_private *dev_priv = dev->dev_private;
5234
5235         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5236                    I965_RCC_CLOCK_GATE_DISABLE |
5237                    I965_RCPB_CLOCK_GATE_DISABLE |
5238                    I965_ISC_CLOCK_GATE_DISABLE |
5239                    I965_FBC_CLOCK_GATE_DISABLE);
5240         I915_WRITE(RENCLK_GATE_D2, 0);
5241         I915_WRITE(MI_ARB_STATE,
5242                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5243 }
5244
5245 static void gen3_init_clock_gating(struct drm_device *dev)
5246 {
5247         struct drm_i915_private *dev_priv = dev->dev_private;
5248         u32 dstate = I915_READ(D_STATE);
5249
5250         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5251                 DSTATE_DOT_CLOCK_GATING;
5252         I915_WRITE(D_STATE, dstate);
5253
5254         if (IS_PINEVIEW(dev))
5255                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5256
5257         /* IIR "flip pending" means done if this bit is set */
5258         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5259 }
5260
5261 static void i85x_init_clock_gating(struct drm_device *dev)
5262 {
5263         struct drm_i915_private *dev_priv = dev->dev_private;
5264
5265         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5266 }
5267
5268 static void i830_init_clock_gating(struct drm_device *dev)
5269 {
5270         struct drm_i915_private *dev_priv = dev->dev_private;
5271
5272         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5273 }
5274
5275 void intel_init_clock_gating(struct drm_device *dev)
5276 {
5277         struct drm_i915_private *dev_priv = dev->dev_private;
5278
5279         dev_priv->display.init_clock_gating(dev);
5280 }
5281
5282 void intel_suspend_hw(struct drm_device *dev)
5283 {
5284         if (HAS_PCH_LPT(dev))
5285                 lpt_suspend_hw(dev);
5286 }
5287
5288 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
5289         for (i = 0;                                                     \
5290              i < (power_domains)->power_well_count &&                   \
5291                  ((power_well) = &(power_domains)->power_wells[i]);     \
5292              i++)                                                       \
5293                 if ((power_well)->domains & (domain_mask))
5294
5295 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5296         for (i = (power_domains)->power_well_count - 1;                  \
5297              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5298              i--)                                                        \
5299                 if ((power_well)->domains & (domain_mask))
5300
5301 /**
5302  * We should only use the power well if we explicitly asked the hardware to
5303  * enable it, so check if it's enabled and also check if we've requested it to
5304  * be enabled.
5305  */
5306 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
5307                                    struct i915_power_well *power_well)
5308 {
5309         return I915_READ(HSW_PWR_WELL_DRIVER) ==
5310                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5311 }
5312
5313 bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
5314                                     enum intel_display_power_domain domain)
5315 {
5316         struct i915_power_domains *power_domains;
5317
5318         power_domains = &dev_priv->power_domains;
5319
5320         return power_domains->domain_use_count[domain];
5321 }
5322
5323 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
5324                                  enum intel_display_power_domain domain)
5325 {
5326         struct i915_power_domains *power_domains;
5327         struct i915_power_well *power_well;
5328         bool is_enabled;
5329         int i;
5330
5331         if (dev_priv->pm.suspended)
5332                 return false;
5333
5334         power_domains = &dev_priv->power_domains;
5335
5336         is_enabled = true;
5337
5338         mutex_lock(&power_domains->lock);
5339         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5340                 if (power_well->always_on)
5341                         continue;
5342
5343                 if (!power_well->ops->is_enabled(dev_priv, power_well)) {
5344                         is_enabled = false;
5345                         break;
5346                 }
5347         }
5348         mutex_unlock(&power_domains->lock);
5349
5350         return is_enabled;
5351 }
5352
5353 /*
5354  * Starting with Haswell, we have a "Power Down Well" that can be turned off
5355  * when not needed anymore. We have 4 registers that can request the power well
5356  * to be enabled, and it will only be disabled if none of the registers is
5357  * requesting it to be enabled.
5358  */
5359 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5360 {
5361         struct drm_device *dev = dev_priv->dev;
5362         unsigned long irqflags;
5363
5364         /*
5365          * After we re-enable the power well, if we touch VGA register 0x3d5
5366          * we'll get unclaimed register interrupts. This stops after we write
5367          * anything to the VGA MSR register. The vgacon module uses this
5368          * register all the time, so if we unbind our driver and, as a
5369          * consequence, bind vgacon, we'll get stuck in an infinite loop at
5370          * console_unlock(). So make here we touch the VGA MSR register, making
5371          * sure vgacon can keep working normally without triggering interrupts
5372          * and error messages.
5373          */
5374         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5375         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5376         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5377
5378         if (IS_BROADWELL(dev)) {
5379                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5380                 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5381                            dev_priv->de_irq_mask[PIPE_B]);
5382                 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5383                            ~dev_priv->de_irq_mask[PIPE_B] |
5384                            GEN8_PIPE_VBLANK);
5385                 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5386                            dev_priv->de_irq_mask[PIPE_C]);
5387                 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5388                            ~dev_priv->de_irq_mask[PIPE_C] |
5389                            GEN8_PIPE_VBLANK);
5390                 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5391                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5392         }
5393 }
5394
5395 static void reset_vblank_counter(struct drm_device *dev, enum pipe pipe)
5396 {
5397         assert_spin_locked(&dev->vbl_lock);
5398
5399         dev->vblank[pipe].last = 0;
5400 }
5401
5402 static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv)
5403 {
5404         struct drm_device *dev = dev_priv->dev;
5405         enum pipe pipe;
5406         unsigned long irqflags;
5407
5408         /*
5409          * After this, the registers on the pipes that are part of the power
5410          * well will become zero, so we have to adjust our counters according to
5411          * that.
5412          *
5413          * FIXME: Should we do this in general in drm_vblank_post_modeset?
5414          */
5415         spin_lock_irqsave(&dev->vbl_lock, irqflags);
5416         for_each_pipe(pipe)
5417                 if (pipe != PIPE_A)
5418                         reset_vblank_counter(dev, pipe);
5419         spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5420 }
5421
5422 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
5423                                struct i915_power_well *power_well, bool enable)
5424 {
5425         bool is_enabled, enable_requested;
5426         uint32_t tmp;
5427
5428         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5429         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5430         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5431
5432         if (enable) {
5433                 if (!enable_requested)
5434                         I915_WRITE(HSW_PWR_WELL_DRIVER,
5435                                    HSW_PWR_WELL_ENABLE_REQUEST);
5436
5437                 if (!is_enabled) {
5438                         DRM_DEBUG_KMS("Enabling power well\n");
5439                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5440                                       HSW_PWR_WELL_STATE_ENABLED), 20))
5441                                 DRM_ERROR("Timeout enabling power well\n");
5442                 }
5443
5444                 hsw_power_well_post_enable(dev_priv);
5445         } else {
5446                 if (enable_requested) {
5447                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5448                         POSTING_READ(HSW_PWR_WELL_DRIVER);
5449                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
5450
5451                         hsw_power_well_post_disable(dev_priv);
5452                 }
5453         }
5454 }
5455
5456 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
5457                                    struct i915_power_well *power_well)
5458 {
5459         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
5460
5461         /*
5462          * We're taking over the BIOS, so clear any requests made by it since
5463          * the driver is in charge now.
5464          */
5465         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5466                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5467 }
5468
5469 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
5470                                   struct i915_power_well *power_well)
5471 {
5472         hsw_set_power_well(dev_priv, power_well, true);
5473 }
5474
5475 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
5476                                    struct i915_power_well *power_well)
5477 {
5478         hsw_set_power_well(dev_priv, power_well, false);
5479 }
5480
5481 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
5482                                            struct i915_power_well *power_well)
5483 {
5484 }
5485
5486 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
5487                                              struct i915_power_well *power_well)
5488 {
5489         return true;
5490 }
5491
5492 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
5493                                struct i915_power_well *power_well, bool enable)
5494 {
5495         enum punit_power_well power_well_id = power_well->data;
5496         u32 mask;
5497         u32 state;
5498         u32 ctrl;
5499
5500         mask = PUNIT_PWRGT_MASK(power_well_id);
5501         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
5502                          PUNIT_PWRGT_PWR_GATE(power_well_id);
5503
5504         mutex_lock(&dev_priv->rps.hw_lock);
5505
5506 #define COND \
5507         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
5508
5509         if (COND)
5510                 goto out;
5511
5512         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
5513         ctrl &= ~mask;
5514         ctrl |= state;
5515         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
5516
5517         if (wait_for(COND, 100))
5518                 DRM_ERROR("timout setting power well state %08x (%08x)\n",
5519                           state,
5520                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
5521
5522 #undef COND
5523
5524 out:
5525         mutex_unlock(&dev_priv->rps.hw_lock);
5526 }
5527
5528 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
5529                                    struct i915_power_well *power_well)
5530 {
5531         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
5532 }
5533
5534 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
5535                                   struct i915_power_well *power_well)
5536 {
5537         vlv_set_power_well(dev_priv, power_well, true);
5538 }
5539
5540 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
5541                                    struct i915_power_well *power_well)
5542 {
5543         vlv_set_power_well(dev_priv, power_well, false);
5544 }
5545
5546 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
5547                                    struct i915_power_well *power_well)
5548 {
5549         int power_well_id = power_well->data;
5550         bool enabled = false;
5551         u32 mask;
5552         u32 state;
5553         u32 ctrl;
5554
5555         mask = PUNIT_PWRGT_MASK(power_well_id);
5556         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
5557
5558         mutex_lock(&dev_priv->rps.hw_lock);
5559
5560         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
5561         /*
5562          * We only ever set the power-on and power-gate states, anything
5563          * else is unexpected.
5564          */
5565         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
5566                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
5567         if (state == ctrl)
5568                 enabled = true;
5569
5570         /*
5571          * A transient state at this point would mean some unexpected party
5572          * is poking at the power controls too.
5573          */
5574         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
5575         WARN_ON(ctrl != state);
5576
5577         mutex_unlock(&dev_priv->rps.hw_lock);
5578
5579         return enabled;
5580 }
5581
5582 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
5583                                           struct i915_power_well *power_well)
5584 {
5585         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
5586
5587         vlv_set_power_well(dev_priv, power_well, true);
5588
5589         spin_lock_irq(&dev_priv->irq_lock);
5590         valleyview_enable_display_irqs(dev_priv);
5591         spin_unlock_irq(&dev_priv->irq_lock);
5592
5593         /*
5594          * During driver initialization we need to defer enabling hotplug
5595          * processing until fbdev is set up.
5596          */
5597         if (dev_priv->enable_hotplug_processing)
5598                 intel_hpd_init(dev_priv->dev);
5599
5600         i915_redisable_vga_power_on(dev_priv->dev);
5601 }
5602
5603 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
5604                                            struct i915_power_well *power_well)
5605 {
5606         struct drm_device *dev = dev_priv->dev;
5607         enum pipe pipe;
5608
5609         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
5610
5611         spin_lock_irq(&dev_priv->irq_lock);
5612         for_each_pipe(pipe)
5613                 __intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
5614
5615         valleyview_disable_display_irqs(dev_priv);
5616         spin_unlock_irq(&dev_priv->irq_lock);
5617
5618         spin_lock_irq(&dev->vbl_lock);
5619         for_each_pipe(pipe)
5620                 reset_vblank_counter(dev, pipe);
5621         spin_unlock_irq(&dev->vbl_lock);
5622
5623         vlv_set_power_well(dev_priv, power_well, false);
5624 }
5625
5626 static void check_power_well_state(struct drm_i915_private *dev_priv,
5627                                    struct i915_power_well *power_well)
5628 {
5629         bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
5630
5631         if (power_well->always_on || !i915.disable_power_well) {
5632                 if (!enabled)
5633                         goto mismatch;
5634
5635                 return;
5636         }
5637
5638         if (enabled != (power_well->count > 0))
5639                 goto mismatch;
5640
5641         return;
5642
5643 mismatch:
5644         WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
5645                   power_well->name, power_well->always_on, enabled,
5646                   power_well->count, i915.disable_power_well);
5647 }
5648
5649 void intel_display_power_get(struct drm_i915_private *dev_priv,
5650                              enum intel_display_power_domain domain)
5651 {
5652         struct i915_power_domains *power_domains;
5653         struct i915_power_well *power_well;
5654         int i;
5655
5656         intel_runtime_pm_get(dev_priv);
5657
5658         power_domains = &dev_priv->power_domains;
5659
5660         mutex_lock(&power_domains->lock);
5661
5662         for_each_power_well(i, power_well, BIT(domain), power_domains) {
5663                 if (!power_well->count++) {
5664                         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
5665                         power_well->ops->enable(dev_priv, power_well);
5666                 }
5667
5668                 check_power_well_state(dev_priv, power_well);
5669         }
5670
5671         power_domains->domain_use_count[domain]++;
5672
5673         mutex_unlock(&power_domains->lock);
5674 }
5675
5676 void intel_display_power_put(struct drm_i915_private *dev_priv,
5677                              enum intel_display_power_domain domain)
5678 {
5679         struct i915_power_domains *power_domains;
5680         struct i915_power_well *power_well;
5681         int i;
5682
5683         power_domains = &dev_priv->power_domains;
5684
5685         mutex_lock(&power_domains->lock);
5686
5687         WARN_ON(!power_domains->domain_use_count[domain]);
5688         power_domains->domain_use_count[domain]--;
5689
5690         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5691                 WARN_ON(!power_well->count);
5692
5693                 if (!--power_well->count && i915.disable_power_well) {
5694                         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
5695                         power_well->ops->disable(dev_priv, power_well);
5696                 }
5697
5698                 check_power_well_state(dev_priv, power_well);
5699         }
5700
5701         mutex_unlock(&power_domains->lock);
5702
5703         intel_runtime_pm_put(dev_priv);
5704 }
5705
5706 static struct i915_power_domains *hsw_pwr;
5707
5708 /* Display audio driver power well request */
5709 void i915_request_power_well(void)
5710 {
5711         struct drm_i915_private *dev_priv;
5712
5713         if (WARN_ON(!hsw_pwr))
5714                 return;
5715
5716         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5717                                 power_domains);
5718         intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
5719 }
5720 EXPORT_SYMBOL_GPL(i915_request_power_well);
5721
5722 /* Display audio driver power well release */
5723 void i915_release_power_well(void)
5724 {
5725         struct drm_i915_private *dev_priv;
5726
5727         if (WARN_ON(!hsw_pwr))
5728                 return;
5729
5730         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5731                                 power_domains);
5732         intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
5733 }
5734 EXPORT_SYMBOL_GPL(i915_release_power_well);
5735
5736 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
5737
5738 #define HSW_ALWAYS_ON_POWER_DOMAINS (                   \
5739         BIT(POWER_DOMAIN_PIPE_A) |                      \
5740         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
5741         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
5742         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
5743         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
5744         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
5745         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
5746         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
5747         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
5748         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
5749         BIT(POWER_DOMAIN_PORT_CRT) |                    \
5750         BIT(POWER_DOMAIN_INIT))
5751 #define HSW_DISPLAY_POWER_DOMAINS (                             \
5752         (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |    \
5753         BIT(POWER_DOMAIN_INIT))
5754
5755 #define BDW_ALWAYS_ON_POWER_DOMAINS (                   \
5756         HSW_ALWAYS_ON_POWER_DOMAINS |                   \
5757         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
5758 #define BDW_DISPLAY_POWER_DOMAINS (                             \
5759         (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) |    \
5760         BIT(POWER_DOMAIN_INIT))
5761
5762 #define VLV_ALWAYS_ON_POWER_DOMAINS     BIT(POWER_DOMAIN_INIT)
5763 #define VLV_DISPLAY_POWER_DOMAINS       POWER_DOMAIN_MASK
5764
5765 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
5766         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
5767         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
5768         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
5769         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
5770         BIT(POWER_DOMAIN_PORT_CRT) |            \
5771         BIT(POWER_DOMAIN_INIT))
5772
5773 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
5774         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
5775         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
5776         BIT(POWER_DOMAIN_INIT))
5777
5778 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
5779         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
5780         BIT(POWER_DOMAIN_INIT))
5781
5782 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
5783         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
5784         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
5785         BIT(POWER_DOMAIN_INIT))
5786
5787 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
5788         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
5789         BIT(POWER_DOMAIN_INIT))
5790
5791 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
5792         .sync_hw = i9xx_always_on_power_well_noop,
5793         .enable = i9xx_always_on_power_well_noop,
5794         .disable = i9xx_always_on_power_well_noop,
5795         .is_enabled = i9xx_always_on_power_well_enabled,
5796 };
5797
5798 static struct i915_power_well i9xx_always_on_power_well[] = {
5799         {
5800                 .name = "always-on",
5801                 .always_on = 1,
5802                 .domains = POWER_DOMAIN_MASK,
5803                 .ops = &i9xx_always_on_power_well_ops,
5804         },
5805 };
5806
5807 static const struct i915_power_well_ops hsw_power_well_ops = {
5808         .sync_hw = hsw_power_well_sync_hw,
5809         .enable = hsw_power_well_enable,
5810         .disable = hsw_power_well_disable,
5811         .is_enabled = hsw_power_well_enabled,
5812 };
5813
5814 static struct i915_power_well hsw_power_wells[] = {
5815         {
5816                 .name = "always-on",
5817                 .always_on = 1,
5818                 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
5819                 .ops = &i9xx_always_on_power_well_ops,
5820         },
5821         {
5822                 .name = "display",
5823                 .domains = HSW_DISPLAY_POWER_DOMAINS,
5824                 .ops = &hsw_power_well_ops,
5825         },
5826 };
5827
5828 static struct i915_power_well bdw_power_wells[] = {
5829         {
5830                 .name = "always-on",
5831                 .always_on = 1,
5832                 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
5833                 .ops = &i9xx_always_on_power_well_ops,
5834         },
5835         {
5836                 .name = "display",
5837                 .domains = BDW_DISPLAY_POWER_DOMAINS,
5838                 .ops = &hsw_power_well_ops,
5839         },
5840 };
5841
5842 static const struct i915_power_well_ops vlv_display_power_well_ops = {
5843         .sync_hw = vlv_power_well_sync_hw,
5844         .enable = vlv_display_power_well_enable,
5845         .disable = vlv_display_power_well_disable,
5846         .is_enabled = vlv_power_well_enabled,
5847 };
5848
5849 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
5850         .sync_hw = vlv_power_well_sync_hw,
5851         .enable = vlv_power_well_enable,
5852         .disable = vlv_power_well_disable,
5853         .is_enabled = vlv_power_well_enabled,
5854 };
5855
5856 static struct i915_power_well vlv_power_wells[] = {
5857         {
5858                 .name = "always-on",
5859                 .always_on = 1,
5860                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
5861                 .ops = &i9xx_always_on_power_well_ops,
5862         },
5863         {
5864                 .name = "display",
5865                 .domains = VLV_DISPLAY_POWER_DOMAINS,
5866                 .data = PUNIT_POWER_WELL_DISP2D,
5867                 .ops = &vlv_display_power_well_ops,
5868         },
5869         {
5870                 .name = "dpio-common",
5871                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
5872                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
5873                 .ops = &vlv_dpio_power_well_ops,
5874         },
5875         {
5876                 .name = "dpio-tx-b-01",
5877                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
5878                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
5879                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
5880                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
5881                 .ops = &vlv_dpio_power_well_ops,
5882                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
5883         },
5884         {
5885                 .name = "dpio-tx-b-23",
5886                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
5887                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
5888                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
5889                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
5890                 .ops = &vlv_dpio_power_well_ops,
5891                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
5892         },
5893         {
5894                 .name = "dpio-tx-c-01",
5895                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
5896                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
5897                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
5898                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
5899                 .ops = &vlv_dpio_power_well_ops,
5900                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
5901         },
5902         {
5903                 .name = "dpio-tx-c-23",
5904                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
5905                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
5906                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
5907                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
5908                 .ops = &vlv_dpio_power_well_ops,
5909                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
5910         },
5911 };
5912
5913 #define set_power_wells(power_domains, __power_wells) ({                \
5914         (power_domains)->power_wells = (__power_wells);                 \
5915         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
5916 })
5917
5918 int intel_power_domains_init(struct drm_i915_private *dev_priv)
5919 {
5920         struct i915_power_domains *power_domains = &dev_priv->power_domains;
5921
5922         mutex_init(&power_domains->lock);
5923
5924         /*
5925          * The enabling order will be from lower to higher indexed wells,
5926          * the disabling order is reversed.
5927          */
5928         if (IS_HASWELL(dev_priv->dev)) {
5929                 set_power_wells(power_domains, hsw_power_wells);
5930                 hsw_pwr = power_domains;
5931         } else if (IS_BROADWELL(dev_priv->dev)) {
5932                 set_power_wells(power_domains, bdw_power_wells);
5933                 hsw_pwr = power_domains;
5934         } else if (IS_VALLEYVIEW(dev_priv->dev)) {
5935                 set_power_wells(power_domains, vlv_power_wells);
5936         } else {
5937                 set_power_wells(power_domains, i9xx_always_on_power_well);
5938         }
5939
5940         return 0;
5941 }
5942
5943 void intel_power_domains_remove(struct drm_i915_private *dev_priv)
5944 {
5945         hsw_pwr = NULL;
5946 }
5947
5948 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
5949 {
5950         struct i915_power_domains *power_domains = &dev_priv->power_domains;
5951         struct i915_power_well *power_well;
5952         int i;
5953
5954         mutex_lock(&power_domains->lock);
5955         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains)
5956                 power_well->ops->sync_hw(dev_priv, power_well);
5957         mutex_unlock(&power_domains->lock);
5958 }
5959
5960 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
5961 {
5962         /* For now, we need the power well to be always enabled. */
5963         intel_display_set_init_power(dev_priv, true);
5964         intel_power_domains_resume(dev_priv);
5965 }
5966
5967 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5968 {
5969         intel_runtime_pm_get(dev_priv);
5970 }
5971
5972 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5973 {
5974         intel_runtime_pm_put(dev_priv);
5975 }
5976
5977 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
5978 {
5979         struct drm_device *dev = dev_priv->dev;
5980         struct device *device = &dev->pdev->dev;
5981
5982         if (!HAS_RUNTIME_PM(dev))
5983                 return;
5984
5985         pm_runtime_get_sync(device);
5986         WARN(dev_priv->pm.suspended, "Device still suspended.\n");
5987 }
5988
5989 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
5990 {
5991         struct drm_device *dev = dev_priv->dev;
5992         struct device *device = &dev->pdev->dev;
5993
5994         if (!HAS_RUNTIME_PM(dev))
5995                 return;
5996
5997         pm_runtime_mark_last_busy(device);
5998         pm_runtime_put_autosuspend(device);
5999 }
6000
6001 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
6002 {
6003         struct drm_device *dev = dev_priv->dev;
6004         struct device *device = &dev->pdev->dev;
6005
6006         if (!HAS_RUNTIME_PM(dev))
6007                 return;
6008
6009         pm_runtime_set_active(device);
6010
6011         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
6012         pm_runtime_mark_last_busy(device);
6013         pm_runtime_use_autosuspend(device);
6014
6015         pm_runtime_put_autosuspend(device);
6016 }
6017
6018 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
6019 {
6020         struct drm_device *dev = dev_priv->dev;
6021         struct device *device = &dev->pdev->dev;
6022
6023         if (!HAS_RUNTIME_PM(dev))
6024                 return;
6025
6026         /* Make sure we're not suspended first. */
6027         pm_runtime_get_sync(device);
6028         pm_runtime_disable(device);
6029 }
6030
6031 /* Set up chip specific power management-related functions */
6032 void intel_init_pm(struct drm_device *dev)
6033 {
6034         struct drm_i915_private *dev_priv = dev->dev_private;
6035
6036         if (HAS_FBC(dev)) {
6037                 if (INTEL_INFO(dev)->gen >= 7) {
6038                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6039                         dev_priv->display.enable_fbc = gen7_enable_fbc;
6040                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
6041                 } else if (INTEL_INFO(dev)->gen >= 5) {
6042                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6043                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
6044                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
6045                 } else if (IS_GM45(dev)) {
6046                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6047                         dev_priv->display.enable_fbc = g4x_enable_fbc;
6048                         dev_priv->display.disable_fbc = g4x_disable_fbc;
6049                 } else {
6050                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6051                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
6052                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
6053
6054                         /* This value was pulled out of someone's hat */
6055                         I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
6056                 }
6057         }
6058
6059         /* For cxsr */
6060         if (IS_PINEVIEW(dev))
6061                 i915_pineview_get_mem_freq(dev);
6062         else if (IS_GEN5(dev))
6063                 i915_ironlake_get_mem_freq(dev);
6064
6065         /* For FIFO watermark updates */
6066         if (HAS_PCH_SPLIT(dev)) {
6067                 ilk_setup_wm_latency(dev);
6068
6069                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6070                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6071                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6072                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6073                         dev_priv->display.update_wm = ilk_update_wm;
6074                         dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6075                 } else {
6076                         DRM_DEBUG_KMS("Failed to read display plane latency. "
6077                                       "Disable CxSR\n");
6078                 }
6079
6080                 if (IS_GEN5(dev))
6081                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
6082                 else if (IS_GEN6(dev))
6083                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
6084                 else if (IS_IVYBRIDGE(dev))
6085                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6086                 else if (IS_HASWELL(dev))
6087                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
6088                 else if (INTEL_INFO(dev)->gen == 8)
6089                         dev_priv->display.init_clock_gating = gen8_init_clock_gating;
6090         } else if (IS_VALLEYVIEW(dev)) {
6091                 dev_priv->display.update_wm = valleyview_update_wm;
6092                 dev_priv->display.init_clock_gating =
6093                         valleyview_init_clock_gating;
6094         } else if (IS_PINEVIEW(dev)) {
6095                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6096                                             dev_priv->is_ddr3,
6097                                             dev_priv->fsb_freq,
6098                                             dev_priv->mem_freq)) {
6099                         DRM_INFO("failed to find known CxSR latency "
6100                                  "(found ddr%s fsb freq %d, mem freq %d), "
6101                                  "disabling CxSR\n",
6102                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
6103                                  dev_priv->fsb_freq, dev_priv->mem_freq);
6104                         /* Disable CxSR and never update its watermark again */
6105                         pineview_disable_cxsr(dev);
6106                         dev_priv->display.update_wm = NULL;
6107                 } else
6108                         dev_priv->display.update_wm = pineview_update_wm;
6109                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6110         } else if (IS_G4X(dev)) {
6111                 dev_priv->display.update_wm = g4x_update_wm;
6112                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6113         } else if (IS_GEN4(dev)) {
6114                 dev_priv->display.update_wm = i965_update_wm;
6115                 if (IS_CRESTLINE(dev))
6116                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6117                 else if (IS_BROADWATER(dev))
6118                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6119         } else if (IS_GEN3(dev)) {
6120                 dev_priv->display.update_wm = i9xx_update_wm;
6121                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6122                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6123         } else if (IS_GEN2(dev)) {
6124                 if (INTEL_INFO(dev)->num_pipes == 1) {
6125                         dev_priv->display.update_wm = i845_update_wm;
6126                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
6127                 } else {
6128                         dev_priv->display.update_wm = i9xx_update_wm;
6129                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
6130                 }
6131
6132                 if (IS_I85X(dev) || IS_I865G(dev))
6133                         dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6134                 else
6135                         dev_priv->display.init_clock_gating = i830_init_clock_gating;
6136         } else {
6137                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
6138         }
6139 }
6140
6141 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6142 {
6143         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6144
6145         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6146                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6147                 return -EAGAIN;
6148         }
6149
6150         I915_WRITE(GEN6_PCODE_DATA, *val);
6151         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6152
6153         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6154                      500)) {
6155                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6156                 return -ETIMEDOUT;
6157         }
6158
6159         *val = I915_READ(GEN6_PCODE_DATA);
6160         I915_WRITE(GEN6_PCODE_DATA, 0);
6161
6162         return 0;
6163 }
6164
6165 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6166 {
6167         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6168
6169         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6170                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6171                 return -EAGAIN;
6172         }
6173
6174         I915_WRITE(GEN6_PCODE_DATA, val);
6175         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6176
6177         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6178                      500)) {
6179                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6180                 return -ETIMEDOUT;
6181         }
6182
6183         I915_WRITE(GEN6_PCODE_DATA, 0);
6184
6185         return 0;
6186 }
6187
6188 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
6189 {
6190         int div;
6191
6192         /* 4 x czclk */
6193         switch (dev_priv->mem_freq) {
6194         case 800:
6195                 div = 10;
6196                 break;
6197         case 1066:
6198                 div = 12;
6199                 break;
6200         case 1333:
6201                 div = 16;
6202                 break;
6203         default:
6204                 return -1;
6205         }
6206
6207         return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
6208 }
6209
6210 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
6211 {
6212         int mul;
6213
6214         /* 4 x czclk */
6215         switch (dev_priv->mem_freq) {
6216         case 800:
6217                 mul = 10;
6218                 break;
6219         case 1066:
6220                 mul = 12;
6221                 break;
6222         case 1333:
6223                 mul = 16;
6224                 break;
6225         default:
6226                 return -1;
6227         }
6228
6229         return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
6230 }
6231
6232 void intel_pm_setup(struct drm_device *dev)
6233 {
6234         struct drm_i915_private *dev_priv = dev->dev_private;
6235
6236         mutex_init(&dev_priv->rps.hw_lock);
6237
6238         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6239                           intel_gen6_powersave_work);
6240
6241         dev_priv->pm.suspended = false;
6242         dev_priv->pm.irqs_disabled = false;
6243 }