drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_fourcc.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 static void
  40 ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
  41                  struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
  42                  unsigned int crtc_w, unsigned int crtc_h,
  43                  uint32_t x, uint32_t y,
  44                  uint32_t src_w, uint32_t src_h)
  45 {
  46         struct drm_device *dev = plane->dev;
  47         struct drm_i915_private *dev_priv = dev->dev_private;
  48         struct intel_plane *intel_plane = to_intel_plane(plane);
  49         int pipe = intel_plane->pipe;
  50         u32 sprctl, sprscale = 0;
  51         unsigned long sprsurf_offset, linear_offset;
  52         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
  53
  54         sprctl = I915_READ(SPRCTL(pipe));
  55
  56         /* Mask out pixel format bits in case we change it */
  57         sprctl &= ~SPRITE_PIXFORMAT_MASK;
  58         sprctl &= ~SPRITE_RGB_ORDER_RGBX;
  59         sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
  60         sprctl &= ~SPRITE_TILED;
  61
  62         switch (fb->pixel_format) {
  63         case DRM_FORMAT_XBGR8888:
  64                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
  65                 break;
  66         case DRM_FORMAT_XRGB8888:
  67                 sprctl |= SPRITE_FORMAT_RGBX888;
  68                 break;
  69         case DRM_FORMAT_YUYV:
  70                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
  71                 break;
  72         case DRM_FORMAT_YVYU:
  73                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
  74                 break;
  75         case DRM_FORMAT_UYVY:
  76                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
  77                 break;
  78         case DRM_FORMAT_VYUY:
  79                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
  80                 break;
  81         default:
  82                 BUG();
  83         }
  84
  85         if (obj->tiling_mode != I915_TILING_NONE)
  86                 sprctl |= SPRITE_TILED;
  87
  88         /* must disable */
  89         sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
  90         sprctl |= SPRITE_ENABLE;
  91
  92         /* Sizes are 0 based */
  93         src_w--;
  94         src_h--;
  95         crtc_w--;
  96         crtc_h--;
  97
  98         intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
  99
 100         /*
 101          * IVB workaround: must disable low power watermarks for at least
 102          * one frame before enabling scaling.  LP watermarks can be re-enabled
 103          * when scaling is disabled.
 104          */
 105         if (crtc_w != src_w || crtc_h != src_h) {
 106                 if (!dev_priv->sprite_scaling_enabled) {
 107                         dev_priv->sprite_scaling_enabled = true;
 108                         intel_update_watermarks(dev);
 109                         intel_wait_for_vblank(dev, pipe);
 110                 }
 111                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 112         } else {
 113                 if (dev_priv->sprite_scaling_enabled) {
 114                         dev_priv->sprite_scaling_enabled = false;
 115                         /* potentially re-enable LP watermarks */
 116                         intel_update_watermarks(dev);
 117                 }
 118         }
 119
 120         I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
 121         I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 122
 123         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
 124         sprsurf_offset =
 125                 intel_gen4_compute_offset_xtiled(&x, &y,
 126                                                  fb->bits_per_pixel / 8,
 127                                                  fb->pitches[0]);
 128         linear_offset -= sprsurf_offset;
 129
 130         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 131          * register */
 132         if (IS_HASWELL(dev))
 133                 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
 134         else if (obj->tiling_mode != I915_TILING_NONE)
 135                 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
 136         else
 137                 I915_WRITE(SPRLINOFF(pipe), linear_offset);
 138
 139         I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 140         if (intel_plane->can_scale)
 141                 I915_WRITE(SPRSCALE(pipe), sprscale);
 142         I915_WRITE(SPRCTL(pipe), sprctl);
 143         I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset + sprsurf_offset);
 144         POSTING_READ(SPRSURF(pipe));
 145 }
 146
 147 static void
 148 ivb_disable_plane(struct drm_plane *plane)
 149 {
 150         struct drm_device *dev = plane->dev;
 151         struct drm_i915_private *dev_priv = dev->dev_private;
 152         struct intel_plane *intel_plane = to_intel_plane(plane);
 153         int pipe = intel_plane->pipe;
 154
 155         I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
 156         /* Can't leave the scaler enabled... */
 157         if (intel_plane->can_scale)
 158                 I915_WRITE(SPRSCALE(pipe), 0);
 159         /* Activate double buffered register update */
 160         I915_MODIFY_DISPBASE(SPRSURF(pipe), 0);
 161         POSTING_READ(SPRSURF(pipe));
 162
 163         dev_priv->sprite_scaling_enabled = false;
 164         intel_update_watermarks(dev);
 165 }
 166
 167 static int
 168 ivb_update_colorkey(struct drm_plane *plane,
 169                     struct drm_intel_sprite_colorkey *key)
 170 {
 171         struct drm_device *dev = plane->dev;
 172         struct drm_i915_private *dev_priv = dev->dev_private;
 173         struct intel_plane *intel_plane;
 174         u32 sprctl;
 175         int ret = 0;
 176
 177         intel_plane = to_intel_plane(plane);
 178
 179         I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value);
 180         I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value);
 181         I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask);
 182
 183         sprctl = I915_READ(SPRCTL(intel_plane->pipe));
 184         sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY);
 185         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 186                 sprctl |= SPRITE_DEST_KEY;
 187         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 188                 sprctl |= SPRITE_SOURCE_KEY;
 189         I915_WRITE(SPRCTL(intel_plane->pipe), sprctl);
 190
 191         POSTING_READ(SPRKEYMSK(intel_plane->pipe));
 192
 193         return ret;
 194 }
 195
 196 static void
 197 ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
 198 {
 199         struct drm_device *dev = plane->dev;
 200         struct drm_i915_private *dev_priv = dev->dev_private;
 201         struct intel_plane *intel_plane;
 202         u32 sprctl;
 203
 204         intel_plane = to_intel_plane(plane);
 205
 206         key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe));
 207         key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe));
 208         key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe));
 209         key->flags = 0;
 210
 211         sprctl = I915_READ(SPRCTL(intel_plane->pipe));
 212
 213         if (sprctl & SPRITE_DEST_KEY)
 214                 key->flags = I915_SET_COLORKEY_DESTINATION;
 215         else if (sprctl & SPRITE_SOURCE_KEY)
 216                 key->flags = I915_SET_COLORKEY_SOURCE;
 217         else
 218                 key->flags = I915_SET_COLORKEY_NONE;
 219 }
 220
 221 static void
 222 ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
 223                  struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
 224                  unsigned int crtc_w, unsigned int crtc_h,
 225                  uint32_t x, uint32_t y,
 226                  uint32_t src_w, uint32_t src_h)
 227 {
 228         struct drm_device *dev = plane->dev;
 229         struct drm_i915_private *dev_priv = dev->dev_private;
 230         struct intel_plane *intel_plane = to_intel_plane(plane);
 231         int pipe = intel_plane->pipe;
 232         unsigned long dvssurf_offset, linear_offset;
 233         u32 dvscntr, dvsscale;
 234         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 235
 236         dvscntr = I915_READ(DVSCNTR(pipe));
 237
 238         /* Mask out pixel format bits in case we change it */
 239         dvscntr &= ~DVS_PIXFORMAT_MASK;
 240         dvscntr &= ~DVS_RGB_ORDER_XBGR;
 241         dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
 242         dvscntr &= ~DVS_TILED;
 243
 244         switch (fb->pixel_format) {
 245         case DRM_FORMAT_XBGR8888:
 246                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 247                 break;
 248         case DRM_FORMAT_XRGB8888:
 249                 dvscntr |= DVS_FORMAT_RGBX888;
 250                 break;
 251         case DRM_FORMAT_YUYV:
 252                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 253                 break;
 254         case DRM_FORMAT_YVYU:
 255                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 256                 break;
 257         case DRM_FORMAT_UYVY:
 258                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 259                 break;
 260         case DRM_FORMAT_VYUY:
 261                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 262                 break;
 263         default:
 264                 BUG();
 265         }
 266
 267         if (obj->tiling_mode != I915_TILING_NONE)
 268                 dvscntr |= DVS_TILED;
 269
 270         if (IS_GEN6(dev))
 271                 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
 272         dvscntr |= DVS_ENABLE;
 273
 274         /* Sizes are 0 based */
 275         src_w--;
 276         src_h--;
 277         crtc_w--;
 278         crtc_h--;
 279
 280         intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
 281
 282         dvsscale = 0;
 283         if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h)
 284                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 285
 286         I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
 287         I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 288
 289         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
 290         dvssurf_offset =
 291                 intel_gen4_compute_offset_xtiled(&x, &y,
 292                                                  fb->bits_per_pixel / 8,
 293                                                  fb->pitches[0]);
 294         linear_offset -= dvssurf_offset;
 295
 296         if (obj->tiling_mode != I915_TILING_NONE)
 297                 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
 298         else
 299                 I915_WRITE(DVSLINOFF(pipe), linear_offset);
 300
 301         I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 302         I915_WRITE(DVSSCALE(pipe), dvsscale);
 303         I915_WRITE(DVSCNTR(pipe), dvscntr);
 304         I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset + dvssurf_offset);
 305         POSTING_READ(DVSSURF(pipe));
 306 }
 307
 308 static void
 309 ilk_disable_plane(struct drm_plane *plane)
 310 {
 311         struct drm_device *dev = plane->dev;
 312         struct drm_i915_private *dev_priv = dev->dev_private;
 313         struct intel_plane *intel_plane = to_intel_plane(plane);
 314         int pipe = intel_plane->pipe;
 315
 316         I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE);
 317         /* Disable the scaler */
 318         I915_WRITE(DVSSCALE(pipe), 0);
 319         /* Flush double buffered register updates */
 320         I915_MODIFY_DISPBASE(DVSSURF(pipe), 0);
 321         POSTING_READ(DVSSURF(pipe));
 322 }
 323
 324 static void
 325 intel_enable_primary(struct drm_crtc *crtc)
 326 {
 327         struct drm_device *dev = crtc->dev;
 328         struct drm_i915_private *dev_priv = dev->dev_private;
 329         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 330         int reg = DSPCNTR(intel_crtc->plane);
 331
 332         if (!intel_crtc->primary_disabled)
 333                 return;
 334
 335         intel_crtc->primary_disabled = false;
 336         intel_update_fbc(dev);
 337
 338         I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
 339 }
 340
 341 static void
 342 intel_disable_primary(struct drm_crtc *crtc)
 343 {
 344         struct drm_device *dev = crtc->dev;
 345         struct drm_i915_private *dev_priv = dev->dev_private;
 346         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 347         int reg = DSPCNTR(intel_crtc->plane);
 348
 349         if (intel_crtc->primary_disabled)
 350                 return;
 351
 352         I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE);
 353
 354         intel_crtc->primary_disabled = true;
 355         intel_update_fbc(dev);
 356 }
 357
 358 static int
 359 ilk_update_colorkey(struct drm_plane *plane,
 360                     struct drm_intel_sprite_colorkey *key)
 361 {
 362         struct drm_device *dev = plane->dev;
 363         struct drm_i915_private *dev_priv = dev->dev_private;
 364         struct intel_plane *intel_plane;
 365         u32 dvscntr;
 366         int ret = 0;
 367
 368         intel_plane = to_intel_plane(plane);
 369
 370         I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value);
 371         I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value);
 372         I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask);
 373
 374         dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
 375         dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY);
 376         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 377                 dvscntr |= DVS_DEST_KEY;
 378         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 379                 dvscntr |= DVS_SOURCE_KEY;
 380         I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr);
 381
 382         POSTING_READ(DVSKEYMSK(intel_plane->pipe));
 383
 384         return ret;
 385 }
 386
 387 static void
 388 ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
 389 {
 390         struct drm_device *dev = plane->dev;
 391         struct drm_i915_private *dev_priv = dev->dev_private;
 392         struct intel_plane *intel_plane;
 393         u32 dvscntr;
 394
 395         intel_plane = to_intel_plane(plane);
 396
 397         key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe));
 398         key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe));
 399         key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe));
 400         key->flags = 0;
 401
 402         dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
 403
 404         if (dvscntr & DVS_DEST_KEY)
 405                 key->flags = I915_SET_COLORKEY_DESTINATION;
 406         else if (dvscntr & DVS_SOURCE_KEY)
 407                 key->flags = I915_SET_COLORKEY_SOURCE;
 408         else
 409                 key->flags = I915_SET_COLORKEY_NONE;
 410 }
 411
 412 static int
 413 intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 414                    struct drm_framebuffer *fb, int crtc_x, int crtc_y,
 415                    unsigned int crtc_w, unsigned int crtc_h,
 416                    uint32_t src_x, uint32_t src_y,
 417                    uint32_t src_w, uint32_t src_h)
 418 {
 419         struct drm_device *dev = plane->dev;
 420         struct drm_i915_private *dev_priv = dev->dev_private;
 421         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 422         struct intel_plane *intel_plane = to_intel_plane(plane);
 423         struct intel_framebuffer *intel_fb;
 424         struct drm_i915_gem_object *obj, *old_obj;
 425         int pipe = intel_plane->pipe;
 426         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 427                                                                       pipe);
 428         int ret = 0;
 429         int x = src_x >> 16, y = src_y >> 16;
 430         int primary_w = crtc->mode.hdisplay, primary_h = crtc->mode.vdisplay;
 431         bool disable_primary = false;
 432
 433         intel_fb = to_intel_framebuffer(fb);
 434         obj = intel_fb->obj;
 435
 436         old_obj = intel_plane->obj;
 437
 438         src_w = src_w >> 16;
 439         src_h = src_h >> 16;
 440
 441         /* Pipe must be running... */
 442         if (!(I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE))
 443                 return -EINVAL;
 444
 445         if (crtc_x >= primary_w || crtc_y >= primary_h)
 446                 return -EINVAL;
 447
 448         /* Don't modify another pipe's plane */
 449         if (intel_plane->pipe != intel_crtc->pipe)
 450                 return -EINVAL;
 451
 452         /* Sprite planes can be linear or x-tiled surfaces */
 453         switch (obj->tiling_mode) {
 454                 case I915_TILING_NONE:
 455                 case I915_TILING_X:
 456                         break;
 457                 default:
 458                         return -EINVAL;
 459         }
 460
 461         /*
 462          * Clamp the width & height into the visible area.  Note we don't
 463          * try to scale the source if part of the visible region is offscreen.
 464          * The caller must handle that by adjusting source offset and size.
 465          */
 466         if ((crtc_x < 0) && ((crtc_x + crtc_w) > 0)) {
 467                 crtc_w += crtc_x;
 468                 crtc_x = 0;
 469         }
 470         if ((crtc_x + crtc_w) <= 0) /* Nothing to display */
 471                 goto out;
 472         if ((crtc_x + crtc_w) > primary_w)
 473                 crtc_w = primary_w - crtc_x;
 474
 475         if ((crtc_y < 0) && ((crtc_y + crtc_h) > 0)) {
 476                 crtc_h += crtc_y;
 477                 crtc_y = 0;
 478         }
 479         if ((crtc_y + crtc_h) <= 0) /* Nothing to display */
 480                 goto out;
 481         if (crtc_y + crtc_h > primary_h)
 482                 crtc_h = primary_h - crtc_y;
 483
 484         if (!crtc_w || !crtc_h) /* Again, nothing to display */
 485                 goto out;
 486
 487         /*
 488          * We may not have a scaler, eg. HSW does not have it any more
 489          */
 490         if (!intel_plane->can_scale && (crtc_w != src_w || crtc_h != src_h))
 491                 return -EINVAL;
 492
 493         /*
 494          * We can take a larger source and scale it down, but
 495          * only so much...  16x is the max on SNB.
 496          */
 497         if (((src_w * src_h) / (crtc_w * crtc_h)) > intel_plane->max_downscale)
 498                 return -EINVAL;
 499
 500         /*
 501          * If the sprite is completely covering the primary plane,
 502          * we can disable the primary and save power.
 503          */
 504         if ((crtc_x == 0) && (crtc_y == 0) &&
 505             (crtc_w == primary_w) && (crtc_h == primary_h))
 506                 disable_primary = true;
 507
 508         mutex_lock(&dev->struct_mutex);
 509
 510         ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
 511         if (ret)
 512                 goto out_unlock;
 513
 514         intel_plane->obj = obj;
 515
 516         /*
 517          * Be sure to re-enable the primary before the sprite is no longer
 518          * covering it fully.
 519          */
 520         if (!disable_primary)
 521                 intel_enable_primary(crtc);
 522
 523         intel_plane->update_plane(plane, fb, obj, crtc_x, crtc_y,
 524                                   crtc_w, crtc_h, x, y, src_w, src_h);
 525
 526         if (disable_primary)
 527                 intel_disable_primary(crtc);
 528
 529         /* Unpin old obj after new one is active to avoid ugliness */
 530         if (old_obj) {
 531                 /*
 532                  * It's fairly common to simply update the position of
 533                  * an existing object.  In that case, we don't need to
 534                  * wait for vblank to avoid ugliness, we only need to
 535                  * do the pin & ref bookkeeping.
 536                  */
 537                 if (old_obj != obj) {
 538                         mutex_unlock(&dev->struct_mutex);
 539                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
 540                         mutex_lock(&dev->struct_mutex);
 541                 }
 542                 intel_unpin_fb_obj(old_obj);
 543         }
 544
 545 out_unlock:
 546         mutex_unlock(&dev->struct_mutex);
 547 out:
 548         return ret;
 549 }
 550
 551 static int
 552 intel_disable_plane(struct drm_plane *plane)
 553 {
 554         struct drm_device *dev = plane->dev;
 555         struct intel_plane *intel_plane = to_intel_plane(plane);
 556         int ret = 0;
 557
 558         if (plane->crtc)
 559                 intel_enable_primary(plane->crtc);
 560         intel_plane->disable_plane(plane);
 561
 562         if (!intel_plane->obj)
 563                 goto out;
 564
 565         mutex_lock(&dev->struct_mutex);
 566         intel_unpin_fb_obj(intel_plane->obj);
 567         intel_plane->obj = NULL;
 568         mutex_unlock(&dev->struct_mutex);
 569 out:
 570
 571         return ret;
 572 }
 573
 574 static void intel_destroy_plane(struct drm_plane *plane)
 575 {
 576         struct intel_plane *intel_plane = to_intel_plane(plane);
 577         intel_disable_plane(plane);
 578         drm_plane_cleanup(plane);
 579         kfree(intel_plane);
 580 }
 581
 582 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 583                               struct drm_file *file_priv)
 584 {
 585         struct drm_intel_sprite_colorkey *set = data;
 586         struct drm_mode_object *obj;
 587         struct drm_plane *plane;
 588         struct intel_plane *intel_plane;
 589         int ret = 0;
 590
 591         if (!drm_core_check_feature(dev, DRIVER_MODESET))
 592                 return -ENODEV;
 593
 594         /* Make sure we don't try to enable both src & dest simultaneously */
 595         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
 596                 return -EINVAL;
 597
 598         mutex_lock(&dev->mode_config.mutex);
 599
 600         obj = drm_mode_object_find(dev, set->plane_id, DRM_MODE_OBJECT_PLANE);
 601         if (!obj) {
 602                 ret = -EINVAL;
 603                 goto out_unlock;
 604         }
 605
 606         plane = obj_to_plane(obj);
 607         intel_plane = to_intel_plane(plane);
 608         ret = intel_plane->update_colorkey(plane, set);
 609
 610 out_unlock:
 611         mutex_unlock(&dev->mode_config.mutex);
 612         return ret;
 613 }
 614
 615 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
 616                               struct drm_file *file_priv)
 617 {
 618         struct drm_intel_sprite_colorkey *get = data;
 619         struct drm_mode_object *obj;
 620         struct drm_plane *plane;
 621         struct intel_plane *intel_plane;
 622         int ret = 0;
 623
 624         if (!drm_core_check_feature(dev, DRIVER_MODESET))
 625                 return -ENODEV;
 626
 627         mutex_lock(&dev->mode_config.mutex);
 628
 629         obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE);
 630         if (!obj) {
 631                 ret = -EINVAL;
 632                 goto out_unlock;
 633         }
 634
 635         plane = obj_to_plane(obj);
 636         intel_plane = to_intel_plane(plane);
 637         intel_plane->get_colorkey(plane, get);
 638
 639 out_unlock:
 640         mutex_unlock(&dev->mode_config.mutex);
 641         return ret;
 642 }
 643
 644 static const struct drm_plane_funcs intel_plane_funcs = {
 645         .update_plane = intel_update_plane,
 646         .disable_plane = intel_disable_plane,
 647         .destroy = intel_destroy_plane,
 648 };
 649
 650 static uint32_t ilk_plane_formats[] = {
 651         DRM_FORMAT_XRGB8888,
 652         DRM_FORMAT_YUYV,
 653         DRM_FORMAT_YVYU,
 654         DRM_FORMAT_UYVY,
 655         DRM_FORMAT_VYUY,
 656 };
 657
 658 static uint32_t snb_plane_formats[] = {
 659         DRM_FORMAT_XBGR8888,
 660         DRM_FORMAT_XRGB8888,
 661         DRM_FORMAT_YUYV,
 662         DRM_FORMAT_YVYU,
 663         DRM_FORMAT_UYVY,
 664         DRM_FORMAT_VYUY,
 665 };
 666
 667 int
 668 intel_plane_init(struct drm_device *dev, enum pipe pipe)
 669 {
 670         struct intel_plane *intel_plane;
 671         unsigned long possible_crtcs;
 672         const uint32_t *plane_formats;
 673         int num_plane_formats;
 674         int ret;
 675
 676         if (INTEL_INFO(dev)->gen < 5)
 677                 return -ENODEV;
 678
 679         intel_plane = kzalloc(sizeof(struct intel_plane), GFP_KERNEL);
 680         if (!intel_plane)
 681                 return -ENOMEM;
 682
 683         switch (INTEL_INFO(dev)->gen) {
 684         case 5:
 685         case 6:
 686                 intel_plane->can_scale = true;
 687                 intel_plane->max_downscale = 16;
 688                 intel_plane->update_plane = ilk_update_plane;
 689                 intel_plane->disable_plane = ilk_disable_plane;
 690                 intel_plane->update_colorkey = ilk_update_colorkey;
 691                 intel_plane->get_colorkey = ilk_get_colorkey;
 692
 693                 if (IS_GEN6(dev)) {
 694                         plane_formats = snb_plane_formats;
 695                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
 696                 } else {
 697                         plane_formats = ilk_plane_formats;
 698                         num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
 699                 }
 700                 break;
 701
 702         case 7:
 703                 if (IS_HASWELL(dev) || IS_VALLEYVIEW(dev))
 704                         intel_plane->can_scale = false;
 705                 else
 706                         intel_plane->can_scale = true;
 707                 intel_plane->max_downscale = 2;
 708                 intel_plane->update_plane = ivb_update_plane;
 709                 intel_plane->disable_plane = ivb_disable_plane;
 710                 intel_plane->update_colorkey = ivb_update_colorkey;
 711                 intel_plane->get_colorkey = ivb_get_colorkey;
 712
 713                 plane_formats = snb_plane_formats;
 714                 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
 715                 break;
 716
 717         default:
 718                 kfree(intel_plane);
 719                 return -ENODEV;
 720         }
 721
 722         intel_plane->pipe = pipe;
 723         possible_crtcs = (1 << pipe);
 724         ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs,
 725                              &intel_plane_funcs,
 726                              plane_formats, num_plane_formats,
 727                              false);
 728         if (ret)
 729                 kfree(intel_plane);
 730
 731         return ret;
 732 }