2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/kernel.h>
22 #include <linux/clk.h>
23 #include <linux/cpufreq.h>
24 #include <linux/module.h>
25 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/slab.h>
29 #include <linux/list.h>
30 #include <linux/iommu.h>
31 #include <linux/types.h>
32 #include <asm/sizes.h>
35 #include <mach/board.h>
36 #include <mach/socinfo.h>
37 #include <mach/iommu_domains.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_fb_helper.h>
43 #include <drm/msm_drm.h>
48 #define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */
50 struct msm_file_private {
51 /* currently we don't do anything useful with this.. but when
52 * per-context address spaces are supported we'd keep track of
53 * the context's page-tables here.
58 struct msm_drm_private {
62 /* when we have more than one 'msm_gpu' these need to be an array: */
64 struct msm_file_private *lastctx;
66 struct drm_fb_helper *fbdev;
68 uint32_t next_fence, completed_fence;
69 wait_queue_head_t fence_event;
71 /* list of GEM objects: */
72 struct list_head inactive_list;
74 struct workqueue_struct *wq;
76 /* registered IOMMU domains: */
77 unsigned int num_iommus;
78 struct iommu_domain *iommus[NUM_DOMAINS];
80 unsigned int num_crtcs;
81 struct drm_crtc *crtcs[8];
83 unsigned int num_encoders;
84 struct drm_encoder *encoders[8];
86 unsigned int num_connectors;
87 struct drm_connector *connectors[8];
91 uint32_t pixel_format;
94 /* As there are different display controller blocks depending on the
95 * snapdragon version, the kms support is split out and the appropriate
96 * implementation is loaded at runtime. The kms module is responsible
97 * for constructing the appropriate planes/crtcs/encoders/connectors.
99 struct msm_kms_funcs {
100 /* hw initialization: */
101 int (*hw_init)(struct msm_kms *kms);
103 void (*irq_preinstall)(struct msm_kms *kms);
104 int (*irq_postinstall)(struct msm_kms *kms);
105 void (*irq_uninstall)(struct msm_kms *kms);
106 irqreturn_t (*irq)(struct msm_kms *kms);
107 int (*enable_vblank)(struct msm_kms *kms, struct drm_crtc *crtc);
108 void (*disable_vblank)(struct msm_kms *kms, struct drm_crtc *crtc);
110 const struct msm_format *(*get_format)(struct msm_kms *kms, uint32_t format);
111 long (*round_pixclk)(struct msm_kms *kms, unsigned long rate,
112 struct drm_encoder *encoder);
114 void (*preclose)(struct msm_kms *kms, struct drm_file *file);
115 void (*destroy)(struct msm_kms *kms);
119 const struct msm_kms_funcs *funcs;
122 struct msm_kms *mdp4_kms_init(struct drm_device *dev);
124 int msm_register_iommu(struct drm_device *dev, struct iommu_domain *iommu);
125 int msm_iommu_attach(struct drm_device *dev, struct iommu_domain *iommu,
126 const char **names, int cnt);
128 int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence,
129 struct timespec *timeout);
130 void msm_update_fence(struct drm_device *dev, uint32_t fence);
132 int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
133 struct drm_file *file);
135 int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
136 int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
137 uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
138 int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
140 int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova);
141 void msm_gem_put_iova(struct drm_gem_object *obj, int id);
142 int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
143 struct drm_mode_create_dumb *args);
144 int msm_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
146 int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
147 uint32_t handle, uint64_t *offset);
148 void *msm_gem_vaddr_locked(struct drm_gem_object *obj);
149 void *msm_gem_vaddr(struct drm_gem_object *obj);
150 int msm_gem_queue_inactive_work(struct drm_gem_object *obj,
151 struct work_struct *work);
152 void msm_gem_move_to_active(struct drm_gem_object *obj,
153 struct msm_gpu *gpu, uint32_t fence);
154 void msm_gem_move_to_inactive(struct drm_gem_object *obj);
155 int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op,
156 struct timespec *timeout);
157 int msm_gem_cpu_fini(struct drm_gem_object *obj);
158 void msm_gem_free_object(struct drm_gem_object *obj);
159 int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
160 uint32_t size, uint32_t flags, uint32_t *handle);
161 struct drm_gem_object *msm_gem_new(struct drm_device *dev,
162 uint32_t size, uint32_t flags);
164 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
165 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
166 struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
167 struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos);
168 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
169 struct drm_file *file, struct drm_mode_fb_cmd2 *mode_cmd);
171 struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
173 struct drm_connector *hdmi_connector_init(struct drm_device *dev,
174 struct drm_encoder *encoder);
175 void __init hdmi_register(void);
176 void __exit hdmi_unregister(void);
178 #ifdef CONFIG_DEBUG_FS
179 void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
180 void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
181 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
184 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
185 const char *dbgname);
186 void msm_writel(u32 data, void __iomem *addr);
187 u32 msm_readl(const void __iomem *addr);
189 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
190 #define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
192 static inline int align_pitch(int width, int bpp)
194 int bytespp = (bpp + 7) / 8;
195 /* adreno needs pitch aligned to 32 pixels: */
196 return bytespp * ALIGN(width, 32);
199 /* for the generated headers: */
200 #define INVALID_IDX(idx) ({BUG(); 0;})
201 #define fui(x) ({BUG(); 0;})
202 #define util_float_to_half(x) ({BUG(); 0;})
205 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
207 /* for conditionally setting boolean flag(s): */
208 #define COND(bool, val) ((bool) ? (val) : 0)
211 #endif /* __MSM_DRV_H__ */