drivers/gpu/drm/nouveau/core/core/falcon.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <core/falcon.h>
  24
  25 #include <subdev/timer.h>
  26
  27 u32
  28 _nouveau_falcon_rd32(struct nouveau_object *object, u64 addr)
  29 {
  30         struct nouveau_falcon *falcon = (void *)object;
  31         return nv_rd32(falcon, falcon->addr + addr);
  32 }
  33
  34 void
  35 _nouveau_falcon_wr32(struct nouveau_object *object, u64 addr, u32 data)
  36 {
  37         struct nouveau_falcon *falcon = (void *)object;
  38         nv_wr32(falcon, falcon->addr + addr, data);
  39 }
  40
  41 int
  42 _nouveau_falcon_init(struct nouveau_object *object)
  43 {
  44         struct nouveau_device *device = nv_device(object);
  45         struct nouveau_falcon *falcon = (void *)object;
  46         const struct firmware *fw;
  47         char name[32] = "internal";
  48         int ret, i;
  49         u32 caps;
  50
  51         /* enable engine, and determine its capabilities */
  52         ret = nouveau_engine_init(&falcon->base);
  53         if (ret)
  54                 return ret;
  55
  56         if (device->chipset <  0xa3 ||
  57             device->chipset == 0xaa || device->chipset == 0xac) {
  58                 falcon->version = 0;
  59                 falcon->secret  = (falcon->addr == 0x087000) ? 1 : 0;
  60         } else {
  61                 caps = nv_ro32(falcon, 0x12c);
  62                 falcon->version = (caps & 0x0000000f);
  63                 falcon->secret  = (caps & 0x00000030) >> 4;
  64         }
  65
  66         caps = nv_ro32(falcon, 0x108);
  67         falcon->code.limit = (caps & 0x000001ff) << 8;
  68         falcon->data.limit = (caps & 0x0003fe00) >> 1;
  69
  70         nv_debug(falcon, "falcon version: %d\n", falcon->version);
  71         nv_debug(falcon, "secret level: %d\n", falcon->secret);
  72         nv_debug(falcon, "code limit: %d\n", falcon->code.limit);
  73         nv_debug(falcon, "data limit: %d\n", falcon->data.limit);
  74
  75         /* wait for 'uc halted' to be signalled before continuing */
  76         if (falcon->secret && falcon->version < 4) {
  77                 if (!falcon->version)
  78                         nv_wait(falcon, 0x008, 0x00000010, 0x00000010);
  79                 else
  80                         nv_wait(falcon, 0x180, 0x80000000, 0);
  81                 nv_wo32(falcon, 0x004, 0x00000010);
  82         }
  83
  84         /* disable all interrupts */
  85         nv_wo32(falcon, 0x014, 0xffffffff);
  86
  87         /* no default ucode provided by the engine implementation, try and
  88          * locate a "self-bootstrapping" firmware image for the engine
  89          */
  90         if (!falcon->code.data) {
  91                 snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03x",
  92                          device->chipset, falcon->addr >> 12);
  93
  94                 ret = request_firmware(&fw, name, &device->pdev->dev);
  95                 if (ret == 0) {
  96                         falcon->code.data = kmemdup(fw->data, fw->size, GFP_KERNEL);
  97                         falcon->code.size = fw->size;
  98                         falcon->data.data = NULL;
  99                         falcon->data.size = 0;
 100                         release_firmware(fw);
 101                 }
 102
 103                 falcon->external = true;
 104         }
 105
 106         /* next step is to try and load "static code/data segment" firmware
 107          * images for the engine
 108          */
 109         if (!falcon->code.data) {
 110                 snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03xd",
 111                          device->chipset, falcon->addr >> 12);
 112
 113                 ret = request_firmware(&fw, name, &device->pdev->dev);
 114                 if (ret) {
 115                         nv_error(falcon, "unable to load firmware data\n");
 116                         return ret;
 117                 }
 118
 119                 falcon->data.data = kmemdup(fw->data, fw->size, GFP_KERNEL);
 120                 falcon->data.size = fw->size;
 121                 release_firmware(fw);
 122                 if (!falcon->data.data)
 123                         return -ENOMEM;
 124
 125                 snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03xc",
 126                          device->chipset, falcon->addr >> 12);
 127
 128                 ret = request_firmware(&fw, name, &device->pdev->dev);
 129                 if (ret) {
 130                         nv_error(falcon, "unable to load firmware code\n");
 131                         return ret;
 132                 }
 133
 134                 falcon->code.data = kmemdup(fw->data, fw->size, GFP_KERNEL);
 135                 falcon->code.size = fw->size;
 136                 release_firmware(fw);
 137                 if (!falcon->code.data)
 138                         return -ENOMEM;
 139         }
 140
 141         nv_debug(falcon, "firmware: %s (%s)\n", name, falcon->data.data ?
 142                  "static code/data segments" : "self-bootstrapping");
 143
 144         /* ensure any "self-bootstrapping" firmware image is in vram */
 145         if (!falcon->data.data && !falcon->core) {
 146                 ret = nouveau_gpuobj_new(object->parent, NULL,
 147                                          falcon->code.size, 256, 0,
 148                                         &falcon->core);
 149                 if (ret) {
 150                         nv_error(falcon, "core allocation failed, %d\n", ret);
 151                         return ret;
 152                 }
 153
 154                 for (i = 0; i < falcon->code.size; i += 4)
 155                         nv_wo32(falcon->core, i, falcon->code.data[i / 4]);
 156         }
 157
 158         /* upload firmware bootloader (or the full code segments) */
 159         if (falcon->core) {
 160                 if (device->card_type < NV_C0)
 161                         nv_wo32(falcon, 0x618, 0x04000000);
 162                 else
 163                         nv_wo32(falcon, 0x618, 0x00000114);
 164                 nv_wo32(falcon, 0x11c, 0);
 165                 nv_wo32(falcon, 0x110, falcon->core->addr >> 8);
 166                 nv_wo32(falcon, 0x114, 0);
 167                 nv_wo32(falcon, 0x118, 0x00006610);
 168         } else {
 169                 if (falcon->code.size > falcon->code.limit ||
 170                     falcon->data.size > falcon->data.limit) {
 171                         nv_error(falcon, "ucode exceeds falcon limit(s)\n");
 172                         return -EINVAL;
 173                 }
 174
 175                 if (falcon->version < 3) {
 176                         nv_wo32(falcon, 0xff8, 0x00100000);
 177                         for (i = 0; i < falcon->code.size / 4; i++)
 178                                 nv_wo32(falcon, 0xff4, falcon->code.data[i]);
 179                 } else {
 180                         nv_wo32(falcon, 0x180, 0x01000000);
 181                         for (i = 0; i < falcon->code.size / 4; i++) {
 182                                 if ((i & 0x3f) == 0)
 183                                         nv_wo32(falcon, 0x188, i >> 6);
 184                                 nv_wo32(falcon, 0x184, falcon->code.data[i]);
 185                         }
 186                 }
 187         }
 188
 189         /* upload data segment (if necessary), zeroing the remainder */
 190         if (falcon->version < 3) {
 191                 nv_wo32(falcon, 0xff8, 0x00000000);
 192                 for (i = 0; !falcon->core && i < falcon->data.size / 4; i++)
 193                         nv_wo32(falcon, 0xff4, falcon->data.data[i]);
 194                 for (; i < falcon->data.limit; i += 4)
 195                         nv_wo32(falcon, 0xff4, 0x00000000);
 196         } else {
 197                 nv_wo32(falcon, 0x1c0, 0x01000000);
 198                 for (i = 0; !falcon->core && i < falcon->data.size / 4; i++)
 199                         nv_wo32(falcon, 0x1c4, falcon->data.data[i]);
 200                 for (; i < falcon->data.limit / 4; i++)
 201                         nv_wo32(falcon, 0x1c4, 0x00000000);
 202         }
 203
 204         /* start it running */
 205         nv_wo32(falcon, 0x10c, 0x00000001); /* BLOCK_ON_FIFO */
 206         nv_wo32(falcon, 0x104, 0x00000000); /* ENTRY */
 207         nv_wo32(falcon, 0x100, 0x00000002); /* TRIGGER */
 208         nv_wo32(falcon, 0x048, 0x00000003); /* FIFO | CHSW */
 209         return 0;
 210 }
 211
 212 int
 213 _nouveau_falcon_fini(struct nouveau_object *object, bool suspend)
 214 {
 215         struct nouveau_falcon *falcon = (void *)object;
 216
 217         if (!suspend) {
 218                 nouveau_gpuobj_ref(NULL, &falcon->core);
 219                 if (falcon->external) {
 220                         kfree(falcon->data.data);
 221                         kfree(falcon->code.data);
 222                         falcon->code.data = NULL;
 223                 }
 224         }
 225
 226         nv_mo32(falcon, 0x048, 0x00000003, 0x00000000);
 227         nv_wo32(falcon, 0x014, 0xffffffff);
 228
 229         return nouveau_engine_fini(&falcon->base, suspend);
 230 }
 231
 232 int
 233 nouveau_falcon_create_(struct nouveau_object *parent,
 234                        struct nouveau_object *engine,
 235                        struct nouveau_oclass *oclass, u32 addr, bool enable,
 236                        const char *iname, const char *fname,
 237                        int length, void **pobject)
 238 {
 239         struct nouveau_falcon *falcon;
 240         int ret;
 241
 242         ret = nouveau_engine_create_(parent, engine, oclass, enable, iname,
 243                                      fname, length, pobject);
 244         falcon = *pobject;
 245         if (ret)
 246                 return ret;
 247
 248         falcon->addr = addr;
 249         return 0;
 250 }