drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h

   1 #ifndef __NVKM_DISP_DP_H__
   2 #define __NVKM_DISP_DP_H__
   3 #define nvkm_dp(p) container_of((p), struct nvkm_dp, outp)
   4 #include "outp.h"
   5
   6 #include <core/notify.h>
   7 #include <subdev/bios.h>
   8 #include <subdev/bios/dp.h>
   9
  10 struct nvkm_dp {
  11         const struct nvkm_output_dp_func *func;
  12         union {
  13                 struct nvkm_outp base;
  14                 struct nvkm_outp outp;
  15         };
  16
  17         struct nvbios_dpout info;
  18         u8 version;
  19
  20         struct nvkm_i2c_aux *aux;
  21
  22         struct nvkm_notify irq;
  23         struct nvkm_notify hpd;
  24         bool present;
  25         u8 dpcd[16];
  26
  27         struct mutex mutex;
  28         struct {
  29                 atomic_t done;
  30                 bool mst;
  31         } lt;
  32 };
  33
  34 #define nvkm_output_dp nvkm_dp
  35
  36 struct nvkm_output_dp_func {
  37         int (*pattern)(struct nvkm_output_dp *, int);
  38         int (*lnk_pwr)(struct nvkm_output_dp *, int nr);
  39         int (*lnk_ctl)(struct nvkm_output_dp *, int nr, int bw, bool ef);
  40         int (*drv_ctl)(struct nvkm_output_dp *, int ln, int vs, int pe, int pc);
  41         void (*vcpi)(struct nvkm_output_dp *, int head, u8 start_slot,
  42                      u8 num_slots, u16 pbn, u16 aligned_pbn);
  43 };
  44
  45 int nvkm_output_dp_train(struct nvkm_output *, u32 rate);
  46
  47 int nvkm_output_dp_new_(const struct nvkm_output_dp_func *, struct nvkm_disp *,
  48                         int index, struct dcb_output *, struct nvkm_output **);
  49
  50 int nv50_pior_dp_new(struct nvkm_disp *, int, struct dcb_output *,
  51                      struct nvkm_output **);
  52
  53 int g94_sor_dp_new(struct nvkm_disp *, int, struct dcb_output *,
  54                    struct nvkm_output **);
  55 int g94_sor_dp_lnk_pwr(struct nvkm_dp *, int);
  56
  57 int gf119_sor_dp_new(struct nvkm_disp *, int, struct dcb_output *,
  58                      struct nvkm_output **);
  59 int gf119_sor_dp_lnk_ctl(struct nvkm_dp *, int, int, bool);
  60 int gf119_sor_dp_drv_ctl(struct nvkm_dp *, int, int, int, int);
  61 void gf119_sor_dp_vcpi(struct nvkm_dp *, int, u8, u8, u16, u16);
  62
  63 int gm107_sor_dp_new(struct nvkm_disp *, int, struct dcb_output *,
  64                      struct nvkm_output **);
  65 int gm107_sor_dp_pattern(struct nvkm_dp *, int);
  66
  67 int gm200_sor_dp_new(struct nvkm_disp *, int, struct dcb_output *,
  68                      struct nvkm_output **);
  69
  70 /* DPCD Receiver Capabilities */
  71 #define DPCD_RC00_DPCD_REV                                              0x00000
  72 #define DPCD_RC01_MAX_LINK_RATE                                         0x00001
  73 #define DPCD_RC02                                                       0x00002
  74 #define DPCD_RC02_ENHANCED_FRAME_CAP                                       0x80
  75 #define DPCD_RC02_TPS3_SUPPORTED                                           0x40
  76 #define DPCD_RC02_MAX_LANE_COUNT                                           0x1f
  77 #define DPCD_RC03                                                       0x00003
  78 #define DPCD_RC03_MAX_DOWNSPREAD                                           0x01
  79 #define DPCD_RC0E_AUX_RD_INTERVAL                                       0x0000e
  80
  81 /* DPCD Link Configuration */
  82 #define DPCD_LC00_LINK_BW_SET                                           0x00100
  83 #define DPCD_LC01                                                       0x00101
  84 #define DPCD_LC01_ENHANCED_FRAME_EN                                        0x80
  85 #define DPCD_LC01_LANE_COUNT_SET                                           0x1f
  86 #define DPCD_LC02                                                       0x00102
  87 #define DPCD_LC02_TRAINING_PATTERN_SET                                     0x03
  88 #define DPCD_LC03(l)                                            ((l) +  0x00103)
  89 #define DPCD_LC03_MAX_PRE_EMPHASIS_REACHED                                 0x20
  90 #define DPCD_LC03_PRE_EMPHASIS_SET                                         0x18
  91 #define DPCD_LC03_MAX_SWING_REACHED                                        0x04
  92 #define DPCD_LC03_VOLTAGE_SWING_SET                                        0x03
  93 #define DPCD_LC0F                                                       0x0010f
  94 #define DPCD_LC0F_LANE1_MAX_POST_CURSOR2_REACHED                           0x40
  95 #define DPCD_LC0F_LANE1_POST_CURSOR2_SET                                   0x30
  96 #define DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED                           0x04
  97 #define DPCD_LC0F_LANE0_POST_CURSOR2_SET                                   0x03
  98 #define DPCD_LC10                                                       0x00110
  99 #define DPCD_LC10_LANE3_MAX_POST_CURSOR2_REACHED                           0x40
 100 #define DPCD_LC10_LANE3_POST_CURSOR2_SET                                   0x30
 101 #define DPCD_LC10_LANE2_MAX_POST_CURSOR2_REACHED                           0x04
 102 #define DPCD_LC10_LANE2_POST_CURSOR2_SET                                   0x03
 103
 104 /* DPCD Link/Sink Status */
 105 #define DPCD_LS02                                                       0x00202
 106 #define DPCD_LS02_LANE1_SYMBOL_LOCKED                                      0x40
 107 #define DPCD_LS02_LANE1_CHANNEL_EQ_DONE                                    0x20
 108 #define DPCD_LS02_LANE1_CR_DONE                                            0x10
 109 #define DPCD_LS02_LANE0_SYMBOL_LOCKED                                      0x04
 110 #define DPCD_LS02_LANE0_CHANNEL_EQ_DONE                                    0x02
 111 #define DPCD_LS02_LANE0_CR_DONE                                            0x01
 112 #define DPCD_LS03                                                       0x00203
 113 #define DPCD_LS03_LANE3_SYMBOL_LOCKED                                      0x40
 114 #define DPCD_LS03_LANE3_CHANNEL_EQ_DONE                                    0x20
 115 #define DPCD_LS03_LANE3_CR_DONE                                            0x10
 116 #define DPCD_LS03_LANE2_SYMBOL_LOCKED                                      0x04
 117 #define DPCD_LS03_LANE2_CHANNEL_EQ_DONE                                    0x02
 118 #define DPCD_LS03_LANE2_CR_DONE                                            0x01
 119 #define DPCD_LS04                                                       0x00204
 120 #define DPCD_LS04_LINK_STATUS_UPDATED                                      0x80
 121 #define DPCD_LS04_DOWNSTREAM_PORT_STATUS_CHANGED                           0x40
 122 #define DPCD_LS04_INTERLANE_ALIGN_DONE                                     0x01
 123 #define DPCD_LS06                                                       0x00206
 124 #define DPCD_LS06_LANE1_PRE_EMPHASIS                                       0xc0
 125 #define DPCD_LS06_LANE1_VOLTAGE_SWING                                      0x30
 126 #define DPCD_LS06_LANE0_PRE_EMPHASIS                                       0x0c
 127 #define DPCD_LS06_LANE0_VOLTAGE_SWING                                      0x03
 128 #define DPCD_LS07                                                       0x00207
 129 #define DPCD_LS07_LANE3_PRE_EMPHASIS                                       0xc0
 130 #define DPCD_LS07_LANE3_VOLTAGE_SWING                                      0x30
 131 #define DPCD_LS07_LANE2_PRE_EMPHASIS                                       0x0c
 132 #define DPCD_LS07_LANE2_VOLTAGE_SWING                                      0x03
 133 #define DPCD_LS0C                                                       0x0020c
 134 #define DPCD_LS0C_LANE3_POST_CURSOR2                                       0xc0
 135 #define DPCD_LS0C_LANE2_POST_CURSOR2                                       0x30
 136 #define DPCD_LS0C_LANE1_POST_CURSOR2                                       0x0c
 137 #define DPCD_LS0C_LANE0_POST_CURSOR2                                       0x03
 138
 139 /* DPCD Sink Control */
 140 #define DPCD_SC00                                                       0x00600
 141 #define DPCD_SC00_SET_POWER                                                0x03
 142 #define DPCD_SC00_SET_POWER_D0                                             0x01
 143 #define DPCD_SC00_SET_POWER_D3                                             0x03
 144 #endif