drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h

   1 #ifndef __NVKM_DISP_OUTP_DP_H__
   2 #define __NVKM_DISP_OUTP_DP_H__
   3 #define nvkm_output_dp(p) container_of((p), struct nvkm_output_dp, base)
   4 #include "outp.h"
   5
   6 #include <core/notify.h>
   7 #include <subdev/bios.h>
   8 #include <subdev/bios/dp.h>
   9
  10 struct nvkm_output_dp {
  11         const struct nvkm_output_dp_func *func;
  12         struct nvkm_output base;
  13
  14         struct nvbios_dpout info;
  15         u8 version;
  16
  17         struct nvkm_i2c_aux *aux;
  18
  19         struct nvkm_notify irq;
  20         struct nvkm_notify hpd;
  21         bool present;
  22         u8 dpcd[16];
  23
  24         struct mutex mutex;
  25         struct {
  26                 atomic_t done;
  27                 bool mst;
  28         } lt;
  29 };
  30
  31 struct nvkm_output_dp_func {
  32         int (*pattern)(struct nvkm_output_dp *, int);
  33         int (*lnk_pwr)(struct nvkm_output_dp *, int nr);
  34         int (*lnk_ctl)(struct nvkm_output_dp *, int nr, int bw, bool ef);
  35         int (*drv_ctl)(struct nvkm_output_dp *, int ln, int vs, int pe, int pc);
  36         void (*vcpi)(struct nvkm_output_dp *, int head, u8 start_slot,
  37                      u8 num_slots, u16 pbn, u16 aligned_pbn);
  38 };
  39
  40 int nvkm_output_dp_train(struct nvkm_output *, u32 rate);
  41
  42 int nvkm_output_dp_ctor(const struct nvkm_output_dp_func *, struct nvkm_disp *,
  43                         int index, struct dcb_output *, struct nvkm_i2c_aux *,
  44                         struct nvkm_output_dp *);
  45 int nvkm_output_dp_new_(const struct nvkm_output_dp_func *, struct nvkm_disp *,
  46                         int index, struct dcb_output *,
  47                         struct nvkm_output **);
  48
  49 int nv50_pior_dp_new(struct nvkm_disp *, int, struct dcb_output *,
  50                      struct nvkm_output **);
  51
  52 int g94_sor_dp_new(struct nvkm_disp *, int, struct dcb_output *,
  53                    struct nvkm_output **);
  54 int g94_sor_dp_lnk_pwr(struct nvkm_output_dp *, int);
  55
  56 int gf119_sor_dp_new(struct nvkm_disp *, int, struct dcb_output *,
  57                      struct nvkm_output **);
  58 int gf119_sor_dp_lnk_ctl(struct nvkm_output_dp *, int, int, bool);
  59 int gf119_sor_dp_drv_ctl(struct nvkm_output_dp *, int, int, int, int);
  60 void gf119_sor_dp_vcpi(struct nvkm_output_dp *, int, u8, u8, u16, u16);
  61
  62 int gm107_sor_dp_new(struct nvkm_disp *, int, struct dcb_output *,
  63                      struct nvkm_output **);
  64 int gm107_sor_dp_pattern(struct nvkm_output_dp *, int);
  65
  66 int gm200_sor_dp_new(struct nvkm_disp *, int, struct dcb_output *,
  67                      struct nvkm_output **);
  68
  69 /* DPCD Receiver Capabilities */
  70 #define DPCD_RC00_DPCD_REV                                              0x00000
  71 #define DPCD_RC01_MAX_LINK_RATE                                         0x00001
  72 #define DPCD_RC02                                                       0x00002
  73 #define DPCD_RC02_ENHANCED_FRAME_CAP                                       0x80
  74 #define DPCD_RC02_TPS3_SUPPORTED                                           0x40
  75 #define DPCD_RC02_MAX_LANE_COUNT                                           0x1f
  76 #define DPCD_RC03                                                       0x00003
  77 #define DPCD_RC03_MAX_DOWNSPREAD                                           0x01
  78 #define DPCD_RC0E_AUX_RD_INTERVAL                                       0x0000e
  79
  80 /* DPCD Link Configuration */
  81 #define DPCD_LC00_LINK_BW_SET                                           0x00100
  82 #define DPCD_LC01                                                       0x00101
  83 #define DPCD_LC01_ENHANCED_FRAME_EN                                        0x80
  84 #define DPCD_LC01_LANE_COUNT_SET                                           0x1f
  85 #define DPCD_LC02                                                       0x00102
  86 #define DPCD_LC02_TRAINING_PATTERN_SET                                     0x03
  87 #define DPCD_LC03(l)                                            ((l) +  0x00103)
  88 #define DPCD_LC03_MAX_PRE_EMPHASIS_REACHED                                 0x20
  89 #define DPCD_LC03_PRE_EMPHASIS_SET                                         0x18
  90 #define DPCD_LC03_MAX_SWING_REACHED                                        0x04
  91 #define DPCD_LC03_VOLTAGE_SWING_SET                                        0x03
  92 #define DPCD_LC0F                                                       0x0010f
  93 #define DPCD_LC0F_LANE1_MAX_POST_CURSOR2_REACHED                           0x40
  94 #define DPCD_LC0F_LANE1_POST_CURSOR2_SET                                   0x30
  95 #define DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED                           0x04
  96 #define DPCD_LC0F_LANE0_POST_CURSOR2_SET                                   0x03
  97 #define DPCD_LC10                                                       0x00110
  98 #define DPCD_LC10_LANE3_MAX_POST_CURSOR2_REACHED                           0x40
  99 #define DPCD_LC10_LANE3_POST_CURSOR2_SET                                   0x30
 100 #define DPCD_LC10_LANE2_MAX_POST_CURSOR2_REACHED                           0x04
 101 #define DPCD_LC10_LANE2_POST_CURSOR2_SET                                   0x03
 102
 103 /* DPCD Link/Sink Status */
 104 #define DPCD_LS02                                                       0x00202
 105 #define DPCD_LS02_LANE1_SYMBOL_LOCKED                                      0x40
 106 #define DPCD_LS02_LANE1_CHANNEL_EQ_DONE                                    0x20
 107 #define DPCD_LS02_LANE1_CR_DONE                                            0x10
 108 #define DPCD_LS02_LANE0_SYMBOL_LOCKED                                      0x04
 109 #define DPCD_LS02_LANE0_CHANNEL_EQ_DONE                                    0x02
 110 #define DPCD_LS02_LANE0_CR_DONE                                            0x01
 111 #define DPCD_LS03                                                       0x00203
 112 #define DPCD_LS03_LANE3_SYMBOL_LOCKED                                      0x40
 113 #define DPCD_LS03_LANE3_CHANNEL_EQ_DONE                                    0x20
 114 #define DPCD_LS03_LANE3_CR_DONE                                            0x10
 115 #define DPCD_LS03_LANE2_SYMBOL_LOCKED                                      0x04
 116 #define DPCD_LS03_LANE2_CHANNEL_EQ_DONE                                    0x02
 117 #define DPCD_LS03_LANE2_CR_DONE                                            0x01
 118 #define DPCD_LS04                                                       0x00204
 119 #define DPCD_LS04_LINK_STATUS_UPDATED                                      0x80
 120 #define DPCD_LS04_DOWNSTREAM_PORT_STATUS_CHANGED                           0x40
 121 #define DPCD_LS04_INTERLANE_ALIGN_DONE                                     0x01
 122 #define DPCD_LS06                                                       0x00206
 123 #define DPCD_LS06_LANE1_PRE_EMPHASIS                                       0xc0
 124 #define DPCD_LS06_LANE1_VOLTAGE_SWING                                      0x30
 125 #define DPCD_LS06_LANE0_PRE_EMPHASIS                                       0x0c
 126 #define DPCD_LS06_LANE0_VOLTAGE_SWING                                      0x03
 127 #define DPCD_LS07                                                       0x00207
 128 #define DPCD_LS07_LANE3_PRE_EMPHASIS                                       0xc0
 129 #define DPCD_LS07_LANE3_VOLTAGE_SWING                                      0x30
 130 #define DPCD_LS07_LANE2_PRE_EMPHASIS                                       0x0c
 131 #define DPCD_LS07_LANE2_VOLTAGE_SWING                                      0x03
 132 #define DPCD_LS0C                                                       0x0020c
 133 #define DPCD_LS0C_LANE3_POST_CURSOR2                                       0xc0
 134 #define DPCD_LS0C_LANE2_POST_CURSOR2                                       0x30
 135 #define DPCD_LS0C_LANE1_POST_CURSOR2                                       0x0c
 136 #define DPCD_LS0C_LANE0_POST_CURSOR2                                       0x03
 137
 138 /* DPCD Sink Control */
 139 #define DPCD_SC00                                                       0x00600
 140 #define DPCD_SC00_SET_POWER                                                0x03
 141 #define DPCD_SC00_SET_POWER_D0                                             0x01
 142 #define DPCD_SC00_SET_POWER_D3                                             0x03
 143 #endif