2 * Copyright 2012 Red Hat Inc.
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27 #include <subdev/timer.h>
30 gm200_sor_soff(struct nvkm_output_dp *outp)
32 return (ffs(outp->base.info.or) - 1) * 0x800;
36 gm200_sor_loff(struct nvkm_output_dp *outp)
38 return gm200_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80;
42 gm200_sor_dp_lane_map(struct nvkm_device *device, u8 lane)
44 return nvkm_ior_find(device->disp, SOR, -1)->func->dp.lanes[lane] * 8;
48 gm200_sor_dp_drv_ctl(struct nvkm_output_dp *outp,
49 int ln, int vs, int pe, int pc)
51 struct nvkm_device *device = outp->base.disp->engine.subdev.device;
52 struct nvkm_bios *bios = device->bios;
53 const u32 shift = gm200_sor_dp_lane_map(device, ln);
54 const u32 loff = gm200_sor_loff(outp);
56 u8 ver, hdr, cnt, len;
57 struct nvbios_dpout info;
58 struct nvbios_dpcfg ocfg;
60 addr = nvbios_dpout_match(bios, outp->base.info.hasht,
61 outp->base.info.hashm,
62 &ver, &hdr, &cnt, &len, &info);
66 addr = nvbios_dpcfg_match(bios, addr, pc, vs, pe,
67 &ver, &hdr, &cnt, &len, &ocfg);
72 data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift);
73 data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift);
74 data[2] = nvkm_rd32(device, 0x61c130 + loff);
75 if ((data[2] & 0x00000f00) < (ocfg.tx_pu << 8) || ln == 0)
76 data[2] = (data[2] & ~0x00000f00) | (ocfg.tx_pu << 8);
77 nvkm_wr32(device, 0x61c118 + loff, data[0] | (ocfg.dc << shift));
78 nvkm_wr32(device, 0x61c120 + loff, data[1] | (ocfg.pe << shift));
79 nvkm_wr32(device, 0x61c130 + loff, data[2]);
80 data[3] = nvkm_rd32(device, 0x61c13c + loff) & ~(0x000000ff << shift);
81 nvkm_wr32(device, 0x61c13c + loff, data[3] | (ocfg.pc << shift));
86 gm200_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
88 struct nvkm_device *device = outp->base.disp->engine.subdev.device;
89 const u32 soff = gm200_sor_soff(outp);
90 const u32 loff = gm200_sor_loff(outp);
93 for (i = 0; i < nr; i++)
94 mask |= 1 << (gm200_sor_dp_lane_map(device, i) >> 3);
96 nvkm_mask(device, 0x61c130 + loff, 0x0000000f, mask);
97 nvkm_mask(device, 0x61c034 + soff, 0x80000000, 0x80000000);
98 nvkm_msec(device, 2000,
99 if (!(nvkm_rd32(device, 0x61c034 + soff) & 0x80000000))
105 static const struct nvkm_output_dp_func
106 gm200_sor_dp_func = {
107 .pattern = gm107_sor_dp_pattern,
108 .lnk_pwr = gm200_sor_dp_lnk_pwr,
109 .lnk_ctl = gf119_sor_dp_lnk_ctl,
110 .drv_ctl = gm200_sor_dp_drv_ctl,
111 .vcpi = gf119_sor_dp_vcpi,
115 gm200_sor_dp_new(struct nvkm_disp *disp, int index, struct dcb_output *dcbE,
116 struct nvkm_output **poutp)
118 return nvkm_output_dp_new_(&gm200_sor_dp_func, disp, index, dcbE, poutp);
122 gm200_sor_magic(struct nvkm_output *outp)
124 struct nvkm_device *device = outp->disp->engine.subdev.device;
125 const u32 soff = outp->or * 0x100;
126 const u32 data = outp->or + 1;
127 if (outp->info.sorconf.link & 1)
128 nvkm_mask(device, 0x612308 + soff, 0x0000001f, 0x00000000 | data);
129 if (outp->info.sorconf.link & 2)
130 nvkm_mask(device, 0x612388 + soff, 0x0000001f, 0x00000010 | data);
133 static const struct nvkm_ior_func
135 .state = gf119_sor_state,
136 .power = nv50_sor_power,
138 .ctrl = gk104_hdmi_ctrl,
141 .lanes = { 0, 1, 2, 3 },
146 gm200_sor_new(struct nvkm_disp *disp, int id)
148 return nvkm_ior_new_(&gm200_sor, disp, SOR, id);