2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
25 #include <core/gpuobj.h>
26 #include <core/firmware.h>
27 #include <engine/falcon.h>
28 #include <subdev/mc.h>
29 #include <subdev/pmu.h>
30 #include <core/msgqueue.h>
31 #include <engine/sec2.h>
34 * struct hsf_fw_header - HS firmware descriptor
35 * @sig_dbg_offset: offset of the debug signature
36 * @sig_dbg_size: size of the debug signature
37 * @sig_prod_offset: offset of the production signature
38 * @sig_prod_size: size of the production signature
39 * @patch_loc: offset of the offset (sic) of where the signature is
40 * @patch_sig: offset of the offset (sic) to add to sig_*_offset
41 * @hdr_offset: offset of the load header (see struct hs_load_header)
42 * @hdr_size: size of above header
44 * This structure is embedded in the HS firmware image at
45 * hs_bin_hdr.header_offset.
47 struct hsf_fw_header {
59 * struct acr_r352_flcn_bl_desc - DMEM bootloader descriptor
60 * @signature: 16B signature for secure code. 0s if no secure code
61 * @ctx_dma: DMA context to be used by BL while loading code/data
62 * @code_dma_base: 256B-aligned Physical FB Address where code is located
63 * (falcon's $xcbase register)
64 * @non_sec_code_off: offset from code_dma_base where the non-secure code is
65 * located. The offset must be multiple of 256 to help perf
66 * @non_sec_code_size: the size of the nonSecure code part.
67 * @sec_code_off: offset from code_dma_base where the secure code is
68 * located. The offset must be multiple of 256 to help perf
69 * @sec_code_size: offset from code_dma_base where the secure code is
70 * located. The offset must be multiple of 256 to help perf
71 * @code_entry_point: code entry point which will be invoked by BL after
73 * @data_dma_base: 256B aligned Physical FB Address where data is located.
74 * (falcon's $xdbase register)
75 * @data_size: size of data block. Should be multiple of 256B
77 * Structure used by the bootloader to load the rest of the code. This has
78 * to be filled by host and copied into DMEM at offset provided in the
79 * hsflcn_bl_desc.bl_desc_dmem_load_off.
81 struct acr_r352_flcn_bl_desc {
87 u32 non_sec_code_size;
98 * acr_r352_generate_flcn_bl_desc - generate generic BL descriptor for LS image
101 acr_r352_generate_flcn_bl_desc(const struct nvkm_acr *acr,
102 const struct ls_ucode_img *img, u64 wpr_addr,
105 struct acr_r352_flcn_bl_desc *desc = _desc;
106 const struct ls_ucode_img_desc *pdesc = &img->ucode_desc;
107 u64 base, addr_code, addr_data;
109 base = wpr_addr + img->ucode_off + pdesc->app_start_offset;
110 addr_code = (base + pdesc->app_resident_code_offset) >> 8;
111 addr_data = (base + pdesc->app_resident_data_offset) >> 8;
113 desc->ctx_dma = FALCON_DMAIDX_UCODE;
114 desc->code_dma_base = lower_32_bits(addr_code);
115 desc->code_dma_base1 = upper_32_bits(addr_code);
116 desc->non_sec_code_off = pdesc->app_resident_code_offset;
117 desc->non_sec_code_size = pdesc->app_resident_code_size;
118 desc->code_entry_point = pdesc->app_imem_entry;
119 desc->data_dma_base = lower_32_bits(addr_data);
120 desc->data_dma_base1 = upper_32_bits(addr_data);
121 desc->data_size = pdesc->app_resident_data_size;
126 * struct hsflcn_acr_desc - data section of the HS firmware
128 * This header is to be copied at the beginning of DMEM by the HS bootloader.
130 * @signature: signature of ACR ucode
131 * @wpr_region_id: region ID holding the WPR header and its details
132 * @wpr_offset: offset from the WPR region holding the wpr header
133 * @regions: region descriptors
134 * @nonwpr_ucode_blob_size: size of LS blob
135 * @nonwpr_ucode_blob_start: FB location of LS blob is
137 struct hsflcn_acr_desc {
139 u8 reserved_dmem[0x200];
141 } ucode_reserved_space;
145 #define FLCN_ACR_MAX_REGIONS 2
155 } region_props[FLCN_ACR_MAX_REGIONS];
158 u64 ucode_blob_base __aligned(8);
169 * Low-secure blob creation
173 * struct acr_r352_lsf_lsb_header - LS firmware header
174 * @signature: signature to verify the firmware against
175 * @ucode_off: offset of the ucode blob in the WPR region. The ucode
176 * blob contains the bootloader, code and data of the
178 * @ucode_size: size of the ucode blob, including bootloader
179 * @data_size: size of the ucode blob data
180 * @bl_code_size: size of the bootloader code
181 * @bl_imem_off: offset in imem of the bootloader
182 * @bl_data_off: offset of the bootloader data in WPR region
183 * @bl_data_size: size of the bootloader data
184 * @app_code_off: offset of the app code relative to ucode_off
185 * @app_code_size: size of the app code
186 * @app_data_off: offset of the app data relative to ucode_off
187 * @app_data_size: size of the app data
188 * @flags: flags for the secure bootloader
190 * This structure is written into the WPR region for each managed falcon. Each
191 * instance is referenced by the lsb_offset member of the corresponding
194 struct acr_r352_lsf_lsb_header {
196 * LS falcon signatures
197 * @prd_keys: signature to use in production mode
198 * @dgb_keys: signature to use in debug mode
199 * @b_prd_present: whether the production key is present
200 * @b_dgb_present: whether the debug key is present
201 * @falcon_id: ID of the falcon the ucode applies to
225 * struct acr_r352_lsf_wpr_header - LS blob WPR Header
226 * @falcon_id: LS falcon ID
227 * @lsb_offset: offset of the lsb_lsf_header in the WPR region
228 * @bootstrap_owner: secure falcon reponsible for bootstrapping the LS falcon
229 * @lazy_bootstrap: skip bootstrapping by ACR
230 * @status: bootstrapping status
232 * An array of these is written at the beginning of the WPR region, one for
233 * each managed falcon. The array is terminated by an instance which falcon_id
234 * is LSF_FALCON_ID_INVALID.
236 struct acr_r352_lsf_wpr_header {
242 #define LSF_IMAGE_STATUS_NONE 0
243 #define LSF_IMAGE_STATUS_COPY 1
244 #define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED 2
245 #define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED 3
246 #define LSF_IMAGE_STATUS_VALIDATION_DONE 4
247 #define LSF_IMAGE_STATUS_VALIDATION_SKIPPED 5
248 #define LSF_IMAGE_STATUS_BOOTSTRAP_READY 6
252 * struct ls_ucode_img_r352 - ucode image augmented with r352 headers
254 struct ls_ucode_img_r352 {
255 struct ls_ucode_img base;
257 struct acr_r352_lsf_wpr_header wpr_header;
258 struct acr_r352_lsf_lsb_header lsb_header;
260 #define ls_ucode_img_r352(i) container_of(i, struct ls_ucode_img_r352, base)
263 * ls_ucode_img_load() - create a lsf_ucode_img and load it
265 struct ls_ucode_img *
266 acr_r352_ls_ucode_img_load(const struct acr_r352 *acr,
267 enum nvkm_secboot_falcon falcon_id)
269 const struct nvkm_subdev *subdev = acr->base.subdev;
270 struct ls_ucode_img_r352 *img;
273 img = kzalloc(sizeof(*img), GFP_KERNEL);
275 return ERR_PTR(-ENOMEM);
277 img->base.falcon_id = falcon_id;
279 ret = acr->func->ls_func[falcon_id]->load(subdev, &img->base);
282 kfree(img->base.ucode_data);
283 kfree(img->base.sig);
288 /* Check that the signature size matches our expectations... */
289 if (img->base.sig_size != sizeof(img->lsb_header.signature)) {
290 nvkm_error(subdev, "invalid signature size for %s falcon!\n",
291 nvkm_secboot_falcon_name[falcon_id]);
292 return ERR_PTR(-EINVAL);
295 /* Copy signature to the right place */
296 memcpy(&img->lsb_header.signature, img->base.sig, img->base.sig_size);
298 /* not needed? the signature should already have the right value */
299 img->lsb_header.signature.falcon_id = falcon_id;
304 #define LSF_LSB_HEADER_ALIGN 256
305 #define LSF_BL_DATA_ALIGN 256
306 #define LSF_BL_DATA_SIZE_ALIGN 256
307 #define LSF_BL_CODE_SIZE_ALIGN 256
308 #define LSF_UCODE_DATA_ALIGN 4096
311 * acr_r352_ls_img_fill_headers - fill the WPR and LSB headers of an image
313 * @img: image to generate for
314 * @offset: offset in the WPR region where this image starts
316 * Allocate space in the WPR area from offset and write the WPR and LSB headers
319 * Return: offset at the end of this image.
322 acr_r352_ls_img_fill_headers(struct acr_r352 *acr,
323 struct ls_ucode_img_r352 *img, u32 offset)
325 struct ls_ucode_img *_img = &img->base;
326 struct acr_r352_lsf_wpr_header *whdr = &img->wpr_header;
327 struct acr_r352_lsf_lsb_header *lhdr = &img->lsb_header;
328 struct ls_ucode_img_desc *desc = &_img->ucode_desc;
329 const struct acr_r352_ls_func *func =
330 acr->func->ls_func[_img->falcon_id];
332 /* Fill WPR header */
333 whdr->falcon_id = _img->falcon_id;
334 whdr->bootstrap_owner = acr->base.boot_falcon;
335 whdr->status = LSF_IMAGE_STATUS_COPY;
337 /* Skip bootstrapping falcons started by someone else than ACR */
338 if (acr->lazy_bootstrap & BIT(_img->falcon_id))
339 whdr->lazy_bootstrap = 1;
341 /* Align, save off, and include an LSB header size */
342 offset = ALIGN(offset, LSF_LSB_HEADER_ALIGN);
343 whdr->lsb_offset = offset;
344 offset += sizeof(*lhdr);
347 * Align, save off, and include the original (static) ucode
350 offset = ALIGN(offset, LSF_UCODE_DATA_ALIGN);
351 _img->ucode_off = lhdr->ucode_off = offset;
352 offset += _img->ucode_size;
355 * For falcons that use a boot loader (BL), we append a loader
356 * desc structure on the end of the ucode image and consider
357 * this the boot loader data. The host will then copy the loader
358 * desc args to this space within the WPR region (before locking
359 * down) and the HS bin will then copy them to DMEM 0 for the
362 lhdr->bl_code_size = ALIGN(desc->bootloader_size,
363 LSF_BL_CODE_SIZE_ALIGN);
364 lhdr->ucode_size = ALIGN(desc->app_resident_data_offset,
365 LSF_BL_CODE_SIZE_ALIGN) + lhdr->bl_code_size;
366 lhdr->data_size = ALIGN(desc->app_size, LSF_BL_CODE_SIZE_ALIGN) +
367 lhdr->bl_code_size - lhdr->ucode_size;
369 * Though the BL is located at 0th offset of the image, the VA
370 * is different to make sure that it doesn't collide the actual
373 lhdr->bl_imem_off = desc->bootloader_imem_offset;
374 lhdr->app_code_off = desc->app_start_offset +
375 desc->app_resident_code_offset;
376 lhdr->app_code_size = desc->app_resident_code_size;
377 lhdr->app_data_off = desc->app_start_offset +
378 desc->app_resident_data_offset;
379 lhdr->app_data_size = desc->app_resident_data_size;
381 lhdr->flags = func->lhdr_flags;
382 if (_img->falcon_id == acr->base.boot_falcon)
383 lhdr->flags |= LSF_FLAG_DMACTL_REQ_CTX;
385 /* Align and save off BL descriptor size */
386 lhdr->bl_data_size = ALIGN(func->bl_desc_size, LSF_BL_DATA_SIZE_ALIGN);
389 * Align, save off, and include the additional BL data
391 offset = ALIGN(offset, LSF_BL_DATA_ALIGN);
392 lhdr->bl_data_off = offset;
393 offset += lhdr->bl_data_size;
399 * acr_r352_ls_fill_headers - fill WPR and LSB headers of all managed images
402 acr_r352_ls_fill_headers(struct acr_r352 *acr, struct list_head *imgs)
404 struct ls_ucode_img_r352 *img;
409 /* Count the number of images to manage */
410 list_for_each(l, imgs)
414 * Start with an array of WPR headers at the base of the WPR.
415 * The expectation here is that the secure falcon will do a single DMA
416 * read of this array and cache it internally so it's ok to pack these.
417 * Also, we add 1 to the falcon count to indicate the end of the array.
419 offset = sizeof(img->wpr_header) * (count + 1);
422 * Walk the managed falcons, accounting for the LSB structs
423 * as well as the ucode images.
425 list_for_each_entry(img, imgs, base.node) {
426 offset = acr_r352_ls_img_fill_headers(acr, img, offset);
433 * acr_r352_ls_write_wpr - write the WPR blob contents
436 acr_r352_ls_write_wpr(struct acr_r352 *acr, struct list_head *imgs,
437 struct nvkm_gpuobj *wpr_blob, u64 wpr_addr)
439 struct ls_ucode_img *_img;
444 list_for_each_entry(_img, imgs, node) {
445 struct ls_ucode_img_r352 *img = ls_ucode_img_r352(_img);
446 const struct acr_r352_ls_func *ls_func =
447 acr->func->ls_func[_img->falcon_id];
448 u8 gdesc[ls_func->bl_desc_size];
450 nvkm_gpuobj_memcpy_to(wpr_blob, pos, &img->wpr_header,
451 sizeof(img->wpr_header));
453 nvkm_gpuobj_memcpy_to(wpr_blob, img->wpr_header.lsb_offset,
454 &img->lsb_header, sizeof(img->lsb_header));
456 /* Generate and write BL descriptor */
457 memset(gdesc, 0, ls_func->bl_desc_size);
458 ls_func->generate_bl_desc(&acr->base, _img, wpr_addr, gdesc);
460 nvkm_gpuobj_memcpy_to(wpr_blob, img->lsb_header.bl_data_off,
461 gdesc, ls_func->bl_desc_size);
464 nvkm_gpuobj_memcpy_to(wpr_blob, img->lsb_header.ucode_off,
465 _img->ucode_data, _img->ucode_size);
467 pos += sizeof(img->wpr_header);
470 nvkm_wo32(wpr_blob, pos, NVKM_SECBOOT_FALCON_INVALID);
477 /* Both size and address of WPR need to be 256K-aligned */
478 #define WPR_ALIGNMENT 0x40000
480 * acr_r352_prepare_ls_blob() - prepare the LS blob
482 * For each securely managed falcon, load the FW, signatures and bootloaders and
483 * prepare a ucode blob. Then, compute the offsets in the WPR region for each
484 * blob, and finally write the headers and ucode blobs into a GPU object that
485 * will be copied into the WPR region by the HS firmware.
488 acr_r352_prepare_ls_blob(struct acr_r352 *acr, u64 wpr_addr, u32 wpr_size)
490 const struct nvkm_subdev *subdev = acr->base.subdev;
491 struct list_head imgs;
492 struct ls_ucode_img *img, *t;
493 unsigned long managed_falcons = acr->base.managed_falcons;
494 int managed_count = 0;
495 u32 image_wpr_size, ls_blob_size;
499 INIT_LIST_HEAD(&imgs);
501 /* Load all LS blobs */
502 for_each_set_bit(falcon_id, &managed_falcons, NVKM_SECBOOT_FALCON_END) {
503 struct ls_ucode_img *img;
505 img = acr->func->ls_ucode_img_load(acr, falcon_id);
507 if (acr->base.optional_falcons & BIT(falcon_id)) {
508 managed_falcons &= ~BIT(falcon_id);
509 nvkm_info(subdev, "skipping %s falcon...\n",
510 nvkm_secboot_falcon_name[falcon_id]);
517 list_add_tail(&img->node, &imgs);
521 /* Commit the actual list of falcons we will manage from now on */
522 acr->base.managed_falcons = managed_falcons;
525 * If the boot falcon has a firmare, let it manage the bootstrap of other
528 if (acr->func->ls_func[acr->base.boot_falcon] &&
529 (managed_falcons & BIT(acr->base.boot_falcon))) {
530 for_each_set_bit(falcon_id, &managed_falcons,
531 NVKM_SECBOOT_FALCON_END) {
532 if (falcon_id == acr->base.boot_falcon)
535 acr->lazy_bootstrap |= BIT(falcon_id);
540 * Fill the WPR and LSF headers with the right offsets and compute
543 image_wpr_size = acr->func->ls_fill_headers(acr, &imgs);
544 image_wpr_size = ALIGN(image_wpr_size, WPR_ALIGNMENT);
546 ls_blob_size = image_wpr_size;
549 * If we need a shadow area, allocate twice the size and use the
552 if (wpr_size == 0 && acr->func->shadow_blob)
555 /* Allocate GPU object that will contain the WPR region */
556 ret = nvkm_gpuobj_new(subdev->device, ls_blob_size, WPR_ALIGNMENT,
557 false, NULL, &acr->ls_blob);
561 nvkm_debug(subdev, "%d managed LS falcons, WPR size is %d bytes\n",
562 managed_count, image_wpr_size);
564 /* If WPR address and size are not fixed, set them to fit the LS blob */
566 wpr_addr = acr->ls_blob->addr;
567 if (acr->func->shadow_blob)
568 wpr_addr += acr->ls_blob->size / 2;
570 wpr_size = image_wpr_size;
572 * But if the WPR region is set by the bootloader, it is illegal for
573 * the HS blob to be larger than this region.
575 } else if (image_wpr_size > wpr_size) {
576 nvkm_error(subdev, "WPR region too small for FW blob!\n");
577 nvkm_error(subdev, "required: %dB\n", image_wpr_size);
578 nvkm_error(subdev, "available: %dB\n", wpr_size);
584 ret = acr->func->ls_write_wpr(acr, &imgs, acr->ls_blob, wpr_addr);
586 nvkm_gpuobj_del(&acr->ls_blob);
589 list_for_each_entry_safe(img, t, &imgs, node) {
590 kfree(img->ucode_data);
602 * acr_r352_hsf_patch_signature() - patch HS blob with correct signature
605 acr_r352_hsf_patch_signature(struct nvkm_secboot *sb, void *acr_image)
607 struct fw_bin_header *hsbin_hdr = acr_image;
608 struct hsf_fw_header *fw_hdr = acr_image + hsbin_hdr->header_offset;
609 void *hs_data = acr_image + hsbin_hdr->data_offset;
613 /* Falcon in debug or production mode? */
614 if (sb->boot_falcon->debug) {
615 sig = acr_image + fw_hdr->sig_dbg_offset;
616 sig_size = fw_hdr->sig_dbg_size;
618 sig = acr_image + fw_hdr->sig_prod_offset;
619 sig_size = fw_hdr->sig_prod_size;
622 /* Patch signature */
623 memcpy(hs_data + fw_hdr->patch_loc, sig + fw_hdr->patch_sig, sig_size);
627 acr_r352_fixup_hs_desc(struct acr_r352 *acr, struct nvkm_secboot *sb,
630 struct hsflcn_acr_desc *desc = _desc;
631 struct nvkm_gpuobj *ls_blob = acr->ls_blob;
633 /* WPR region information if WPR is not fixed */
634 if (sb->wpr_size == 0) {
635 u64 wpr_start = ls_blob->addr;
636 u64 wpr_end = wpr_start + ls_blob->size;
638 desc->wpr_region_id = 1;
639 desc->regions.no_regions = 2;
640 desc->regions.region_props[0].start_addr = wpr_start >> 8;
641 desc->regions.region_props[0].end_addr = wpr_end >> 8;
642 desc->regions.region_props[0].region_id = 1;
643 desc->regions.region_props[0].read_mask = 0xf;
644 desc->regions.region_props[0].write_mask = 0xc;
645 desc->regions.region_props[0].client_mask = 0x2;
647 desc->ucode_blob_base = ls_blob->addr;
648 desc->ucode_blob_size = ls_blob->size;
653 acr_r352_generate_hs_bl_desc(const struct hsf_load_header *hdr, void *_bl_desc,
656 struct acr_r352_flcn_bl_desc *bl_desc = _bl_desc;
657 u64 addr_code, addr_data;
659 addr_code = offset >> 8;
660 addr_data = (offset + hdr->data_dma_base) >> 8;
662 bl_desc->ctx_dma = FALCON_DMAIDX_VIRT;
663 bl_desc->code_dma_base = lower_32_bits(addr_code);
664 bl_desc->non_sec_code_off = hdr->non_sec_code_off;
665 bl_desc->non_sec_code_size = hdr->non_sec_code_size;
666 bl_desc->sec_code_off = hsf_load_header_app_off(hdr, 0);
667 bl_desc->sec_code_size = hsf_load_header_app_size(hdr, 0);
668 bl_desc->code_entry_point = 0;
669 bl_desc->data_dma_base = lower_32_bits(addr_data);
670 bl_desc->data_size = hdr->data_size;
674 * acr_r352_prepare_hs_blob - load and prepare a HS blob and BL descriptor
676 * @sb secure boot instance to prepare for
677 * @fw name of the HS firmware to load
678 * @blob pointer to gpuobj that will be allocated to receive the HS FW payload
679 * @bl_desc pointer to the BL descriptor to write for this firmware
680 * @patch whether we should patch the HS descriptor (only for HS loaders)
683 acr_r352_prepare_hs_blob(struct acr_r352 *acr, struct nvkm_secboot *sb,
684 const char *fw, struct nvkm_gpuobj **blob,
685 struct hsf_load_header *load_header, bool patch)
687 struct nvkm_subdev *subdev = &sb->subdev;
689 struct fw_bin_header *hsbin_hdr;
690 struct hsf_fw_header *fw_hdr;
691 struct hsf_load_header *load_hdr;
695 acr_image = nvkm_acr_load_firmware(subdev, fw, 0);
696 if (IS_ERR(acr_image))
697 return PTR_ERR(acr_image);
699 hsbin_hdr = acr_image;
700 fw_hdr = acr_image + hsbin_hdr->header_offset;
701 load_hdr = acr_image + fw_hdr->hdr_offset;
702 acr_data = acr_image + hsbin_hdr->data_offset;
704 /* Patch signature */
705 acr_r352_hsf_patch_signature(sb, acr_image);
707 /* Patch descriptor with WPR information? */
709 struct hsflcn_acr_desc *desc;
711 desc = acr_data + load_hdr->data_dma_base;
712 acr->func->fixup_hs_desc(acr, sb, desc);
715 if (load_hdr->num_apps > ACR_R352_MAX_APPS) {
716 nvkm_error(subdev, "more apps (%d) than supported (%d)!",
717 load_hdr->num_apps, ACR_R352_MAX_APPS);
721 memcpy(load_header, load_hdr, sizeof(*load_header) +
722 (sizeof(load_hdr->apps[0]) * 2 * load_hdr->num_apps));
724 /* Create ACR blob and copy HS data to it */
725 ret = nvkm_gpuobj_new(subdev->device, ALIGN(hsbin_hdr->data_size, 256),
726 0x1000, false, NULL, blob);
731 nvkm_gpuobj_memcpy_to(*blob, 0, acr_data, hsbin_hdr->data_size);
741 acr_r352_prepare_hsbl_blob(struct acr_r352 *acr)
743 const struct nvkm_subdev *subdev = acr->base.subdev;
744 struct fw_bin_header *hdr;
745 struct fw_bl_desc *hsbl_desc;
747 acr->hsbl_blob = nvkm_acr_load_firmware(subdev, "acr/bl", 0);
748 if (IS_ERR(acr->hsbl_blob)) {
749 int ret = PTR_ERR(acr->hsbl_blob);
751 acr->hsbl_blob = NULL;
755 hdr = acr->hsbl_blob;
756 hsbl_desc = acr->hsbl_blob + hdr->header_offset;
762 * acr_r352_load_blobs - load blobs common to all ACR V1 versions.
764 * This includes the LS blob, HS ucode loading blob, and HS bootloader.
766 * The HS ucode unload blob is only used on dGPU if the WPR region is variable.
769 acr_r352_load_blobs(struct acr_r352 *acr, struct nvkm_secboot *sb)
773 /* Firmware already loaded? */
774 if (acr->firmware_ok)
777 /* Load and prepare the managed falcon's firmwares */
778 ret = acr_r352_prepare_ls_blob(acr, sb->wpr_addr, sb->wpr_size);
782 /* Load the HS firmware that will load the LS firmwares */
783 if (!acr->load_blob) {
784 ret = acr_r352_prepare_hs_blob(acr, sb, "acr/ucode_load",
786 &acr->load_bl_header, true);
791 /* If the ACR region is dynamically programmed, we need an unload FW */
792 if (sb->wpr_size == 0) {
793 ret = acr_r352_prepare_hs_blob(acr, sb, "acr/ucode_unload",
795 &acr->unload_bl_header, false);
800 /* Load the HS firmware bootloader */
801 if (!acr->hsbl_blob) {
802 ret = acr_r352_prepare_hsbl_blob(acr);
807 acr->firmware_ok = true;
808 nvkm_debug(&sb->subdev, "LS blob successfully created\n");
814 * acr_r352_load() - prepare HS falcon to run the specified blob, mapped.
816 * Returns the start address to use, or a negative error value.
819 acr_r352_load(struct nvkm_acr *_acr, struct nvkm_falcon *falcon,
820 struct nvkm_gpuobj *blob, u64 offset)
822 struct acr_r352 *acr = acr_r352(_acr);
823 struct fw_bin_header *hdr = acr->hsbl_blob;
824 struct fw_bl_desc *hsbl_desc = acr->hsbl_blob + hdr->header_offset;
825 void *blob_data = acr->hsbl_blob + hdr->data_offset;
826 void *hsbl_code = blob_data + hsbl_desc->code_off;
827 void *hsbl_data = blob_data + hsbl_desc->data_off;
828 u32 code_size = ALIGN(hsbl_desc->code_size, 256);
829 const struct hsf_load_header *load_hdr;
830 const u32 bl_desc_size = acr->func->hs_bl_desc_size;
831 u8 bl_desc[bl_desc_size];
833 /* Find the bootloader descriptor for our blob and copy it */
834 if (blob == acr->load_blob) {
835 load_hdr = &acr->load_bl_header;
836 } else if (blob == acr->unload_blob) {
837 load_hdr = &acr->unload_bl_header;
839 nvkm_error(_acr->subdev, "invalid secure boot blob!\n");
844 * Copy HS bootloader data
846 nvkm_falcon_load_dmem(falcon, hsbl_data, 0x0, hsbl_desc->data_size, 0);
848 /* Copy HS bootloader code to end of IMEM */
849 nvkm_falcon_load_imem(falcon, hsbl_code, falcon->code.limit - code_size,
850 code_size, hsbl_desc->start_tag, 0, false);
852 /* Generate the BL header */
853 memset(bl_desc, 0, bl_desc_size);
854 acr->func->generate_hs_bl_desc(load_hdr, bl_desc, offset);
857 * Copy HS BL header where the HS descriptor expects it to be
859 nvkm_falcon_load_dmem(falcon, bl_desc, hsbl_desc->dmem_load_off,
862 return hsbl_desc->start_tag << 8;
866 acr_r352_shutdown(struct acr_r352 *acr, struct nvkm_secboot *sb)
868 struct nvkm_subdev *subdev = &sb->subdev;
871 /* Run the unload blob to unprotect the WPR region */
872 if (acr->unload_blob && sb->wpr_set) {
875 nvkm_debug(subdev, "running HS unload blob\n");
876 ret = sb->func->run_blob(sb, acr->unload_blob, sb->halt_falcon);
880 * Unload blob will return this error code - it is not an error
881 * and the expected behavior on RM as well
883 if (ret && ret != 0x1d) {
884 nvkm_error(subdev, "HS unload failed, ret 0x%08x", ret);
887 nvkm_debug(subdev, "HS unload blob completed\n");
890 for (i = 0; i < NVKM_SECBOOT_FALCON_END; i++)
891 acr->falcon_state[i] = NON_SECURE;
899 * Check if the WPR region has been indeed set by the ACR firmware, and
900 * matches where it should be.
903 acr_r352_wpr_is_set(const struct acr_r352 *acr, const struct nvkm_secboot *sb)
905 const struct nvkm_subdev *subdev = &sb->subdev;
906 const struct nvkm_device *device = subdev->device;
908 u64 wpr_range_lo, wpr_range_hi;
910 nvkm_wr32(device, 0x100cd4, 0x2);
911 wpr_lo = (nvkm_rd32(device, 0x100cd4) & ~0xff);
913 nvkm_wr32(device, 0x100cd4, 0x3);
914 wpr_hi = (nvkm_rd32(device, 0x100cd4) & ~0xff);
917 if (sb->wpr_size != 0) {
918 wpr_range_lo = sb->wpr_addr;
919 wpr_range_hi = wpr_range_lo + sb->wpr_size;
921 wpr_range_lo = acr->ls_blob->addr;
922 wpr_range_hi = wpr_range_lo + acr->ls_blob->size;
925 return (wpr_lo >= wpr_range_lo && wpr_lo < wpr_range_hi &&
926 wpr_hi > wpr_range_lo && wpr_hi <= wpr_range_hi);
930 acr_r352_bootstrap(struct acr_r352 *acr, struct nvkm_secboot *sb)
932 const struct nvkm_subdev *subdev = &sb->subdev;
933 unsigned long managed_falcons = acr->base.managed_falcons;
940 /* Make sure all blobs are ready */
941 ret = acr_r352_load_blobs(acr, sb);
945 nvkm_debug(subdev, "running HS load blob\n");
946 ret = sb->func->run_blob(sb, acr->load_blob, sb->boot_falcon);
947 /* clear halt interrupt */
948 nvkm_falcon_clear_interrupt(sb->boot_falcon, 0x10);
949 sb->wpr_set = acr_r352_wpr_is_set(acr, sb);
952 } else if (ret > 0) {
953 nvkm_error(subdev, "HS load failed, ret 0x%08x", ret);
956 nvkm_debug(subdev, "HS load blob completed\n");
957 /* WPR must be set at this point */
959 nvkm_error(subdev, "ACR blob completed but WPR not set!\n");
963 /* Run LS firmwares post_run hooks */
964 for_each_set_bit(falcon_id, &managed_falcons, NVKM_SECBOOT_FALCON_END) {
965 const struct acr_r352_ls_func *func =
966 acr->func->ls_func[falcon_id];
969 func->post_run(&acr->base, sb);
972 /* Re-start ourselves if we are managed */
973 if (!nvkm_secboot_is_managed(sb, acr->base.boot_falcon))
976 /* Enable interrupts */
977 nvkm_falcon_wr32(sb->boot_falcon, 0x10, 0xff);
978 nvkm_mc_intr_mask(subdev->device, sb->boot_falcon->owner->index, true);
980 /* Start LS firmware on boot falcon */
981 nvkm_falcon_start(sb->boot_falcon);
982 nvkm_debug(subdev, "%s started\n",
983 nvkm_secboot_falcon_name[acr->base.boot_falcon]);
989 * acr_r352_reset_nopmu - dummy reset method when no PMU firmware is loaded
991 * Reset is done by re-executing secure boot from scratch, with lazy bootstrap
992 * disabled. This has the effect of making all managed falcons ready-to-run.
995 acr_r352_reset_nopmu(struct acr_r352 *acr, struct nvkm_secboot *sb,
996 enum nvkm_secboot_falcon falcon)
1001 * Perform secure boot each time we are called on FECS. Since only FECS
1002 * and GPCCS are managed and started together, this ought to be safe.
1004 if (falcon != NVKM_SECBOOT_FALCON_FECS)
1007 ret = acr_r352_shutdown(acr, sb);
1011 ret = acr_r352_bootstrap(acr, sb);
1016 acr->falcon_state[falcon] = RESET;
1021 * acr_r352_reset() - execute secure boot from the prepared state
1023 * Load the HS bootloader and ask the falcon to run it. This will in turn
1024 * load the HS firmware and run it, so once the falcon stops all the managed
1025 * falcons should have their LS firmware loaded and be ready to run.
1028 acr_r352_reset(struct nvkm_acr *_acr, struct nvkm_secboot *sb,
1029 enum nvkm_secboot_falcon falcon)
1031 struct acr_r352 *acr = acr_r352(_acr);
1032 struct nvkm_msgqueue *queue;
1033 const char *fname = nvkm_secboot_falcon_name[falcon];
1034 bool wpr_already_set = sb->wpr_set;
1037 /* Make sure secure boot is performed */
1038 ret = acr_r352_bootstrap(acr, sb);
1042 /* No PMU interface? */
1043 if (!nvkm_secboot_is_managed(sb, _acr->boot_falcon)) {
1044 /* Redo secure boot entirely if it was already done */
1045 if (wpr_already_set)
1046 return acr_r352_reset_nopmu(acr, sb, falcon);
1047 /* Else return the result of the initial invokation */
1052 switch (_acr->boot_falcon) {
1053 case NVKM_SECBOOT_FALCON_PMU:
1054 queue = sb->subdev.device->pmu->queue;
1056 case NVKM_SECBOOT_FALCON_SEC2:
1057 queue = sb->subdev.device->sec2->queue;
1063 /* Otherwise just ask the LS firmware to reset the falcon */
1064 nvkm_debug(&sb->subdev, "resetting %s falcon\n", fname);
1065 ret = nvkm_msgqueue_acr_boot_falcon(queue, falcon);
1067 nvkm_error(&sb->subdev, "cannot boot %s falcon\n", fname);
1070 nvkm_debug(&sb->subdev, "falcon %s reset\n", fname);
1076 acr_r352_fini(struct nvkm_acr *_acr, struct nvkm_secboot *sb, bool suspend)
1078 struct acr_r352 *acr = acr_r352(_acr);
1080 return acr_r352_shutdown(acr, sb);
1084 acr_r352_dtor(struct nvkm_acr *_acr)
1086 struct acr_r352 *acr = acr_r352(_acr);
1088 nvkm_gpuobj_del(&acr->unload_blob);
1090 kfree(acr->hsbl_blob);
1091 nvkm_gpuobj_del(&acr->load_blob);
1092 nvkm_gpuobj_del(&acr->ls_blob);
1097 const struct acr_r352_ls_func
1098 acr_r352_ls_fecs_func = {
1099 .load = acr_ls_ucode_load_fecs,
1100 .generate_bl_desc = acr_r352_generate_flcn_bl_desc,
1101 .bl_desc_size = sizeof(struct acr_r352_flcn_bl_desc),
1104 const struct acr_r352_ls_func
1105 acr_r352_ls_gpccs_func = {
1106 .load = acr_ls_ucode_load_gpccs,
1107 .generate_bl_desc = acr_r352_generate_flcn_bl_desc,
1108 .bl_desc_size = sizeof(struct acr_r352_flcn_bl_desc),
1109 /* GPCCS will be loaded using PRI */
1110 .lhdr_flags = LSF_FLAG_FORCE_PRIV_LOAD,
1116 * struct acr_r352_pmu_bl_desc - PMU DMEM bootloader descriptor
1117 * @dma_idx: DMA context to be used by BL while loading code/data
1118 * @code_dma_base: 256B-aligned Physical FB Address where code is located
1119 * @total_code_size: total size of the code part in the ucode
1120 * @code_size_to_load: size of the code part to load in PMU IMEM.
1121 * @code_entry_point: entry point in the code.
1122 * @data_dma_base: Physical FB address where data part of ucode is located
1123 * @data_size: Total size of the data portion.
1124 * @overlay_dma_base: Physical Fb address for resident code present in ucode
1125 * @argc: Total number of args
1126 * @argv: offset where args are copied into PMU's DMEM.
1128 * Structure used by the PMU bootloader to load the rest of the code
1130 struct acr_r352_pmu_bl_desc {
1133 u32 code_size_total;
1134 u32 code_size_to_load;
1135 u32 code_entry_point;
1138 u32 overlay_dma_base;
1143 u16 overlay_dma_base1;
1147 * acr_r352_generate_pmu_bl_desc() - populate a DMEM BL descriptor for PMU LS image
1151 acr_r352_generate_pmu_bl_desc(const struct nvkm_acr *acr,
1152 const struct ls_ucode_img *img, u64 wpr_addr,
1155 const struct ls_ucode_img_desc *pdesc = &img->ucode_desc;
1156 const struct nvkm_pmu *pmu = acr->subdev->device->pmu;
1157 struct acr_r352_pmu_bl_desc *desc = _desc;
1163 base = wpr_addr + img->ucode_off + pdesc->app_start_offset;
1164 addr_code = (base + pdesc->app_resident_code_offset) >> 8;
1165 addr_data = (base + pdesc->app_resident_data_offset) >> 8;
1166 addr_args = pmu->falcon->data.limit;
1167 addr_args -= NVKM_MSGQUEUE_CMDLINE_SIZE;
1169 desc->dma_idx = FALCON_DMAIDX_UCODE;
1170 desc->code_dma_base = lower_32_bits(addr_code);
1171 desc->code_dma_base1 = upper_32_bits(addr_code);
1172 desc->code_size_total = pdesc->app_size;
1173 desc->code_size_to_load = pdesc->app_resident_code_size;
1174 desc->code_entry_point = pdesc->app_imem_entry;
1175 desc->data_dma_base = lower_32_bits(addr_data);
1176 desc->data_dma_base1 = upper_32_bits(addr_data);
1177 desc->data_size = pdesc->app_resident_data_size;
1178 desc->overlay_dma_base = lower_32_bits(addr_code);
1179 desc->overlay_dma_base1 = upper_32_bits(addr_code);
1181 desc->argv = addr_args;
1184 static const struct acr_r352_ls_func
1185 acr_r352_ls_pmu_func = {
1186 .load = acr_ls_ucode_load_pmu,
1187 .generate_bl_desc = acr_r352_generate_pmu_bl_desc,
1188 .bl_desc_size = sizeof(struct acr_r352_pmu_bl_desc),
1189 .post_run = acr_ls_pmu_post_run,
1192 const struct acr_r352_func
1194 .fixup_hs_desc = acr_r352_fixup_hs_desc,
1195 .generate_hs_bl_desc = acr_r352_generate_hs_bl_desc,
1196 .hs_bl_desc_size = sizeof(struct acr_r352_flcn_bl_desc),
1197 .ls_ucode_img_load = acr_r352_ls_ucode_img_load,
1198 .ls_fill_headers = acr_r352_ls_fill_headers,
1199 .ls_write_wpr = acr_r352_ls_write_wpr,
1201 [NVKM_SECBOOT_FALCON_FECS] = &acr_r352_ls_fecs_func,
1202 [NVKM_SECBOOT_FALCON_GPCCS] = &acr_r352_ls_gpccs_func,
1203 [NVKM_SECBOOT_FALCON_PMU] = &acr_r352_ls_pmu_func,
1207 static const struct nvkm_acr_func
1208 acr_r352_base_func = {
1209 .dtor = acr_r352_dtor,
1210 .fini = acr_r352_fini,
1211 .load = acr_r352_load,
1212 .reset = acr_r352_reset,
1216 acr_r352_new_(const struct acr_r352_func *func,
1217 enum nvkm_secboot_falcon boot_falcon,
1218 unsigned long managed_falcons)
1220 struct acr_r352 *acr;
1223 /* Check that all requested falcons are supported */
1224 for_each_set_bit(i, &managed_falcons, NVKM_SECBOOT_FALCON_END) {
1225 if (!func->ls_func[i])
1226 return ERR_PTR(-ENOTSUPP);
1229 acr = kzalloc(sizeof(*acr), GFP_KERNEL);
1231 return ERR_PTR(-ENOMEM);
1233 acr->base.boot_falcon = boot_falcon;
1234 acr->base.managed_falcons = managed_falcons;
1235 acr->base.func = &acr_r352_base_func;
1242 acr_r352_new(unsigned long managed_falcons)
1244 return acr_r352_new_(&acr_r352_func, NVKM_SECBOOT_FALCON_PMU,