drivers/gpu/drm/radeon/evergreend.h

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #ifndef EVERGREEND_H
  25 #define EVERGREEND_H
  26
  27 #define EVERGREEN_MAX_SH_GPRS           256
  28 #define EVERGREEN_MAX_TEMP_GPRS         16
  29 #define EVERGREEN_MAX_SH_THREADS        256
  30 #define EVERGREEN_MAX_SH_STACK_ENTRIES  4096
  31 #define EVERGREEN_MAX_FRC_EOV_CNT       16384
  32 #define EVERGREEN_MAX_BACKENDS          8
  33 #define EVERGREEN_MAX_BACKENDS_MASK     0xFF
  34 #define EVERGREEN_MAX_SIMDS             16
  35 #define EVERGREEN_MAX_SIMDS_MASK        0xFFFF
  36 #define EVERGREEN_MAX_PIPES             8
  37 #define EVERGREEN_MAX_PIPES_MASK        0xFF
  38 #define EVERGREEN_MAX_LDS_NUM           0xFFFF
  39
  40 /* Registers */
  41
  42 #define RCU_IND_INDEX                                   0x100
  43 #define RCU_IND_DATA                                    0x104
  44
  45 #define GRBM_GFX_INDEX                                  0x802C
  46 #define         INSTANCE_INDEX(x)                       ((x) << 0)
  47 #define         SE_INDEX(x)                             ((x) << 16)
  48 #define         INSTANCE_BROADCAST_WRITES               (1 << 30)
  49 #define         SE_BROADCAST_WRITES                     (1 << 31)
  50 #define RLC_GFX_INDEX                                   0x3fC4
  51 #define CC_GC_SHADER_PIPE_CONFIG                        0x8950
  52 #define         WRITE_DIS                               (1 << 0)
  53 #define CC_RB_BACKEND_DISABLE                           0x98F4
  54 #define         BACKEND_DISABLE(x)                      ((x) << 16)
  55 #define GB_ADDR_CONFIG                                  0x98F8
  56 #define         NUM_PIPES(x)                            ((x) << 0)
  57 #define         PIPE_INTERLEAVE_SIZE(x)                 ((x) << 4)
  58 #define         BANK_INTERLEAVE_SIZE(x)                 ((x) << 8)
  59 #define         NUM_SHADER_ENGINES(x)                   ((x) << 12)
  60 #define         SHADER_ENGINE_TILE_SIZE(x)              ((x) << 16)
  61 #define         NUM_GPUS(x)                             ((x) << 20)
  62 #define         MULTI_GPU_TILE_SIZE(x)                  ((x) << 24)
  63 #define         ROW_SIZE(x)                             ((x) << 28)
  64 #define GB_BACKEND_MAP                                  0x98FC
  65 #define DMIF_ADDR_CONFIG                                0xBD4
  66 #define HDP_ADDR_CONFIG                                 0x2F48
  67
  68 #define CC_SYS_RB_BACKEND_DISABLE                       0x3F88
  69 #define GC_USER_RB_BACKEND_DISABLE                      0x9B7C
  70
  71 #define CGTS_SYS_TCC_DISABLE                            0x3F90
  72 #define CGTS_TCC_DISABLE                                0x9148
  73 #define CGTS_USER_SYS_TCC_DISABLE                       0x3F94
  74 #define CGTS_USER_TCC_DISABLE                           0x914C
  75
  76 #define CONFIG_MEMSIZE                                  0x5428
  77
  78 #define CP_ME_CNTL                                      0x86D8
  79 #define         CP_ME_HALT                                      (1 << 28)
  80 #define         CP_PFP_HALT                                     (1 << 26)
  81 #define CP_ME_RAM_DATA                                  0xC160
  82 #define CP_ME_RAM_RADDR                                 0xC158
  83 #define CP_ME_RAM_WADDR                                 0xC15C
  84 #define CP_MEQ_THRESHOLDS                               0x8764
  85 #define         STQ_SPLIT(x)                                    ((x) << 0)
  86 #define CP_PERFMON_CNTL                                 0x87FC
  87 #define CP_PFP_UCODE_ADDR                               0xC150
  88 #define CP_PFP_UCODE_DATA                               0xC154
  89 #define CP_QUEUE_THRESHOLDS                             0x8760
  90 #define         ROQ_IB1_START(x)                                ((x) << 0)
  91 #define         ROQ_IB2_START(x)                                ((x) << 8)
  92 #define CP_RB_CNTL                                      0xC104
  93 #define         RB_BUFSZ(x)                                     ((x) << 0)
  94 #define         RB_BLKSZ(x)                                     ((x) << 8)
  95 #define         RB_NO_UPDATE                                    (1 << 27)
  96 #define         RB_RPTR_WR_ENA                                  (1 << 31)
  97 #define         BUF_SWAP_32BIT                                  (2 << 16)
  98 #define CP_RB_RPTR                                      0x8700
  99 #define CP_RB_RPTR_ADDR                                 0xC10C
 100 #define CP_RB_RPTR_ADDR_HI                              0xC110
 101 #define CP_RB_RPTR_WR                                   0xC108
 102 #define CP_RB_WPTR                                      0xC114
 103 #define CP_RB_WPTR_ADDR                                 0xC118
 104 #define CP_RB_WPTR_ADDR_HI                              0xC11C
 105 #define CP_RB_WPTR_DELAY                                0x8704
 106 #define CP_SEM_WAIT_TIMER                               0x85BC
 107
 108
 109 #define GC_USER_SHADER_PIPE_CONFIG                      0x8954
 110 #define         INACTIVE_QD_PIPES(x)                            ((x) << 8)
 111 #define         INACTIVE_QD_PIPES_MASK                          0x0000FF00
 112 #define         INACTIVE_SIMDS(x)                               ((x) << 16)
 113 #define         INACTIVE_SIMDS_MASK                             0x00FF0000
 114
 115 #define GRBM_CNTL                                       0x8000
 116 #define         GRBM_READ_TIMEOUT(x)                            ((x) << 0)
 117 #define GRBM_SOFT_RESET                                 0x8020
 118 #define         SOFT_RESET_CP                                   (1 << 0)
 119 #define         SOFT_RESET_CB                                   (1 << 1)
 120 #define         SOFT_RESET_DB                                   (1 << 3)
 121 #define         SOFT_RESET_PA                                   (1 << 5)
 122 #define         SOFT_RESET_SC                                   (1 << 6)
 123 #define         SOFT_RESET_SPI                                  (1 << 8)
 124 #define         SOFT_RESET_SH                                   (1 << 9)
 125 #define         SOFT_RESET_SX                                   (1 << 10)
 126 #define         SOFT_RESET_TC                                   (1 << 11)
 127 #define         SOFT_RESET_TA                                   (1 << 12)
 128 #define         SOFT_RESET_VC                                   (1 << 13)
 129 #define         SOFT_RESET_VGT                                  (1 << 14)
 130
 131 #define GRBM_STATUS                                     0x8010
 132 #define         CMDFIFO_AVAIL_MASK                              0x0000000F
 133 #define         SRBM_RQ_PENDING                                 (1 << 5)
 134 #define         CF_RQ_PENDING                                   (1 << 7)
 135 #define         PF_RQ_PENDING                                   (1 << 8)
 136 #define         GRBM_EE_BUSY                                    (1 << 10)
 137 #define         SX_CLEAN                                        (1 << 11)
 138 #define         DB_CLEAN                                        (1 << 12)
 139 #define         CB_CLEAN                                        (1 << 13)
 140 #define         TA_BUSY                                         (1 << 14)
 141 #define         VGT_BUSY_NO_DMA                                 (1 << 16)
 142 #define         VGT_BUSY                                        (1 << 17)
 143 #define         SX_BUSY                                         (1 << 20)
 144 #define         SH_BUSY                                         (1 << 21)
 145 #define         SPI_BUSY                                        (1 << 22)
 146 #define         SC_BUSY                                         (1 << 24)
 147 #define         PA_BUSY                                         (1 << 25)
 148 #define         DB_BUSY                                         (1 << 26)
 149 #define         CP_COHERENCY_BUSY                               (1 << 28)
 150 #define         CP_BUSY                                         (1 << 29)
 151 #define         CB_BUSY                                         (1 << 30)
 152 #define         GUI_ACTIVE                                      (1 << 31)
 153 #define GRBM_STATUS_SE0                                 0x8014
 154 #define GRBM_STATUS_SE1                                 0x8018
 155 #define         SE_SX_CLEAN                                     (1 << 0)
 156 #define         SE_DB_CLEAN                                     (1 << 1)
 157 #define         SE_CB_CLEAN                                     (1 << 2)
 158 #define         SE_TA_BUSY                                      (1 << 25)
 159 #define         SE_SX_BUSY                                      (1 << 26)
 160 #define         SE_SPI_BUSY                                     (1 << 27)
 161 #define         SE_SH_BUSY                                      (1 << 28)
 162 #define         SE_SC_BUSY                                      (1 << 29)
 163 #define         SE_DB_BUSY                                      (1 << 30)
 164 #define         SE_CB_BUSY                                      (1 << 31)
 165
 166 #define HDP_HOST_PATH_CNTL                              0x2C00
 167 #define HDP_NONSURFACE_BASE                             0x2C04
 168 #define HDP_NONSURFACE_INFO                             0x2C08
 169 #define HDP_NONSURFACE_SIZE                             0x2C0C
 170 #define HDP_REG_COHERENCY_FLUSH_CNTL                    0x54A0
 171 #define HDP_TILING_CONFIG                               0x2F3C
 172
 173 #define MC_SHARED_CHMAP                                         0x2004
 174 #define         NOOFCHAN_SHIFT                                  12
 175 #define         NOOFCHAN_MASK                                   0x00003000
 176
 177 #define MC_ARB_RAMCFG                                   0x2760
 178 #define         NOOFBANK_SHIFT                                  0
 179 #define         NOOFBANK_MASK                                   0x00000003
 180 #define         NOOFRANK_SHIFT                                  2
 181 #define         NOOFRANK_MASK                                   0x00000004
 182 #define         NOOFROWS_SHIFT                                  3
 183 #define         NOOFROWS_MASK                                   0x00000038
 184 #define         NOOFCOLS_SHIFT                                  6
 185 #define         NOOFCOLS_MASK                                   0x000000C0
 186 #define         CHANSIZE_SHIFT                                  8
 187 #define         CHANSIZE_MASK                                   0x00000100
 188 #define         BURSTLENGTH_SHIFT                               9
 189 #define         BURSTLENGTH_MASK                                0x00000200
 190 #define         CHANSIZE_OVERRIDE                               (1 << 11)
 191 #define MC_VM_AGP_TOP                                   0x2028
 192 #define MC_VM_AGP_BOT                                   0x202C
 193 #define MC_VM_AGP_BASE                                  0x2030
 194 #define MC_VM_FB_LOCATION                               0x2024
 195 #define MC_VM_MB_L1_TLB0_CNTL                           0x2234
 196 #define MC_VM_MB_L1_TLB1_CNTL                           0x2238
 197 #define MC_VM_MB_L1_TLB2_CNTL                           0x223C
 198 #define MC_VM_MB_L1_TLB3_CNTL                           0x2240
 199 #define         ENABLE_L1_TLB                                   (1 << 0)
 200 #define         ENABLE_L1_FRAGMENT_PROCESSING                   (1 << 1)
 201 #define         SYSTEM_ACCESS_MODE_PA_ONLY                      (0 << 3)
 202 #define         SYSTEM_ACCESS_MODE_USE_SYS_MAP                  (1 << 3)
 203 #define         SYSTEM_ACCESS_MODE_IN_SYS                       (2 << 3)
 204 #define         SYSTEM_ACCESS_MODE_NOT_IN_SYS                   (3 << 3)
 205 #define         SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU       (0 << 5)
 206 #define         EFFECTIVE_L1_TLB_SIZE(x)                        ((x)<<15)
 207 #define         EFFECTIVE_L1_QUEUE_SIZE(x)                      ((x)<<18)
 208 #define MC_VM_MD_L1_TLB0_CNTL                           0x2654
 209 #define MC_VM_MD_L1_TLB1_CNTL                           0x2658
 210 #define MC_VM_MD_L1_TLB2_CNTL                           0x265C
 211 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR              0x203C
 212 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR                 0x2038
 213 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR                  0x2034
 214
 215 #define PA_CL_ENHANCE                                   0x8A14
 216 #define         CLIP_VTX_REORDER_ENA                            (1 << 0)
 217 #define         NUM_CLIP_SEQ(x)                                 ((x) << 1)
 218 #define PA_SC_AA_CONFIG                                 0x28C04
 219 #define PA_SC_CLIPRECT_RULE                             0x2820C
 220 #define PA_SC_EDGERULE                                  0x28230
 221 #define PA_SC_FIFO_SIZE                                 0x8BCC
 222 #define         SC_PRIM_FIFO_SIZE(x)                            ((x) << 0)
 223 #define         SC_HIZ_TILE_FIFO_SIZE(x)                        ((x) << 12)
 224 #define         SC_EARLYZ_TILE_FIFO_SIZE(x)                     ((x) << 20)
 225 #define PA_SC_FORCE_EOV_MAX_CNTS                        0x8B24
 226 #define         FORCE_EOV_MAX_CLK_CNT(x)                        ((x) << 0)
 227 #define         FORCE_EOV_MAX_REZ_CNT(x)                        ((x) << 16)
 228 #define PA_SC_LINE_STIPPLE                              0x28A0C
 229 #define PA_SC_LINE_STIPPLE_STATE                        0x8B10
 230
 231 #define SCRATCH_REG0                                    0x8500
 232 #define SCRATCH_REG1                                    0x8504
 233 #define SCRATCH_REG2                                    0x8508
 234 #define SCRATCH_REG3                                    0x850C
 235 #define SCRATCH_REG4                                    0x8510
 236 #define SCRATCH_REG5                                    0x8514
 237 #define SCRATCH_REG6                                    0x8518
 238 #define SCRATCH_REG7                                    0x851C
 239 #define SCRATCH_UMSK                                    0x8540
 240 #define SCRATCH_ADDR                                    0x8544
 241
 242 #define SMX_DC_CTL0                                     0xA020
 243 #define         USE_HASH_FUNCTION                               (1 << 0)
 244 #define         NUMBER_OF_SETS(x)                               ((x) << 1)
 245 #define         FLUSH_ALL_ON_EVENT                              (1 << 10)
 246 #define         STALL_ON_EVENT                                  (1 << 11)
 247 #define SMX_EVENT_CTL                                   0xA02C
 248 #define         ES_FLUSH_CTL(x)                                 ((x) << 0)
 249 #define         GS_FLUSH_CTL(x)                                 ((x) << 3)
 250 #define         ACK_FLUSH_CTL(x)                                ((x) << 6)
 251 #define         SYNC_FLUSH_CTL                                  (1 << 8)
 252
 253 #define SPI_CONFIG_CNTL                                 0x9100
 254 #define         GPR_WRITE_PRIORITY(x)                           ((x) << 0)
 255 #define SPI_CONFIG_CNTL_1                               0x913C
 256 #define         VTX_DONE_DELAY(x)                               ((x) << 0)
 257 #define         INTERP_ONE_PRIM_PER_ROW                         (1 << 4)
 258 #define SPI_INPUT_Z                                     0x286D8
 259 #define SPI_PS_IN_CONTROL_0                             0x286CC
 260 #define         NUM_INTERP(x)                                   ((x)<<0)
 261 #define         POSITION_ENA                                    (1<<8)
 262 #define         POSITION_CENTROID                               (1<<9)
 263 #define         POSITION_ADDR(x)                                ((x)<<10)
 264 #define         PARAM_GEN(x)                                    ((x)<<15)
 265 #define         PARAM_GEN_ADDR(x)                               ((x)<<19)
 266 #define         BARYC_SAMPLE_CNTL(x)                            ((x)<<26)
 267 #define         PERSP_GRADIENT_ENA                              (1<<28)
 268 #define         LINEAR_GRADIENT_ENA                             (1<<29)
 269 #define         POSITION_SAMPLE                                 (1<<30)
 270 #define         BARYC_AT_SAMPLE_ENA                             (1<<31)
 271
 272 #define SQ_CONFIG                                       0x8C00
 273 #define         VC_ENABLE                                       (1 << 0)
 274 #define         EXPORT_SRC_C                                    (1 << 1)
 275 #define         CS_PRIO(x)                                      ((x) << 18)
 276 #define         LS_PRIO(x)                                      ((x) << 20)
 277 #define         HS_PRIO(x)                                      ((x) << 22)
 278 #define         PS_PRIO(x)                                      ((x) << 24)
 279 #define         VS_PRIO(x)                                      ((x) << 26)
 280 #define         GS_PRIO(x)                                      ((x) << 28)
 281 #define         ES_PRIO(x)                                      ((x) << 30)
 282 #define SQ_GPR_RESOURCE_MGMT_1                          0x8C04
 283 #define         NUM_PS_GPRS(x)                                  ((x) << 0)
 284 #define         NUM_VS_GPRS(x)                                  ((x) << 16)
 285 #define         NUM_CLAUSE_TEMP_GPRS(x)                         ((x) << 28)
 286 #define SQ_GPR_RESOURCE_MGMT_2                          0x8C08
 287 #define         NUM_GS_GPRS(x)                                  ((x) << 0)
 288 #define         NUM_ES_GPRS(x)                                  ((x) << 16)
 289 #define SQ_GPR_RESOURCE_MGMT_3                          0x8C0C
 290 #define         NUM_HS_GPRS(x)                                  ((x) << 0)
 291 #define         NUM_LS_GPRS(x)                                  ((x) << 16)
 292 #define SQ_THREAD_RESOURCE_MGMT                         0x8C18
 293 #define         NUM_PS_THREADS(x)                               ((x) << 0)
 294 #define         NUM_VS_THREADS(x)                               ((x) << 8)
 295 #define         NUM_GS_THREADS(x)                               ((x) << 16)
 296 #define         NUM_ES_THREADS(x)                               ((x) << 24)
 297 #define SQ_THREAD_RESOURCE_MGMT_2                       0x8C1C
 298 #define         NUM_HS_THREADS(x)                               ((x) << 0)
 299 #define         NUM_LS_THREADS(x)                               ((x) << 8)
 300 #define SQ_STACK_RESOURCE_MGMT_1                        0x8C20
 301 #define         NUM_PS_STACK_ENTRIES(x)                         ((x) << 0)
 302 #define         NUM_VS_STACK_ENTRIES(x)                         ((x) << 16)
 303 #define SQ_STACK_RESOURCE_MGMT_2                        0x8C24
 304 #define         NUM_GS_STACK_ENTRIES(x)                         ((x) << 0)
 305 #define         NUM_ES_STACK_ENTRIES(x)                         ((x) << 16)
 306 #define SQ_STACK_RESOURCE_MGMT_3                        0x8C28
 307 #define         NUM_HS_STACK_ENTRIES(x)                         ((x) << 0)
 308 #define         NUM_LS_STACK_ENTRIES(x)                         ((x) << 16)
 309 #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ                    0x8D8C
 310 #define SQ_LDS_RESOURCE_MGMT                            0x8E2C
 311
 312 #define SQ_MS_FIFO_SIZES                                0x8CF0
 313 #define         CACHE_FIFO_SIZE(x)                              ((x) << 0)
 314 #define         FETCH_FIFO_HIWATER(x)                           ((x) << 8)
 315 #define         DONE_FIFO_HIWATER(x)                            ((x) << 16)
 316 #define         ALU_UPDATE_FIFO_HIWATER(x)                      ((x) << 24)
 317
 318 #define SX_DEBUG_1                                      0x9058
 319 #define         ENABLE_NEW_SMX_ADDRESS                          (1 << 16)
 320 #define SX_EXPORT_BUFFER_SIZES                          0x900C
 321 #define         COLOR_BUFFER_SIZE(x)                            ((x) << 0)
 322 #define         POSITION_BUFFER_SIZE(x)                         ((x) << 8)
 323 #define         SMX_BUFFER_SIZE(x)                              ((x) << 16)
 324 #define SX_MISC                                         0x28350
 325
 326 #define CB_PERF_CTR0_SEL_0                              0x9A20
 327 #define CB_PERF_CTR0_SEL_1                              0x9A24
 328 #define CB_PERF_CTR1_SEL_0                              0x9A28
 329 #define CB_PERF_CTR1_SEL_1                              0x9A2C
 330 #define CB_PERF_CTR2_SEL_0                              0x9A30
 331 #define CB_PERF_CTR2_SEL_1                              0x9A34
 332 #define CB_PERF_CTR3_SEL_0                              0x9A38
 333 #define CB_PERF_CTR3_SEL_1                              0x9A3C
 334
 335 #define TA_CNTL_AUX                                     0x9508
 336 #define         DISABLE_CUBE_WRAP                               (1 << 0)
 337 #define         DISABLE_CUBE_ANISO                              (1 << 1)
 338 #define         SYNC_GRADIENT                                   (1 << 24)
 339 #define         SYNC_WALKER                                     (1 << 25)
 340 #define         SYNC_ALIGNER                                    (1 << 26)
 341
 342 #define VGT_CACHE_INVALIDATION                          0x88C4
 343 #define         CACHE_INVALIDATION(x)                           ((x) << 0)
 344 #define                 VC_ONLY                                         0
 345 #define                 TC_ONLY                                         1
 346 #define                 VC_AND_TC                                       2
 347 #define         AUTO_INVLD_EN(x)                                ((x) << 6)
 348 #define                 NO_AUTO                                         0
 349 #define                 ES_AUTO                                         1
 350 #define                 GS_AUTO                                         2
 351 #define                 ES_AND_GS_AUTO                                  3
 352 #define VGT_GS_VERTEX_REUSE                             0x88D4
 353 #define VGT_NUM_INSTANCES                               0x8974
 354 #define VGT_OUT_DEALLOC_CNTL                            0x28C5C
 355 #define         DEALLOC_DIST_MASK                               0x0000007F
 356 #define VGT_VERTEX_REUSE_BLOCK_CNTL                     0x28C58
 357 #define         VTX_REUSE_DEPTH_MASK                            0x000000FF
 358
 359 #define VM_CONTEXT0_CNTL                                0x1410
 360 #define         ENABLE_CONTEXT                                  (1 << 0)
 361 #define         PAGE_TABLE_DEPTH(x)                             (((x) & 3) << 1)
 362 #define         RANGE_PROTECTION_FAULT_ENABLE_DEFAULT           (1 << 4)
 363 #define VM_CONTEXT1_CNTL                                0x1414
 364 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR                0x153C
 365 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR                 0x157C
 366 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR               0x155C
 367 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR       0x1518
 368 #define VM_CONTEXT0_REQUEST_RESPONSE                    0x1470
 369 #define         REQUEST_TYPE(x)                                 (((x) & 0xf) << 0)
 370 #define         RESPONSE_TYPE_MASK                              0x000000F0
 371 #define         RESPONSE_TYPE_SHIFT                             4
 372 #define VM_L2_CNTL                                      0x1400
 373 #define         ENABLE_L2_CACHE                                 (1 << 0)
 374 #define         ENABLE_L2_FRAGMENT_PROCESSING                   (1 << 1)
 375 #define         ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE         (1 << 9)
 376 #define         EFFECTIVE_L2_QUEUE_SIZE(x)                      (((x) & 7) << 14)
 377 #define VM_L2_CNTL2                                     0x1404
 378 #define         INVALIDATE_ALL_L1_TLBS                          (1 << 0)
 379 #define         INVALIDATE_L2_CACHE                             (1 << 1)
 380 #define VM_L2_CNTL3                                     0x1408
 381 #define         BANK_SELECT(x)                                  ((x) << 0)
 382 #define         CACHE_UPDATE_MODE(x)                            ((x) << 6)
 383 #define VM_L2_STATUS                                    0x140C
 384 #define         L2_BUSY                                         (1 << 0)
 385
 386 #define WAIT_UNTIL                                      0x8040
 387
 388 #define SRBM_STATUS                                     0x0E50
 389 #define SRBM_SOFT_RESET                                 0x0E60
 390 #define         SRBM_SOFT_RESET_ALL_MASK                0x00FEEFA6
 391 #define         SOFT_RESET_BIF                          (1 << 1)
 392 #define         SOFT_RESET_CG                           (1 << 2)
 393 #define         SOFT_RESET_DC                           (1 << 5)
 394 #define         SOFT_RESET_GRBM                         (1 << 8)
 395 #define         SOFT_RESET_HDP                          (1 << 9)
 396 #define         SOFT_RESET_IH                           (1 << 10)
 397 #define         SOFT_RESET_MC                           (1 << 11)
 398 #define         SOFT_RESET_RLC                          (1 << 13)
 399 #define         SOFT_RESET_ROM                          (1 << 14)
 400 #define         SOFT_RESET_SEM                          (1 << 15)
 401 #define         SOFT_RESET_VMC                          (1 << 17)
 402 #define         SOFT_RESET_TST                          (1 << 21)
 403 #define         SOFT_RESET_REGBB                        (1 << 22)
 404 #define         SOFT_RESET_ORB                          (1 << 23)
 405
 406 #endif