2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include "atom-bits.h"
33 /* from radeon_encoder.c */
35 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
37 extern void radeon_link_encoder_connector(struct drm_device *dev);
39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
40 uint32_t supported_device, u16 caps);
42 /* from radeon_connector.c */
44 radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 uint32_t igp_lane_info,
50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
54 /* from radeon_legacy_encoder.c */
56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
57 uint32_t supported_device);
60 static int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
61 u16 voltage_id, u16 *voltage);
63 union atom_supported_devices {
64 struct _ATOM_SUPPORTED_DEVICES_INFO info;
65 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
66 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
69 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
70 ATOM_GPIO_I2C_ASSIGMENT *gpio,
73 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
74 if ((rdev->family == CHIP_R420) ||
75 (rdev->family == CHIP_R423) ||
76 (rdev->family == CHIP_RV410)) {
77 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
78 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
79 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
80 gpio->ucClkMaskShift = 0x19;
81 gpio->ucDataMaskShift = 0x18;
85 /* some evergreen boards have bad data for this entry */
86 if (ASIC_IS_DCE4(rdev)) {
88 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
89 (gpio->sucI2cId.ucAccess == 0)) {
90 gpio->sucI2cId.ucAccess = 0x97;
91 gpio->ucDataMaskShift = 8;
92 gpio->ucDataEnShift = 8;
93 gpio->ucDataY_Shift = 8;
94 gpio->ucDataA_Shift = 8;
98 /* some DCE3 boards have bad data for this entry */
99 if (ASIC_IS_DCE3(rdev)) {
101 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
102 (gpio->sucI2cId.ucAccess == 0x94))
103 gpio->sucI2cId.ucAccess = 0x14;
107 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
109 struct radeon_i2c_bus_rec i2c;
111 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
113 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
114 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
115 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
116 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
117 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
118 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
119 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
120 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
121 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
122 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
123 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
124 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
125 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
126 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
127 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
128 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
130 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
131 i2c.hw_capable = true;
133 i2c.hw_capable = false;
135 if (gpio->sucI2cId.ucAccess == 0xa0)
140 i2c.i2c_id = gpio->sucI2cId.ucAccess;
142 if (i2c.mask_clk_reg)
150 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
153 struct atom_context *ctx = rdev->mode_info.atom_context;
154 ATOM_GPIO_I2C_ASSIGMENT *gpio;
155 struct radeon_i2c_bus_rec i2c;
156 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
157 struct _ATOM_GPIO_I2C_INFO *i2c_info;
158 uint16_t data_offset, size;
161 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
164 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
165 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
167 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
168 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
170 for (i = 0; i < num_indices; i++) {
171 gpio = &i2c_info->asGPIO_Info[i];
173 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
175 if (gpio->sucI2cId.ucAccess == id) {
176 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
185 void radeon_atombios_i2c_init(struct radeon_device *rdev)
187 struct atom_context *ctx = rdev->mode_info.atom_context;
188 ATOM_GPIO_I2C_ASSIGMENT *gpio;
189 struct radeon_i2c_bus_rec i2c;
190 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
191 struct _ATOM_GPIO_I2C_INFO *i2c_info;
192 uint16_t data_offset, size;
196 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
197 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
199 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
200 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
202 for (i = 0; i < num_indices; i++) {
203 gpio = &i2c_info->asGPIO_Info[i];
205 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
207 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
210 sprintf(stmp, "0x%x", i2c.i2c_id);
211 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
217 static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
220 struct atom_context *ctx = rdev->mode_info.atom_context;
221 struct radeon_gpio_rec gpio;
222 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
223 struct _ATOM_GPIO_PIN_LUT *gpio_info;
224 ATOM_GPIO_PIN_ASSIGNMENT *pin;
225 u16 data_offset, size;
228 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
231 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
232 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
234 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
235 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
237 for (i = 0; i < num_indices; i++) {
238 pin = &gpio_info->asGPIO_Pin[i];
239 if (id == pin->ucGPIO_ID) {
240 gpio.id = pin->ucGPIO_ID;
241 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
242 gpio.mask = (1 << pin->ucGpioPinBitShift);
252 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
253 struct radeon_gpio_rec *gpio)
255 struct radeon_hpd hpd;
258 memset(&hpd, 0, sizeof(struct radeon_hpd));
260 if (ASIC_IS_DCE6(rdev))
261 reg = SI_DC_GPIO_HPD_A;
262 else if (ASIC_IS_DCE4(rdev))
263 reg = EVERGREEN_DC_GPIO_HPD_A;
265 reg = AVIVO_DC_GPIO_HPD_A;
268 if (gpio->reg == reg) {
271 hpd.hpd = RADEON_HPD_1;
274 hpd.hpd = RADEON_HPD_2;
277 hpd.hpd = RADEON_HPD_3;
280 hpd.hpd = RADEON_HPD_4;
283 hpd.hpd = RADEON_HPD_5;
286 hpd.hpd = RADEON_HPD_6;
289 hpd.hpd = RADEON_HPD_NONE;
293 hpd.hpd = RADEON_HPD_NONE;
297 static bool radeon_atom_apply_quirks(struct drm_device *dev,
298 uint32_t supported_device,
300 struct radeon_i2c_bus_rec *i2c_bus,
302 struct radeon_hpd *hpd)
305 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
306 if ((dev->pdev->device == 0x791e) &&
307 (dev->pdev->subsystem_vendor == 0x1043) &&
308 (dev->pdev->subsystem_device == 0x826d)) {
309 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
310 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
311 *connector_type = DRM_MODE_CONNECTOR_DVID;
314 /* Asrock RS600 board lists the DVI port as HDMI */
315 if ((dev->pdev->device == 0x7941) &&
316 (dev->pdev->subsystem_vendor == 0x1849) &&
317 (dev->pdev->subsystem_device == 0x7941)) {
318 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
319 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
320 *connector_type = DRM_MODE_CONNECTOR_DVID;
323 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
324 if ((dev->pdev->device == 0x796e) &&
325 (dev->pdev->subsystem_vendor == 0x1462) &&
326 (dev->pdev->subsystem_device == 0x7302)) {
327 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
328 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
332 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
333 if ((dev->pdev->device == 0x7941) &&
334 (dev->pdev->subsystem_vendor == 0x147b) &&
335 (dev->pdev->subsystem_device == 0x2412)) {
336 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
340 /* Falcon NW laptop lists vga ddc line for LVDS */
341 if ((dev->pdev->device == 0x5653) &&
342 (dev->pdev->subsystem_vendor == 0x1462) &&
343 (dev->pdev->subsystem_device == 0x0291)) {
344 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
345 i2c_bus->valid = false;
350 /* HIS X1300 is DVI+VGA, not DVI+DVI */
351 if ((dev->pdev->device == 0x7146) &&
352 (dev->pdev->subsystem_vendor == 0x17af) &&
353 (dev->pdev->subsystem_device == 0x2058)) {
354 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
358 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
359 if ((dev->pdev->device == 0x7142) &&
360 (dev->pdev->subsystem_vendor == 0x1458) &&
361 (dev->pdev->subsystem_device == 0x2134)) {
362 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
368 if ((dev->pdev->device == 0x71C5) &&
369 (dev->pdev->subsystem_vendor == 0x106b) &&
370 (dev->pdev->subsystem_device == 0x0080)) {
371 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
372 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
374 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
378 /* mac rv630, rv730, others */
379 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
380 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
381 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
382 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
385 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
386 if ((dev->pdev->device == 0x9598) &&
387 (dev->pdev->subsystem_vendor == 0x1043) &&
388 (dev->pdev->subsystem_device == 0x01da)) {
389 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
390 *connector_type = DRM_MODE_CONNECTOR_DVII;
394 /* ASUS HD 3600 board lists the DVI port as HDMI */
395 if ((dev->pdev->device == 0x9598) &&
396 (dev->pdev->subsystem_vendor == 0x1043) &&
397 (dev->pdev->subsystem_device == 0x01e4)) {
398 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
399 *connector_type = DRM_MODE_CONNECTOR_DVII;
403 /* ASUS HD 3450 board lists the DVI port as HDMI */
404 if ((dev->pdev->device == 0x95C5) &&
405 (dev->pdev->subsystem_vendor == 0x1043) &&
406 (dev->pdev->subsystem_device == 0x01e2)) {
407 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
408 *connector_type = DRM_MODE_CONNECTOR_DVII;
412 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
413 * HDMI + VGA reporting as HDMI
415 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
416 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
417 *connector_type = DRM_MODE_CONNECTOR_VGA;
422 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
423 * on the laptop and a DVI port on the docking station and
424 * both share the same encoder, hpd pin, and ddc line.
425 * So while the bios table is technically correct,
426 * we drop the DVI port here since xrandr has no concept of
427 * encoders and will try and drive both connectors
428 * with different crtcs which isn't possible on the hardware
429 * side and leaves no crtcs for LVDS or VGA.
431 if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
432 (dev->pdev->subsystem_vendor == 0x1025) &&
433 (dev->pdev->subsystem_device == 0x013c)) {
434 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
435 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
436 /* actually it's a DVI-D port not DVI-I */
437 *connector_type = DRM_MODE_CONNECTOR_DVID;
442 /* XFX Pine Group device rv730 reports no VGA DDC lines
443 * even though they are wired up to record 0x93
445 if ((dev->pdev->device == 0x9498) &&
446 (dev->pdev->subsystem_vendor == 0x1682) &&
447 (dev->pdev->subsystem_device == 0x2452) &&
448 (i2c_bus->valid == false) &&
449 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
450 struct radeon_device *rdev = dev->dev_private;
451 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
454 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
455 if (((dev->pdev->device == 0x9802) || (dev->pdev->device == 0x9806)) &&
456 (dev->pdev->subsystem_vendor == 0x1734) &&
457 (dev->pdev->subsystem_device == 0x11bd)) {
458 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
459 *connector_type = DRM_MODE_CONNECTOR_DVII;
461 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
462 *connector_type = DRM_MODE_CONNECTOR_DVII;
470 const int supported_devices_connector_convert[] = {
471 DRM_MODE_CONNECTOR_Unknown,
472 DRM_MODE_CONNECTOR_VGA,
473 DRM_MODE_CONNECTOR_DVII,
474 DRM_MODE_CONNECTOR_DVID,
475 DRM_MODE_CONNECTOR_DVIA,
476 DRM_MODE_CONNECTOR_SVIDEO,
477 DRM_MODE_CONNECTOR_Composite,
478 DRM_MODE_CONNECTOR_LVDS,
479 DRM_MODE_CONNECTOR_Unknown,
480 DRM_MODE_CONNECTOR_Unknown,
481 DRM_MODE_CONNECTOR_HDMIA,
482 DRM_MODE_CONNECTOR_HDMIB,
483 DRM_MODE_CONNECTOR_Unknown,
484 DRM_MODE_CONNECTOR_Unknown,
485 DRM_MODE_CONNECTOR_9PinDIN,
486 DRM_MODE_CONNECTOR_DisplayPort
489 const uint16_t supported_devices_connector_object_id_convert[] = {
490 CONNECTOR_OBJECT_ID_NONE,
491 CONNECTOR_OBJECT_ID_VGA,
492 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
493 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
494 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
495 CONNECTOR_OBJECT_ID_COMPOSITE,
496 CONNECTOR_OBJECT_ID_SVIDEO,
497 CONNECTOR_OBJECT_ID_LVDS,
498 CONNECTOR_OBJECT_ID_9PIN_DIN,
499 CONNECTOR_OBJECT_ID_9PIN_DIN,
500 CONNECTOR_OBJECT_ID_DISPLAYPORT,
501 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
502 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
503 CONNECTOR_OBJECT_ID_SVIDEO
506 const int object_connector_convert[] = {
507 DRM_MODE_CONNECTOR_Unknown,
508 DRM_MODE_CONNECTOR_DVII,
509 DRM_MODE_CONNECTOR_DVII,
510 DRM_MODE_CONNECTOR_DVID,
511 DRM_MODE_CONNECTOR_DVID,
512 DRM_MODE_CONNECTOR_VGA,
513 DRM_MODE_CONNECTOR_Composite,
514 DRM_MODE_CONNECTOR_SVIDEO,
515 DRM_MODE_CONNECTOR_Unknown,
516 DRM_MODE_CONNECTOR_Unknown,
517 DRM_MODE_CONNECTOR_9PinDIN,
518 DRM_MODE_CONNECTOR_Unknown,
519 DRM_MODE_CONNECTOR_HDMIA,
520 DRM_MODE_CONNECTOR_HDMIB,
521 DRM_MODE_CONNECTOR_LVDS,
522 DRM_MODE_CONNECTOR_9PinDIN,
523 DRM_MODE_CONNECTOR_Unknown,
524 DRM_MODE_CONNECTOR_Unknown,
525 DRM_MODE_CONNECTOR_Unknown,
526 DRM_MODE_CONNECTOR_DisplayPort,
527 DRM_MODE_CONNECTOR_eDP,
528 DRM_MODE_CONNECTOR_Unknown
531 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
533 struct radeon_device *rdev = dev->dev_private;
534 struct radeon_mode_info *mode_info = &rdev->mode_info;
535 struct atom_context *ctx = mode_info->atom_context;
536 int index = GetIndexIntoMasterTable(DATA, Object_Header);
537 u16 size, data_offset;
539 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
540 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
541 ATOM_OBJECT_TABLE *router_obj;
542 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
543 ATOM_OBJECT_HEADER *obj_header;
544 int i, j, k, path_size, device_support;
546 u16 igp_lane_info, conn_id, connector_object_id;
547 struct radeon_i2c_bus_rec ddc_bus;
548 struct radeon_router router;
549 struct radeon_gpio_rec gpio;
550 struct radeon_hpd hpd;
552 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
558 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
559 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
560 (ctx->bios + data_offset +
561 le16_to_cpu(obj_header->usDisplayPathTableOffset));
562 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
563 (ctx->bios + data_offset +
564 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
565 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
566 (ctx->bios + data_offset +
567 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
568 router_obj = (ATOM_OBJECT_TABLE *)
569 (ctx->bios + data_offset +
570 le16_to_cpu(obj_header->usRouterObjectTableOffset));
571 device_support = le16_to_cpu(obj_header->usDeviceSupport);
574 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
575 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
576 ATOM_DISPLAY_OBJECT_PATH *path;
578 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
579 path_size += le16_to_cpu(path->usSize);
581 if (device_support & le16_to_cpu(path->usDeviceTag)) {
582 uint8_t con_obj_id, con_obj_num, con_obj_type;
585 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
588 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
591 (le16_to_cpu(path->usConnObjectId) &
592 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
594 /* TODO CV support */
595 if (le16_to_cpu(path->usDeviceTag) ==
596 ATOM_DEVICE_CV_SUPPORT)
600 if ((rdev->flags & RADEON_IS_IGP) &&
602 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
603 uint16_t igp_offset = 0;
604 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
607 GetIndexIntoMasterTable(DATA,
608 IntegratedSystemInfo);
610 if (atom_parse_data_header(ctx, index, &size, &frev,
611 &crev, &igp_offset)) {
615 (ATOM_INTEGRATED_SYSTEM_INFO_V2
616 *) (ctx->bios + igp_offset);
619 uint32_t slot_config, ct;
621 if (con_obj_num == 1)
630 ct = (slot_config >> 16) & 0xff;
632 object_connector_convert
634 connector_object_id = ct;
636 slot_config & 0xffff;
644 object_connector_convert[con_obj_id];
645 connector_object_id = con_obj_id;
650 object_connector_convert[con_obj_id];
651 connector_object_id = con_obj_id;
654 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
657 router.ddc_valid = false;
658 router.cd_valid = false;
659 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
660 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
663 (le16_to_cpu(path->usGraphicObjIds[j]) &
664 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
666 (le16_to_cpu(path->usGraphicObjIds[j]) &
667 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
669 (le16_to_cpu(path->usGraphicObjIds[j]) &
670 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
672 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
673 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
674 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
675 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
676 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
677 (ctx->bios + data_offset +
678 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
679 ATOM_ENCODER_CAP_RECORD *cap_record;
682 while (record->ucRecordSize > 0 &&
683 record->ucRecordType > 0 &&
684 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
685 switch (record->ucRecordType) {
686 case ATOM_ENCODER_CAP_RECORD_TYPE:
687 cap_record =(ATOM_ENCODER_CAP_RECORD *)
689 caps = le16_to_cpu(cap_record->usEncoderCap);
692 record = (ATOM_COMMON_RECORD_HEADER *)
693 ((char *)record + record->ucRecordSize);
695 radeon_add_atom_encoder(dev,
703 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
704 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
705 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
706 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
707 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
708 (ctx->bios + data_offset +
709 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
710 ATOM_I2C_RECORD *i2c_record;
711 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
712 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
713 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
714 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
715 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
716 (ctx->bios + data_offset +
717 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
720 router.router_id = router_obj_id;
721 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
723 if (le16_to_cpu(path->usConnObjectId) ==
724 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
728 while (record->ucRecordSize > 0 &&
729 record->ucRecordType > 0 &&
730 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
731 switch (record->ucRecordType) {
732 case ATOM_I2C_RECORD_TYPE:
737 (ATOM_I2C_ID_CONFIG_ACCESS *)
738 &i2c_record->sucI2cId;
740 radeon_lookup_i2c_gpio(rdev,
743 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
745 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
746 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
748 router.ddc_valid = true;
749 router.ddc_mux_type = ddc_path->ucMuxType;
750 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
751 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
753 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
754 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
756 router.cd_valid = true;
757 router.cd_mux_type = cd_path->ucMuxType;
758 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
759 router.cd_mux_state = cd_path->ucMuxState[enum_id];
762 record = (ATOM_COMMON_RECORD_HEADER *)
763 ((char *)record + record->ucRecordSize);
770 /* look up gpio for ddc, hpd */
771 ddc_bus.valid = false;
772 hpd.hpd = RADEON_HPD_NONE;
773 if ((le16_to_cpu(path->usDeviceTag) &
774 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
775 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
776 if (le16_to_cpu(path->usConnObjectId) ==
777 le16_to_cpu(con_obj->asObjects[j].
779 ATOM_COMMON_RECORD_HEADER
781 (ATOM_COMMON_RECORD_HEADER
783 (ctx->bios + data_offset +
784 le16_to_cpu(con_obj->
787 ATOM_I2C_RECORD *i2c_record;
788 ATOM_HPD_INT_RECORD *hpd_record;
789 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
791 while (record->ucRecordSize > 0 &&
792 record->ucRecordType > 0 &&
793 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
794 switch (record->ucRecordType) {
795 case ATOM_I2C_RECORD_TYPE:
800 (ATOM_I2C_ID_CONFIG_ACCESS *)
801 &i2c_record->sucI2cId;
802 ddc_bus = radeon_lookup_i2c_gpio(rdev,
806 case ATOM_HPD_INT_RECORD_TYPE:
808 (ATOM_HPD_INT_RECORD *)
810 gpio = radeon_lookup_gpio(rdev,
811 hpd_record->ucHPDIntGPIOID);
812 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
813 hpd.plugged_state = hpd_record->ucPlugged_PinState;
817 (ATOM_COMMON_RECORD_HEADER
828 /* needed for aux chan transactions */
829 ddc_bus.hpd = hpd.hpd;
831 conn_id = le16_to_cpu(path->usConnObjectId);
833 if (!radeon_atom_apply_quirks
834 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
835 &ddc_bus, &conn_id, &hpd))
838 radeon_add_atom_connector(dev,
842 connector_type, &ddc_bus,
851 radeon_link_encoder_connector(dev);
856 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
860 struct radeon_device *rdev = dev->dev_private;
862 if (rdev->flags & RADEON_IS_IGP) {
863 return supported_devices_connector_object_id_convert
865 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
866 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
867 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
868 struct radeon_mode_info *mode_info = &rdev->mode_info;
869 struct atom_context *ctx = mode_info->atom_context;
870 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
871 uint16_t size, data_offset;
873 ATOM_XTMDS_INFO *xtmds;
875 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
876 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
878 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
879 if (connector_type == DRM_MODE_CONNECTOR_DVII)
880 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
882 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
884 if (connector_type == DRM_MODE_CONNECTOR_DVII)
885 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
887 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
890 return supported_devices_connector_object_id_convert
893 return supported_devices_connector_object_id_convert
898 struct bios_connector {
903 struct radeon_i2c_bus_rec ddc_bus;
904 struct radeon_hpd hpd;
907 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
911 struct radeon_device *rdev = dev->dev_private;
912 struct radeon_mode_info *mode_info = &rdev->mode_info;
913 struct atom_context *ctx = mode_info->atom_context;
914 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
915 uint16_t size, data_offset;
917 uint16_t device_support;
919 union atom_supported_devices *supported_devices;
920 int i, j, max_device;
921 struct bios_connector *bios_connectors;
922 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
923 struct radeon_router router;
925 router.ddc_valid = false;
926 router.cd_valid = false;
928 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
929 if (!bios_connectors)
932 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
934 kfree(bios_connectors);
939 (union atom_supported_devices *)(ctx->bios + data_offset);
941 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
944 max_device = ATOM_MAX_SUPPORTED_DEVICE;
946 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
948 for (i = 0; i < max_device; i++) {
949 ATOM_CONNECTOR_INFO_I2C ci =
950 supported_devices->info.asConnInfo[i];
952 bios_connectors[i].valid = false;
954 if (!(device_support & (1 << i))) {
958 if (i == ATOM_DEVICE_CV_INDEX) {
959 DRM_DEBUG_KMS("Skipping Component Video\n");
963 bios_connectors[i].connector_type =
964 supported_devices_connector_convert[ci.sucConnectorInfo.
968 if (bios_connectors[i].connector_type ==
969 DRM_MODE_CONNECTOR_Unknown)
972 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
974 bios_connectors[i].line_mux =
975 ci.sucI2cId.ucAccess;
977 /* give tv unique connector ids */
978 if (i == ATOM_DEVICE_TV1_INDEX) {
979 bios_connectors[i].ddc_bus.valid = false;
980 bios_connectors[i].line_mux = 50;
981 } else if (i == ATOM_DEVICE_TV2_INDEX) {
982 bios_connectors[i].ddc_bus.valid = false;
983 bios_connectors[i].line_mux = 51;
984 } else if (i == ATOM_DEVICE_CV_INDEX) {
985 bios_connectors[i].ddc_bus.valid = false;
986 bios_connectors[i].line_mux = 52;
988 bios_connectors[i].ddc_bus =
989 radeon_lookup_i2c_gpio(rdev,
990 bios_connectors[i].line_mux);
992 if ((crev > 1) && (frev > 1)) {
993 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
996 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
999 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1002 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1006 if (i == ATOM_DEVICE_DFP1_INDEX)
1007 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1008 else if (i == ATOM_DEVICE_DFP2_INDEX)
1009 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1011 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1014 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1015 * shared with a DVI port, we'll pick up the DVI connector when we
1016 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1018 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1019 bios_connectors[i].connector_type =
1020 DRM_MODE_CONNECTOR_VGA;
1022 if (!radeon_atom_apply_quirks
1023 (dev, (1 << i), &bios_connectors[i].connector_type,
1024 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1025 &bios_connectors[i].hpd))
1028 bios_connectors[i].valid = true;
1029 bios_connectors[i].devices = (1 << i);
1031 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1032 radeon_add_atom_encoder(dev,
1033 radeon_get_encoder_enum(dev,
1039 radeon_add_legacy_encoder(dev,
1040 radeon_get_encoder_enum(dev,
1046 /* combine shared connectors */
1047 for (i = 0; i < max_device; i++) {
1048 if (bios_connectors[i].valid) {
1049 for (j = 0; j < max_device; j++) {
1050 if (bios_connectors[j].valid && (i != j)) {
1051 if (bios_connectors[i].line_mux ==
1052 bios_connectors[j].line_mux) {
1053 /* make sure not to combine LVDS */
1054 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1055 bios_connectors[i].line_mux = 53;
1056 bios_connectors[i].ddc_bus.valid = false;
1059 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1060 bios_connectors[j].line_mux = 53;
1061 bios_connectors[j].ddc_bus.valid = false;
1064 /* combine analog and digital for DVI-I */
1065 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1066 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1067 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1068 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1069 bios_connectors[i].devices |=
1070 bios_connectors[j].devices;
1071 bios_connectors[i].connector_type =
1072 DRM_MODE_CONNECTOR_DVII;
1073 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1074 bios_connectors[i].hpd =
1075 bios_connectors[j].hpd;
1076 bios_connectors[j].valid = false;
1084 /* add the connectors */
1085 for (i = 0; i < max_device; i++) {
1086 if (bios_connectors[i].valid) {
1087 uint16_t connector_object_id =
1088 atombios_get_connector_object_id(dev,
1089 bios_connectors[i].connector_type,
1090 bios_connectors[i].devices);
1091 radeon_add_atom_connector(dev,
1092 bios_connectors[i].line_mux,
1093 bios_connectors[i].devices,
1096 &bios_connectors[i].ddc_bus,
1098 connector_object_id,
1099 &bios_connectors[i].hpd,
1104 radeon_link_encoder_connector(dev);
1106 kfree(bios_connectors);
1110 union firmware_info {
1111 ATOM_FIRMWARE_INFO info;
1112 ATOM_FIRMWARE_INFO_V1_2 info_12;
1113 ATOM_FIRMWARE_INFO_V1_3 info_13;
1114 ATOM_FIRMWARE_INFO_V1_4 info_14;
1115 ATOM_FIRMWARE_INFO_V2_1 info_21;
1116 ATOM_FIRMWARE_INFO_V2_2 info_22;
1119 bool radeon_atom_get_clock_info(struct drm_device *dev)
1121 struct radeon_device *rdev = dev->dev_private;
1122 struct radeon_mode_info *mode_info = &rdev->mode_info;
1123 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1124 union firmware_info *firmware_info;
1126 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1127 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1128 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1129 struct radeon_pll *spll = &rdev->clock.spll;
1130 struct radeon_pll *mpll = &rdev->clock.mpll;
1131 uint16_t data_offset;
1133 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1134 &frev, &crev, &data_offset)) {
1136 (union firmware_info *)(mode_info->atom_context->bios +
1139 p1pll->reference_freq =
1140 le16_to_cpu(firmware_info->info.usReferenceClock);
1141 p1pll->reference_div = 0;
1144 p1pll->pll_out_min =
1145 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1147 p1pll->pll_out_min =
1148 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1149 p1pll->pll_out_max =
1150 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1153 p1pll->lcd_pll_out_min =
1154 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1155 if (p1pll->lcd_pll_out_min == 0)
1156 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1157 p1pll->lcd_pll_out_max =
1158 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1159 if (p1pll->lcd_pll_out_max == 0)
1160 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1162 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1163 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1166 if (p1pll->pll_out_min == 0) {
1167 if (ASIC_IS_AVIVO(rdev))
1168 p1pll->pll_out_min = 64800;
1170 p1pll->pll_out_min = 20000;
1174 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1176 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1181 if (ASIC_IS_DCE4(rdev))
1182 spll->reference_freq =
1183 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1185 spll->reference_freq =
1186 le16_to_cpu(firmware_info->info.usReferenceClock);
1187 spll->reference_div = 0;
1190 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1192 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1195 if (spll->pll_out_min == 0) {
1196 if (ASIC_IS_AVIVO(rdev))
1197 spll->pll_out_min = 64800;
1199 spll->pll_out_min = 20000;
1203 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1205 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1208 if (ASIC_IS_DCE4(rdev))
1209 mpll->reference_freq =
1210 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1212 mpll->reference_freq =
1213 le16_to_cpu(firmware_info->info.usReferenceClock);
1214 mpll->reference_div = 0;
1217 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1219 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1222 if (mpll->pll_out_min == 0) {
1223 if (ASIC_IS_AVIVO(rdev))
1224 mpll->pll_out_min = 64800;
1226 mpll->pll_out_min = 20000;
1230 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1232 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1234 rdev->clock.default_sclk =
1235 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1236 rdev->clock.default_mclk =
1237 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1239 if (ASIC_IS_DCE4(rdev)) {
1240 rdev->clock.default_dispclk =
1241 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1242 if (rdev->clock.default_dispclk == 0) {
1243 if (ASIC_IS_DCE5(rdev))
1244 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1246 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1248 rdev->clock.dp_extclk =
1249 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1253 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1254 if (rdev->clock.max_pixel_clock == 0)
1255 rdev->clock.max_pixel_clock = 40000;
1264 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1265 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1268 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1270 struct radeon_mode_info *mode_info = &rdev->mode_info;
1271 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1272 union igp_info *igp_info;
1276 /* sideport is AMD only */
1277 if (rdev->family == CHIP_RS600)
1280 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1281 &frev, &crev, &data_offset)) {
1282 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1286 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1290 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1294 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1301 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1302 struct radeon_encoder_int_tmds *tmds)
1304 struct drm_device *dev = encoder->base.dev;
1305 struct radeon_device *rdev = dev->dev_private;
1306 struct radeon_mode_info *mode_info = &rdev->mode_info;
1307 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1308 uint16_t data_offset;
1309 struct _ATOM_TMDS_INFO *tmds_info;
1314 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1315 &frev, &crev, &data_offset)) {
1317 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1320 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1321 for (i = 0; i < 4; i++) {
1322 tmds->tmds_pll[i].freq =
1323 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1324 tmds->tmds_pll[i].value =
1325 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1326 tmds->tmds_pll[i].value |=
1327 (tmds_info->asMiscInfo[i].
1328 ucPLL_VCO_Gain & 0x3f) << 6;
1329 tmds->tmds_pll[i].value |=
1330 (tmds_info->asMiscInfo[i].
1331 ucPLL_DutyCycle & 0xf) << 12;
1332 tmds->tmds_pll[i].value |=
1333 (tmds_info->asMiscInfo[i].
1334 ucPLL_VoltageSwing & 0xf) << 16;
1336 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1337 tmds->tmds_pll[i].freq,
1338 tmds->tmds_pll[i].value);
1340 if (maxfreq == tmds->tmds_pll[i].freq) {
1341 tmds->tmds_pll[i].freq = 0xffffffff;
1350 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1351 struct radeon_atom_ss *ss,
1354 struct radeon_mode_info *mode_info = &rdev->mode_info;
1355 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1356 uint16_t data_offset, size;
1357 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1361 memset(ss, 0, sizeof(struct radeon_atom_ss));
1362 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1363 &frev, &crev, &data_offset)) {
1365 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1367 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1368 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1370 for (i = 0; i < num_indices; i++) {
1371 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1373 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1374 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1375 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1376 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1377 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1378 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1386 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1387 struct radeon_atom_ss *ss,
1390 struct radeon_mode_info *mode_info = &rdev->mode_info;
1391 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1392 u16 data_offset, size;
1393 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info;
1395 u16 percentage = 0, rate = 0;
1397 /* get any igp specific overrides */
1398 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1399 &frev, &crev, &data_offset)) {
1400 igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *)
1401 (mode_info->atom_context->bios + data_offset);
1403 case ASIC_INTERNAL_SS_ON_TMDS:
1404 percentage = le16_to_cpu(igp_info->usDVISSPercentage);
1405 rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz);
1407 case ASIC_INTERNAL_SS_ON_HDMI:
1408 percentage = le16_to_cpu(igp_info->usHDMISSPercentage);
1409 rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz);
1411 case ASIC_INTERNAL_SS_ON_LVDS:
1412 percentage = le16_to_cpu(igp_info->usLvdsSSPercentage);
1413 rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
1417 ss->percentage = percentage;
1423 union asic_ss_info {
1424 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1425 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1426 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1429 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1430 struct radeon_atom_ss *ss,
1433 struct radeon_mode_info *mode_info = &rdev->mode_info;
1434 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1435 uint16_t data_offset, size;
1436 union asic_ss_info *ss_info;
1440 memset(ss, 0, sizeof(struct radeon_atom_ss));
1441 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1442 &frev, &crev, &data_offset)) {
1445 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1449 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1450 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1452 for (i = 0; i < num_indices; i++) {
1453 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1454 (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
1456 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1457 ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1458 ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1464 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1465 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1466 for (i = 0; i < num_indices; i++) {
1467 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1468 (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
1470 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1471 ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1472 ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1478 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1479 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1480 for (i = 0; i < num_indices; i++) {
1481 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1482 (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
1484 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1485 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1486 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1487 if (rdev->flags & RADEON_IS_IGP)
1488 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1494 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1503 struct _ATOM_LVDS_INFO info;
1504 struct _ATOM_LVDS_INFO_V12 info_12;
1507 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1511 struct drm_device *dev = encoder->base.dev;
1512 struct radeon_device *rdev = dev->dev_private;
1513 struct radeon_mode_info *mode_info = &rdev->mode_info;
1514 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1515 uint16_t data_offset, misc;
1516 union lvds_info *lvds_info;
1518 struct radeon_encoder_atom_dig *lvds = NULL;
1519 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1521 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1522 &frev, &crev, &data_offset)) {
1524 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1526 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1531 lvds->native_mode.clock =
1532 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1533 lvds->native_mode.hdisplay =
1534 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1535 lvds->native_mode.vdisplay =
1536 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1537 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1538 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1539 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1540 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1541 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1542 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1543 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1544 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1545 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1546 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1547 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1548 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1549 lvds->panel_pwr_delay =
1550 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1551 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1553 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1554 if (misc & ATOM_VSYNC_POLARITY)
1555 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1556 if (misc & ATOM_HSYNC_POLARITY)
1557 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1558 if (misc & ATOM_COMPOSITESYNC)
1559 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1560 if (misc & ATOM_INTERLACE)
1561 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1562 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1563 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1565 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1566 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1568 /* set crtc values */
1569 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1571 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1573 encoder->native_mode = lvds->native_mode;
1575 if (encoder_enum == 2)
1578 lvds->linkb = false;
1580 /* parse the lcd record table */
1581 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1582 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1583 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1584 bool bad_record = false;
1587 if ((frev == 1) && (crev < 2))
1589 record = (u8 *)(mode_info->atom_context->bios +
1590 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1593 record = (u8 *)(mode_info->atom_context->bios +
1595 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1596 while (*record != ATOM_RECORD_END_TYPE) {
1598 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1599 record += sizeof(ATOM_PATCH_RECORD_MODE);
1601 case LCD_RTS_RECORD_TYPE:
1602 record += sizeof(ATOM_LCD_RTS_RECORD);
1604 case LCD_CAP_RECORD_TYPE:
1605 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1607 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1608 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1609 if (fake_edid_record->ucFakeEDIDLength) {
1612 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1613 edid = kmalloc(edid_size, GFP_KERNEL);
1615 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1616 fake_edid_record->ucFakeEDIDLength);
1618 if (drm_edid_is_valid(edid)) {
1619 rdev->mode_info.bios_hardcoded_edid = edid;
1620 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1625 record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1627 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1628 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1629 lvds->native_mode.width_mm = panel_res_record->usHSize;
1630 lvds->native_mode.height_mm = panel_res_record->usVSize;
1631 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1634 DRM_ERROR("Bad LCD record %d\n", *record);
1646 struct radeon_encoder_primary_dac *
1647 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1649 struct drm_device *dev = encoder->base.dev;
1650 struct radeon_device *rdev = dev->dev_private;
1651 struct radeon_mode_info *mode_info = &rdev->mode_info;
1652 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1653 uint16_t data_offset;
1654 struct _COMPASSIONATE_DATA *dac_info;
1657 struct radeon_encoder_primary_dac *p_dac = NULL;
1659 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1660 &frev, &crev, &data_offset)) {
1661 dac_info = (struct _COMPASSIONATE_DATA *)
1662 (mode_info->atom_context->bios + data_offset);
1664 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1669 bg = dac_info->ucDAC1_BG_Adjustment;
1670 dac = dac_info->ucDAC1_DAC_Adjustment;
1671 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1677 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1678 struct drm_display_mode *mode)
1680 struct radeon_mode_info *mode_info = &rdev->mode_info;
1681 ATOM_ANALOG_TV_INFO *tv_info;
1682 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1683 ATOM_DTD_FORMAT *dtd_timings;
1684 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1686 u16 data_offset, misc;
1688 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1689 &frev, &crev, &data_offset))
1694 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1695 if (index >= MAX_SUPPORTED_TV_TIMING)
1698 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1699 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1700 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1701 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1702 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1704 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1705 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1706 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1707 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1708 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1711 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1712 if (misc & ATOM_VSYNC_POLARITY)
1713 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1714 if (misc & ATOM_HSYNC_POLARITY)
1715 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1716 if (misc & ATOM_COMPOSITESYNC)
1717 mode->flags |= DRM_MODE_FLAG_CSYNC;
1718 if (misc & ATOM_INTERLACE)
1719 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1720 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1721 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1723 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1726 /* PAL timings appear to have wrong values for totals */
1727 mode->crtc_htotal -= 1;
1728 mode->crtc_vtotal -= 1;
1732 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1733 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1736 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1737 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1738 le16_to_cpu(dtd_timings->usHBlanking_Time);
1739 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1740 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1741 le16_to_cpu(dtd_timings->usHSyncOffset);
1742 mode->crtc_hsync_end = mode->crtc_hsync_start +
1743 le16_to_cpu(dtd_timings->usHSyncWidth);
1745 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1746 le16_to_cpu(dtd_timings->usVBlanking_Time);
1747 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1748 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1749 le16_to_cpu(dtd_timings->usVSyncOffset);
1750 mode->crtc_vsync_end = mode->crtc_vsync_start +
1751 le16_to_cpu(dtd_timings->usVSyncWidth);
1754 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1755 if (misc & ATOM_VSYNC_POLARITY)
1756 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1757 if (misc & ATOM_HSYNC_POLARITY)
1758 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1759 if (misc & ATOM_COMPOSITESYNC)
1760 mode->flags |= DRM_MODE_FLAG_CSYNC;
1761 if (misc & ATOM_INTERLACE)
1762 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1763 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1764 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1766 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1773 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1775 struct radeon_mode_info *mode_info = &rdev->mode_info;
1776 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1777 uint16_t data_offset;
1779 struct _ATOM_ANALOG_TV_INFO *tv_info;
1780 enum radeon_tv_std tv_std = TV_STD_NTSC;
1782 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1783 &frev, &crev, &data_offset)) {
1785 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1786 (mode_info->atom_context->bios + data_offset);
1788 switch (tv_info->ucTV_BootUpDefaultStandard) {
1790 tv_std = TV_STD_NTSC;
1791 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1794 tv_std = TV_STD_NTSC_J;
1795 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1798 tv_std = TV_STD_PAL;
1799 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1802 tv_std = TV_STD_PAL_M;
1803 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1806 tv_std = TV_STD_PAL_N;
1807 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1810 tv_std = TV_STD_PAL_CN;
1811 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1814 tv_std = TV_STD_PAL_60;
1815 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1818 tv_std = TV_STD_SECAM;
1819 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1822 tv_std = TV_STD_NTSC;
1823 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1830 struct radeon_encoder_tv_dac *
1831 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1833 struct drm_device *dev = encoder->base.dev;
1834 struct radeon_device *rdev = dev->dev_private;
1835 struct radeon_mode_info *mode_info = &rdev->mode_info;
1836 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1837 uint16_t data_offset;
1838 struct _COMPASSIONATE_DATA *dac_info;
1841 struct radeon_encoder_tv_dac *tv_dac = NULL;
1843 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1844 &frev, &crev, &data_offset)) {
1846 dac_info = (struct _COMPASSIONATE_DATA *)
1847 (mode_info->atom_context->bios + data_offset);
1849 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1854 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1855 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1856 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1858 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1859 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1860 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1862 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1863 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1864 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1866 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1871 static const char *thermal_controller_names[] = {
1882 static const char *pp_lib_thermal_controller_names[] = {
1904 struct _ATOM_POWERPLAY_INFO info;
1905 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1906 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1907 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1908 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1909 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1912 union pplib_clock_info {
1913 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1914 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1915 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1916 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1917 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
1920 union pplib_power_state {
1921 struct _ATOM_PPLIB_STATE v1;
1922 struct _ATOM_PPLIB_STATE_V2 v2;
1925 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1927 u32 misc, u32 misc2)
1929 rdev->pm.power_state[state_index].misc = misc;
1930 rdev->pm.power_state[state_index].misc2 = misc2;
1931 /* order matters! */
1932 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1933 rdev->pm.power_state[state_index].type =
1934 POWER_STATE_TYPE_POWERSAVE;
1935 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1936 rdev->pm.power_state[state_index].type =
1937 POWER_STATE_TYPE_BATTERY;
1938 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1939 rdev->pm.power_state[state_index].type =
1940 POWER_STATE_TYPE_BATTERY;
1941 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1942 rdev->pm.power_state[state_index].type =
1943 POWER_STATE_TYPE_BALANCED;
1944 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1945 rdev->pm.power_state[state_index].type =
1946 POWER_STATE_TYPE_PERFORMANCE;
1947 rdev->pm.power_state[state_index].flags &=
1948 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1950 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1951 rdev->pm.power_state[state_index].type =
1952 POWER_STATE_TYPE_BALANCED;
1953 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1954 rdev->pm.power_state[state_index].type =
1955 POWER_STATE_TYPE_DEFAULT;
1956 rdev->pm.default_power_state_index = state_index;
1957 rdev->pm.power_state[state_index].default_clock_mode =
1958 &rdev->pm.power_state[state_index].clock_info[0];
1959 } else if (state_index == 0) {
1960 rdev->pm.power_state[state_index].clock_info[0].flags |=
1961 RADEON_PM_MODE_NO_DISPLAY;
1965 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
1967 struct radeon_mode_info *mode_info = &rdev->mode_info;
1968 u32 misc, misc2 = 0;
1969 int num_modes = 0, i;
1970 int state_index = 0;
1971 struct radeon_i2c_bus_rec i2c_bus;
1972 union power_info *power_info;
1973 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1977 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1978 &frev, &crev, &data_offset))
1980 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1982 /* add the i2c bus for thermal/fan chip */
1983 if (power_info->info.ucOverdriveThermalController > 0) {
1984 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1985 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1986 power_info->info.ucOverdriveControllerAddress >> 1);
1987 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1988 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1989 if (rdev->pm.i2c_bus) {
1990 struct i2c_board_info info = { };
1991 const char *name = thermal_controller_names[power_info->info.
1992 ucOverdriveThermalController];
1993 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1994 strlcpy(info.type, name, sizeof(info.type));
1995 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1998 num_modes = power_info->info.ucNumOfPowerModeEntries;
1999 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2000 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2003 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
2004 if (!rdev->pm.power_state)
2006 /* last mode is usually default, array is low to high */
2007 for (i = 0; i < num_modes; i++) {
2008 rdev->pm.power_state[state_index].clock_info =
2009 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2010 if (!rdev->pm.power_state[state_index].clock_info)
2012 rdev->pm.power_state[state_index].num_clock_modes = 1;
2013 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2016 rdev->pm.power_state[state_index].clock_info[0].mclk =
2017 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2018 rdev->pm.power_state[state_index].clock_info[0].sclk =
2019 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2020 /* skip invalid modes */
2021 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2022 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2024 rdev->pm.power_state[state_index].pcie_lanes =
2025 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2026 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2027 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2028 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2029 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2031 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2032 radeon_lookup_gpio(rdev,
2033 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2034 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2035 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2038 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2040 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2041 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2043 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2044 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2046 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2047 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2051 rdev->pm.power_state[state_index].clock_info[0].mclk =
2052 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2053 rdev->pm.power_state[state_index].clock_info[0].sclk =
2054 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2055 /* skip invalid modes */
2056 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2057 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2059 rdev->pm.power_state[state_index].pcie_lanes =
2060 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2061 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2062 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2063 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2064 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2065 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2067 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2068 radeon_lookup_gpio(rdev,
2069 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2070 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2071 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2074 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2076 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2077 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2079 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2080 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2082 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2083 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2087 rdev->pm.power_state[state_index].clock_info[0].mclk =
2088 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2089 rdev->pm.power_state[state_index].clock_info[0].sclk =
2090 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2091 /* skip invalid modes */
2092 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2093 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2095 rdev->pm.power_state[state_index].pcie_lanes =
2096 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2097 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2098 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2099 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2100 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2101 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2103 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2104 radeon_lookup_gpio(rdev,
2105 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2106 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2107 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2110 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2112 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2113 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2115 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2116 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2117 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2118 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2120 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2121 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2124 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2125 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2130 /* last mode is usually default */
2131 if (rdev->pm.default_power_state_index == -1) {
2132 rdev->pm.power_state[state_index - 1].type =
2133 POWER_STATE_TYPE_DEFAULT;
2134 rdev->pm.default_power_state_index = state_index - 1;
2135 rdev->pm.power_state[state_index - 1].default_clock_mode =
2136 &rdev->pm.power_state[state_index - 1].clock_info[0];
2137 rdev->pm.power_state[state_index].flags &=
2138 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2139 rdev->pm.power_state[state_index].misc = 0;
2140 rdev->pm.power_state[state_index].misc2 = 0;
2145 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2146 ATOM_PPLIB_THERMALCONTROLLER *controller)
2148 struct radeon_i2c_bus_rec i2c_bus;
2150 /* add the i2c bus for thermal/fan chip */
2151 if (controller->ucType > 0) {
2152 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2153 DRM_INFO("Internal thermal controller %s fan control\n",
2154 (controller->ucFanParameters &
2155 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2156 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2157 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2158 DRM_INFO("Internal thermal controller %s fan control\n",
2159 (controller->ucFanParameters &
2160 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2161 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2162 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2163 DRM_INFO("Internal thermal controller %s fan control\n",
2164 (controller->ucFanParameters &
2165 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2166 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2167 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2168 DRM_INFO("Internal thermal controller %s fan control\n",
2169 (controller->ucFanParameters &
2170 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2171 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2172 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2173 DRM_INFO("Internal thermal controller %s fan control\n",
2174 (controller->ucFanParameters &
2175 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2176 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2177 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2178 DRM_INFO("Internal thermal controller %s fan control\n",
2179 (controller->ucFanParameters &
2180 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2181 rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2182 } else if ((controller->ucType ==
2183 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2184 (controller->ucType ==
2185 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2186 (controller->ucType ==
2187 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2188 DRM_INFO("Special thermal controller config\n");
2190 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2191 pp_lib_thermal_controller_names[controller->ucType],
2192 controller->ucI2cAddress >> 1,
2193 (controller->ucFanParameters &
2194 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2195 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2196 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2197 if (rdev->pm.i2c_bus) {
2198 struct i2c_board_info info = { };
2199 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2200 info.addr = controller->ucI2cAddress >> 1;
2201 strlcpy(info.type, name, sizeof(info.type));
2202 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2208 static void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2209 u16 *vddc, u16 *vddci)
2211 struct radeon_mode_info *mode_info = &rdev->mode_info;
2212 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2215 union firmware_info *firmware_info;
2220 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2221 &frev, &crev, &data_offset)) {
2223 (union firmware_info *)(mode_info->atom_context->bios +
2225 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2226 if ((frev == 2) && (crev >= 2))
2227 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2231 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2232 int state_index, int mode_index,
2233 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2236 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2237 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2240 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci);
2242 rdev->pm.power_state[state_index].misc = misc;
2243 rdev->pm.power_state[state_index].misc2 = misc2;
2244 rdev->pm.power_state[state_index].pcie_lanes =
2245 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2246 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2247 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2248 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2249 rdev->pm.power_state[state_index].type =
2250 POWER_STATE_TYPE_BATTERY;
2252 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2253 rdev->pm.power_state[state_index].type =
2254 POWER_STATE_TYPE_BALANCED;
2256 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2257 rdev->pm.power_state[state_index].type =
2258 POWER_STATE_TYPE_PERFORMANCE;
2260 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2261 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2262 rdev->pm.power_state[state_index].type =
2263 POWER_STATE_TYPE_PERFORMANCE;
2266 rdev->pm.power_state[state_index].flags = 0;
2267 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2268 rdev->pm.power_state[state_index].flags |=
2269 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2270 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2271 rdev->pm.power_state[state_index].type =
2272 POWER_STATE_TYPE_DEFAULT;
2273 rdev->pm.default_power_state_index = state_index;
2274 rdev->pm.power_state[state_index].default_clock_mode =
2275 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2276 if (ASIC_IS_DCE5(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2277 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2278 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2279 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2280 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2281 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2283 /* patch the table values with the default slck/mclk from firmware info */
2284 for (j = 0; j < mode_index; j++) {
2285 rdev->pm.power_state[state_index].clock_info[j].mclk =
2286 rdev->clock.default_mclk;
2287 rdev->pm.power_state[state_index].clock_info[j].sclk =
2288 rdev->clock.default_sclk;
2290 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2297 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2298 int state_index, int mode_index,
2299 union pplib_clock_info *clock_info)
2304 if (rdev->flags & RADEON_IS_IGP) {
2305 if (rdev->family >= CHIP_PALM) {
2306 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2307 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2308 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2310 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2311 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2312 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2314 } else if (ASIC_IS_DCE6(rdev)) {
2315 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2316 sclk |= clock_info->si.ucEngineClockHigh << 16;
2317 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2318 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2319 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2320 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2321 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2323 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2324 le16_to_cpu(clock_info->si.usVDDC);
2325 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2326 le16_to_cpu(clock_info->si.usVDDCI);
2327 } else if (ASIC_IS_DCE4(rdev)) {
2328 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2329 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2330 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2331 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2332 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2333 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2334 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2336 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2337 le16_to_cpu(clock_info->evergreen.usVDDC);
2338 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2339 le16_to_cpu(clock_info->evergreen.usVDDCI);
2341 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2342 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2343 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2344 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2345 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2346 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2347 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2349 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2350 le16_to_cpu(clock_info->r600.usVDDC);
2353 /* patch up vddc if necessary */
2354 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2355 case ATOM_VIRTUAL_VOLTAGE_ID0:
2356 case ATOM_VIRTUAL_VOLTAGE_ID1:
2357 case ATOM_VIRTUAL_VOLTAGE_ID2:
2358 case ATOM_VIRTUAL_VOLTAGE_ID3:
2359 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2360 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2362 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2368 if (rdev->flags & RADEON_IS_IGP) {
2369 /* skip invalid modes */
2370 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2373 /* skip invalid modes */
2374 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2375 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2381 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2383 struct radeon_mode_info *mode_info = &rdev->mode_info;
2384 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2385 union pplib_power_state *power_state;
2387 int state_index = 0, mode_index = 0;
2388 union pplib_clock_info *clock_info;
2390 union power_info *power_info;
2391 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2395 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2396 &frev, &crev, &data_offset))
2398 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2400 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2401 if (power_info->pplib.ucNumStates == 0)
2403 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2404 power_info->pplib.ucNumStates, GFP_KERNEL);
2405 if (!rdev->pm.power_state)
2407 /* first mode is usually default, followed by low to high */
2408 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2410 power_state = (union pplib_power_state *)
2411 (mode_info->atom_context->bios + data_offset +
2412 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2413 i * power_info->pplib.ucStateEntrySize);
2414 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2415 (mode_info->atom_context->bios + data_offset +
2416 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2417 (power_state->v1.ucNonClockStateIndex *
2418 power_info->pplib.ucNonClockSize));
2419 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2420 ((power_info->pplib.ucStateEntrySize - 1) ?
2421 (power_info->pplib.ucStateEntrySize - 1) : 1),
2423 if (!rdev->pm.power_state[i].clock_info)
2425 if (power_info->pplib.ucStateEntrySize - 1) {
2426 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2427 clock_info = (union pplib_clock_info *)
2428 (mode_info->atom_context->bios + data_offset +
2429 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2430 (power_state->v1.ucClockStateIndices[j] *
2431 power_info->pplib.ucClockInfoSize));
2432 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2433 state_index, mode_index,
2439 rdev->pm.power_state[state_index].clock_info[0].mclk =
2440 rdev->clock.default_mclk;
2441 rdev->pm.power_state[state_index].clock_info[0].sclk =
2442 rdev->clock.default_sclk;
2445 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2447 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2452 /* if multiple clock modes, mark the lowest as no display */
2453 for (i = 0; i < state_index; i++) {
2454 if (rdev->pm.power_state[i].num_clock_modes > 1)
2455 rdev->pm.power_state[i].clock_info[0].flags |=
2456 RADEON_PM_MODE_NO_DISPLAY;
2458 /* first mode is usually default */
2459 if (rdev->pm.default_power_state_index == -1) {
2460 rdev->pm.power_state[0].type =
2461 POWER_STATE_TYPE_DEFAULT;
2462 rdev->pm.default_power_state_index = 0;
2463 rdev->pm.power_state[0].default_clock_mode =
2464 &rdev->pm.power_state[0].clock_info[0];
2469 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2471 struct radeon_mode_info *mode_info = &rdev->mode_info;
2472 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2473 union pplib_power_state *power_state;
2474 int i, j, non_clock_array_index, clock_array_index;
2475 int state_index = 0, mode_index = 0;
2476 union pplib_clock_info *clock_info;
2477 struct _StateArray *state_array;
2478 struct _ClockInfoArray *clock_info_array;
2479 struct _NonClockInfoArray *non_clock_info_array;
2481 union power_info *power_info;
2482 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2486 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2487 &frev, &crev, &data_offset))
2489 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2491 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2492 state_array = (struct _StateArray *)
2493 (mode_info->atom_context->bios + data_offset +
2494 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2495 clock_info_array = (struct _ClockInfoArray *)
2496 (mode_info->atom_context->bios + data_offset +
2497 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2498 non_clock_info_array = (struct _NonClockInfoArray *)
2499 (mode_info->atom_context->bios + data_offset +
2500 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2501 if (state_array->ucNumEntries == 0)
2503 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2504 state_array->ucNumEntries, GFP_KERNEL);
2505 if (!rdev->pm.power_state)
2507 for (i = 0; i < state_array->ucNumEntries; i++) {
2509 power_state = (union pplib_power_state *)&state_array->states[i];
2510 /* XXX this might be an inagua bug... */
2511 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2512 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2513 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2514 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2515 (power_state->v2.ucNumDPMLevels ?
2516 power_state->v2.ucNumDPMLevels : 1),
2518 if (!rdev->pm.power_state[i].clock_info)
2520 if (power_state->v2.ucNumDPMLevels) {
2521 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2522 clock_array_index = power_state->v2.clockInfoIndex[j];
2523 /* XXX this might be an inagua bug... */
2524 if (clock_array_index >= clock_info_array->ucNumEntries)
2526 clock_info = (union pplib_clock_info *)
2527 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2528 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2529 state_index, mode_index,
2535 rdev->pm.power_state[state_index].clock_info[0].mclk =
2536 rdev->clock.default_mclk;
2537 rdev->pm.power_state[state_index].clock_info[0].sclk =
2538 rdev->clock.default_sclk;
2541 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2543 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2548 /* if multiple clock modes, mark the lowest as no display */
2549 for (i = 0; i < state_index; i++) {
2550 if (rdev->pm.power_state[i].num_clock_modes > 1)
2551 rdev->pm.power_state[i].clock_info[0].flags |=
2552 RADEON_PM_MODE_NO_DISPLAY;
2554 /* first mode is usually default */
2555 if (rdev->pm.default_power_state_index == -1) {
2556 rdev->pm.power_state[0].type =
2557 POWER_STATE_TYPE_DEFAULT;
2558 rdev->pm.default_power_state_index = 0;
2559 rdev->pm.power_state[0].default_clock_mode =
2560 &rdev->pm.power_state[0].clock_info[0];
2565 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2567 struct radeon_mode_info *mode_info = &rdev->mode_info;
2568 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2571 int state_index = 0;
2573 rdev->pm.default_power_state_index = -1;
2575 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2576 &frev, &crev, &data_offset)) {
2581 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2585 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2588 state_index = radeon_atombios_parse_power_table_6(rdev);
2595 if (state_index == 0) {
2596 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2597 if (rdev->pm.power_state) {
2598 rdev->pm.power_state[0].clock_info =
2599 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2600 if (rdev->pm.power_state[0].clock_info) {
2601 /* add the default mode */
2602 rdev->pm.power_state[state_index].type =
2603 POWER_STATE_TYPE_DEFAULT;
2604 rdev->pm.power_state[state_index].num_clock_modes = 1;
2605 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2606 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2607 rdev->pm.power_state[state_index].default_clock_mode =
2608 &rdev->pm.power_state[state_index].clock_info[0];
2609 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2610 rdev->pm.power_state[state_index].pcie_lanes = 16;
2611 rdev->pm.default_power_state_index = state_index;
2612 rdev->pm.power_state[state_index].flags = 0;
2618 rdev->pm.num_power_states = state_index;
2620 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2621 rdev->pm.current_clock_mode_index = 0;
2622 if (rdev->pm.default_power_state_index >= 0)
2623 rdev->pm.current_vddc =
2624 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2626 rdev->pm.current_vddc = 0;
2629 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2631 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2632 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2634 args.ucEnable = enable;
2636 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2639 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2641 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2642 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2644 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2645 return le32_to_cpu(args.ulReturnEngineClock);
2648 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2650 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2651 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2653 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2654 return le32_to_cpu(args.ulReturnMemoryClock);
2657 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2660 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2661 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2663 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
2665 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2668 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2671 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2672 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2674 if (rdev->flags & RADEON_IS_IGP)
2677 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
2679 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2683 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2684 struct _SET_VOLTAGE_PARAMETERS v1;
2685 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2686 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
2689 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
2691 union set_voltage args;
2692 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2693 u8 frev, crev, volt_index = voltage_level;
2695 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2698 /* 0xff01 is a flag rather then an actual voltage */
2699 if (voltage_level == 0xff01)
2704 args.v1.ucVoltageType = voltage_type;
2705 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2706 args.v1.ucVoltageIndex = volt_index;
2709 args.v2.ucVoltageType = voltage_type;
2710 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2711 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
2714 args.v3.ucVoltageType = voltage_type;
2715 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
2716 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
2719 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2723 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2726 static int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
2727 u16 voltage_id, u16 *voltage)
2729 union set_voltage args;
2730 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2733 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2740 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
2741 args.v2.ucVoltageMode = 0;
2742 args.v2.usVoltageLevel = 0;
2744 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2746 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
2749 args.v3.ucVoltageType = voltage_type;
2750 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
2751 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
2753 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2755 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
2758 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2765 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2767 struct radeon_device *rdev = dev->dev_private;
2768 uint32_t bios_2_scratch, bios_6_scratch;
2770 if (rdev->family >= CHIP_R600) {
2771 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2772 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2774 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2775 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2778 /* let the bios control the backlight */
2779 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2781 /* tell the bios not to handle mode switching */
2782 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
2784 if (rdev->family >= CHIP_R600) {
2785 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2786 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2788 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2789 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2794 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2796 uint32_t scratch_reg;
2799 if (rdev->family >= CHIP_R600)
2800 scratch_reg = R600_BIOS_0_SCRATCH;
2802 scratch_reg = RADEON_BIOS_0_SCRATCH;
2804 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2805 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2808 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2810 uint32_t scratch_reg;
2813 if (rdev->family >= CHIP_R600)
2814 scratch_reg = R600_BIOS_0_SCRATCH;
2816 scratch_reg = RADEON_BIOS_0_SCRATCH;
2818 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2819 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2822 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2824 struct drm_device *dev = encoder->dev;
2825 struct radeon_device *rdev = dev->dev_private;
2826 uint32_t bios_6_scratch;
2828 if (rdev->family >= CHIP_R600)
2829 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2831 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2834 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2835 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
2837 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2838 bios_6_scratch |= ATOM_S6_ACC_MODE;
2841 if (rdev->family >= CHIP_R600)
2842 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2844 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2847 /* at some point we may want to break this out into individual functions */
2849 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2850 struct drm_encoder *encoder,
2853 struct drm_device *dev = connector->dev;
2854 struct radeon_device *rdev = dev->dev_private;
2855 struct radeon_connector *radeon_connector =
2856 to_radeon_connector(connector);
2857 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2858 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2860 if (rdev->family >= CHIP_R600) {
2861 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2862 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2863 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2865 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2866 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2867 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2870 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2871 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2873 DRM_DEBUG_KMS("TV1 connected\n");
2874 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2875 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2877 DRM_DEBUG_KMS("TV1 disconnected\n");
2878 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2879 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2880 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2883 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2884 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2886 DRM_DEBUG_KMS("CV connected\n");
2887 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2888 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2890 DRM_DEBUG_KMS("CV disconnected\n");
2891 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2892 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2893 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2896 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2897 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2899 DRM_DEBUG_KMS("LCD1 connected\n");
2900 bios_0_scratch |= ATOM_S0_LCD1;
2901 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2902 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2904 DRM_DEBUG_KMS("LCD1 disconnected\n");
2905 bios_0_scratch &= ~ATOM_S0_LCD1;
2906 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2907 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2910 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2911 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2913 DRM_DEBUG_KMS("CRT1 connected\n");
2914 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2915 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2916 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2918 DRM_DEBUG_KMS("CRT1 disconnected\n");
2919 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2920 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2921 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2924 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2925 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2927 DRM_DEBUG_KMS("CRT2 connected\n");
2928 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2929 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2930 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2932 DRM_DEBUG_KMS("CRT2 disconnected\n");
2933 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2934 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2935 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2938 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2939 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2941 DRM_DEBUG_KMS("DFP1 connected\n");
2942 bios_0_scratch |= ATOM_S0_DFP1;
2943 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2944 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2946 DRM_DEBUG_KMS("DFP1 disconnected\n");
2947 bios_0_scratch &= ~ATOM_S0_DFP1;
2948 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2949 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2952 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2953 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2955 DRM_DEBUG_KMS("DFP2 connected\n");
2956 bios_0_scratch |= ATOM_S0_DFP2;
2957 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2958 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2960 DRM_DEBUG_KMS("DFP2 disconnected\n");
2961 bios_0_scratch &= ~ATOM_S0_DFP2;
2962 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2963 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2966 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2967 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2969 DRM_DEBUG_KMS("DFP3 connected\n");
2970 bios_0_scratch |= ATOM_S0_DFP3;
2971 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2972 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2974 DRM_DEBUG_KMS("DFP3 disconnected\n");
2975 bios_0_scratch &= ~ATOM_S0_DFP3;
2976 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2977 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2980 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2981 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2983 DRM_DEBUG_KMS("DFP4 connected\n");
2984 bios_0_scratch |= ATOM_S0_DFP4;
2985 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2986 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2988 DRM_DEBUG_KMS("DFP4 disconnected\n");
2989 bios_0_scratch &= ~ATOM_S0_DFP4;
2990 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2991 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2994 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2995 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2997 DRM_DEBUG_KMS("DFP5 connected\n");
2998 bios_0_scratch |= ATOM_S0_DFP5;
2999 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
3000 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
3002 DRM_DEBUG_KMS("DFP5 disconnected\n");
3003 bios_0_scratch &= ~ATOM_S0_DFP5;
3004 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
3005 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
3008 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
3009 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
3011 DRM_DEBUG_KMS("DFP6 connected\n");
3012 bios_0_scratch |= ATOM_S0_DFP6;
3013 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
3014 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
3016 DRM_DEBUG_KMS("DFP6 disconnected\n");
3017 bios_0_scratch &= ~ATOM_S0_DFP6;
3018 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
3019 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
3023 if (rdev->family >= CHIP_R600) {
3024 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
3025 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
3026 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
3028 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3029 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
3030 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3035 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3037 struct drm_device *dev = encoder->dev;
3038 struct radeon_device *rdev = dev->dev_private;
3039 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3040 uint32_t bios_3_scratch;
3042 if (ASIC_IS_DCE4(rdev))
3045 if (rdev->family >= CHIP_R600)
3046 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
3048 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
3050 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3051 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
3052 bios_3_scratch |= (crtc << 18);
3054 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3055 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
3056 bios_3_scratch |= (crtc << 24);
3058 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3059 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
3060 bios_3_scratch |= (crtc << 16);
3062 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3063 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
3064 bios_3_scratch |= (crtc << 20);
3066 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3067 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
3068 bios_3_scratch |= (crtc << 17);
3070 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3071 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
3072 bios_3_scratch |= (crtc << 19);
3074 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3075 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
3076 bios_3_scratch |= (crtc << 23);
3078 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3079 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
3080 bios_3_scratch |= (crtc << 25);
3083 if (rdev->family >= CHIP_R600)
3084 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
3086 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
3090 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3092 struct drm_device *dev = encoder->dev;
3093 struct radeon_device *rdev = dev->dev_private;
3094 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3095 uint32_t bios_2_scratch;
3097 if (ASIC_IS_DCE4(rdev))
3100 if (rdev->family >= CHIP_R600)
3101 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
3103 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
3105 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3107 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
3109 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
3111 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3113 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
3115 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
3117 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3119 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
3121 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
3123 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3125 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
3127 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
3129 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3131 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
3133 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
3135 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3137 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
3139 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
3141 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3143 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
3145 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
3147 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3149 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
3151 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
3153 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
3155 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
3157 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
3159 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
3161 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
3163 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
3166 if (rdev->family >= CHIP_R600)
3167 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
3169 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);