drivers/gpu/drm/radeon/radeon_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include <drm/radeon_drm.h>
  36 #include "radeon.h"
  37 #include "radeon_trace.h"
  38
  39
  40 int radeon_ttm_init(struct radeon_device *rdev);
  41 void radeon_ttm_fini(struct radeon_device *rdev);
  42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
  43
  44 /*
  45  * To exclude mutual BO access we rely on bo_reserve exclusion, as all
  46  * function are calling it.
  47  */
  48
  49 void radeon_bo_clear_va(struct radeon_bo *bo)
  50 {
  51         struct radeon_bo_va *bo_va, *tmp;
  52
  53         list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
  54                 /* remove from all vm address space */
  55                 radeon_vm_bo_rmv(bo->rdev, bo_va);
  56         }
  57 }
  58
  59 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  60 {
  61         struct radeon_bo *bo;
  62
  63         bo = container_of(tbo, struct radeon_bo, tbo);
  64         mutex_lock(&bo->rdev->gem.mutex);
  65         list_del_init(&bo->list);
  66         mutex_unlock(&bo->rdev->gem.mutex);
  67         radeon_bo_clear_surface_reg(bo);
  68         radeon_bo_clear_va(bo);
  69         drm_gem_object_release(&bo->gem_base);
  70         kfree(bo);
  71 }
  72
  73 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
  74 {
  75         if (bo->destroy == &radeon_ttm_bo_destroy)
  76                 return true;
  77         return false;
  78 }
  79
  80 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
  81 {
  82         u32 c = 0;
  83
  84         rbo->placement.fpfn = 0;
  85         rbo->placement.lpfn = 0;
  86         rbo->placement.placement = rbo->placements;
  87         if (domain & RADEON_GEM_DOMAIN_VRAM)
  88                 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
  89                                         TTM_PL_FLAG_VRAM;
  90         if (domain & RADEON_GEM_DOMAIN_GTT) {
  91                 if (rbo->rdev->flags & RADEON_IS_AGP) {
  92                         rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;
  93                 } else {
  94                         rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
  95                 }
  96         }
  97         if (domain & RADEON_GEM_DOMAIN_CPU) {
  98                 if (rbo->rdev->flags & RADEON_IS_AGP) {
  99                         rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM;
 100                 } else {
 101                         rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM;
 102                 }
 103         }
 104         if (!c)
 105                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
 106         rbo->placement.num_placement = c;
 107
 108         c = 0;
 109         rbo->placement.busy_placement = rbo->busy_placements;
 110         if (rbo->rdev->flags & RADEON_IS_AGP) {
 111                 rbo->busy_placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;
 112         } else {
 113                 rbo->busy_placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
 114         }
 115         rbo->placement.num_busy_placement = c;
 116 }
 117
 118 int radeon_bo_create(struct radeon_device *rdev,
 119                      unsigned long size, int byte_align, bool kernel, u32 domain,
 120                      struct sg_table *sg, struct radeon_bo **bo_ptr)
 121 {
 122         struct radeon_bo *bo;
 123         enum ttm_bo_type type;
 124         unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 125         size_t acc_size;
 126         int r;
 127
 128         size = ALIGN(size, PAGE_SIZE);
 129
 130         rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
 131         if (kernel) {
 132                 type = ttm_bo_type_kernel;
 133         } else if (sg) {
 134                 type = ttm_bo_type_sg;
 135         } else {
 136                 type = ttm_bo_type_device;
 137         }
 138         *bo_ptr = NULL;
 139
 140         acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
 141                                        sizeof(struct radeon_bo));
 142
 143         bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
 144         if (bo == NULL)
 145                 return -ENOMEM;
 146         r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
 147         if (unlikely(r)) {
 148                 kfree(bo);
 149                 return r;
 150         }
 151         bo->rdev = rdev;
 152         bo->gem_base.driver_private = NULL;
 153         bo->surface_reg = -1;
 154         INIT_LIST_HEAD(&bo->list);
 155         INIT_LIST_HEAD(&bo->va);
 156         radeon_ttm_placement_from_domain(bo, domain);
 157         /* Kernel allocation are uninterruptible */
 158         down_read(&rdev->pm.mclk_lock);
 159         r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
 160                         &bo->placement, page_align, !kernel, NULL,
 161                         acc_size, sg, &radeon_ttm_bo_destroy);
 162         up_read(&rdev->pm.mclk_lock);
 163         if (unlikely(r != 0)) {
 164                 return r;
 165         }
 166         *bo_ptr = bo;
 167
 168         trace_radeon_bo_create(bo);
 169
 170         return 0;
 171 }
 172
 173 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
 174 {
 175         bool is_iomem;
 176         int r;
 177
 178         if (bo->kptr) {
 179                 if (ptr) {
 180                         *ptr = bo->kptr;
 181                 }
 182                 return 0;
 183         }
 184         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 185         if (r) {
 186                 return r;
 187         }
 188         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 189         if (ptr) {
 190                 *ptr = bo->kptr;
 191         }
 192         radeon_bo_check_tiling(bo, 0, 0);
 193         return 0;
 194 }
 195
 196 void radeon_bo_kunmap(struct radeon_bo *bo)
 197 {
 198         if (bo->kptr == NULL)
 199                 return;
 200         bo->kptr = NULL;
 201         radeon_bo_check_tiling(bo, 0, 0);
 202         ttm_bo_kunmap(&bo->kmap);
 203 }
 204
 205 void radeon_bo_unref(struct radeon_bo **bo)
 206 {
 207         struct ttm_buffer_object *tbo;
 208         struct radeon_device *rdev;
 209
 210         if ((*bo) == NULL)
 211                 return;
 212         rdev = (*bo)->rdev;
 213         tbo = &((*bo)->tbo);
 214         down_read(&rdev->pm.mclk_lock);
 215         ttm_bo_unref(&tbo);
 216         up_read(&rdev->pm.mclk_lock);
 217         if (tbo == NULL)
 218                 *bo = NULL;
 219 }
 220
 221 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
 222                              u64 *gpu_addr)
 223 {
 224         int r, i;
 225
 226         if (bo->pin_count) {
 227                 bo->pin_count++;
 228                 if (gpu_addr)
 229                         *gpu_addr = radeon_bo_gpu_offset(bo);
 230
 231                 if (max_offset != 0) {
 232                         u64 domain_start;
 233
 234                         if (domain == RADEON_GEM_DOMAIN_VRAM)
 235                                 domain_start = bo->rdev->mc.vram_start;
 236                         else
 237                                 domain_start = bo->rdev->mc.gtt_start;
 238                         WARN_ON_ONCE(max_offset <
 239                                      (radeon_bo_gpu_offset(bo) - domain_start));
 240                 }
 241
 242                 return 0;
 243         }
 244         radeon_ttm_placement_from_domain(bo, domain);
 245         if (domain == RADEON_GEM_DOMAIN_VRAM) {
 246                 /* force to pin into visible video ram */
 247                 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 248         }
 249         if (max_offset) {
 250                 u64 lpfn = max_offset >> PAGE_SHIFT;
 251
 252                 if (!bo->placement.lpfn)
 253                         bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;
 254
 255                 if (lpfn < bo->placement.lpfn)
 256                         bo->placement.lpfn = lpfn;
 257         }
 258         for (i = 0; i < bo->placement.num_placement; i++)
 259                 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
 260         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 261         if (likely(r == 0)) {
 262                 bo->pin_count = 1;
 263                 if (gpu_addr != NULL)
 264                         *gpu_addr = radeon_bo_gpu_offset(bo);
 265         }
 266         if (unlikely(r != 0))
 267                 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
 268         return r;
 269 }
 270
 271 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
 272 {
 273         return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
 274 }
 275
 276 int radeon_bo_unpin(struct radeon_bo *bo)
 277 {
 278         int r, i;
 279
 280         if (!bo->pin_count) {
 281                 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
 282                 return 0;
 283         }
 284         bo->pin_count--;
 285         if (bo->pin_count)
 286                 return 0;
 287         for (i = 0; i < bo->placement.num_placement; i++)
 288                 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
 289         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 290         if (unlikely(r != 0))
 291                 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
 292         return r;
 293 }
 294
 295 int radeon_bo_evict_vram(struct radeon_device *rdev)
 296 {
 297         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 298         if (0 && (rdev->flags & RADEON_IS_IGP)) {
 299                 if (rdev->mc.igp_sideport_enabled == false)
 300                         /* Useless to evict on IGP chips */
 301                         return 0;
 302         }
 303         return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
 304 }
 305
 306 void radeon_bo_force_delete(struct radeon_device *rdev)
 307 {
 308         struct radeon_bo *bo, *n;
 309
 310         if (list_empty(&rdev->gem.objects)) {
 311                 return;
 312         }
 313         dev_err(rdev->dev, "Userspace still has active objects !\n");
 314         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 315                 mutex_lock(&rdev->ddev->struct_mutex);
 316                 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
 317                         &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
 318                         *((unsigned long *)&bo->gem_base.refcount));
 319                 mutex_lock(&bo->rdev->gem.mutex);
 320                 list_del_init(&bo->list);
 321                 mutex_unlock(&bo->rdev->gem.mutex);
 322                 /* this should unref the ttm bo */
 323                 drm_gem_object_unreference(&bo->gem_base);
 324                 mutex_unlock(&rdev->ddev->struct_mutex);
 325         }
 326 }
 327
 328 int radeon_bo_init(struct radeon_device *rdev)
 329 {
 330         /* Add an MTRR for the VRAM */
 331         rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
 332                         MTRR_TYPE_WRCOMB, 1);
 333         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 334                 rdev->mc.mc_vram_size >> 20,
 335                 (unsigned long long)rdev->mc.aper_size >> 20);
 336         DRM_INFO("RAM width %dbits %cDR\n",
 337                         rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
 338         return radeon_ttm_init(rdev);
 339 }
 340
 341 void radeon_bo_fini(struct radeon_device *rdev)
 342 {
 343         radeon_ttm_fini(rdev);
 344 }
 345
 346 void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
 347                                 struct list_head *head)
 348 {
 349         if (lobj->wdomain) {
 350                 list_add(&lobj->tv.head, head);
 351         } else {
 352                 list_add_tail(&lobj->tv.head, head);
 353         }
 354 }
 355
 356 int radeon_bo_list_validate(struct list_head *head)
 357 {
 358         struct radeon_bo_list *lobj;
 359         struct radeon_bo *bo;
 360         int r;
 361
 362         r = ttm_eu_reserve_buffers(head);
 363         if (unlikely(r != 0)) {
 364                 return r;
 365         }
 366         list_for_each_entry(lobj, head, tv.head) {
 367                 bo = lobj->bo;
 368                 if (!bo->pin_count) {
 369                         r = ttm_bo_validate(&bo->tbo, &bo->placement,
 370                                                 true, false);
 371                         if (unlikely(r)) {
 372                                 return r;
 373                         }
 374                 }
 375                 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
 376                 lobj->tiling_flags = bo->tiling_flags;
 377         }
 378         return 0;
 379 }
 380
 381 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
 382                              struct vm_area_struct *vma)
 383 {
 384         return ttm_fbdev_mmap(vma, &bo->tbo);
 385 }
 386
 387 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
 388 {
 389         struct radeon_device *rdev = bo->rdev;
 390         struct radeon_surface_reg *reg;
 391         struct radeon_bo *old_object;
 392         int steal;
 393         int i;
 394
 395         BUG_ON(!radeon_bo_is_reserved(bo));
 396
 397         if (!bo->tiling_flags)
 398                 return 0;
 399
 400         if (bo->surface_reg >= 0) {
 401                 reg = &rdev->surface_regs[bo->surface_reg];
 402                 i = bo->surface_reg;
 403                 goto out;
 404         }
 405
 406         steal = -1;
 407         for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
 408
 409                 reg = &rdev->surface_regs[i];
 410                 if (!reg->bo)
 411                         break;
 412
 413                 old_object = reg->bo;
 414                 if (old_object->pin_count == 0)
 415                         steal = i;
 416         }
 417
 418         /* if we are all out */
 419         if (i == RADEON_GEM_MAX_SURFACES) {
 420                 if (steal == -1)
 421                         return -ENOMEM;
 422                 /* find someone with a surface reg and nuke their BO */
 423                 reg = &rdev->surface_regs[steal];
 424                 old_object = reg->bo;
 425                 /* blow away the mapping */
 426                 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
 427                 ttm_bo_unmap_virtual(&old_object->tbo);
 428                 old_object->surface_reg = -1;
 429                 i = steal;
 430         }
 431
 432         bo->surface_reg = i;
 433         reg->bo = bo;
 434
 435 out:
 436         radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
 437                                bo->tbo.mem.start << PAGE_SHIFT,
 438                                bo->tbo.num_pages << PAGE_SHIFT);
 439         return 0;
 440 }
 441
 442 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
 443 {
 444         struct radeon_device *rdev = bo->rdev;
 445         struct radeon_surface_reg *reg;
 446
 447         if (bo->surface_reg == -1)
 448                 return;
 449
 450         reg = &rdev->surface_regs[bo->surface_reg];
 451         radeon_clear_surface_reg(rdev, bo->surface_reg);
 452
 453         reg->bo = NULL;
 454         bo->surface_reg = -1;
 455 }
 456
 457 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
 458                                 uint32_t tiling_flags, uint32_t pitch)
 459 {
 460         struct radeon_device *rdev = bo->rdev;
 461         int r;
 462
 463         if (rdev->family >= CHIP_CEDAR) {
 464                 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
 465
 466                 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
 467                 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
 468                 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
 469                 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
 470                 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
 471                 switch (bankw) {
 472                 case 0:
 473                 case 1:
 474                 case 2:
 475                 case 4:
 476                 case 8:
 477                         break;
 478                 default:
 479                         return -EINVAL;
 480                 }
 481                 switch (bankh) {
 482                 case 0:
 483                 case 1:
 484                 case 2:
 485                 case 4:
 486                 case 8:
 487                         break;
 488                 default:
 489                         return -EINVAL;
 490                 }
 491                 switch (mtaspect) {
 492                 case 0:
 493                 case 1:
 494                 case 2:
 495                 case 4:
 496                 case 8:
 497                         break;
 498                 default:
 499                         return -EINVAL;
 500                 }
 501                 if (tilesplit > 6) {
 502                         return -EINVAL;
 503                 }
 504                 if (stilesplit > 6) {
 505                         return -EINVAL;
 506                 }
 507         }
 508         r = radeon_bo_reserve(bo, false);
 509         if (unlikely(r != 0))
 510                 return r;
 511         bo->tiling_flags = tiling_flags;
 512         bo->pitch = pitch;
 513         radeon_bo_unreserve(bo);
 514         return 0;
 515 }
 516
 517 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
 518                                 uint32_t *tiling_flags,
 519                                 uint32_t *pitch)
 520 {
 521         BUG_ON(!radeon_bo_is_reserved(bo));
 522         if (tiling_flags)
 523                 *tiling_flags = bo->tiling_flags;
 524         if (pitch)
 525                 *pitch = bo->pitch;
 526 }
 527
 528 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
 529                                 bool force_drop)
 530 {
 531         BUG_ON(!radeon_bo_is_reserved(bo) && !force_drop);
 532
 533         if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
 534                 return 0;
 535
 536         if (force_drop) {
 537                 radeon_bo_clear_surface_reg(bo);
 538                 return 0;
 539         }
 540
 541         if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
 542                 if (!has_moved)
 543                         return 0;
 544
 545                 if (bo->surface_reg >= 0)
 546                         radeon_bo_clear_surface_reg(bo);
 547                 return 0;
 548         }
 549
 550         if ((bo->surface_reg >= 0) && !has_moved)
 551                 return 0;
 552
 553         return radeon_bo_get_surface_reg(bo);
 554 }
 555
 556 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
 557                            struct ttm_mem_reg *mem)
 558 {
 559         struct radeon_bo *rbo;
 560         if (!radeon_ttm_bo_is_radeon_bo(bo))
 561                 return;
 562         rbo = container_of(bo, struct radeon_bo, tbo);
 563         radeon_bo_check_tiling(rbo, 0, 1);
 564         radeon_vm_bo_invalidate(rbo->rdev, rbo);
 565 }
 566
 567 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 568 {
 569         struct radeon_device *rdev;
 570         struct radeon_bo *rbo;
 571         unsigned long offset, size;
 572         int r;
 573
 574         if (!radeon_ttm_bo_is_radeon_bo(bo))
 575                 return 0;
 576         rbo = container_of(bo, struct radeon_bo, tbo);
 577         radeon_bo_check_tiling(rbo, 0, 0);
 578         rdev = rbo->rdev;
 579         if (bo->mem.mem_type == TTM_PL_VRAM) {
 580                 size = bo->mem.num_pages << PAGE_SHIFT;
 581                 offset = bo->mem.start << PAGE_SHIFT;
 582                 if ((offset + size) > rdev->mc.visible_vram_size) {
 583                         /* hurrah the memory is not visible ! */
 584                         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
 585                         rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
 586                         r = ttm_bo_validate(bo, &rbo->placement, false, false);
 587                         if (unlikely(r != 0))
 588                                 return r;
 589                         offset = bo->mem.start << PAGE_SHIFT;
 590                         /* this should not happen */
 591                         if ((offset + size) > rdev->mc.visible_vram_size)
 592                                 return -EINVAL;
 593                 }
 594         }
 595         return 0;
 596 }
 597
 598 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
 599 {
 600         int r;
 601
 602         r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
 603         if (unlikely(r != 0))
 604                 return r;
 605         spin_lock(&bo->tbo.bdev->fence_lock);
 606         if (mem_type)
 607                 *mem_type = bo->tbo.mem.mem_type;
 608         if (bo->tbo.sync_obj)
 609                 r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
 610         spin_unlock(&bo->tbo.bdev->fence_lock);
 611         ttm_bo_unreserve(&bo->tbo);
 612         return r;
 613 }
 614
 615
 616 /**
 617  * radeon_bo_reserve - reserve bo
 618  * @bo:         bo structure
 619  * @no_intr:    don't return -ERESTARTSYS on pending signal
 620  *
 621  * Returns:
 622  * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
 623  * a signal. Release all buffer reservations and return to user-space.
 624  */
 625 int radeon_bo_reserve(struct radeon_bo *bo, bool no_intr)
 626 {
 627         int r;
 628
 629         r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0);
 630         if (unlikely(r != 0)) {
 631                 if (r != -ERESTARTSYS)
 632                         dev_err(bo->rdev->dev, "%p reserve failed\n", bo);
 633                 return r;
 634         }
 635         return 0;
 636 }