drivers/gpu/drm/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include <drm/drmP.h>
  24 #include "radeon.h"
  25 #include "avivod.h"
  26 #include "atom.h"
  27 #include <linux/power_supply.h>
  28 #include <linux/hwmon.h>
  29 #include <linux/hwmon-sysfs.h>
  30
  31 #define RADEON_IDLE_LOOP_MS 100
  32 #define RADEON_RECLOCK_DELAY_MS 200
  33 #define RADEON_WAIT_VBLANK_TIMEOUT 200
  34
  35 static const char *radeon_pm_state_type_name[5] = {
  36         "",
  37         "Powersave",
  38         "Battery",
  39         "Balanced",
  40         "Performance",
  41 };
  42
  43 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
  44 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  45 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
  46 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
  47 static void radeon_pm_update_profile(struct radeon_device *rdev);
  48 static void radeon_pm_set_clocks(struct radeon_device *rdev);
  49
  50 int radeon_pm_get_type_index(struct radeon_device *rdev,
  51                              enum radeon_pm_state_type ps_type,
  52                              int instance)
  53 {
  54         int i;
  55         int found_instance = -1;
  56
  57         for (i = 0; i < rdev->pm.num_power_states; i++) {
  58                 if (rdev->pm.power_state[i].type == ps_type) {
  59                         found_instance++;
  60                         if (found_instance == instance)
  61                                 return i;
  62                 }
  63         }
  64         /* return default if no match */
  65         return rdev->pm.default_power_state_index;
  66 }
  67
  68 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
  69 {
  70         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
  71                 if (rdev->pm.profile == PM_PROFILE_AUTO) {
  72                         mutex_lock(&rdev->pm.mutex);
  73                         radeon_pm_update_profile(rdev);
  74                         radeon_pm_set_clocks(rdev);
  75                         mutex_unlock(&rdev->pm.mutex);
  76                 }
  77         }
  78 }
  79
  80 static void radeon_pm_update_profile(struct radeon_device *rdev)
  81 {
  82         switch (rdev->pm.profile) {
  83         case PM_PROFILE_DEFAULT:
  84                 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
  85                 break;
  86         case PM_PROFILE_AUTO:
  87                 if (power_supply_is_system_supplied() > 0) {
  88                         if (rdev->pm.active_crtc_count > 1)
  89                                 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
  90                         else
  91                                 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
  92                 } else {
  93                         if (rdev->pm.active_crtc_count > 1)
  94                                 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
  95                         else
  96                                 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
  97                 }
  98                 break;
  99         case PM_PROFILE_LOW:
 100                 if (rdev->pm.active_crtc_count > 1)
 101                         rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
 102                 else
 103                         rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
 104                 break;
 105         case PM_PROFILE_MID:
 106                 if (rdev->pm.active_crtc_count > 1)
 107                         rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
 108                 else
 109                         rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
 110                 break;
 111         case PM_PROFILE_HIGH:
 112                 if (rdev->pm.active_crtc_count > 1)
 113                         rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
 114                 else
 115                         rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
 116                 break;
 117         }
 118
 119         if (rdev->pm.active_crtc_count == 0) {
 120                 rdev->pm.requested_power_state_index =
 121                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
 122                 rdev->pm.requested_clock_mode_index =
 123                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
 124         } else {
 125                 rdev->pm.requested_power_state_index =
 126                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
 127                 rdev->pm.requested_clock_mode_index =
 128                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
 129         }
 130 }
 131
 132 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
 133 {
 134         struct radeon_bo *bo, *n;
 135
 136         if (list_empty(&rdev->gem.objects))
 137                 return;
 138
 139         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 140                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 141                         ttm_bo_unmap_virtual(&bo->tbo);
 142         }
 143 }
 144
 145 static void radeon_sync_with_vblank(struct radeon_device *rdev)
 146 {
 147         if (rdev->pm.active_crtcs) {
 148                 rdev->pm.vblank_sync = false;
 149                 wait_event_timeout(
 150                         rdev->irq.vblank_queue, rdev->pm.vblank_sync,
 151                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
 152         }
 153 }
 154
 155 static void radeon_set_power_state(struct radeon_device *rdev)
 156 {
 157         u32 sclk, mclk;
 158         bool misc_after = false;
 159
 160         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 161             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 162                 return;
 163
 164         if (radeon_gui_idle(rdev)) {
 165                 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 166                         clock_info[rdev->pm.requested_clock_mode_index].sclk;
 167                 if (sclk > rdev->pm.default_sclk)
 168                         sclk = rdev->pm.default_sclk;
 169
 170                 /* starting with BTC, there is one state that is used for both
 171                  * MH and SH.  Difference is that we always use the high clock index for
 172                  * mclk and vddci.
 173                  */
 174                 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
 175                     (rdev->family >= CHIP_BARTS) &&
 176                     rdev->pm.active_crtc_count &&
 177                     ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
 178                      (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
 179                         mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 180                                 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
 181                 else
 182                         mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 183                                 clock_info[rdev->pm.requested_clock_mode_index].mclk;
 184
 185                 if (mclk > rdev->pm.default_mclk)
 186                         mclk = rdev->pm.default_mclk;
 187
 188                 /* upvolt before raising clocks, downvolt after lowering clocks */
 189                 if (sclk < rdev->pm.current_sclk)
 190                         misc_after = true;
 191
 192                 radeon_sync_with_vblank(rdev);
 193
 194                 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 195                         if (!radeon_pm_in_vbl(rdev))
 196                                 return;
 197                 }
 198
 199                 radeon_pm_prepare(rdev);
 200
 201                 if (!misc_after)
 202                         /* voltage, pcie lanes, etc.*/
 203                         radeon_pm_misc(rdev);
 204
 205                 /* set engine clock */
 206                 if (sclk != rdev->pm.current_sclk) {
 207                         radeon_pm_debug_check_in_vbl(rdev, false);
 208                         radeon_set_engine_clock(rdev, sclk);
 209                         radeon_pm_debug_check_in_vbl(rdev, true);
 210                         rdev->pm.current_sclk = sclk;
 211                         DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
 212                 }
 213
 214                 /* set memory clock */
 215                 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 216                         radeon_pm_debug_check_in_vbl(rdev, false);
 217                         radeon_set_memory_clock(rdev, mclk);
 218                         radeon_pm_debug_check_in_vbl(rdev, true);
 219                         rdev->pm.current_mclk = mclk;
 220                         DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
 221                 }
 222
 223                 if (misc_after)
 224                         /* voltage, pcie lanes, etc.*/
 225                         radeon_pm_misc(rdev);
 226
 227                 radeon_pm_finish(rdev);
 228
 229                 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
 230                 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
 231         } else
 232                 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
 233 }
 234
 235 static void radeon_pm_set_clocks(struct radeon_device *rdev)
 236 {
 237         int i, r;
 238
 239         /* no need to take locks, etc. if nothing's going to change */
 240         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 241             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 242                 return;
 243
 244         mutex_lock(&rdev->ddev->struct_mutex);
 245         down_write(&rdev->pm.mclk_lock);
 246         mutex_lock(&rdev->ring_lock);
 247
 248         /* wait for the rings to drain */
 249         for (i = 0; i < RADEON_NUM_RINGS; i++) {
 250                 struct radeon_ring *ring = &rdev->ring[i];
 251                 if (!ring->ready) {
 252                         continue;
 253                 }
 254                 r = radeon_fence_wait_empty_locked(rdev, i);
 255                 if (r) {
 256                         /* needs a GPU reset dont reset here */
 257                         mutex_unlock(&rdev->ring_lock);
 258                         up_write(&rdev->pm.mclk_lock);
 259                         mutex_unlock(&rdev->ddev->struct_mutex);
 260                         return;
 261                 }
 262         }
 263
 264         radeon_unmap_vram_bos(rdev);
 265
 266         if (rdev->irq.installed) {
 267                 for (i = 0; i < rdev->num_crtc; i++) {
 268                         if (rdev->pm.active_crtcs & (1 << i)) {
 269                                 rdev->pm.req_vblank |= (1 << i);
 270                                 drm_vblank_get(rdev->ddev, i);
 271                         }
 272                 }
 273         }
 274
 275         radeon_set_power_state(rdev);
 276
 277         if (rdev->irq.installed) {
 278                 for (i = 0; i < rdev->num_crtc; i++) {
 279                         if (rdev->pm.req_vblank & (1 << i)) {
 280                                 rdev->pm.req_vblank &= ~(1 << i);
 281                                 drm_vblank_put(rdev->ddev, i);
 282                         }
 283                 }
 284         }
 285
 286         /* update display watermarks based on new power state */
 287         radeon_update_bandwidth_info(rdev);
 288         if (rdev->pm.active_crtc_count)
 289                 radeon_bandwidth_update(rdev);
 290
 291         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 292
 293         mutex_unlock(&rdev->ring_lock);
 294         up_write(&rdev->pm.mclk_lock);
 295         mutex_unlock(&rdev->ddev->struct_mutex);
 296 }
 297
 298 static void radeon_pm_print_states(struct radeon_device *rdev)
 299 {
 300         int i, j;
 301         struct radeon_power_state *power_state;
 302         struct radeon_pm_clock_info *clock_info;
 303
 304         DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
 305         for (i = 0; i < rdev->pm.num_power_states; i++) {
 306                 power_state = &rdev->pm.power_state[i];
 307                 DRM_DEBUG_DRIVER("State %d: %s\n", i,
 308                         radeon_pm_state_type_name[power_state->type]);
 309                 if (i == rdev->pm.default_power_state_index)
 310                         DRM_DEBUG_DRIVER("\tDefault");
 311                 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
 312                         DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
 313                 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 314                         DRM_DEBUG_DRIVER("\tSingle display only\n");
 315                 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
 316                 for (j = 0; j < power_state->num_clock_modes; j++) {
 317                         clock_info = &(power_state->clock_info[j]);
 318                         if (rdev->flags & RADEON_IS_IGP)
 319                                 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
 320                                                  j,
 321                                                  clock_info->sclk * 10);
 322                         else
 323                                 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
 324                                                  j,
 325                                                  clock_info->sclk * 10,
 326                                                  clock_info->mclk * 10,
 327                                                  clock_info->voltage.voltage);
 328                 }
 329         }
 330 }
 331
 332 static ssize_t radeon_get_pm_profile(struct device *dev,
 333                                      struct device_attribute *attr,
 334                                      char *buf)
 335 {
 336         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 337         struct radeon_device *rdev = ddev->dev_private;
 338         int cp = rdev->pm.profile;
 339
 340         return snprintf(buf, PAGE_SIZE, "%s\n",
 341                         (cp == PM_PROFILE_AUTO) ? "auto" :
 342                         (cp == PM_PROFILE_LOW) ? "low" :
 343                         (cp == PM_PROFILE_MID) ? "mid" :
 344                         (cp == PM_PROFILE_HIGH) ? "high" : "default");
 345 }
 346
 347 static ssize_t radeon_set_pm_profile(struct device *dev,
 348                                      struct device_attribute *attr,
 349                                      const char *buf,
 350                                      size_t count)
 351 {
 352         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 353         struct radeon_device *rdev = ddev->dev_private;
 354
 355         mutex_lock(&rdev->pm.mutex);
 356         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 357                 if (strncmp("default", buf, strlen("default")) == 0)
 358                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 359                 else if (strncmp("auto", buf, strlen("auto")) == 0)
 360                         rdev->pm.profile = PM_PROFILE_AUTO;
 361                 else if (strncmp("low", buf, strlen("low")) == 0)
 362                         rdev->pm.profile = PM_PROFILE_LOW;
 363                 else if (strncmp("mid", buf, strlen("mid")) == 0)
 364                         rdev->pm.profile = PM_PROFILE_MID;
 365                 else if (strncmp("high", buf, strlen("high")) == 0)
 366                         rdev->pm.profile = PM_PROFILE_HIGH;
 367                 else {
 368                         count = -EINVAL;
 369                         goto fail;
 370                 }
 371                 radeon_pm_update_profile(rdev);
 372                 radeon_pm_set_clocks(rdev);
 373         } else
 374                 count = -EINVAL;
 375
 376 fail:
 377         mutex_unlock(&rdev->pm.mutex);
 378
 379         return count;
 380 }
 381
 382 static ssize_t radeon_get_pm_method(struct device *dev,
 383                                     struct device_attribute *attr,
 384                                     char *buf)
 385 {
 386         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 387         struct radeon_device *rdev = ddev->dev_private;
 388         int pm = rdev->pm.pm_method;
 389
 390         return snprintf(buf, PAGE_SIZE, "%s\n",
 391                         (pm == PM_METHOD_DYNPM) ? "dynpm" :
 392                         (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
 393 }
 394
 395 static ssize_t radeon_set_pm_method(struct device *dev,
 396                                     struct device_attribute *attr,
 397                                     const char *buf,
 398                                     size_t count)
 399 {
 400         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 401         struct radeon_device *rdev = ddev->dev_private;
 402
 403         /* we don't support the legacy modes with dpm */
 404         if (rdev->pm.pm_method == PM_METHOD_DPM) {
 405                 count = -EINVAL;
 406                 goto fail;
 407         }
 408
 409         if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
 410                 mutex_lock(&rdev->pm.mutex);
 411                 rdev->pm.pm_method = PM_METHOD_DYNPM;
 412                 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 413                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 414                 mutex_unlock(&rdev->pm.mutex);
 415         } else if (strncmp("profile", buf, strlen("profile")) == 0) {
 416                 mutex_lock(&rdev->pm.mutex);
 417                 /* disable dynpm */
 418                 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 419                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 420                 rdev->pm.pm_method = PM_METHOD_PROFILE;
 421                 mutex_unlock(&rdev->pm.mutex);
 422                 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 423         } else {
 424                 count = -EINVAL;
 425                 goto fail;
 426         }
 427         radeon_pm_compute_clocks(rdev);
 428 fail:
 429         return count;
 430 }
 431
 432 static ssize_t radeon_get_dpm_state(struct device *dev,
 433                                     struct device_attribute *attr,
 434                                     char *buf)
 435 {
 436         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 437         struct radeon_device *rdev = ddev->dev_private;
 438         enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
 439
 440         return snprintf(buf, PAGE_SIZE, "%s\n",
 441                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 442                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 443 }
 444
 445 static ssize_t radeon_set_dpm_state(struct device *dev,
 446                                     struct device_attribute *attr,
 447                                     const char *buf,
 448                                     size_t count)
 449 {
 450         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 451         struct radeon_device *rdev = ddev->dev_private;
 452
 453         mutex_lock(&rdev->pm.mutex);
 454         if (strncmp("battery", buf, strlen("battery")) == 0)
 455                 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
 456         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 457                 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
 458         else if (strncmp("performance", buf, strlen("performance")) == 0)
 459                 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
 460         else {
 461                 mutex_unlock(&rdev->pm.mutex);
 462                 count = -EINVAL;
 463                 goto fail;
 464         }
 465         mutex_unlock(&rdev->pm.mutex);
 466         radeon_pm_compute_clocks(rdev);
 467 fail:
 468         return count;
 469 }
 470
 471 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
 472                                                        struct device_attribute *attr,
 473                                                        char *buf)
 474 {
 475         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 476         struct radeon_device *rdev = ddev->dev_private;
 477         enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
 478
 479         return snprintf(buf, PAGE_SIZE, "%s\n",
 480                         (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 481                         (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
 482 }
 483
 484 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
 485                                                        struct device_attribute *attr,
 486                                                        const char *buf,
 487                                                        size_t count)
 488 {
 489         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 490         struct radeon_device *rdev = ddev->dev_private;
 491         enum radeon_dpm_forced_level level;
 492         int ret = 0;
 493
 494         mutex_lock(&rdev->pm.mutex);
 495         if (strncmp("low", buf, strlen("low")) == 0) {
 496                 level = RADEON_DPM_FORCED_LEVEL_LOW;
 497         } else if (strncmp("high", buf, strlen("high")) == 0) {
 498                 level = RADEON_DPM_FORCED_LEVEL_HIGH;
 499         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 500                 level = RADEON_DPM_FORCED_LEVEL_AUTO;
 501         } else {
 502                 mutex_unlock(&rdev->pm.mutex);
 503                 count = -EINVAL;
 504                 goto fail;
 505         }
 506         if (rdev->asic->dpm.force_performance_level) {
 507                 ret = radeon_dpm_force_performance_level(rdev, level);
 508                 if (ret)
 509                         count = -EINVAL;
 510         }
 511         mutex_unlock(&rdev->pm.mutex);
 512 fail:
 513         return count;
 514 }
 515
 516 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
 517 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
 518 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
 519 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
 520                    radeon_get_dpm_forced_performance_level,
 521                    radeon_set_dpm_forced_performance_level);
 522
 523 static ssize_t radeon_hwmon_show_temp(struct device *dev,
 524                                       struct device_attribute *attr,
 525                                       char *buf)
 526 {
 527         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 528         struct radeon_device *rdev = ddev->dev_private;
 529         int temp;
 530
 531         if (rdev->asic->pm.get_temperature)
 532                 temp = radeon_get_temperature(rdev);
 533         else
 534                 temp = 0;
 535
 536         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 537 }
 538
 539 static ssize_t radeon_hwmon_show_name(struct device *dev,
 540                                       struct device_attribute *attr,
 541                                       char *buf)
 542 {
 543         return sprintf(buf, "radeon\n");
 544 }
 545
 546 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
 547 static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
 548
 549 static struct attribute *hwmon_attributes[] = {
 550         &sensor_dev_attr_temp1_input.dev_attr.attr,
 551         &sensor_dev_attr_name.dev_attr.attr,
 552         NULL
 553 };
 554
 555 static const struct attribute_group hwmon_attrgroup = {
 556         .attrs = hwmon_attributes,
 557 };
 558
 559 static int radeon_hwmon_init(struct radeon_device *rdev)
 560 {
 561         int err = 0;
 562
 563         rdev->pm.int_hwmon_dev = NULL;
 564
 565         switch (rdev->pm.int_thermal_type) {
 566         case THERMAL_TYPE_RV6XX:
 567         case THERMAL_TYPE_RV770:
 568         case THERMAL_TYPE_EVERGREEN:
 569         case THERMAL_TYPE_NI:
 570         case THERMAL_TYPE_SUMO:
 571         case THERMAL_TYPE_SI:
 572         case THERMAL_TYPE_CI:
 573         case THERMAL_TYPE_KV:
 574                 if (rdev->asic->pm.get_temperature == NULL)
 575                         return err;
 576                 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
 577                 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
 578                         err = PTR_ERR(rdev->pm.int_hwmon_dev);
 579                         dev_err(rdev->dev,
 580                                 "Unable to register hwmon device: %d\n", err);
 581                         break;
 582                 }
 583                 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
 584                 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
 585                                          &hwmon_attrgroup);
 586                 if (err) {
 587                         dev_err(rdev->dev,
 588                                 "Unable to create hwmon sysfs file: %d\n", err);
 589                         hwmon_device_unregister(rdev->dev);
 590                 }
 591                 break;
 592         default:
 593                 break;
 594         }
 595
 596         return err;
 597 }
 598
 599 static void radeon_hwmon_fini(struct radeon_device *rdev)
 600 {
 601         if (rdev->pm.int_hwmon_dev) {
 602                 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
 603                 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
 604         }
 605 }
 606
 607 static void radeon_dpm_thermal_work_handler(struct work_struct *work)
 608 {
 609         struct radeon_device *rdev =
 610                 container_of(work, struct radeon_device,
 611                              pm.dpm.thermal.work);
 612         /* switch to the thermal state */
 613         enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
 614
 615         if (!rdev->pm.dpm_enabled)
 616                 return;
 617
 618         if (rdev->asic->pm.get_temperature) {
 619                 int temp = radeon_get_temperature(rdev);
 620
 621                 if (temp < rdev->pm.dpm.thermal.min_temp)
 622                         /* switch back the user state */
 623                         dpm_state = rdev->pm.dpm.user_state;
 624         } else {
 625                 if (rdev->pm.dpm.thermal.high_to_low)
 626                         /* switch back the user state */
 627                         dpm_state = rdev->pm.dpm.user_state;
 628         }
 629         mutex_lock(&rdev->pm.mutex);
 630         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
 631                 rdev->pm.dpm.thermal_active = true;
 632         else
 633                 rdev->pm.dpm.thermal_active = false;
 634         rdev->pm.dpm.state = dpm_state;
 635         mutex_unlock(&rdev->pm.mutex);
 636
 637         radeon_pm_compute_clocks(rdev);
 638 }
 639
 640 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
 641                                                      enum radeon_pm_state_type dpm_state)
 642 {
 643         int i;
 644         struct radeon_ps *ps;
 645         u32 ui_class;
 646         bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
 647                 true : false;
 648
 649         /* check if the vblank period is too short to adjust the mclk */
 650         if (single_display && rdev->asic->dpm.vblank_too_short) {
 651                 if (radeon_dpm_vblank_too_short(rdev))
 652                         single_display = false;
 653         }
 654
 655         /* certain older asics have a separare 3D performance state,
 656          * so try that first if the user selected performance
 657          */
 658         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
 659                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
 660         /* balanced states don't exist at the moment */
 661         if (dpm_state == POWER_STATE_TYPE_BALANCED)
 662                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 663
 664 restart_search:
 665         /* Pick the best power state based on current conditions */
 666         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
 667                 ps = &rdev->pm.dpm.ps[i];
 668                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
 669                 switch (dpm_state) {
 670                 /* user states */
 671                 case POWER_STATE_TYPE_BATTERY:
 672                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
 673                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 674                                         if (single_display)
 675                                                 return ps;
 676                                 } else
 677                                         return ps;
 678                         }
 679                         break;
 680                 case POWER_STATE_TYPE_BALANCED:
 681                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
 682                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 683                                         if (single_display)
 684                                                 return ps;
 685                                 } else
 686                                         return ps;
 687                         }
 688                         break;
 689                 case POWER_STATE_TYPE_PERFORMANCE:
 690                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
 691                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 692                                         if (single_display)
 693                                                 return ps;
 694                                 } else
 695                                         return ps;
 696                         }
 697                         break;
 698                 /* internal states */
 699                 case POWER_STATE_TYPE_INTERNAL_UVD:
 700                         if (rdev->pm.dpm.uvd_ps)
 701                                 return rdev->pm.dpm.uvd_ps;
 702                         else
 703                                 break;
 704                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 705                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
 706                                 return ps;
 707                         break;
 708                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 709                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
 710                                 return ps;
 711                         break;
 712                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 713                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
 714                                 return ps;
 715                         break;
 716                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 717                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
 718                                 return ps;
 719                         break;
 720                 case POWER_STATE_TYPE_INTERNAL_BOOT:
 721                         return rdev->pm.dpm.boot_ps;
 722                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
 723                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
 724                                 return ps;
 725                         break;
 726                 case POWER_STATE_TYPE_INTERNAL_ACPI:
 727                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
 728                                 return ps;
 729                         break;
 730                 case POWER_STATE_TYPE_INTERNAL_ULV:
 731                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
 732                                 return ps;
 733                         break;
 734                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
 735                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
 736                                 return ps;
 737                         break;
 738                 default:
 739                         break;
 740                 }
 741         }
 742         /* use a fallback state if we didn't match */
 743         switch (dpm_state) {
 744         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 745                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
 746                 goto restart_search;
 747         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 748         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 749         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 750                 if (rdev->pm.dpm.uvd_ps) {
 751                         return rdev->pm.dpm.uvd_ps;
 752                 } else {
 753                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 754                         goto restart_search;
 755                 }
 756         case POWER_STATE_TYPE_INTERNAL_THERMAL:
 757                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
 758                 goto restart_search;
 759         case POWER_STATE_TYPE_INTERNAL_ACPI:
 760                 dpm_state = POWER_STATE_TYPE_BATTERY;
 761                 goto restart_search;
 762         case POWER_STATE_TYPE_BATTERY:
 763         case POWER_STATE_TYPE_BALANCED:
 764         case POWER_STATE_TYPE_INTERNAL_3DPERF:
 765                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 766                 goto restart_search;
 767         default:
 768                 break;
 769         }
 770
 771         return NULL;
 772 }
 773
 774 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
 775 {
 776         int i;
 777         struct radeon_ps *ps;
 778         enum radeon_pm_state_type dpm_state;
 779         int ret;
 780
 781         /* if dpm init failed */
 782         if (!rdev->pm.dpm_enabled)
 783                 return;
 784
 785         if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
 786                 /* add other state override checks here */
 787                 if ((!rdev->pm.dpm.thermal_active) &&
 788                     (!rdev->pm.dpm.uvd_active))
 789                         rdev->pm.dpm.state = rdev->pm.dpm.user_state;
 790         }
 791         dpm_state = rdev->pm.dpm.state;
 792
 793         ps = radeon_dpm_pick_power_state(rdev, dpm_state);
 794         if (ps)
 795                 rdev->pm.dpm.requested_ps = ps;
 796         else
 797                 return;
 798
 799         /* no need to reprogram if nothing changed unless we are on BTC+ */
 800         if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
 801                 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
 802                         /* for pre-BTC and APUs if the num crtcs changed but state is the same,
 803                          * all we need to do is update the display configuration.
 804                          */
 805                         if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
 806                                 /* update display watermarks based on new power state */
 807                                 radeon_bandwidth_update(rdev);
 808                                 /* update displays */
 809                                 radeon_dpm_display_configuration_changed(rdev);
 810                                 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
 811                                 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
 812                         }
 813                         return;
 814                 } else {
 815                         /* for BTC+ if the num crtcs hasn't changed and state is the same,
 816                          * nothing to do, if the num crtcs is > 1 and state is the same,
 817                          * update display configuration.
 818                          */
 819                         if (rdev->pm.dpm.new_active_crtcs ==
 820                             rdev->pm.dpm.current_active_crtcs) {
 821                                 return;
 822                         } else {
 823                                 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
 824                                     (rdev->pm.dpm.new_active_crtc_count > 1)) {
 825                                         /* update display watermarks based on new power state */
 826                                         radeon_bandwidth_update(rdev);
 827                                         /* update displays */
 828                                         radeon_dpm_display_configuration_changed(rdev);
 829                                         rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
 830                                         rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
 831                                         return;
 832                                 }
 833                         }
 834                 }
 835         }
 836
 837         printk("switching from power state:\n");
 838         radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
 839         printk("switching to power state:\n");
 840         radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
 841
 842         mutex_lock(&rdev->ddev->struct_mutex);
 843         down_write(&rdev->pm.mclk_lock);
 844         mutex_lock(&rdev->ring_lock);
 845
 846         ret = radeon_dpm_pre_set_power_state(rdev);
 847         if (ret)
 848                 goto done;
 849
 850         /* update display watermarks based on new power state */
 851         radeon_bandwidth_update(rdev);
 852         /* update displays */
 853         radeon_dpm_display_configuration_changed(rdev);
 854
 855         rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
 856         rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
 857
 858         /* wait for the rings to drain */
 859         for (i = 0; i < RADEON_NUM_RINGS; i++) {
 860                 struct radeon_ring *ring = &rdev->ring[i];
 861                 if (ring->ready)
 862                         radeon_fence_wait_empty_locked(rdev, i);
 863         }
 864
 865         /* program the new power state */
 866         radeon_dpm_set_power_state(rdev);
 867
 868         /* update current power state */
 869         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
 870
 871         radeon_dpm_post_set_power_state(rdev);
 872
 873         /* force low perf level for thermal */
 874         if (rdev->pm.dpm.thermal_active &&
 875             rdev->asic->dpm.force_performance_level) {
 876                 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
 877         }
 878
 879 done:
 880         mutex_unlock(&rdev->ring_lock);
 881         up_write(&rdev->pm.mclk_lock);
 882         mutex_unlock(&rdev->ddev->struct_mutex);
 883 }
 884
 885 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
 886 {
 887         enum radeon_pm_state_type dpm_state;
 888
 889         if (enable) {
 890                 mutex_lock(&rdev->pm.mutex);
 891                 rdev->pm.dpm.uvd_active = true;
 892                 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
 893                         dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
 894                 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
 895                         dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
 896                 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
 897                         dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
 898                 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
 899                         dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
 900                 else
 901                         dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
 902                 rdev->pm.dpm.state = dpm_state;
 903                 mutex_unlock(&rdev->pm.mutex);
 904         } else {
 905                 mutex_lock(&rdev->pm.mutex);
 906                 rdev->pm.dpm.uvd_active = false;
 907                 mutex_unlock(&rdev->pm.mutex);
 908         }
 909
 910         radeon_pm_compute_clocks(rdev);
 911 }
 912
 913 static void radeon_pm_suspend_old(struct radeon_device *rdev)
 914 {
 915         mutex_lock(&rdev->pm.mutex);
 916         if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 917                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
 918                         rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
 919         }
 920         mutex_unlock(&rdev->pm.mutex);
 921
 922         cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 923 }
 924
 925 static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
 926 {
 927         mutex_lock(&rdev->pm.mutex);
 928         /* disable dpm */
 929         radeon_dpm_disable(rdev);
 930         /* reset the power state */
 931         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
 932         rdev->pm.dpm_enabled = false;
 933         mutex_unlock(&rdev->pm.mutex);
 934 }
 935
 936 void radeon_pm_suspend(struct radeon_device *rdev)
 937 {
 938         if (rdev->pm.pm_method == PM_METHOD_DPM)
 939                 radeon_pm_suspend_dpm(rdev);
 940         else
 941                 radeon_pm_suspend_old(rdev);
 942 }
 943
 944 static void radeon_pm_resume_old(struct radeon_device *rdev)
 945 {
 946         /* set up the default clocks if the MC ucode is loaded */
 947         if ((rdev->family >= CHIP_BARTS) &&
 948             (rdev->family <= CHIP_HAINAN) &&
 949             rdev->mc_fw) {
 950                 if (rdev->pm.default_vddc)
 951                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
 952                                                 SET_VOLTAGE_TYPE_ASIC_VDDC);
 953                 if (rdev->pm.default_vddci)
 954                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
 955                                                 SET_VOLTAGE_TYPE_ASIC_VDDCI);
 956                 if (rdev->pm.default_sclk)
 957                         radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
 958                 if (rdev->pm.default_mclk)
 959                         radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
 960         }
 961         /* asic init will reset the default power state */
 962         mutex_lock(&rdev->pm.mutex);
 963         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
 964         rdev->pm.current_clock_mode_index = 0;
 965         rdev->pm.current_sclk = rdev->pm.default_sclk;
 966         rdev->pm.current_mclk = rdev->pm.default_mclk;
 967         rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
 968         rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
 969         if (rdev->pm.pm_method == PM_METHOD_DYNPM
 970             && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
 971                 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 972                 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 973                                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 974         }
 975         mutex_unlock(&rdev->pm.mutex);
 976         radeon_pm_compute_clocks(rdev);
 977 }
 978
 979 static void radeon_pm_resume_dpm(struct radeon_device *rdev)
 980 {
 981         int ret;
 982
 983         /* asic init will reset to the boot state */
 984         mutex_lock(&rdev->pm.mutex);
 985         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
 986         radeon_dpm_setup_asic(rdev);
 987         ret = radeon_dpm_enable(rdev);
 988         mutex_unlock(&rdev->pm.mutex);
 989         if (ret) {
 990                 DRM_ERROR("radeon: dpm resume failed\n");
 991                 if ((rdev->family >= CHIP_BARTS) &&
 992                     (rdev->family <= CHIP_HAINAN) &&
 993                     rdev->mc_fw) {
 994                         if (rdev->pm.default_vddc)
 995                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
 996                                                         SET_VOLTAGE_TYPE_ASIC_VDDC);
 997                         if (rdev->pm.default_vddci)
 998                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
 999                                                         SET_VOLTAGE_TYPE_ASIC_VDDCI);
1000                         if (rdev->pm.default_sclk)
1001                                 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1002                         if (rdev->pm.default_mclk)
1003                                 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1004                 }
1005         } else {
1006                 rdev->pm.dpm_enabled = true;
1007                 radeon_pm_compute_clocks(rdev);
1008         }
1009 }
1010
1011 void radeon_pm_resume(struct radeon_device *rdev)
1012 {
1013         if (rdev->pm.pm_method == PM_METHOD_DPM)
1014                 radeon_pm_resume_dpm(rdev);
1015         else
1016                 radeon_pm_resume_old(rdev);
1017 }
1018
1019 static int radeon_pm_init_old(struct radeon_device *rdev)
1020 {
1021         int ret;
1022
1023         rdev->pm.profile = PM_PROFILE_DEFAULT;
1024         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1025         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1026         rdev->pm.dynpm_can_upclock = true;
1027         rdev->pm.dynpm_can_downclock = true;
1028         rdev->pm.default_sclk = rdev->clock.default_sclk;
1029         rdev->pm.default_mclk = rdev->clock.default_mclk;
1030         rdev->pm.current_sclk = rdev->clock.default_sclk;
1031         rdev->pm.current_mclk = rdev->clock.default_mclk;
1032         rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1033
1034         if (rdev->bios) {
1035                 if (rdev->is_atom_bios)
1036                         radeon_atombios_get_power_modes(rdev);
1037                 else
1038                         radeon_combios_get_power_modes(rdev);
1039                 radeon_pm_print_states(rdev);
1040                 radeon_pm_init_profile(rdev);
1041                 /* set up the default clocks if the MC ucode is loaded */
1042                 if ((rdev->family >= CHIP_BARTS) &&
1043                     (rdev->family <= CHIP_HAINAN) &&
1044                     rdev->mc_fw) {
1045                         if (rdev->pm.default_vddc)
1046                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1047                                                         SET_VOLTAGE_TYPE_ASIC_VDDC);
1048                         if (rdev->pm.default_vddci)
1049                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1050                                                         SET_VOLTAGE_TYPE_ASIC_VDDCI);
1051                         if (rdev->pm.default_sclk)
1052                                 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1053                         if (rdev->pm.default_mclk)
1054                                 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1055                 }
1056         }
1057
1058         /* set up the internal thermal sensor if applicable */
1059         ret = radeon_hwmon_init(rdev);
1060         if (ret)
1061                 return ret;
1062
1063         INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1064
1065         if (rdev->pm.num_power_states > 1) {
1066                 /* where's the best place to put these? */
1067                 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1068                 if (ret)
1069                         DRM_ERROR("failed to create device file for power profile\n");
1070                 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1071                 if (ret)
1072                         DRM_ERROR("failed to create device file for power method\n");
1073
1074                 if (radeon_debugfs_pm_init(rdev)) {
1075                         DRM_ERROR("Failed to register debugfs file for PM!\n");
1076                 }
1077
1078                 DRM_INFO("radeon: power management initialized\n");
1079         }
1080
1081         return 0;
1082 }
1083
1084 static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1085 {
1086         int i;
1087
1088         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1089                 printk("== power state %d ==\n", i);
1090                 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1091         }
1092 }
1093
1094 static int radeon_pm_init_dpm(struct radeon_device *rdev)
1095 {
1096         int ret;
1097
1098         /* default to performance state */
1099         rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1100         rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1101         rdev->pm.default_sclk = rdev->clock.default_sclk;
1102         rdev->pm.default_mclk = rdev->clock.default_mclk;
1103         rdev->pm.current_sclk = rdev->clock.default_sclk;
1104         rdev->pm.current_mclk = rdev->clock.default_mclk;
1105         rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1106
1107         if (rdev->bios && rdev->is_atom_bios)
1108                 radeon_atombios_get_power_modes(rdev);
1109         else
1110                 return -EINVAL;
1111
1112         /* set up the internal thermal sensor if applicable */
1113         ret = radeon_hwmon_init(rdev);
1114         if (ret)
1115                 return ret;
1116
1117         INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1118         mutex_lock(&rdev->pm.mutex);
1119         radeon_dpm_init(rdev);
1120         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1121         radeon_dpm_print_power_states(rdev);
1122         radeon_dpm_setup_asic(rdev);
1123         ret = radeon_dpm_enable(rdev);
1124         mutex_unlock(&rdev->pm.mutex);
1125         if (ret) {
1126                 rdev->pm.dpm_enabled = false;
1127                 if ((rdev->family >= CHIP_BARTS) &&
1128                     (rdev->family <= CHIP_HAINAN) &&
1129                     rdev->mc_fw) {
1130                         if (rdev->pm.default_vddc)
1131                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1132                                                         SET_VOLTAGE_TYPE_ASIC_VDDC);
1133                         if (rdev->pm.default_vddci)
1134                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1135                                                         SET_VOLTAGE_TYPE_ASIC_VDDCI);
1136                         if (rdev->pm.default_sclk)
1137                                 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1138                         if (rdev->pm.default_mclk)
1139                                 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1140                 }
1141                 DRM_ERROR("radeon: dpm initialization failed\n");
1142                 return ret;
1143         }
1144         rdev->pm.dpm_enabled = true;
1145         radeon_pm_compute_clocks(rdev);
1146
1147         if (rdev->pm.num_power_states > 1) {
1148                 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1149                 if (ret)
1150                         DRM_ERROR("failed to create device file for dpm state\n");
1151                 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1152                 if (ret)
1153                         DRM_ERROR("failed to create device file for dpm state\n");
1154                 /* XXX: these are noops for dpm but are here for backwards compat */
1155                 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1156                 if (ret)
1157                         DRM_ERROR("failed to create device file for power profile\n");
1158                 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1159                 if (ret)
1160                         DRM_ERROR("failed to create device file for power method\n");
1161
1162                 if (radeon_debugfs_pm_init(rdev)) {
1163                         DRM_ERROR("Failed to register debugfs file for dpm!\n");
1164                 }
1165
1166                 DRM_INFO("radeon: dpm initialized\n");
1167         }
1168
1169         return 0;
1170 }
1171
1172 int radeon_pm_init(struct radeon_device *rdev)
1173 {
1174         /* enable dpm on rv6xx+ */
1175         switch (rdev->family) {
1176         case CHIP_RV610:
1177         case CHIP_RV630:
1178         case CHIP_RV620:
1179         case CHIP_RV635:
1180         case CHIP_RV670:
1181         case CHIP_RS780:
1182         case CHIP_RS880:
1183         case CHIP_RV770:
1184         case CHIP_RV730:
1185         case CHIP_RV710:
1186         case CHIP_RV740:
1187         case CHIP_CEDAR:
1188         case CHIP_REDWOOD:
1189         case CHIP_JUNIPER:
1190         case CHIP_CYPRESS:
1191         case CHIP_HEMLOCK:
1192         case CHIP_PALM:
1193         case CHIP_SUMO:
1194         case CHIP_SUMO2:
1195         case CHIP_BARTS:
1196         case CHIP_TURKS:
1197         case CHIP_CAICOS:
1198         case CHIP_CAYMAN:
1199         case CHIP_ARUBA:
1200         case CHIP_TAHITI:
1201         case CHIP_PITCAIRN:
1202         case CHIP_VERDE:
1203         case CHIP_OLAND:
1204         case CHIP_HAINAN:
1205         case CHIP_KABINI:
1206         case CHIP_KAVERI:
1207                 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1208                 if (!rdev->rlc_fw)
1209                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1210                 else if ((rdev->family >= CHIP_RV770) &&
1211                          (!(rdev->flags & RADEON_IS_IGP)) &&
1212                          (!rdev->smc_fw))
1213                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1214                 else if (radeon_dpm == 1)
1215                         rdev->pm.pm_method = PM_METHOD_DPM;
1216                 else
1217                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1218                 break;
1219         default:
1220                 /* default to profile method */
1221                 rdev->pm.pm_method = PM_METHOD_PROFILE;
1222                 break;
1223         }
1224
1225         if (rdev->pm.pm_method == PM_METHOD_DPM)
1226                 return radeon_pm_init_dpm(rdev);
1227         else
1228                 return radeon_pm_init_old(rdev);
1229 }
1230
1231 static void radeon_pm_fini_old(struct radeon_device *rdev)
1232 {
1233         if (rdev->pm.num_power_states > 1) {
1234                 mutex_lock(&rdev->pm.mutex);
1235                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1236                         rdev->pm.profile = PM_PROFILE_DEFAULT;
1237                         radeon_pm_update_profile(rdev);
1238                         radeon_pm_set_clocks(rdev);
1239                 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1240                         /* reset default clocks */
1241                         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1242                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1243                         radeon_pm_set_clocks(rdev);
1244                 }
1245                 mutex_unlock(&rdev->pm.mutex);
1246
1247                 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1248
1249                 device_remove_file(rdev->dev, &dev_attr_power_profile);
1250                 device_remove_file(rdev->dev, &dev_attr_power_method);
1251         }
1252
1253         if (rdev->pm.power_state)
1254                 kfree(rdev->pm.power_state);
1255
1256         radeon_hwmon_fini(rdev);
1257 }
1258
1259 static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1260 {
1261         if (rdev->pm.num_power_states > 1) {
1262                 mutex_lock(&rdev->pm.mutex);
1263                 radeon_dpm_disable(rdev);
1264                 mutex_unlock(&rdev->pm.mutex);
1265
1266                 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1267                 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1268                 /* XXX backwards compat */
1269                 device_remove_file(rdev->dev, &dev_attr_power_profile);
1270                 device_remove_file(rdev->dev, &dev_attr_power_method);
1271         }
1272         radeon_dpm_fini(rdev);
1273
1274         if (rdev->pm.power_state)
1275                 kfree(rdev->pm.power_state);
1276
1277         radeon_hwmon_fini(rdev);
1278 }
1279
1280 void radeon_pm_fini(struct radeon_device *rdev)
1281 {
1282         if (rdev->pm.pm_method == PM_METHOD_DPM)
1283                 radeon_pm_fini_dpm(rdev);
1284         else
1285                 radeon_pm_fini_old(rdev);
1286 }
1287
1288 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
1289 {
1290         struct drm_device *ddev = rdev->ddev;
1291         struct drm_crtc *crtc;
1292         struct radeon_crtc *radeon_crtc;
1293
1294         if (rdev->pm.num_power_states < 2)
1295                 return;
1296
1297         mutex_lock(&rdev->pm.mutex);
1298
1299         rdev->pm.active_crtcs = 0;
1300         rdev->pm.active_crtc_count = 0;
1301         list_for_each_entry(crtc,
1302                 &ddev->mode_config.crtc_list, head) {
1303                 radeon_crtc = to_radeon_crtc(crtc);
1304                 if (radeon_crtc->enabled) {
1305                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1306                         rdev->pm.active_crtc_count++;
1307                 }
1308         }
1309
1310         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1311                 radeon_pm_update_profile(rdev);
1312                 radeon_pm_set_clocks(rdev);
1313         } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1314                 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1315                         if (rdev->pm.active_crtc_count > 1) {
1316                                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1317                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1318
1319                                         rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1320                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1321                                         radeon_pm_get_dynpm_state(rdev);
1322                                         radeon_pm_set_clocks(rdev);
1323
1324                                         DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1325                                 }
1326                         } else if (rdev->pm.active_crtc_count == 1) {
1327                                 /* TODO: Increase clocks if needed for current mode */
1328
1329                                 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1330                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1331                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1332                                         radeon_pm_get_dynpm_state(rdev);
1333                                         radeon_pm_set_clocks(rdev);
1334
1335                                         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1336                                                               msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1337                                 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1338                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1339                                         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1340                                                               msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1341                                         DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1342                                 }
1343                         } else { /* count == 0 */
1344                                 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1345                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1346
1347                                         rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1348                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1349                                         radeon_pm_get_dynpm_state(rdev);
1350                                         radeon_pm_set_clocks(rdev);
1351                                 }
1352                         }
1353                 }
1354         }
1355
1356         mutex_unlock(&rdev->pm.mutex);
1357 }
1358
1359 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1360 {
1361         struct drm_device *ddev = rdev->ddev;
1362         struct drm_crtc *crtc;
1363         struct radeon_crtc *radeon_crtc;
1364
1365         mutex_lock(&rdev->pm.mutex);
1366
1367         /* update active crtc counts */
1368         rdev->pm.dpm.new_active_crtcs = 0;
1369         rdev->pm.dpm.new_active_crtc_count = 0;
1370         list_for_each_entry(crtc,
1371                 &ddev->mode_config.crtc_list, head) {
1372                 radeon_crtc = to_radeon_crtc(crtc);
1373                 if (crtc->enabled) {
1374                         rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1375                         rdev->pm.dpm.new_active_crtc_count++;
1376                 }
1377         }
1378
1379         /* update battery/ac status */
1380         if (power_supply_is_system_supplied() > 0)
1381                 rdev->pm.dpm.ac_power = true;
1382         else
1383                 rdev->pm.dpm.ac_power = false;
1384
1385         radeon_dpm_change_power_state_locked(rdev);
1386
1387         mutex_unlock(&rdev->pm.mutex);
1388
1389 }
1390
1391 void radeon_pm_compute_clocks(struct radeon_device *rdev)
1392 {
1393         if (rdev->pm.pm_method == PM_METHOD_DPM)
1394                 radeon_pm_compute_clocks_dpm(rdev);
1395         else
1396                 radeon_pm_compute_clocks_old(rdev);
1397 }
1398
1399 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
1400 {
1401         int  crtc, vpos, hpos, vbl_status;
1402         bool in_vbl = true;
1403
1404         /* Iterate over all active crtc's. All crtc's must be in vblank,
1405          * otherwise return in_vbl == false.
1406          */
1407         for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1408                 if (rdev->pm.active_crtcs & (1 << crtc)) {
1409                         vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
1410                         if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1411                             !(vbl_status & DRM_SCANOUTPOS_INVBL))
1412                                 in_vbl = false;
1413                 }
1414         }
1415
1416         return in_vbl;
1417 }
1418
1419 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
1420 {
1421         u32 stat_crtc = 0;
1422         bool in_vbl = radeon_pm_in_vbl(rdev);
1423
1424         if (in_vbl == false)
1425                 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
1426                          finish ? "exit" : "entry");
1427         return in_vbl;
1428 }
1429
1430 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
1431 {
1432         struct radeon_device *rdev;
1433         int resched;
1434         rdev = container_of(work, struct radeon_device,
1435                                 pm.dynpm_idle_work.work);
1436
1437         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1438         mutex_lock(&rdev->pm.mutex);
1439         if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1440                 int not_processed = 0;
1441                 int i;
1442
1443                 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1444                         struct radeon_ring *ring = &rdev->ring[i];
1445
1446                         if (ring->ready) {
1447                                 not_processed += radeon_fence_count_emitted(rdev, i);
1448                                 if (not_processed >= 3)
1449                                         break;
1450                         }
1451                 }
1452
1453                 if (not_processed >= 3) { /* should upclock */
1454                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1455                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1456                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1457                                    rdev->pm.dynpm_can_upclock) {
1458                                 rdev->pm.dynpm_planned_action =
1459                                         DYNPM_ACTION_UPCLOCK;
1460                                 rdev->pm.dynpm_action_timeout = jiffies +
1461                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1462                         }
1463                 } else if (not_processed == 0) { /* should downclock */
1464                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1465                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1466                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1467                                    rdev->pm.dynpm_can_downclock) {
1468                                 rdev->pm.dynpm_planned_action =
1469                                         DYNPM_ACTION_DOWNCLOCK;
1470                                 rdev->pm.dynpm_action_timeout = jiffies +
1471                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1472                         }
1473                 }
1474
1475                 /* Note, radeon_pm_set_clocks is called with static_switch set
1476                  * to false since we want to wait for vbl to avoid flicker.
1477                  */
1478                 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1479                     jiffies > rdev->pm.dynpm_action_timeout) {
1480                         radeon_pm_get_dynpm_state(rdev);
1481                         radeon_pm_set_clocks(rdev);
1482                 }
1483
1484                 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1485                                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1486         }
1487         mutex_unlock(&rdev->pm.mutex);
1488         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1489 }
1490
1491 /*
1492  * Debugfs info
1493  */
1494 #if defined(CONFIG_DEBUG_FS)
1495
1496 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1497 {
1498         struct drm_info_node *node = (struct drm_info_node *) m->private;
1499         struct drm_device *dev = node->minor->dev;
1500         struct radeon_device *rdev = dev->dev_private;
1501
1502         if (rdev->pm.dpm_enabled) {
1503                 mutex_lock(&rdev->pm.mutex);
1504                 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1505                         radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1506                 else
1507                         seq_printf(m, "Debugfs support not implemented for this asic\n");
1508                 mutex_unlock(&rdev->pm.mutex);
1509         } else {
1510                 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1511                 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1512                 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1513                         seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1514                 else
1515                         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1516                 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1517                 if (rdev->asic->pm.get_memory_clock)
1518                         seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1519                 if (rdev->pm.current_vddc)
1520                         seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1521                 if (rdev->asic->pm.get_pcie_lanes)
1522                         seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1523         }
1524
1525         return 0;
1526 }
1527
1528 static struct drm_info_list radeon_pm_info_list[] = {
1529         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1530 };
1531 #endif
1532
1533 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
1534 {
1535 #if defined(CONFIG_DEBUG_FS)
1536         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
1537 #else
1538         return 0;
1539 #endif
1540 }