drivers/i2c/busses/i2c-mt65xx.c

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: Xudong Chen <xudong.chen@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/clk.h>
  16 #include <linux/completion.h>
  17 #include <linux/delay.h>
  18 #include <linux/device.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/err.h>
  21 #include <linux/errno.h>
  22 #include <linux/i2c.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/module.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/scatterlist.h>
  33 #include <linux/sched.h>
  34 #include <linux/slab.h>
  35
  36 #define I2C_RS_TRANSFER                 (1 << 4)
  37 #define I2C_HS_NACKERR                  (1 << 2)
  38 #define I2C_ACKERR                      (1 << 1)
  39 #define I2C_TRANSAC_COMP                (1 << 0)
  40 #define I2C_TRANSAC_START               (1 << 0)
  41 #define I2C_RS_MUL_CNFG                 (1 << 15)
  42 #define I2C_RS_MUL_TRIG                 (1 << 14)
  43 #define I2C_DCM_DISABLE                 0x0000
  44 #define I2C_IO_CONFIG_OPEN_DRAIN        0x0003
  45 #define I2C_IO_CONFIG_PUSH_PULL         0x0000
  46 #define I2C_SOFT_RST                    0x0001
  47 #define I2C_FIFO_ADDR_CLR               0x0001
  48 #define I2C_DELAY_LEN                   0x0002
  49 #define I2C_ST_START_CON                0x8001
  50 #define I2C_FS_START_CON                0x1800
  51 #define I2C_TIME_CLR_VALUE              0x0000
  52 #define I2C_TIME_DEFAULT_VALUE          0x0003
  53 #define I2C_FS_TIME_INIT_VALUE          0x1303
  54 #define I2C_WRRD_TRANAC_VALUE           0x0002
  55 #define I2C_RD_TRANAC_VALUE             0x0001
  56
  57 #define I2C_DMA_CON_TX                  0x0000
  58 #define I2C_DMA_CON_RX                  0x0001
  59 #define I2C_DMA_START_EN                0x0001
  60 #define I2C_DMA_INT_FLAG_NONE           0x0000
  61 #define I2C_DMA_CLR_FLAG                0x0000
  62 #define I2C_DMA_HARD_RST                0x0002
  63 #define I2C_DMA_4G_MODE                 0x0001
  64
  65 #define I2C_DEFAULT_SPEED               100000  /* hz */
  66 #define MAX_FS_MODE_SPEED               400000
  67 #define MAX_HS_MODE_SPEED               3400000
  68 #define MAX_SAMPLE_CNT_DIV              8
  69 #define MAX_STEP_CNT_DIV                64
  70 #define MAX_HS_STEP_CNT_DIV             8
  71
  72 #define I2C_CONTROL_RS                  (0x1 << 1)
  73 #define I2C_CONTROL_DMA_EN              (0x1 << 2)
  74 #define I2C_CONTROL_CLK_EXT_EN          (0x1 << 3)
  75 #define I2C_CONTROL_DIR_CHANGE          (0x1 << 4)
  76 #define I2C_CONTROL_ACKERR_DET_EN       (0x1 << 5)
  77 #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
  78 #define I2C_CONTROL_WRAPPER             (0x1 << 0)
  79
  80 #define I2C_DRV_NAME            "i2c-mt65xx"
  81
  82 enum DMA_REGS_OFFSET {
  83         OFFSET_INT_FLAG = 0x0,
  84         OFFSET_INT_EN = 0x04,
  85         OFFSET_EN = 0x08,
  86         OFFSET_RST = 0x0c,
  87         OFFSET_CON = 0x18,
  88         OFFSET_TX_MEM_ADDR = 0x1c,
  89         OFFSET_RX_MEM_ADDR = 0x20,
  90         OFFSET_TX_LEN = 0x24,
  91         OFFSET_RX_LEN = 0x28,
  92         OFFSET_TX_4G_MODE = 0x54,
  93         OFFSET_RX_4G_MODE = 0x58,
  94 };
  95
  96 enum i2c_trans_st_rs {
  97         I2C_TRANS_STOP = 0,
  98         I2C_TRANS_REPEATED_START,
  99 };
 100
 101 enum mtk_trans_op {
 102         I2C_MASTER_WR = 1,
 103         I2C_MASTER_RD,
 104         I2C_MASTER_WRRD,
 105 };
 106
 107 enum I2C_REGS_OFFSET {
 108         OFFSET_DATA_PORT = 0x0,
 109         OFFSET_SLAVE_ADDR = 0x04,
 110         OFFSET_INTR_MASK = 0x08,
 111         OFFSET_INTR_STAT = 0x0c,
 112         OFFSET_CONTROL = 0x10,
 113         OFFSET_TRANSFER_LEN = 0x14,
 114         OFFSET_TRANSAC_LEN = 0x18,
 115         OFFSET_DELAY_LEN = 0x1c,
 116         OFFSET_TIMING = 0x20,
 117         OFFSET_START = 0x24,
 118         OFFSET_EXT_CONF = 0x28,
 119         OFFSET_FIFO_STAT = 0x30,
 120         OFFSET_FIFO_THRESH = 0x34,
 121         OFFSET_FIFO_ADDR_CLR = 0x38,
 122         OFFSET_IO_CONFIG = 0x40,
 123         OFFSET_RSV_DEBUG = 0x44,
 124         OFFSET_HS = 0x48,
 125         OFFSET_SOFTRESET = 0x50,
 126         OFFSET_DCM_EN = 0x54,
 127         OFFSET_PATH_DIR = 0x60,
 128         OFFSET_DEBUGSTAT = 0x64,
 129         OFFSET_DEBUGCTRL = 0x68,
 130         OFFSET_TRANSFER_LEN_AUX = 0x6c,
 131 };
 132
 133 struct mtk_i2c_compatible {
 134         const struct i2c_adapter_quirks *quirks;
 135         unsigned char pmic_i2c: 1;
 136         unsigned char dcm: 1;
 137         unsigned char auto_restart: 1;
 138         unsigned char aux_len_reg: 1;
 139         unsigned char support_33bits: 1;
 140 };
 141
 142 struct mtk_i2c {
 143         struct i2c_adapter adap;        /* i2c host adapter */
 144         struct device *dev;
 145         struct completion msg_complete;
 146
 147         /* set in i2c probe */
 148         void __iomem *base;             /* i2c base addr */
 149         void __iomem *pdmabase;         /* dma base address*/
 150         struct clk *clk_main;           /* main clock for i2c bus */
 151         struct clk *clk_dma;            /* DMA clock for i2c via DMA */
 152         struct clk *clk_pmic;           /* PMIC clock for i2c from PMIC */
 153         bool have_pmic;                 /* can use i2c pins from PMIC */
 154         bool use_push_pull;             /* IO config push-pull mode */
 155
 156         u16 irq_stat;                   /* interrupt status */
 157         unsigned int speed_hz;          /* The speed in transfer */
 158         enum mtk_trans_op op;
 159         u16 timing_reg;
 160         u16 high_speed_reg;
 161         unsigned char auto_restart;
 162         bool ignore_restart_irq;
 163         const struct mtk_i2c_compatible *dev_comp;
 164 };
 165
 166 static const struct i2c_adapter_quirks mt6577_i2c_quirks = {
 167         .flags = I2C_AQ_COMB_WRITE_THEN_READ,
 168         .max_num_msgs = 1,
 169         .max_write_len = 255,
 170         .max_read_len = 255,
 171         .max_comb_1st_msg_len = 255,
 172         .max_comb_2nd_msg_len = 31,
 173 };
 174
 175 static const struct mtk_i2c_compatible mt6577_compat = {
 176         .quirks = &mt6577_i2c_quirks,
 177         .pmic_i2c = 0,
 178         .dcm = 1,
 179         .auto_restart = 0,
 180         .aux_len_reg = 0,
 181         .support_33bits = 0,
 182 };
 183
 184 static const struct mtk_i2c_compatible mt6589_compat = {
 185         .quirks = &mt6577_i2c_quirks,
 186         .pmic_i2c = 1,
 187         .dcm = 0,
 188         .auto_restart = 0,
 189         .aux_len_reg = 0,
 190         .support_33bits = 0,
 191 };
 192
 193 static const struct mtk_i2c_compatible mt8173_compat = {
 194         .pmic_i2c = 0,
 195         .dcm = 1,
 196         .auto_restart = 1,
 197         .aux_len_reg = 1,
 198         .support_33bits = 1,
 199 };
 200
 201 static const struct of_device_id mtk_i2c_of_match[] = {
 202         { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
 203         { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
 204         { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
 205         {}
 206 };
 207 MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
 208
 209 static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
 210 {
 211         int ret;
 212
 213         ret = clk_prepare_enable(i2c->clk_dma);
 214         if (ret)
 215                 return ret;
 216
 217         ret = clk_prepare_enable(i2c->clk_main);
 218         if (ret)
 219                 goto err_main;
 220
 221         if (i2c->have_pmic) {
 222                 ret = clk_prepare_enable(i2c->clk_pmic);
 223                 if (ret)
 224                         goto err_pmic;
 225         }
 226         return 0;
 227
 228 err_pmic:
 229         clk_disable_unprepare(i2c->clk_main);
 230 err_main:
 231         clk_disable_unprepare(i2c->clk_dma);
 232
 233         return ret;
 234 }
 235
 236 static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
 237 {
 238         if (i2c->have_pmic)
 239                 clk_disable_unprepare(i2c->clk_pmic);
 240
 241         clk_disable_unprepare(i2c->clk_main);
 242         clk_disable_unprepare(i2c->clk_dma);
 243 }
 244
 245 static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
 246 {
 247         u16 control_reg;
 248
 249         writew(I2C_SOFT_RST, i2c->base + OFFSET_SOFTRESET);
 250
 251         /* Set ioconfig */
 252         if (i2c->use_push_pull)
 253                 writew(I2C_IO_CONFIG_PUSH_PULL, i2c->base + OFFSET_IO_CONFIG);
 254         else
 255                 writew(I2C_IO_CONFIG_OPEN_DRAIN, i2c->base + OFFSET_IO_CONFIG);
 256
 257         if (i2c->dev_comp->dcm)
 258                 writew(I2C_DCM_DISABLE, i2c->base + OFFSET_DCM_EN);
 259
 260         writew(i2c->timing_reg, i2c->base + OFFSET_TIMING);
 261         writew(i2c->high_speed_reg, i2c->base + OFFSET_HS);
 262
 263         /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
 264         if (i2c->have_pmic)
 265                 writew(I2C_CONTROL_WRAPPER, i2c->base + OFFSET_PATH_DIR);
 266
 267         control_reg = I2C_CONTROL_ACKERR_DET_EN |
 268                       I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
 269         writew(control_reg, i2c->base + OFFSET_CONTROL);
 270         writew(I2C_DELAY_LEN, i2c->base + OFFSET_DELAY_LEN);
 271
 272         writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
 273         udelay(50);
 274         writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
 275 }
 276
 277 /*
 278  * Calculate i2c port speed
 279  *
 280  * Hardware design:
 281  * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
 282  * clock_div: fixed in hardware, but may be various in different SoCs
 283  *
 284  * The calculation want to pick the highest bus frequency that is still
 285  * less than or equal to i2c->speed_hz. The calculation try to get
 286  * sample_cnt and step_cn
 287  */
 288 static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk,
 289                              unsigned int clock_div)
 290 {
 291         unsigned int clk_src;
 292         unsigned int step_cnt;
 293         unsigned int sample_cnt;
 294         unsigned int max_step_cnt;
 295         unsigned int target_speed;
 296         unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV;
 297         unsigned int base_step_cnt;
 298         unsigned int opt_div;
 299         unsigned int best_mul;
 300         unsigned int cnt_mul;
 301
 302         clk_src = parent_clk / clock_div;
 303         target_speed = i2c->speed_hz;
 304
 305         if (target_speed > MAX_HS_MODE_SPEED)
 306                 target_speed = MAX_HS_MODE_SPEED;
 307
 308         if (target_speed > MAX_FS_MODE_SPEED)
 309                 max_step_cnt = MAX_HS_STEP_CNT_DIV;
 310         else
 311                 max_step_cnt = MAX_STEP_CNT_DIV;
 312
 313         base_step_cnt = max_step_cnt;
 314         /* Find the best combination */
 315         opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
 316         best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
 317
 318         /* Search for the best pair (sample_cnt, step_cnt) with
 319          * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
 320          * 0 < step_cnt < max_step_cnt
 321          * sample_cnt * step_cnt >= opt_div
 322          * optimizing for sample_cnt * step_cnt being minimal
 323          */
 324         for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
 325                 step_cnt = DIV_ROUND_UP(opt_div, sample_cnt);
 326                 cnt_mul = step_cnt * sample_cnt;
 327                 if (step_cnt > max_step_cnt)
 328                         continue;
 329
 330                 if (cnt_mul < best_mul) {
 331                         best_mul = cnt_mul;
 332                         base_sample_cnt = sample_cnt;
 333                         base_step_cnt = step_cnt;
 334                         if (best_mul == opt_div)
 335                                 break;
 336                 }
 337         }
 338
 339         sample_cnt = base_sample_cnt;
 340         step_cnt = base_step_cnt;
 341
 342         if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) {
 343                 /* In this case, hardware can't support such
 344                  * low i2c_bus_freq
 345                  */
 346                 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed);
 347                 return -EINVAL;
 348         }
 349
 350         step_cnt--;
 351         sample_cnt--;
 352
 353         if (target_speed > MAX_FS_MODE_SPEED) {
 354                 /* Set the high speed mode register */
 355                 i2c->timing_reg = I2C_FS_TIME_INIT_VALUE;
 356                 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
 357                         (sample_cnt << 12) | (step_cnt << 8);
 358         } else {
 359                 i2c->timing_reg = (sample_cnt << 8) | (step_cnt << 0);
 360                 /* Disable the high speed transaction */
 361                 i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
 362         }
 363
 364         return 0;
 365 }
 366
 367 static inline u32 mtk_i2c_set_4g_mode(dma_addr_t addr)
 368 {
 369         return (addr & BIT_ULL(32)) ? I2C_DMA_4G_MODE : I2C_DMA_CLR_FLAG;
 370 }
 371
 372 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
 373                                int num, int left_num)
 374 {
 375         u16 addr_reg;
 376         u16 start_reg;
 377         u16 control_reg;
 378         u16 restart_flag = 0;
 379         u32 reg_4g_mode;
 380         dma_addr_t rpaddr = 0;
 381         dma_addr_t wpaddr = 0;
 382         int ret;
 383
 384         i2c->irq_stat = 0;
 385
 386         if (i2c->auto_restart)
 387                 restart_flag = I2C_RS_TRANSFER;
 388
 389         reinit_completion(&i2c->msg_complete);
 390
 391         control_reg = readw(i2c->base + OFFSET_CONTROL) &
 392                         ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
 393         if ((i2c->speed_hz > 400000) || (left_num >= 1))
 394                 control_reg |= I2C_CONTROL_RS;
 395
 396         if (i2c->op == I2C_MASTER_WRRD)
 397                 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
 398
 399         writew(control_reg, i2c->base + OFFSET_CONTROL);
 400
 401         /* set start condition */
 402         if (i2c->speed_hz <= 100000)
 403                 writew(I2C_ST_START_CON, i2c->base + OFFSET_EXT_CONF);
 404         else
 405                 writew(I2C_FS_START_CON, i2c->base + OFFSET_EXT_CONF);
 406
 407         addr_reg = i2c_8bit_addr_from_msg(msgs);
 408         writew(addr_reg, i2c->base + OFFSET_SLAVE_ADDR);
 409
 410         /* Clear interrupt status */
 411         writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
 412                I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_STAT);
 413         writew(I2C_FIFO_ADDR_CLR, i2c->base + OFFSET_FIFO_ADDR_CLR);
 414
 415         /* Enable interrupt */
 416         writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
 417                I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_MASK);
 418
 419         /* Set transfer and transaction len */
 420         if (i2c->op == I2C_MASTER_WRRD) {
 421                 if (i2c->dev_comp->aux_len_reg) {
 422                         writew(msgs->len, i2c->base + OFFSET_TRANSFER_LEN);
 423                         writew((msgs + 1)->len, i2c->base +
 424                                OFFSET_TRANSFER_LEN_AUX);
 425                 } else {
 426                         writew(msgs->len | ((msgs + 1)->len) << 8,
 427                                i2c->base + OFFSET_TRANSFER_LEN);
 428                 }
 429                 writew(I2C_WRRD_TRANAC_VALUE, i2c->base + OFFSET_TRANSAC_LEN);
 430         } else {
 431                 writew(msgs->len, i2c->base + OFFSET_TRANSFER_LEN);
 432                 writew(num, i2c->base + OFFSET_TRANSAC_LEN);
 433         }
 434
 435         /* Prepare buffer data to start transfer */
 436         if (i2c->op == I2C_MASTER_RD) {
 437                 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
 438                 writel(I2C_DMA_CON_RX, i2c->pdmabase + OFFSET_CON);
 439                 rpaddr = dma_map_single(i2c->dev, msgs->buf,
 440                                         msgs->len, DMA_FROM_DEVICE);
 441                 if (dma_mapping_error(i2c->dev, rpaddr))
 442                         return -ENOMEM;
 443
 444                 if (i2c->dev_comp->support_33bits) {
 445                         reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
 446                         writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
 447                 }
 448
 449                 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
 450                 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
 451         } else if (i2c->op == I2C_MASTER_WR) {
 452                 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
 453                 writel(I2C_DMA_CON_TX, i2c->pdmabase + OFFSET_CON);
 454                 wpaddr = dma_map_single(i2c->dev, msgs->buf,
 455                                         msgs->len, DMA_TO_DEVICE);
 456                 if (dma_mapping_error(i2c->dev, wpaddr))
 457                         return -ENOMEM;
 458
 459                 if (i2c->dev_comp->support_33bits) {
 460                         reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
 461                         writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
 462                 }
 463
 464                 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
 465                 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
 466         } else {
 467                 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
 468                 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_CON);
 469                 wpaddr = dma_map_single(i2c->dev, msgs->buf,
 470                                         msgs->len, DMA_TO_DEVICE);
 471                 if (dma_mapping_error(i2c->dev, wpaddr))
 472                         return -ENOMEM;
 473                 rpaddr = dma_map_single(i2c->dev, (msgs + 1)->buf,
 474                                         (msgs + 1)->len,
 475                                         DMA_FROM_DEVICE);
 476                 if (dma_mapping_error(i2c->dev, rpaddr)) {
 477                         dma_unmap_single(i2c->dev, wpaddr,
 478                                          msgs->len, DMA_TO_DEVICE);
 479                         return -ENOMEM;
 480                 }
 481
 482                 if (i2c->dev_comp->support_33bits) {
 483                         reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
 484                         writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
 485
 486                         reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
 487                         writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
 488                 }
 489
 490                 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
 491                 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
 492                 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
 493                 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN);
 494         }
 495
 496         writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN);
 497
 498         if (!i2c->auto_restart) {
 499                 start_reg = I2C_TRANSAC_START;
 500         } else {
 501                 start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG;
 502                 if (left_num >= 1)
 503                         start_reg |= I2C_RS_MUL_CNFG;
 504         }
 505         writew(start_reg, i2c->base + OFFSET_START);
 506
 507         ret = wait_for_completion_timeout(&i2c->msg_complete,
 508                                           i2c->adap.timeout);
 509
 510         /* Clear interrupt mask */
 511         writew(~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
 512                I2C_TRANSAC_COMP), i2c->base + OFFSET_INTR_MASK);
 513
 514         if (i2c->op == I2C_MASTER_WR) {
 515                 dma_unmap_single(i2c->dev, wpaddr,
 516                                  msgs->len, DMA_TO_DEVICE);
 517         } else if (i2c->op == I2C_MASTER_RD) {
 518                 dma_unmap_single(i2c->dev, rpaddr,
 519                                  msgs->len, DMA_FROM_DEVICE);
 520         } else {
 521                 dma_unmap_single(i2c->dev, wpaddr, msgs->len,
 522                                  DMA_TO_DEVICE);
 523                 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len,
 524                                  DMA_FROM_DEVICE);
 525         }
 526
 527         if (ret == 0) {
 528                 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);
 529                 mtk_i2c_init_hw(i2c);
 530                 return -ETIMEDOUT;
 531         }
 532
 533         completion_done(&i2c->msg_complete);
 534
 535         if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) {
 536                 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
 537                 mtk_i2c_init_hw(i2c);
 538                 return -ENXIO;
 539         }
 540
 541         return 0;
 542 }
 543
 544 static int mtk_i2c_transfer(struct i2c_adapter *adap,
 545                             struct i2c_msg msgs[], int num)
 546 {
 547         int ret;
 548         int left_num = num;
 549         struct mtk_i2c *i2c = i2c_get_adapdata(adap);
 550
 551         ret = mtk_i2c_clock_enable(i2c);
 552         if (ret)
 553                 return ret;
 554
 555         i2c->auto_restart = i2c->dev_comp->auto_restart;
 556
 557         /* checking if we can skip restart and optimize using WRRD mode */
 558         if (i2c->auto_restart && num == 2) {
 559                 if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) &&
 560                     msgs[0].addr == msgs[1].addr) {
 561                         i2c->auto_restart = 0;
 562                 }
 563         }
 564
 565         if (i2c->auto_restart && num >= 2 && i2c->speed_hz > MAX_FS_MODE_SPEED)
 566                 /* ignore the first restart irq after the master code,
 567                  * otherwise the first transfer will be discarded.
 568                  */
 569                 i2c->ignore_restart_irq = true;
 570         else
 571                 i2c->ignore_restart_irq = false;
 572
 573         while (left_num--) {
 574                 if (!msgs->buf) {
 575                         dev_dbg(i2c->dev, "data buffer is NULL.\n");
 576                         ret = -EINVAL;
 577                         goto err_exit;
 578                 }
 579
 580                 if (msgs->flags & I2C_M_RD)
 581                         i2c->op = I2C_MASTER_RD;
 582                 else
 583                         i2c->op = I2C_MASTER_WR;
 584
 585                 if (!i2c->auto_restart) {
 586                         if (num > 1) {
 587                                 /* combined two messages into one transaction */
 588                                 i2c->op = I2C_MASTER_WRRD;
 589                                 left_num--;
 590                         }
 591                 }
 592
 593                 /* always use DMA mode. */
 594                 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num);
 595                 if (ret < 0)
 596                         goto err_exit;
 597
 598                 msgs++;
 599         }
 600         /* the return value is number of executed messages */
 601         ret = num;
 602
 603 err_exit:
 604         mtk_i2c_clock_disable(i2c);
 605         return ret;
 606 }
 607
 608 static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
 609 {
 610         struct mtk_i2c *i2c = dev_id;
 611         u16 restart_flag = 0;
 612         u16 intr_stat;
 613
 614         if (i2c->auto_restart)
 615                 restart_flag = I2C_RS_TRANSFER;
 616
 617         intr_stat = readw(i2c->base + OFFSET_INTR_STAT);
 618         writew(intr_stat, i2c->base + OFFSET_INTR_STAT);
 619
 620         /*
 621          * when occurs ack error, i2c controller generate two interrupts
 622          * first is the ack error interrupt, then the complete interrupt
 623          * i2c->irq_stat need keep the two interrupt value.
 624          */
 625         i2c->irq_stat |= intr_stat;
 626
 627         if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) {
 628                 i2c->ignore_restart_irq = false;
 629                 i2c->irq_stat = 0;
 630                 writew(I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG | I2C_TRANSAC_START,
 631                        i2c->base + OFFSET_START);
 632         } else {
 633                 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag))
 634                         complete(&i2c->msg_complete);
 635         }
 636
 637         return IRQ_HANDLED;
 638 }
 639
 640 static u32 mtk_i2c_functionality(struct i2c_adapter *adap)
 641 {
 642         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 643 }
 644
 645 static const struct i2c_algorithm mtk_i2c_algorithm = {
 646         .master_xfer = mtk_i2c_transfer,
 647         .functionality = mtk_i2c_functionality,
 648 };
 649
 650 static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c,
 651                             unsigned int *clk_src_div)
 652 {
 653         int ret;
 654
 655         ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz);
 656         if (ret < 0)
 657                 i2c->speed_hz = I2C_DEFAULT_SPEED;
 658
 659         ret = of_property_read_u32(np, "clock-div", clk_src_div);
 660         if (ret < 0)
 661                 return ret;
 662
 663         if (*clk_src_div == 0)
 664                 return -EINVAL;
 665
 666         i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic");
 667         i2c->use_push_pull =
 668                 of_property_read_bool(np, "mediatek,use-push-pull");
 669
 670         return 0;
 671 }
 672
 673 static int mtk_i2c_probe(struct platform_device *pdev)
 674 {
 675         const struct of_device_id *of_id;
 676         int ret = 0;
 677         struct mtk_i2c *i2c;
 678         struct clk *clk;
 679         unsigned int clk_src_div;
 680         struct resource *res;
 681         int irq;
 682
 683         i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
 684         if (!i2c)
 685                 return -ENOMEM;
 686
 687         ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c, &clk_src_div);
 688         if (ret)
 689                 return -EINVAL;
 690
 691         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 692         i2c->base = devm_ioremap_resource(&pdev->dev, res);
 693         if (IS_ERR(i2c->base))
 694                 return PTR_ERR(i2c->base);
 695
 696         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 697         i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res);
 698         if (IS_ERR(i2c->pdmabase))
 699                 return PTR_ERR(i2c->pdmabase);
 700
 701         irq = platform_get_irq(pdev, 0);
 702         if (irq <= 0)
 703                 return irq;
 704
 705         init_completion(&i2c->msg_complete);
 706
 707         of_id = of_match_node(mtk_i2c_of_match, pdev->dev.of_node);
 708         if (!of_id)
 709                 return -EINVAL;
 710
 711         i2c->dev_comp = of_id->data;
 712         i2c->adap.dev.of_node = pdev->dev.of_node;
 713         i2c->dev = &pdev->dev;
 714         i2c->adap.dev.parent = &pdev->dev;
 715         i2c->adap.owner = THIS_MODULE;
 716         i2c->adap.algo = &mtk_i2c_algorithm;
 717         i2c->adap.quirks = i2c->dev_comp->quirks;
 718         i2c->adap.timeout = 2 * HZ;
 719         i2c->adap.retries = 1;
 720
 721         if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c)
 722                 return -EINVAL;
 723
 724         i2c->clk_main = devm_clk_get(&pdev->dev, "main");
 725         if (IS_ERR(i2c->clk_main)) {
 726                 dev_err(&pdev->dev, "cannot get main clock\n");
 727                 return PTR_ERR(i2c->clk_main);
 728         }
 729
 730         i2c->clk_dma = devm_clk_get(&pdev->dev, "dma");
 731         if (IS_ERR(i2c->clk_dma)) {
 732                 dev_err(&pdev->dev, "cannot get dma clock\n");
 733                 return PTR_ERR(i2c->clk_dma);
 734         }
 735
 736         clk = i2c->clk_main;
 737         if (i2c->have_pmic) {
 738                 i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic");
 739                 if (IS_ERR(i2c->clk_pmic)) {
 740                         dev_err(&pdev->dev, "cannot get pmic clock\n");
 741                         return PTR_ERR(i2c->clk_pmic);
 742                 }
 743                 clk = i2c->clk_pmic;
 744         }
 745
 746         strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
 747
 748         ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk), clk_src_div);
 749         if (ret) {
 750                 dev_err(&pdev->dev, "Failed to set the speed.\n");
 751                 return -EINVAL;
 752         }
 753
 754         if (i2c->dev_comp->support_33bits) {
 755                 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(33));
 756                 if (ret) {
 757                         dev_err(&pdev->dev, "dma_set_mask return error.\n");
 758                         return ret;
 759                 }
 760         }
 761
 762         ret = mtk_i2c_clock_enable(i2c);
 763         if (ret) {
 764                 dev_err(&pdev->dev, "clock enable failed!\n");
 765                 return ret;
 766         }
 767         mtk_i2c_init_hw(i2c);
 768         mtk_i2c_clock_disable(i2c);
 769
 770         ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
 771                                IRQF_TRIGGER_NONE, I2C_DRV_NAME, i2c);
 772         if (ret < 0) {
 773                 dev_err(&pdev->dev,
 774                         "Request I2C IRQ %d fail\n", irq);
 775                 return ret;
 776         }
 777
 778         i2c_set_adapdata(&i2c->adap, i2c);
 779         ret = i2c_add_adapter(&i2c->adap);
 780         if (ret)
 781                 return ret;
 782
 783         platform_set_drvdata(pdev, i2c);
 784
 785         return 0;
 786 }
 787
 788 static int mtk_i2c_remove(struct platform_device *pdev)
 789 {
 790         struct mtk_i2c *i2c = platform_get_drvdata(pdev);
 791
 792         i2c_del_adapter(&i2c->adap);
 793
 794         return 0;
 795 }
 796
 797 #ifdef CONFIG_PM_SLEEP
 798 static int mtk_i2c_resume(struct device *dev)
 799 {
 800         struct mtk_i2c *i2c = dev_get_drvdata(dev);
 801
 802         mtk_i2c_init_hw(i2c);
 803
 804         return 0;
 805 }
 806 #endif
 807
 808 static const struct dev_pm_ops mtk_i2c_pm = {
 809         SET_SYSTEM_SLEEP_PM_OPS(NULL, mtk_i2c_resume)
 810 };
 811
 812 static struct platform_driver mtk_i2c_driver = {
 813         .probe = mtk_i2c_probe,
 814         .remove = mtk_i2c_remove,
 815         .driver = {
 816                 .name = I2C_DRV_NAME,
 817                 .pm = &mtk_i2c_pm,
 818                 .of_match_table = of_match_ptr(mtk_i2c_of_match),
 819         },
 820 };
 821
 822 module_platform_driver(mtk_i2c_driver);
 823
 824 MODULE_LICENSE("GPL v2");
 825 MODULE_DESCRIPTION("MediaTek I2C Bus Driver");
 826 MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>");