drivers/i2c/busses/i2c-tegra.c

   1 /*
   2  * drivers/i2c/busses/i2c-tegra.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Author: Colin Cross <ccross@android.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/clk.h>
  22 #include <linux/err.h>
  23 #include <linux/i2c.h>
  24 #include <linux/io.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/slab.h>
  28 #include <linux/i2c-tegra.h>
  29 #include <linux/of_i2c.h>
  30 #include <linux/of_device.h>
  31 #include <linux/module.h>
  32
  33 #include <asm/unaligned.h>
  34
  35 #include <mach/clk.h>
  36
  37 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
  38 #define BYTES_PER_FIFO_WORD 4
  39
  40 #define I2C_CNFG                                0x000
  41 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT             12
  42 #define I2C_CNFG_PACKET_MODE_EN                 (1<<10)
  43 #define I2C_CNFG_NEW_MASTER_FSM                 (1<<11)
  44 #define I2C_STATUS                              0x01C
  45 #define I2C_SL_CNFG                             0x020
  46 #define I2C_SL_CNFG_NACK                        (1<<1)
  47 #define I2C_SL_CNFG_NEWSL                       (1<<2)
  48 #define I2C_SL_ADDR1                            0x02c
  49 #define I2C_SL_ADDR2                            0x030
  50 #define I2C_TX_FIFO                             0x050
  51 #define I2C_RX_FIFO                             0x054
  52 #define I2C_PACKET_TRANSFER_STATUS              0x058
  53 #define I2C_FIFO_CONTROL                        0x05c
  54 #define I2C_FIFO_CONTROL_TX_FLUSH               (1<<1)
  55 #define I2C_FIFO_CONTROL_RX_FLUSH               (1<<0)
  56 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT          5
  57 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT          2
  58 #define I2C_FIFO_STATUS                         0x060
  59 #define I2C_FIFO_STATUS_TX_MASK                 0xF0
  60 #define I2C_FIFO_STATUS_TX_SHIFT                4
  61 #define I2C_FIFO_STATUS_RX_MASK                 0x0F
  62 #define I2C_FIFO_STATUS_RX_SHIFT                0
  63 #define I2C_INT_MASK                            0x064
  64 #define I2C_INT_STATUS                          0x068
  65 #define I2C_INT_PACKET_XFER_COMPLETE            (1<<7)
  66 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE       (1<<6)
  67 #define I2C_INT_TX_FIFO_OVERFLOW                (1<<5)
  68 #define I2C_INT_RX_FIFO_UNDERFLOW               (1<<4)
  69 #define I2C_INT_NO_ACK                          (1<<3)
  70 #define I2C_INT_ARBITRATION_LOST                (1<<2)
  71 #define I2C_INT_TX_FIFO_DATA_REQ                (1<<1)
  72 #define I2C_INT_RX_FIFO_DATA_REQ                (1<<0)
  73 #define I2C_CLK_DIVISOR                         0x06c
  74
  75 #define DVC_CTRL_REG1                           0x000
  76 #define DVC_CTRL_REG1_INTR_EN                   (1<<10)
  77 #define DVC_CTRL_REG2                           0x004
  78 #define DVC_CTRL_REG3                           0x008
  79 #define DVC_CTRL_REG3_SW_PROG                   (1<<26)
  80 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN          (1<<30)
  81 #define DVC_STATUS                              0x00c
  82 #define DVC_STATUS_I2C_DONE_INTR                (1<<30)
  83
  84 #define I2C_ERR_NONE                            0x00
  85 #define I2C_ERR_NO_ACK                          0x01
  86 #define I2C_ERR_ARBITRATION_LOST                0x02
  87 #define I2C_ERR_UNKNOWN_INTERRUPT               0x04
  88
  89 #define PACKET_HEADER0_HEADER_SIZE_SHIFT        28
  90 #define PACKET_HEADER0_PACKET_ID_SHIFT          16
  91 #define PACKET_HEADER0_CONT_ID_SHIFT            12
  92 #define PACKET_HEADER0_PROTOCOL_I2C             (1<<4)
  93
  94 #define I2C_HEADER_HIGHSPEED_MODE               (1<<22)
  95 #define I2C_HEADER_CONT_ON_NAK                  (1<<21)
  96 #define I2C_HEADER_SEND_START_BYTE              (1<<20)
  97 #define I2C_HEADER_READ                         (1<<19)
  98 #define I2C_HEADER_10BIT_ADDR                   (1<<18)
  99 #define I2C_HEADER_IE_ENABLE                    (1<<17)
 100 #define I2C_HEADER_REPEAT_START                 (1<<16)
 101 #define I2C_HEADER_CONTINUE_XFER                (1<<15)
 102 #define I2C_HEADER_MASTER_ADDR_SHIFT            12
 103 #define I2C_HEADER_SLAVE_ADDR_SHIFT             1
 104 /*
 105  * msg_end_type: The bus control which need to be send at end of transfer.
 106  * @MSG_END_STOP: Send stop pulse at end of transfer.
 107  * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
 108  * @MSG_END_CONTINUE: The following on message is coming and so do not send
 109  *              stop or repeat start.
 110  */
 111 enum msg_end_type {
 112         MSG_END_STOP,
 113         MSG_END_REPEAT_START,
 114         MSG_END_CONTINUE,
 115 };
 116
 117 /**
 118  * struct tegra_i2c_hw_feature : Different HW support on Tegra
 119  * @has_continue_xfer_support: Continue transfer supports.
 120  */
 121
 122 struct tegra_i2c_hw_feature {
 123         bool has_continue_xfer_support;
 124 };
 125
 126 /**
 127  * struct tegra_i2c_dev - per device i2c context
 128  * @dev: device reference for power management
 129  * @hw: Tegra i2c hw feature.
 130  * @adapter: core i2c layer adapter information
 131  * @div_clk: clock reference for div clock of i2c controller.
 132  * @fast_clk: clock reference for fast clock of i2c controller.
 133  * @base: ioremapped registers cookie
 134  * @cont_id: i2c controller id, used for for packet header
 135  * @irq: irq number of transfer complete interrupt
 136  * @is_dvc: identifies the DVC i2c controller, has a different register layout
 137  * @msg_complete: transfer completion notifier
 138  * @msg_err: error code for completed message
 139  * @msg_buf: pointer to current message data
 140  * @msg_buf_remaining: size of unsent data in the message buffer
 141  * @msg_read: identifies read transfers
 142  * @bus_clk_rate: current i2c bus clock rate
 143  * @is_suspended: prevents i2c controller accesses after suspend is called
 144  */
 145 struct tegra_i2c_dev {
 146         struct device *dev;
 147         const struct tegra_i2c_hw_feature *hw;
 148         struct i2c_adapter adapter;
 149         struct clk *div_clk;
 150         struct clk *fast_clk;
 151         void __iomem *base;
 152         int cont_id;
 153         int irq;
 154         bool irq_disabled;
 155         int is_dvc;
 156         struct completion msg_complete;
 157         int msg_err;
 158         u8 *msg_buf;
 159         size_t msg_buf_remaining;
 160         int msg_read;
 161         unsigned long bus_clk_rate;
 162         bool is_suspended;
 163 };
 164
 165 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
 166 {
 167         writel(val, i2c_dev->base + reg);
 168 }
 169
 170 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 171 {
 172         return readl(i2c_dev->base + reg);
 173 }
 174
 175 /*
 176  * i2c_writel and i2c_readl will offset the register if necessary to talk
 177  * to the I2C block inside the DVC block
 178  */
 179 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
 180         unsigned long reg)
 181 {
 182         if (i2c_dev->is_dvc)
 183                 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
 184         return reg;
 185 }
 186
 187 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
 188         unsigned long reg)
 189 {
 190         writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 191
 192         /* Read back register to make sure that register writes completed */
 193         if (reg != I2C_TX_FIFO)
 194                 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 195 }
 196
 197 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 198 {
 199         return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 200 }
 201
 202 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
 203         unsigned long reg, int len)
 204 {
 205         writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 206 }
 207
 208 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
 209         unsigned long reg, int len)
 210 {
 211         readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 212 }
 213
 214 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 215 {
 216         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
 217         int_mask &= ~mask;
 218         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 219 }
 220
 221 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 222 {
 223         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
 224         int_mask |= mask;
 225         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 226 }
 227
 228 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
 229 {
 230         unsigned long timeout = jiffies + HZ;
 231         u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
 232         val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
 233         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 234
 235         while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
 236                 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
 237                 if (time_after(jiffies, timeout)) {
 238                         dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
 239                         return -ETIMEDOUT;
 240                 }
 241                 msleep(1);
 242         }
 243         return 0;
 244 }
 245
 246 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
 247 {
 248         u32 val;
 249         int rx_fifo_avail;
 250         u8 *buf = i2c_dev->msg_buf;
 251         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 252         int words_to_transfer;
 253
 254         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 255         rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
 256                 I2C_FIFO_STATUS_RX_SHIFT;
 257
 258         /* Rounds down to not include partial word at the end of buf */
 259         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 260         if (words_to_transfer > rx_fifo_avail)
 261                 words_to_transfer = rx_fifo_avail;
 262
 263         i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
 264
 265         buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 266         buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 267         rx_fifo_avail -= words_to_transfer;
 268
 269         /*
 270          * If there is a partial word at the end of buf, handle it manually to
 271          * prevent overwriting past the end of buf
 272          */
 273         if (rx_fifo_avail > 0 && buf_remaining > 0) {
 274                 BUG_ON(buf_remaining > 3);
 275                 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
 276                 memcpy(buf, &val, buf_remaining);
 277                 buf_remaining = 0;
 278                 rx_fifo_avail--;
 279         }
 280
 281         BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
 282         i2c_dev->msg_buf_remaining = buf_remaining;
 283         i2c_dev->msg_buf = buf;
 284         return 0;
 285 }
 286
 287 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
 288 {
 289         u32 val;
 290         int tx_fifo_avail;
 291         u8 *buf = i2c_dev->msg_buf;
 292         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 293         int words_to_transfer;
 294
 295         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 296         tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
 297                 I2C_FIFO_STATUS_TX_SHIFT;
 298
 299         /* Rounds down to not include partial word at the end of buf */
 300         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 301
 302         /* It's very common to have < 4 bytes, so optimize that case. */
 303         if (words_to_transfer) {
 304                 if (words_to_transfer > tx_fifo_avail)
 305                         words_to_transfer = tx_fifo_avail;
 306
 307                 /*
 308                  * Update state before writing to FIFO.  If this casues us
 309                  * to finish writing all bytes (AKA buf_remaining goes to 0) we
 310                  * have a potential for an interrupt (PACKET_XFER_COMPLETE is
 311                  * not maskable).  We need to make sure that the isr sees
 312                  * buf_remaining as 0 and doesn't call us back re-entrantly.
 313                  */
 314                 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 315                 tx_fifo_avail -= words_to_transfer;
 316                 i2c_dev->msg_buf_remaining = buf_remaining;
 317                 i2c_dev->msg_buf = buf +
 318                         words_to_transfer * BYTES_PER_FIFO_WORD;
 319                 barrier();
 320
 321                 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
 322
 323                 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 324         }
 325
 326         /*
 327          * If there is a partial word at the end of buf, handle it manually to
 328          * prevent reading past the end of buf, which could cross a page
 329          * boundary and fault.
 330          */
 331         if (tx_fifo_avail > 0 && buf_remaining > 0) {
 332                 BUG_ON(buf_remaining > 3);
 333                 memcpy(&val, buf, buf_remaining);
 334
 335                 /* Again update before writing to FIFO to make sure isr sees. */
 336                 i2c_dev->msg_buf_remaining = 0;
 337                 i2c_dev->msg_buf = NULL;
 338                 barrier();
 339
 340                 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
 341         }
 342
 343         return 0;
 344 }
 345
 346 /*
 347  * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
 348  * block.  This block is identical to the rest of the I2C blocks, except that
 349  * it only supports master mode, it has registers moved around, and it needs
 350  * some extra init to get it into I2C mode.  The register moves are handled
 351  * by i2c_readl and i2c_writel
 352  */
 353 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
 354 {
 355         u32 val = 0;
 356         val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
 357         val |= DVC_CTRL_REG3_SW_PROG;
 358         val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
 359         dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
 360
 361         val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
 362         val |= DVC_CTRL_REG1_INTR_EN;
 363         dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
 364 }
 365
 366 static inline int tegra_i2c_clock_enable(struct tegra_i2c_dev *i2c_dev)
 367 {
 368         int ret;
 369         ret = clk_prepare_enable(i2c_dev->fast_clk);
 370         if (ret < 0) {
 371                 dev_err(i2c_dev->dev,
 372                         "Enabling fast clk failed, err %d\n", ret);
 373                 return ret;
 374         }
 375         ret = clk_prepare_enable(i2c_dev->div_clk);
 376         if (ret < 0) {
 377                 dev_err(i2c_dev->dev,
 378                         "Enabling div clk failed, err %d\n", ret);
 379                 clk_disable_unprepare(i2c_dev->fast_clk);
 380         }
 381         return ret;
 382 }
 383
 384 static inline void tegra_i2c_clock_disable(struct tegra_i2c_dev *i2c_dev)
 385 {
 386         clk_disable_unprepare(i2c_dev->div_clk);
 387         clk_disable_unprepare(i2c_dev->fast_clk);
 388 }
 389
 390 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
 391 {
 392         u32 val;
 393         int err = 0;
 394
 395         tegra_i2c_clock_enable(i2c_dev);
 396
 397         tegra_periph_reset_assert(i2c_dev->div_clk);
 398         udelay(2);
 399         tegra_periph_reset_deassert(i2c_dev->div_clk);
 400
 401         if (i2c_dev->is_dvc)
 402                 tegra_dvc_init(i2c_dev);
 403
 404         val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
 405                 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
 406         i2c_writel(i2c_dev, val, I2C_CNFG);
 407         i2c_writel(i2c_dev, 0, I2C_INT_MASK);
 408         clk_set_rate(i2c_dev->div_clk, i2c_dev->bus_clk_rate * 8);
 409
 410         if (!i2c_dev->is_dvc) {
 411                 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
 412                 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
 413                 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
 414                 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
 415                 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
 416
 417         }
 418
 419         val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
 420                 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
 421         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 422
 423         if (tegra_i2c_flush_fifos(i2c_dev))
 424                 err = -ETIMEDOUT;
 425
 426         tegra_i2c_clock_disable(i2c_dev);
 427
 428         if (i2c_dev->irq_disabled) {
 429                 i2c_dev->irq_disabled = 0;
 430                 enable_irq(i2c_dev->irq);
 431         }
 432
 433         return err;
 434 }
 435
 436 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
 437 {
 438         u32 status;
 439         const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 440         struct tegra_i2c_dev *i2c_dev = dev_id;
 441
 442         status = i2c_readl(i2c_dev, I2C_INT_STATUS);
 443
 444         if (status == 0) {
 445                 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
 446                          i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
 447                          i2c_readl(i2c_dev, I2C_STATUS),
 448                          i2c_readl(i2c_dev, I2C_CNFG));
 449                 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 450
 451                 if (!i2c_dev->irq_disabled) {
 452                         disable_irq_nosync(i2c_dev->irq);
 453                         i2c_dev->irq_disabled = 1;
 454                 }
 455                 goto err;
 456         }
 457
 458         if (unlikely(status & status_err)) {
 459                 if (status & I2C_INT_NO_ACK)
 460                         i2c_dev->msg_err |= I2C_ERR_NO_ACK;
 461                 if (status & I2C_INT_ARBITRATION_LOST)
 462                         i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
 463                 goto err;
 464         }
 465
 466         if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
 467                 if (i2c_dev->msg_buf_remaining)
 468                         tegra_i2c_empty_rx_fifo(i2c_dev);
 469                 else
 470                         BUG();
 471         }
 472
 473         if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
 474                 if (i2c_dev->msg_buf_remaining)
 475                         tegra_i2c_fill_tx_fifo(i2c_dev);
 476                 else
 477                         tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
 478         }
 479
 480         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 481         if (i2c_dev->is_dvc)
 482                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 483
 484         if (status & I2C_INT_PACKET_XFER_COMPLETE) {
 485                 BUG_ON(i2c_dev->msg_buf_remaining);
 486                 complete(&i2c_dev->msg_complete);
 487         }
 488         return IRQ_HANDLED;
 489 err:
 490         /* An error occurred, mask all interrupts */
 491         tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
 492                 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
 493                 I2C_INT_RX_FIFO_DATA_REQ);
 494         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 495         if (i2c_dev->is_dvc)
 496                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 497
 498         complete(&i2c_dev->msg_complete);
 499         return IRQ_HANDLED;
 500 }
 501
 502 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
 503         struct i2c_msg *msg, enum msg_end_type end_state)
 504 {
 505         u32 packet_header;
 506         u32 int_mask;
 507         int ret;
 508
 509         tegra_i2c_flush_fifos(i2c_dev);
 510
 511         if (msg->len == 0)
 512                 return -EINVAL;
 513
 514         i2c_dev->msg_buf = msg->buf;
 515         i2c_dev->msg_buf_remaining = msg->len;
 516         i2c_dev->msg_err = I2C_ERR_NONE;
 517         i2c_dev->msg_read = (msg->flags & I2C_M_RD);
 518         INIT_COMPLETION(i2c_dev->msg_complete);
 519
 520         packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
 521                         PACKET_HEADER0_PROTOCOL_I2C |
 522                         (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
 523                         (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
 524         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 525
 526         packet_header = msg->len - 1;
 527         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 528
 529         packet_header = I2C_HEADER_IE_ENABLE;
 530         if (end_state == MSG_END_CONTINUE)
 531                 packet_header |= I2C_HEADER_CONTINUE_XFER;
 532         else if (end_state == MSG_END_REPEAT_START)
 533                 packet_header |= I2C_HEADER_REPEAT_START;
 534         if (msg->flags & I2C_M_TEN) {
 535                 packet_header |= msg->addr;
 536                 packet_header |= I2C_HEADER_10BIT_ADDR;
 537         } else {
 538                 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
 539         }
 540         if (msg->flags & I2C_M_IGNORE_NAK)
 541                 packet_header |= I2C_HEADER_CONT_ON_NAK;
 542         if (msg->flags & I2C_M_RD)
 543                 packet_header |= I2C_HEADER_READ;
 544         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 545
 546         if (!(msg->flags & I2C_M_RD))
 547                 tegra_i2c_fill_tx_fifo(i2c_dev);
 548
 549         int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 550         if (msg->flags & I2C_M_RD)
 551                 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
 552         else if (i2c_dev->msg_buf_remaining)
 553                 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
 554         tegra_i2c_unmask_irq(i2c_dev, int_mask);
 555         dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
 556                 i2c_readl(i2c_dev, I2C_INT_MASK));
 557
 558         ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT);
 559         tegra_i2c_mask_irq(i2c_dev, int_mask);
 560
 561         if (WARN_ON(ret == 0)) {
 562                 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
 563
 564                 tegra_i2c_init(i2c_dev);
 565                 return -ETIMEDOUT;
 566         }
 567
 568         dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n",
 569                 ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
 570
 571         if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
 572                 return 0;
 573
 574         /*
 575          * NACK interrupt is generated before the I2C controller generates the
 576          * STOP condition on the bus. So wait for 2 clock periods before resetting
 577          * the controller so that STOP condition has been delivered properly.
 578          */
 579         if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
 580                 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
 581
 582         tegra_i2c_init(i2c_dev);
 583         if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
 584                 if (msg->flags & I2C_M_IGNORE_NAK)
 585                         return 0;
 586                 return -EREMOTEIO;
 587         }
 588
 589         return -EIO;
 590 }
 591
 592 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
 593         int num)
 594 {
 595         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 596         int i;
 597         int ret = 0;
 598
 599         if (i2c_dev->is_suspended)
 600                 return -EBUSY;
 601
 602         tegra_i2c_clock_enable(i2c_dev);
 603         for (i = 0; i < num; i++) {
 604                 enum msg_end_type end_type = MSG_END_STOP;
 605                 if (i < (num - 1)) {
 606                         if (msgs[i + 1].flags & I2C_M_NOSTART)
 607                                 end_type = MSG_END_CONTINUE;
 608                         else
 609                                 end_type = MSG_END_REPEAT_START;
 610                 }
 611                 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
 612                 if (ret)
 613                         break;
 614         }
 615         tegra_i2c_clock_disable(i2c_dev);
 616         return ret ?: i;
 617 }
 618
 619 static u32 tegra_i2c_func(struct i2c_adapter *adap)
 620 {
 621         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 622         u32 ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
 623                                 I2C_FUNC_PROTOCOL_MANGLING;
 624
 625         if (i2c_dev->hw->has_continue_xfer_support)
 626                 ret |= I2C_FUNC_NOSTART;
 627         return ret;
 628 }
 629
 630 static const struct i2c_algorithm tegra_i2c_algo = {
 631         .master_xfer    = tegra_i2c_xfer,
 632         .functionality  = tegra_i2c_func,
 633 };
 634
 635 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
 636         .has_continue_xfer_support = false,
 637 };
 638
 639 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
 640         .has_continue_xfer_support = true,
 641 };
 642
 643 #if defined(CONFIG_OF)
 644 /* Match table for of_platform binding */
 645 static const struct of_device_id tegra_i2c_of_match[] = {
 646         { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
 647         { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
 648         { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
 649         {},
 650 };
 651 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
 652 #endif
 653
 654 static int tegra_i2c_probe(struct platform_device *pdev)
 655 {
 656         struct tegra_i2c_dev *i2c_dev;
 657         struct tegra_i2c_platform_data *pdata = pdev->dev.platform_data;
 658         struct resource *res;
 659         struct clk *div_clk;
 660         struct clk *fast_clk;
 661         const unsigned int *prop;
 662         void __iomem *base;
 663         int irq;
 664         int ret = 0;
 665
 666         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 667         if (!res) {
 668                 dev_err(&pdev->dev, "no mem resource\n");
 669                 return -EINVAL;
 670         }
 671
 672         base = devm_request_and_ioremap(&pdev->dev, res);
 673         if (!base) {
 674                 dev_err(&pdev->dev, "Cannot request/ioremap I2C registers\n");
 675                 return -EADDRNOTAVAIL;
 676         }
 677
 678         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 679         if (!res) {
 680                 dev_err(&pdev->dev, "no irq resource\n");
 681                 return -EINVAL;
 682         }
 683         irq = res->start;
 684
 685         div_clk = devm_clk_get(&pdev->dev, "div-clk");
 686         if (IS_ERR(div_clk)) {
 687                 dev_err(&pdev->dev, "missing controller clock");
 688                 return PTR_ERR(div_clk);
 689         }
 690
 691         fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
 692         if (IS_ERR(fast_clk)) {
 693                 dev_err(&pdev->dev, "missing bus clock");
 694                 return PTR_ERR(fast_clk);
 695         }
 696
 697         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
 698         if (!i2c_dev) {
 699                 dev_err(&pdev->dev, "Could not allocate struct tegra_i2c_dev");
 700                 return -ENOMEM;
 701         }
 702
 703         i2c_dev->base = base;
 704         i2c_dev->div_clk = div_clk;
 705         i2c_dev->fast_clk = fast_clk;
 706         i2c_dev->adapter.algo = &tegra_i2c_algo;
 707         i2c_dev->irq = irq;
 708         i2c_dev->cont_id = pdev->id;
 709         i2c_dev->dev = &pdev->dev;
 710
 711         i2c_dev->bus_clk_rate = 100000; /* default clock rate */
 712         if (pdata) {
 713                 i2c_dev->bus_clk_rate = pdata->bus_clk_rate;
 714
 715         } else if (i2c_dev->dev->of_node) {    /* if there is a device tree node ... */
 716                 prop = of_get_property(i2c_dev->dev->of_node,
 717                                 "clock-frequency", NULL);
 718                 if (prop)
 719                         i2c_dev->bus_clk_rate = be32_to_cpup(prop);
 720         }
 721
 722         i2c_dev->hw = &tegra20_i2c_hw;
 723
 724         if (pdev->dev.of_node) {
 725                 const struct of_device_id *match;
 726                 match = of_match_device(of_match_ptr(tegra_i2c_of_match),
 727                                                 &pdev->dev);
 728                 i2c_dev->hw = match->data;
 729                 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
 730                                                 "nvidia,tegra20-i2c-dvc");
 731         } else if (pdev->id == 3) {
 732                 i2c_dev->is_dvc = 1;
 733         }
 734         init_completion(&i2c_dev->msg_complete);
 735
 736         platform_set_drvdata(pdev, i2c_dev);
 737
 738         ret = tegra_i2c_init(i2c_dev);
 739         if (ret) {
 740                 dev_err(&pdev->dev, "Failed to initialize i2c controller");
 741                 return ret;
 742         }
 743
 744         ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
 745                         tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);
 746         if (ret) {
 747                 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
 748                 return ret;
 749         }
 750
 751         i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
 752         i2c_dev->adapter.owner = THIS_MODULE;
 753         i2c_dev->adapter.class = I2C_CLASS_HWMON;
 754         strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
 755                 sizeof(i2c_dev->adapter.name));
 756         i2c_dev->adapter.algo = &tegra_i2c_algo;
 757         i2c_dev->adapter.dev.parent = &pdev->dev;
 758         i2c_dev->adapter.nr = pdev->id;
 759         i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
 760
 761         ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
 762         if (ret) {
 763                 dev_err(&pdev->dev, "Failed to add I2C adapter\n");
 764                 return ret;
 765         }
 766
 767         of_i2c_register_devices(&i2c_dev->adapter);
 768
 769         return 0;
 770 }
 771
 772 static int tegra_i2c_remove(struct platform_device *pdev)
 773 {
 774         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 775         i2c_del_adapter(&i2c_dev->adapter);
 776         return 0;
 777 }
 778
 779 #ifdef CONFIG_PM_SLEEP
 780 static int tegra_i2c_suspend(struct device *dev)
 781 {
 782         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 783
 784         i2c_lock_adapter(&i2c_dev->adapter);
 785         i2c_dev->is_suspended = true;
 786         i2c_unlock_adapter(&i2c_dev->adapter);
 787
 788         return 0;
 789 }
 790
 791 static int tegra_i2c_resume(struct device *dev)
 792 {
 793         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 794         int ret;
 795
 796         i2c_lock_adapter(&i2c_dev->adapter);
 797
 798         ret = tegra_i2c_init(i2c_dev);
 799
 800         if (ret) {
 801                 i2c_unlock_adapter(&i2c_dev->adapter);
 802                 return ret;
 803         }
 804
 805         i2c_dev->is_suspended = false;
 806
 807         i2c_unlock_adapter(&i2c_dev->adapter);
 808
 809         return 0;
 810 }
 811
 812 static SIMPLE_DEV_PM_OPS(tegra_i2c_pm, tegra_i2c_suspend, tegra_i2c_resume);
 813 #define TEGRA_I2C_PM    (&tegra_i2c_pm)
 814 #else
 815 #define TEGRA_I2C_PM    NULL
 816 #endif
 817
 818 static struct platform_driver tegra_i2c_driver = {
 819         .probe   = tegra_i2c_probe,
 820         .remove  = tegra_i2c_remove,
 821         .driver  = {
 822                 .name  = "tegra-i2c",
 823                 .owner = THIS_MODULE,
 824                 .of_match_table = of_match_ptr(tegra_i2c_of_match),
 825                 .pm    = TEGRA_I2C_PM,
 826         },
 827 };
 828
 829 static int __init tegra_i2c_init_driver(void)
 830 {
 831         return platform_driver_register(&tegra_i2c_driver);
 832 }
 833
 834 static void __exit tegra_i2c_exit_driver(void)
 835 {
 836         platform_driver_unregister(&tegra_i2c_driver);
 837 }
 838
 839 subsys_initcall(tegra_i2c_init_driver);
 840 module_exit(tegra_i2c_exit_driver);
 841
 842 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
 843 MODULE_AUTHOR("Colin Cross");
 844 MODULE_LICENSE("GPL v2");