2 * intel_idle.c - native hardware idle loop for modern Intel processors
4 * Copyright (c) 2010, Intel Corporation.
5 * Len Brown <len.brown@intel.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 * intel_idle is a cpuidle driver that loads on specific Intel processors
23 * in lieu of the legacy ACPI processor_idle driver. The intent is to
24 * make Linux more efficient on these processors, as intel_idle knows
25 * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
31 * All CPUs have same idle states as boot CPU
33 * Chipset BM_STS (bus master status) bit is a NOP
34 * for preventing entry into deep C-stats
40 * The driver currently initializes for_each_online_cpu() upon modprobe.
41 * It it unaware of subsequent processors hot-added to the system.
42 * This means that if you boot with maxcpus=n and later online
43 * processors above n, those processors will use C1 only.
45 * ACPI has a .suspend hack to turn off deep c-statees during suspend
46 * to avoid complications with the lapic timer workaround.
47 * Have not seen issues with suspend, but may need same workaround here.
49 * There is currently no kernel-based automatic probing/loading mechanism
50 * if the driver is built as a module.
53 /* un-comment DEBUG to enable pr_debug() statements */
56 #include <linux/kernel.h>
57 #include <linux/cpuidle.h>
58 #include <linux/clockchips.h>
59 #include <linux/hrtimer.h> /* ktime_get_real() */
60 #include <trace/events/power.h>
61 #include <linux/sched.h>
62 #include <linux/notifier.h>
63 #include <linux/cpu.h>
64 #include <linux/module.h>
65 #include <asm/mwait.h>
68 #define INTEL_IDLE_VERSION "0.4"
69 #define PREFIX "intel_idle: "
71 static struct cpuidle_driver intel_idle_driver = {
75 /* intel_idle.max_cstate=0 disables driver */
76 static int max_cstate = MWAIT_MAX_NUM_CSTATES - 1;
78 static unsigned int mwait_substates;
80 #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
81 /* Reliable LAPIC Timer States, bit 1 for C1 etc. */
82 static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */
84 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
85 static int intel_idle(struct cpuidle_device *dev,
86 struct cpuidle_driver *drv, int index);
88 static struct cpuidle_state *cpuidle_state_table;
91 * Hardware C-state auto-demotion may not always be optimal.
92 * Indicate which enable bits to clear here.
94 static unsigned long long auto_demotion_disable_flags;
97 * Set this flag for states where the HW flushes the TLB for us
98 * and so we don't need cross-calls to keep it consistent.
99 * If this flag is set, SW flushes the TLB, so even if the
100 * HW doesn't do the flushing, this flag is safe to use.
102 #define CPUIDLE_FLAG_TLB_FLUSHED 0x10000
105 * States are indexed by the cstate number,
106 * which is also the index into the MWAIT hint array.
107 * Thus C0 is a dummy.
109 static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
113 .desc = "MWAIT 0x00",
114 .flags = CPUIDLE_FLAG_TIME_VALID,
116 .target_residency = 6,
117 .enter = &intel_idle },
120 .desc = "MWAIT 0x10",
121 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
123 .target_residency = 80,
124 .enter = &intel_idle },
127 .desc = "MWAIT 0x20",
128 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
130 .target_residency = 800,
131 .enter = &intel_idle },
134 static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = {
138 .desc = "MWAIT 0x00",
139 .flags = CPUIDLE_FLAG_TIME_VALID,
141 .target_residency = 1,
142 .enter = &intel_idle },
145 .desc = "MWAIT 0x10",
146 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
148 .target_residency = 211,
149 .enter = &intel_idle },
152 .desc = "MWAIT 0x20",
153 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
155 .target_residency = 345,
156 .enter = &intel_idle },
159 .desc = "MWAIT 0x30",
160 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
162 .target_residency = 345,
163 .enter = &intel_idle },
166 static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
170 .desc = "MWAIT 0x00",
171 .flags = CPUIDLE_FLAG_TIME_VALID,
173 .target_residency = 4,
174 .enter = &intel_idle },
177 .desc = "MWAIT 0x10",
178 .flags = CPUIDLE_FLAG_TIME_VALID,
180 .target_residency = 80,
181 .enter = &intel_idle },
185 .desc = "MWAIT 0x30",
186 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
188 .target_residency = 400,
189 .enter = &intel_idle },
193 .desc = "MWAIT 0x52",
194 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
196 .target_residency = 560,
197 .enter = &intel_idle },
200 static int get_driver_data(int cstate)
205 case 1: /* MWAIT C1 */
208 case 2: /* MWAIT C2 */
211 case 3: /* MWAIT C3 */
214 case 4: /* MWAIT C4 */
217 case 5: /* MWAIT C5 */
220 case 6: /* MWAIT C6 */
231 * @dev: cpuidle_device
232 * @drv: cpuidle driver
233 * @index: index of cpuidle state
236 static int intel_idle(struct cpuidle_device *dev,
237 struct cpuidle_driver *drv, int index)
239 unsigned long ecx = 1; /* break on interrupt flag */
240 struct cpuidle_state *state = &drv->states[index];
241 struct cpuidle_state_usage *state_usage = &dev->states_usage[index];
242 unsigned long eax = (unsigned long)cpuidle_get_statedata(state_usage);
244 ktime_t kt_before, kt_after;
246 int cpu = smp_processor_id();
248 cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
253 * leave_mm() to avoid costly and often unnecessary wakeups
254 * for flushing the user TLB's associated with the active mm.
256 if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
259 if (!(lapic_timer_reliable_states & (1 << (cstate))))
260 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
262 kt_before = ktime_get_real();
264 stop_critical_timings();
265 if (!need_resched()) {
267 __monitor((void *)¤t_thread_info()->flags, 0, 0);
273 start_critical_timings();
275 kt_after = ktime_get_real();
276 usec_delta = ktime_to_us(ktime_sub(kt_after, kt_before));
280 if (!(lapic_timer_reliable_states & (1 << (cstate))))
281 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
283 /* Update cpuidle counters */
284 dev->last_residency = (int)usec_delta;
289 static void __setup_broadcast_timer(void *arg)
291 unsigned long reason = (unsigned long)arg;
292 int cpu = smp_processor_id();
295 CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
297 clockevents_notify(reason, &cpu);
300 static void auto_demotion_disable(void *dummy)
302 unsigned long long msr_bits;
304 rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
305 msr_bits &= ~auto_demotion_disable_flags;
306 wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
309 static void __intel_idle_notify_handler(void *arg)
311 if (auto_demotion_disable_flags)
312 auto_demotion_disable(NULL);
314 if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
315 __setup_broadcast_timer((void *)true);
318 static int setup_intelidle_cpuhp_notify(struct notifier_block *n,
319 unsigned long action, void *hcpu)
321 int hotcpu = (unsigned long)hcpu;
323 switch (action & 0xf) {
325 smp_call_function_single(hotcpu, __intel_idle_notify_handler,
332 static struct notifier_block setup_intelidle_notifier = {
333 .notifier_call = setup_intelidle_cpuhp_notify,
339 static int intel_idle_probe(void)
341 unsigned int eax, ebx, ecx;
343 if (max_cstate == 0) {
344 pr_debug(PREFIX "disabled\n");
348 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
351 if (!boot_cpu_has(X86_FEATURE_MWAIT))
354 if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
357 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
359 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
360 !(ecx & CPUID5_ECX_INTERRUPT_BREAK))
363 pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
366 if (boot_cpu_data.x86 != 6) /* family 6 */
369 switch (boot_cpu_data.x86_model) {
371 case 0x1A: /* Core i7, Xeon 5500 series */
372 case 0x1E: /* Core i7 and i5 Processor - Lynnfield Jasper Forest */
373 case 0x1F: /* Core i7 and i5 Processor - Nehalem */
374 case 0x2E: /* Nehalem-EX Xeon */
375 case 0x2F: /* Westmere-EX Xeon */
376 case 0x25: /* Westmere */
377 case 0x2C: /* Westmere */
378 cpuidle_state_table = nehalem_cstates;
379 auto_demotion_disable_flags =
380 (NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE);
383 case 0x1C: /* 28 - Atom Processor */
384 cpuidle_state_table = atom_cstates;
387 case 0x26: /* 38 - Lincroft Atom Processor */
388 cpuidle_state_table = atom_cstates;
389 auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE;
393 case 0x2D: /* SNB Xeon */
394 cpuidle_state_table = snb_cstates;
398 pr_debug(PREFIX "does not run on family %d model %d\n",
399 boot_cpu_data.x86, boot_cpu_data.x86_model);
403 if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */
404 lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
406 on_each_cpu(__setup_broadcast_timer, (void *)true, 1);
408 pr_debug(PREFIX "v" INTEL_IDLE_VERSION
409 " model 0x%X\n", boot_cpu_data.x86_model);
411 pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
412 lapic_timer_reliable_states);
417 * intel_idle_cpuidle_devices_uninit()
418 * unregister, free cpuidle_devices
420 static void intel_idle_cpuidle_devices_uninit(void)
423 struct cpuidle_device *dev;
425 for_each_online_cpu(i) {
426 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
427 cpuidle_unregister_device(dev);
430 free_percpu(intel_idle_cpuidle_devices);
434 * intel_idle_cpuidle_driver_init()
435 * allocate, initialize cpuidle_states
437 static int intel_idle_cpuidle_driver_init(void)
440 struct cpuidle_driver *drv = &intel_idle_driver;
442 drv->state_count = 1;
444 for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
447 if (cstate > max_cstate) {
448 printk(PREFIX "max_cstate %d reached\n",
453 /* does the state exist in CPUID.MWAIT? */
454 num_substates = (mwait_substates >> ((cstate) * 4))
455 & MWAIT_SUBSTATE_MASK;
456 if (num_substates == 0)
458 /* is the state not enabled? */
459 if (cpuidle_state_table[cstate].enter == NULL) {
460 /* does the driver not know about the state? */
461 if (*cpuidle_state_table[cstate].name == '\0')
462 pr_debug(PREFIX "unaware of model 0x%x"
464 " contact lenb@kernel.org",
465 boot_cpu_data.x86_model, cstate);
470 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
471 mark_tsc_unstable("TSC halts in idle"
472 " states deeper than C2");
474 drv->states[drv->state_count] = /* structure copy */
475 cpuidle_state_table[cstate];
477 drv->state_count += 1;
480 if (auto_demotion_disable_flags)
481 on_each_cpu(auto_demotion_disable, NULL, 1);
488 * intel_idle_cpuidle_devices_init()
489 * allocate, initialize, register cpuidle_devices
491 static int intel_idle_cpuidle_devices_init(void)
494 struct cpuidle_device *dev;
496 intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
497 if (intel_idle_cpuidle_devices == NULL)
500 for_each_online_cpu(i) {
501 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
503 dev->state_count = 1;
505 for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
508 if (cstate > max_cstate) {
509 printk(PREFIX "max_cstate %d reached\n",
514 /* does the state exist in CPUID.MWAIT? */
515 num_substates = (mwait_substates >> ((cstate) * 4))
516 & MWAIT_SUBSTATE_MASK;
517 if (num_substates == 0)
519 /* is the state not enabled? */
520 if (cpuidle_state_table[cstate].enter == NULL) {
524 dev->states_usage[dev->state_count].driver_data =
525 (void *)get_driver_data(cstate);
527 dev->state_count += 1;
531 if (cpuidle_register_device(dev)) {
532 pr_debug(PREFIX "cpuidle_register_device %d failed!\n",
534 intel_idle_cpuidle_devices_uninit();
543 static int __init intel_idle_init(void)
547 /* Do not load intel_idle at all for now if idle= is passed */
548 if (boot_option_idle_override != IDLE_NO_OVERRIDE)
551 retval = intel_idle_probe();
555 intel_idle_cpuidle_driver_init();
556 retval = cpuidle_register_driver(&intel_idle_driver);
558 printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
559 cpuidle_get_driver()->name);
563 retval = intel_idle_cpuidle_devices_init();
565 cpuidle_unregister_driver(&intel_idle_driver);
569 if (auto_demotion_disable_flags || lapic_timer_reliable_states !=
570 LAPIC_TIMER_ALWAYS_RELIABLE)
571 register_cpu_notifier(&setup_intelidle_notifier);
576 static void __exit intel_idle_exit(void)
578 intel_idle_cpuidle_devices_uninit();
579 cpuidle_unregister_driver(&intel_idle_driver);
581 if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
582 on_each_cpu(__setup_broadcast_timer, (void *)false, 1);
584 if (auto_demotion_disable_flags || lapic_timer_reliable_states !=
585 LAPIC_TIMER_ALWAYS_RELIABLE)
586 unregister_cpu_notifier(&setup_intelidle_notifier);
591 module_init(intel_idle_init);
592 module_exit(intel_idle_exit);
594 module_param(max_cstate, int, 0444);
596 MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
597 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
598 MODULE_LICENSE("GPL");