drivers/infiniband/hw/mlx5/qp.c

   1 /*
   2  * Copyright (c) 2013, Mellanox Technologies inc.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <rdma/ib_umem.h>
  35 #include "mlx5_ib.h"
  36 #include "user.h"
  37
  38 /* not supported currently */
  39 static int wq_signature;
  40
  41 enum {
  42         MLX5_IB_ACK_REQ_FREQ    = 8,
  43 };
  44
  45 enum {
  46         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  47         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  48         MLX5_IB_LINK_TYPE_IB            = 0,
  49         MLX5_IB_LINK_TYPE_ETH           = 1
  50 };
  51
  52 enum {
  53         MLX5_IB_SQ_STRIDE       = 6,
  54         MLX5_IB_CACHE_LINE_SIZE = 64,
  55 };
  56
  57 static const u32 mlx5_ib_opcode[] = {
  58         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
  59         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
  60         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
  61         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
  62         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
  63         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
  64         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
  65         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
  66         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
  67         [IB_WR_FAST_REG_MR]                     = MLX5_OPCODE_UMR,
  68         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
  69         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
  70         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
  71 };
  72
  73 struct umr_wr {
  74         u64                             virt_addr;
  75         struct ib_pd                   *pd;
  76         unsigned int                    page_shift;
  77         unsigned int                    npages;
  78         u32                             length;
  79         int                             access_flags;
  80         u32                             mkey;
  81 };
  82
  83 static int is_qp0(enum ib_qp_type qp_type)
  84 {
  85         return qp_type == IB_QPT_SMI;
  86 }
  87
  88 static int is_qp1(enum ib_qp_type qp_type)
  89 {
  90         return qp_type == IB_QPT_GSI;
  91 }
  92
  93 static int is_sqp(enum ib_qp_type qp_type)
  94 {
  95         return is_qp0(qp_type) || is_qp1(qp_type);
  96 }
  97
  98 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
  99 {
 100         return mlx5_buf_offset(&qp->buf, offset);
 101 }
 102
 103 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
 104 {
 105         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 106 }
 107
 108 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
 109 {
 110         return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
 111 }
 112
 113 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
 114 {
 115         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 116         struct ib_event event;
 117
 118         if (type == MLX5_EVENT_TYPE_PATH_MIG)
 119                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 120
 121         if (ibqp->event_handler) {
 122                 event.device     = ibqp->device;
 123                 event.element.qp = ibqp;
 124                 switch (type) {
 125                 case MLX5_EVENT_TYPE_PATH_MIG:
 126                         event.event = IB_EVENT_PATH_MIG;
 127                         break;
 128                 case MLX5_EVENT_TYPE_COMM_EST:
 129                         event.event = IB_EVENT_COMM_EST;
 130                         break;
 131                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 132                         event.event = IB_EVENT_SQ_DRAINED;
 133                         break;
 134                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 135                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 136                         break;
 137                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 138                         event.event = IB_EVENT_QP_FATAL;
 139                         break;
 140                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 141                         event.event = IB_EVENT_PATH_MIG_ERR;
 142                         break;
 143                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 144                         event.event = IB_EVENT_QP_REQ_ERR;
 145                         break;
 146                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 147                         event.event = IB_EVENT_QP_ACCESS_ERR;
 148                         break;
 149                 default:
 150                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
 151                         return;
 152                 }
 153
 154                 ibqp->event_handler(&event, ibqp->qp_context);
 155         }
 156 }
 157
 158 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
 159                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
 160 {
 161         int wqe_size;
 162         int wq_size;
 163
 164         /* Sanity check RQ size before proceeding */
 165         if (cap->max_recv_wr  > dev->mdev.caps.max_wqes)
 166                 return -EINVAL;
 167
 168         if (!has_rq) {
 169                 qp->rq.max_gs = 0;
 170                 qp->rq.wqe_cnt = 0;
 171                 qp->rq.wqe_shift = 0;
 172         } else {
 173                 if (ucmd) {
 174                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
 175                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
 176                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 177                         qp->rq.max_post = qp->rq.wqe_cnt;
 178                 } else {
 179                         wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
 180                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
 181                         wqe_size = roundup_pow_of_two(wqe_size);
 182                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
 183                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
 184                         qp->rq.wqe_cnt = wq_size / wqe_size;
 185                         if (wqe_size > dev->mdev.caps.max_rq_desc_sz) {
 186                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
 187                                             wqe_size,
 188                                             dev->mdev.caps.max_rq_desc_sz);
 189                                 return -EINVAL;
 190                         }
 191                         qp->rq.wqe_shift = ilog2(wqe_size);
 192                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 193                         qp->rq.max_post = qp->rq.wqe_cnt;
 194                 }
 195         }
 196
 197         return 0;
 198 }
 199
 200 static int sq_overhead(enum ib_qp_type qp_type)
 201 {
 202         int size = 0;
 203
 204         switch (qp_type) {
 205         case IB_QPT_XRC_INI:
 206                 size += sizeof(struct mlx5_wqe_xrc_seg);
 207                 /* fall through */
 208         case IB_QPT_RC:
 209                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 210                         sizeof(struct mlx5_wqe_atomic_seg) +
 211                         sizeof(struct mlx5_wqe_raddr_seg);
 212                 break;
 213
 214         case IB_QPT_XRC_TGT:
 215                 return 0;
 216
 217         case IB_QPT_UC:
 218                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 219                         sizeof(struct mlx5_wqe_raddr_seg);
 220                 break;
 221
 222         case IB_QPT_UD:
 223         case IB_QPT_SMI:
 224         case IB_QPT_GSI:
 225                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 226                         sizeof(struct mlx5_wqe_datagram_seg);
 227                 break;
 228
 229         case MLX5_IB_QPT_REG_UMR:
 230                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 231                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 232                         sizeof(struct mlx5_mkey_seg);
 233                 break;
 234
 235         default:
 236                 return -EINVAL;
 237         }
 238
 239         return size;
 240 }
 241
 242 static int calc_send_wqe(struct ib_qp_init_attr *attr)
 243 {
 244         int inl_size = 0;
 245         int size;
 246
 247         size = sq_overhead(attr->qp_type);
 248         if (size < 0)
 249                 return size;
 250
 251         if (attr->cap.max_inline_data) {
 252                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
 253                         attr->cap.max_inline_data;
 254         }
 255
 256         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
 257
 258         return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
 259 }
 260
 261 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
 262                         struct mlx5_ib_qp *qp)
 263 {
 264         int wqe_size;
 265         int wq_size;
 266
 267         if (!attr->cap.max_send_wr)
 268                 return 0;
 269
 270         wqe_size = calc_send_wqe(attr);
 271         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
 272         if (wqe_size < 0)
 273                 return wqe_size;
 274
 275         if (wqe_size > dev->mdev.caps.max_sq_desc_sz) {
 276                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
 277                             wqe_size, dev->mdev.caps.max_sq_desc_sz);
 278                 return -EINVAL;
 279         }
 280
 281         qp->max_inline_data = wqe_size - sq_overhead(attr->qp_type) -
 282                 sizeof(struct mlx5_wqe_inline_seg);
 283         attr->cap.max_inline_data = qp->max_inline_data;
 284
 285         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
 286         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
 287         if (qp->sq.wqe_cnt > dev->mdev.caps.max_wqes) {
 288                 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
 289                             qp->sq.wqe_cnt, dev->mdev.caps.max_wqes);
 290                 return -ENOMEM;
 291         }
 292         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 293         qp->sq.max_gs = attr->cap.max_send_sge;
 294         qp->sq.max_post = wq_size / wqe_size;
 295         attr->cap.max_send_wr = qp->sq.max_post;
 296
 297         return wq_size;
 298 }
 299
 300 static int set_user_buf_size(struct mlx5_ib_dev *dev,
 301                             struct mlx5_ib_qp *qp,
 302                             struct mlx5_ib_create_qp *ucmd)
 303 {
 304         int desc_sz = 1 << qp->sq.wqe_shift;
 305
 306         if (desc_sz > dev->mdev.caps.max_sq_desc_sz) {
 307                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
 308                              desc_sz, dev->mdev.caps.max_sq_desc_sz);
 309                 return -EINVAL;
 310         }
 311
 312         if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
 313                 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
 314                              ucmd->sq_wqe_count, ucmd->sq_wqe_count);
 315                 return -EINVAL;
 316         }
 317
 318         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
 319
 320         if (qp->sq.wqe_cnt > dev->mdev.caps.max_wqes) {
 321                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
 322                              qp->sq.wqe_cnt, dev->mdev.caps.max_wqes);
 323                 return -EINVAL;
 324         }
 325
 326         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 327                 (qp->sq.wqe_cnt << 6);
 328
 329         return 0;
 330 }
 331
 332 static int qp_has_rq(struct ib_qp_init_attr *attr)
 333 {
 334         if (attr->qp_type == IB_QPT_XRC_INI ||
 335             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 336             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
 337             !attr->cap.max_recv_wr)
 338                 return 0;
 339
 340         return 1;
 341 }
 342
 343 static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
 344 {
 345         int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
 346         int start_uuar;
 347         int i;
 348
 349         start_uuar = nuuars - uuari->num_low_latency_uuars;
 350         for (i = start_uuar; i < nuuars; i++) {
 351                 if (!test_bit(i, uuari->bitmap)) {
 352                         set_bit(i, uuari->bitmap);
 353                         uuari->count[i]++;
 354                         return i;
 355                 }
 356         }
 357
 358         return -ENOMEM;
 359 }
 360
 361 static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
 362 {
 363         int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
 364         int minidx = 1;
 365         int uuarn;
 366         int end;
 367         int i;
 368
 369         end = nuuars - uuari->num_low_latency_uuars;
 370
 371         for (i = 1; i < end; i++) {
 372                 uuarn = i & 3;
 373                 if (uuarn == 2 || uuarn == 3)
 374                         continue;
 375
 376                 if (uuari->count[i] < uuari->count[minidx])
 377                         minidx = i;
 378         }
 379
 380         uuari->count[minidx]++;
 381         return minidx;
 382 }
 383
 384 static int alloc_uuar(struct mlx5_uuar_info *uuari,
 385                       enum mlx5_ib_latency_class lat)
 386 {
 387         int uuarn = -EINVAL;
 388
 389         mutex_lock(&uuari->lock);
 390         switch (lat) {
 391         case MLX5_IB_LATENCY_CLASS_LOW:
 392                 uuarn = 0;
 393                 uuari->count[uuarn]++;
 394                 break;
 395
 396         case MLX5_IB_LATENCY_CLASS_MEDIUM:
 397                 uuarn = alloc_med_class_uuar(uuari);
 398                 break;
 399
 400         case MLX5_IB_LATENCY_CLASS_HIGH:
 401                 uuarn = alloc_high_class_uuar(uuari);
 402                 break;
 403
 404         case MLX5_IB_LATENCY_CLASS_FAST_PATH:
 405                 uuarn = 2;
 406                 break;
 407         }
 408         mutex_unlock(&uuari->lock);
 409
 410         return uuarn;
 411 }
 412
 413 static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 414 {
 415         clear_bit(uuarn, uuari->bitmap);
 416         --uuari->count[uuarn];
 417 }
 418
 419 static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 420 {
 421         clear_bit(uuarn, uuari->bitmap);
 422         --uuari->count[uuarn];
 423 }
 424
 425 static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 426 {
 427         int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
 428         int high_uuar = nuuars - uuari->num_low_latency_uuars;
 429
 430         mutex_lock(&uuari->lock);
 431         if (uuarn == 0) {
 432                 --uuari->count[uuarn];
 433                 goto out;
 434         }
 435
 436         if (uuarn < high_uuar) {
 437                 free_med_class_uuar(uuari, uuarn);
 438                 goto out;
 439         }
 440
 441         free_high_class_uuar(uuari, uuarn);
 442
 443 out:
 444         mutex_unlock(&uuari->lock);
 445 }
 446
 447 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
 448 {
 449         switch (state) {
 450         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
 451         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
 452         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
 453         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
 454         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
 455         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
 456         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
 457         default:                return -1;
 458         }
 459 }
 460
 461 static int to_mlx5_st(enum ib_qp_type type)
 462 {
 463         switch (type) {
 464         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
 465         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
 466         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
 467         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
 468         case IB_QPT_XRC_INI:
 469         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
 470         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
 471         case IB_QPT_GSI:                return MLX5_QP_ST_QP1;
 472         case IB_QPT_RAW_IPV6:           return MLX5_QP_ST_RAW_IPV6;
 473         case IB_QPT_RAW_ETHERTYPE:      return MLX5_QP_ST_RAW_ETHERTYPE;
 474         case IB_QPT_RAW_PACKET:
 475         case IB_QPT_MAX:
 476         default:                return -EINVAL;
 477         }
 478 }
 479
 480 static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
 481 {
 482         return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
 483 }
 484
 485 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 486                           struct mlx5_ib_qp *qp, struct ib_udata *udata,
 487                           struct mlx5_create_qp_mbox_in **in,
 488                           struct mlx5_ib_create_qp_resp *resp, int *inlen)
 489 {
 490         struct mlx5_ib_ucontext *context;
 491         struct mlx5_ib_create_qp ucmd;
 492         int page_shift;
 493         int uar_index;
 494         int npages;
 495         u32 offset;
 496         int uuarn;
 497         int ncont;
 498         int err;
 499
 500         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
 501         if (err) {
 502                 mlx5_ib_dbg(dev, "copy failed\n");
 503                 return err;
 504         }
 505
 506         context = to_mucontext(pd->uobject->context);
 507         /*
 508          * TBD: should come from the verbs when we have the API
 509          */
 510         uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
 511         if (uuarn < 0) {
 512                 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
 513                 mlx5_ib_dbg(dev, "reverting to high latency\n");
 514                 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
 515                 if (uuarn < 0) {
 516                         mlx5_ib_dbg(dev, "uuar allocation failed\n");
 517                         return uuarn;
 518                 }
 519         }
 520
 521         uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
 522         mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
 523
 524         err = set_user_buf_size(dev, qp, &ucmd);
 525         if (err)
 526                 goto err_uuar;
 527
 528         qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
 529                                qp->buf_size, 0, 0);
 530         if (IS_ERR(qp->umem)) {
 531                 mlx5_ib_dbg(dev, "umem_get failed\n");
 532                 err = PTR_ERR(qp->umem);
 533                 goto err_uuar;
 534         }
 535
 536         mlx5_ib_cont_pages(qp->umem, ucmd.buf_addr, &npages, &page_shift,
 537                            &ncont, NULL);
 538         err = mlx5_ib_get_buf_offset(ucmd.buf_addr, page_shift, &offset);
 539         if (err) {
 540                 mlx5_ib_warn(dev, "bad offset\n");
 541                 goto err_umem;
 542         }
 543         mlx5_ib_dbg(dev, "addr 0x%llx, size %d, npages %d, page_shift %d, ncont %d, offset %d\n",
 544                     ucmd.buf_addr, qp->buf_size, npages, page_shift, ncont, offset);
 545
 546         *inlen = sizeof(**in) + sizeof(*(*in)->pas) * ncont;
 547         *in = mlx5_vzalloc(*inlen);
 548         if (!*in) {
 549                 err = -ENOMEM;
 550                 goto err_umem;
 551         }
 552         mlx5_ib_populate_pas(dev, qp->umem, page_shift, (*in)->pas, 0);
 553         (*in)->ctx.log_pg_sz_remote_qpn =
 554                 cpu_to_be32((page_shift - PAGE_SHIFT) << 24);
 555         (*in)->ctx.params2 = cpu_to_be32(offset << 6);
 556
 557         (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
 558         resp->uuar_index = uuarn;
 559         qp->uuarn = uuarn;
 560
 561         err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
 562         if (err) {
 563                 mlx5_ib_dbg(dev, "map failed\n");
 564                 goto err_free;
 565         }
 566
 567         err = ib_copy_to_udata(udata, resp, sizeof(*resp));
 568         if (err) {
 569                 mlx5_ib_dbg(dev, "copy failed\n");
 570                 goto err_unmap;
 571         }
 572         qp->create_type = MLX5_QP_USER;
 573
 574         return 0;
 575
 576 err_unmap:
 577         mlx5_ib_db_unmap_user(context, &qp->db);
 578
 579 err_free:
 580         mlx5_vfree(*in);
 581
 582 err_umem:
 583         ib_umem_release(qp->umem);
 584
 585 err_uuar:
 586         free_uuar(&context->uuari, uuarn);
 587         return err;
 588 }
 589
 590 static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp)
 591 {
 592         struct mlx5_ib_ucontext *context;
 593
 594         context = to_mucontext(pd->uobject->context);
 595         mlx5_ib_db_unmap_user(context, &qp->db);
 596         ib_umem_release(qp->umem);
 597         free_uuar(&context->uuari, qp->uuarn);
 598 }
 599
 600 static int create_kernel_qp(struct mlx5_ib_dev *dev,
 601                             struct ib_qp_init_attr *init_attr,
 602                             struct mlx5_ib_qp *qp,
 603                             struct mlx5_create_qp_mbox_in **in, int *inlen)
 604 {
 605         enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
 606         struct mlx5_uuar_info *uuari;
 607         int uar_index;
 608         int uuarn;
 609         int err;
 610
 611         uuari = &dev->mdev.priv.uuari;
 612         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
 613                 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
 614
 615         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
 616                 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
 617
 618         uuarn = alloc_uuar(uuari, lc);
 619         if (uuarn < 0) {
 620                 mlx5_ib_dbg(dev, "\n");
 621                 return -ENOMEM;
 622         }
 623
 624         qp->bf = &uuari->bfs[uuarn];
 625         uar_index = qp->bf->uar->index;
 626
 627         err = calc_sq_size(dev, init_attr, qp);
 628         if (err < 0) {
 629                 mlx5_ib_dbg(dev, "err %d\n", err);
 630                 goto err_uuar;
 631         }
 632
 633         qp->rq.offset = 0;
 634         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 635         qp->buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
 636
 637         err = mlx5_buf_alloc(&dev->mdev, qp->buf_size, PAGE_SIZE * 2, &qp->buf);
 638         if (err) {
 639                 mlx5_ib_dbg(dev, "err %d\n", err);
 640                 goto err_uuar;
 641         }
 642
 643         qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
 644         *inlen = sizeof(**in) + sizeof(*(*in)->pas) * qp->buf.npages;
 645         *in = mlx5_vzalloc(*inlen);
 646         if (!*in) {
 647                 err = -ENOMEM;
 648                 goto err_buf;
 649         }
 650         (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
 651         (*in)->ctx.log_pg_sz_remote_qpn = cpu_to_be32((qp->buf.page_shift - PAGE_SHIFT) << 24);
 652         /* Set "fast registration enabled" for all kernel QPs */
 653         (*in)->ctx.params1 |= cpu_to_be32(1 << 11);
 654         (*in)->ctx.sq_crq_size |= cpu_to_be16(1 << 4);
 655
 656         mlx5_fill_page_array(&qp->buf, (*in)->pas);
 657
 658         err = mlx5_db_alloc(&dev->mdev, &qp->db);
 659         if (err) {
 660                 mlx5_ib_dbg(dev, "err %d\n", err);
 661                 goto err_free;
 662         }
 663
 664         qp->db.db[0] = 0;
 665         qp->db.db[1] = 0;
 666
 667         qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
 668         qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
 669         qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
 670         qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
 671         qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
 672
 673         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
 674             !qp->sq.w_list || !qp->sq.wqe_head) {
 675                 err = -ENOMEM;
 676                 goto err_wrid;
 677         }
 678         qp->create_type = MLX5_QP_KERNEL;
 679
 680         return 0;
 681
 682 err_wrid:
 683         mlx5_db_free(&dev->mdev, &qp->db);
 684         kfree(qp->sq.wqe_head);
 685         kfree(qp->sq.w_list);
 686         kfree(qp->sq.wrid);
 687         kfree(qp->sq.wr_data);
 688         kfree(qp->rq.wrid);
 689
 690 err_free:
 691         mlx5_vfree(*in);
 692
 693 err_buf:
 694         mlx5_buf_free(&dev->mdev, &qp->buf);
 695
 696 err_uuar:
 697         free_uuar(&dev->mdev.priv.uuari, uuarn);
 698         return err;
 699 }
 700
 701 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
 702 {
 703         mlx5_db_free(&dev->mdev, &qp->db);
 704         kfree(qp->sq.wqe_head);
 705         kfree(qp->sq.w_list);
 706         kfree(qp->sq.wrid);
 707         kfree(qp->sq.wr_data);
 708         kfree(qp->rq.wrid);
 709         mlx5_buf_free(&dev->mdev, &qp->buf);
 710         free_uuar(&dev->mdev.priv.uuari, qp->bf->uuarn);
 711 }
 712
 713 static __be32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
 714 {
 715         if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
 716             (attr->qp_type == IB_QPT_XRC_INI))
 717                 return cpu_to_be32(MLX5_SRQ_RQ);
 718         else if (!qp->has_rq)
 719                 return cpu_to_be32(MLX5_ZERO_LEN_RQ);
 720         else
 721                 return cpu_to_be32(MLX5_NON_ZERO_RQ);
 722 }
 723
 724 static int is_connected(enum ib_qp_type qp_type)
 725 {
 726         if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
 727                 return 1;
 728
 729         return 0;
 730 }
 731
 732 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 733                             struct ib_qp_init_attr *init_attr,
 734                             struct ib_udata *udata, struct mlx5_ib_qp *qp)
 735 {
 736         struct mlx5_ib_resources *devr = &dev->devr;
 737         struct mlx5_ib_create_qp_resp resp;
 738         struct mlx5_create_qp_mbox_in *in;
 739         struct mlx5_ib_create_qp ucmd;
 740         int inlen = sizeof(*in);
 741         int err;
 742
 743         mutex_init(&qp->mutex);
 744         spin_lock_init(&qp->sq.lock);
 745         spin_lock_init(&qp->rq.lock);
 746
 747         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 748                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
 749
 750         if (pd && pd->uobject) {
 751                 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
 752                         mlx5_ib_dbg(dev, "copy failed\n");
 753                         return -EFAULT;
 754                 }
 755
 756                 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
 757                 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
 758         } else {
 759                 qp->wq_sig = !!wq_signature;
 760         }
 761
 762         qp->has_rq = qp_has_rq(init_attr);
 763         err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
 764                           qp, (pd && pd->uobject) ? &ucmd : NULL);
 765         if (err) {
 766                 mlx5_ib_dbg(dev, "err %d\n", err);
 767                 return err;
 768         }
 769
 770         if (pd) {
 771                 if (pd->uobject) {
 772                         mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
 773                         if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
 774                             ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
 775                                 mlx5_ib_dbg(dev, "invalid rq params\n");
 776                                 return -EINVAL;
 777                         }
 778                         if (ucmd.sq_wqe_count > dev->mdev.caps.max_wqes) {
 779                                 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
 780                                             ucmd.sq_wqe_count, dev->mdev.caps.max_wqes);
 781                                 return -EINVAL;
 782                         }
 783                         err = create_user_qp(dev, pd, qp, udata, &in, &resp, &inlen);
 784                         if (err)
 785                                 mlx5_ib_dbg(dev, "err %d\n", err);
 786                 } else {
 787                         err = create_kernel_qp(dev, init_attr, qp, &in, &inlen);
 788                         if (err)
 789                                 mlx5_ib_dbg(dev, "err %d\n", err);
 790                         else
 791                                 qp->pa_lkey = to_mpd(pd)->pa_lkey;
 792                 }
 793
 794                 if (err)
 795                         return err;
 796         } else {
 797                 in = mlx5_vzalloc(sizeof(*in));
 798                 if (!in)
 799                         return -ENOMEM;
 800
 801                 qp->create_type = MLX5_QP_EMPTY;
 802         }
 803
 804         if (is_sqp(init_attr->qp_type))
 805                 qp->port = init_attr->port_num;
 806
 807         in->ctx.flags = cpu_to_be32(to_mlx5_st(init_attr->qp_type) << 16 |
 808                                     MLX5_QP_PM_MIGRATED << 11);
 809
 810         if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
 811                 in->ctx.flags_pd = cpu_to_be32(to_mpd(pd ? pd : devr->p0)->pdn);
 812         else
 813                 in->ctx.flags_pd = cpu_to_be32(MLX5_QP_LAT_SENSITIVE);
 814
 815         if (qp->wq_sig)
 816                 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_ENABLE_SIG);
 817
 818         if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
 819                 int rcqe_sz;
 820                 int scqe_sz;
 821
 822                 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
 823                 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
 824
 825                 if (rcqe_sz == 128)
 826                         in->ctx.cs_res = MLX5_RES_SCAT_DATA64_CQE;
 827                 else
 828                         in->ctx.cs_res = MLX5_RES_SCAT_DATA32_CQE;
 829
 830                 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
 831                         if (scqe_sz == 128)
 832                                 in->ctx.cs_req = MLX5_REQ_SCAT_DATA64_CQE;
 833                         else
 834                                 in->ctx.cs_req = MLX5_REQ_SCAT_DATA32_CQE;
 835                 }
 836         }
 837
 838         if (qp->rq.wqe_cnt) {
 839                 in->ctx.rq_size_stride = (qp->rq.wqe_shift - 4);
 840                 in->ctx.rq_size_stride |= ilog2(qp->rq.wqe_cnt) << 3;
 841         }
 842
 843         in->ctx.rq_type_srqn = get_rx_type(qp, init_attr);
 844
 845         if (qp->sq.wqe_cnt)
 846                 in->ctx.sq_crq_size |= cpu_to_be16(ilog2(qp->sq.wqe_cnt) << 11);
 847         else
 848                 in->ctx.sq_crq_size |= cpu_to_be16(0x8000);
 849
 850         /* Set default resources */
 851         switch (init_attr->qp_type) {
 852         case IB_QPT_XRC_TGT:
 853                 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
 854                 in->ctx.cqn_send = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
 855                 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
 856                 in->ctx.xrcd = cpu_to_be32(to_mxrcd(init_attr->xrcd)->xrcdn);
 857                 break;
 858         case IB_QPT_XRC_INI:
 859                 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
 860                 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
 861                 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
 862                 break;
 863         default:
 864                 if (init_attr->srq) {
 865                         in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x0)->xrcdn);
 866                         in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(init_attr->srq)->msrq.srqn);
 867                 } else {
 868                         in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
 869                         in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
 870                 }
 871         }
 872
 873         if (init_attr->send_cq)
 874                 in->ctx.cqn_send = cpu_to_be32(to_mcq(init_attr->send_cq)->mcq.cqn);
 875
 876         if (init_attr->recv_cq)
 877                 in->ctx.cqn_recv = cpu_to_be32(to_mcq(init_attr->recv_cq)->mcq.cqn);
 878
 879         in->ctx.db_rec_addr = cpu_to_be64(qp->db.dma);
 880
 881         err = mlx5_core_create_qp(&dev->mdev, &qp->mqp, in, inlen);
 882         if (err) {
 883                 mlx5_ib_dbg(dev, "create qp failed\n");
 884                 goto err_create;
 885         }
 886
 887         mlx5_vfree(in);
 888         /* Hardware wants QPN written in big-endian order (after
 889          * shifting) for send doorbell.  Precompute this value to save
 890          * a little bit when posting sends.
 891          */
 892         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
 893
 894         qp->mqp.event = mlx5_ib_qp_event;
 895
 896         return 0;
 897
 898 err_create:
 899         if (qp->create_type == MLX5_QP_USER)
 900                 destroy_qp_user(pd, qp);
 901         else if (qp->create_type == MLX5_QP_KERNEL)
 902                 destroy_qp_kernel(dev, qp);
 903
 904         mlx5_vfree(in);
 905         return err;
 906 }
 907
 908 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
 909         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
 910 {
 911         if (send_cq) {
 912                 if (recv_cq) {
 913                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
 914                                 spin_lock_irq(&send_cq->lock);
 915                                 spin_lock_nested(&recv_cq->lock,
 916                                                  SINGLE_DEPTH_NESTING);
 917                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
 918                                 spin_lock_irq(&send_cq->lock);
 919                                 __acquire(&recv_cq->lock);
 920                         } else {
 921                                 spin_lock_irq(&recv_cq->lock);
 922                                 spin_lock_nested(&send_cq->lock,
 923                                                  SINGLE_DEPTH_NESTING);
 924                         }
 925                 } else {
 926                         spin_lock_irq(&send_cq->lock);
 927                 }
 928         } else if (recv_cq) {
 929                 spin_lock_irq(&recv_cq->lock);
 930         }
 931 }
 932
 933 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
 934         __releases(&send_cq->lock) __releases(&recv_cq->lock)
 935 {
 936         if (send_cq) {
 937                 if (recv_cq) {
 938                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
 939                                 spin_unlock(&recv_cq->lock);
 940                                 spin_unlock_irq(&send_cq->lock);
 941                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
 942                                 __release(&recv_cq->lock);
 943                                 spin_unlock_irq(&send_cq->lock);
 944                         } else {
 945                                 spin_unlock(&send_cq->lock);
 946                                 spin_unlock_irq(&recv_cq->lock);
 947                         }
 948                 } else {
 949                         spin_unlock_irq(&send_cq->lock);
 950                 }
 951         } else if (recv_cq) {
 952                 spin_unlock_irq(&recv_cq->lock);
 953         }
 954 }
 955
 956 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
 957 {
 958         return to_mpd(qp->ibqp.pd);
 959 }
 960
 961 static void get_cqs(struct mlx5_ib_qp *qp,
 962                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
 963 {
 964         switch (qp->ibqp.qp_type) {
 965         case IB_QPT_XRC_TGT:
 966                 *send_cq = NULL;
 967                 *recv_cq = NULL;
 968                 break;
 969         case MLX5_IB_QPT_REG_UMR:
 970         case IB_QPT_XRC_INI:
 971                 *send_cq = to_mcq(qp->ibqp.send_cq);
 972                 *recv_cq = NULL;
 973                 break;
 974
 975         case IB_QPT_SMI:
 976         case IB_QPT_GSI:
 977         case IB_QPT_RC:
 978         case IB_QPT_UC:
 979         case IB_QPT_UD:
 980         case IB_QPT_RAW_IPV6:
 981         case IB_QPT_RAW_ETHERTYPE:
 982                 *send_cq = to_mcq(qp->ibqp.send_cq);
 983                 *recv_cq = to_mcq(qp->ibqp.recv_cq);
 984                 break;
 985
 986         case IB_QPT_RAW_PACKET:
 987         case IB_QPT_MAX:
 988         default:
 989                 *send_cq = NULL;
 990                 *recv_cq = NULL;
 991                 break;
 992         }
 993 }
 994
 995 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
 996 {
 997         struct mlx5_ib_cq *send_cq, *recv_cq;
 998         struct mlx5_modify_qp_mbox_in *in;
 999         int err;
1000
1001         in = kzalloc(sizeof(*in), GFP_KERNEL);
1002         if (!in)
1003                 return;
1004         if (qp->state != IB_QPS_RESET)
1005                 if (mlx5_core_qp_modify(&dev->mdev, to_mlx5_state(qp->state),
1006                                         MLX5_QP_STATE_RST, in, sizeof(*in), &qp->mqp))
1007                         mlx5_ib_warn(dev, "mlx5_ib: modify QP %06x to RESET failed\n",
1008                                      qp->mqp.qpn);
1009
1010         get_cqs(qp, &send_cq, &recv_cq);
1011
1012         if (qp->create_type == MLX5_QP_KERNEL) {
1013                 mlx5_ib_lock_cqs(send_cq, recv_cq);
1014                 __mlx5_ib_cq_clean(recv_cq, qp->mqp.qpn,
1015                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1016                 if (send_cq != recv_cq)
1017                         __mlx5_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1018                 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1019         }
1020
1021         err = mlx5_core_destroy_qp(&dev->mdev, &qp->mqp);
1022         if (err)
1023                 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", qp->mqp.qpn);
1024         kfree(in);
1025
1026
1027         if (qp->create_type == MLX5_QP_KERNEL)
1028                 destroy_qp_kernel(dev, qp);
1029         else if (qp->create_type == MLX5_QP_USER)
1030                 destroy_qp_user(&get_pd(qp)->ibpd, qp);
1031 }
1032
1033 static const char *ib_qp_type_str(enum ib_qp_type type)
1034 {
1035         switch (type) {
1036         case IB_QPT_SMI:
1037                 return "IB_QPT_SMI";
1038         case IB_QPT_GSI:
1039                 return "IB_QPT_GSI";
1040         case IB_QPT_RC:
1041                 return "IB_QPT_RC";
1042         case IB_QPT_UC:
1043                 return "IB_QPT_UC";
1044         case IB_QPT_UD:
1045                 return "IB_QPT_UD";
1046         case IB_QPT_RAW_IPV6:
1047                 return "IB_QPT_RAW_IPV6";
1048         case IB_QPT_RAW_ETHERTYPE:
1049                 return "IB_QPT_RAW_ETHERTYPE";
1050         case IB_QPT_XRC_INI:
1051                 return "IB_QPT_XRC_INI";
1052         case IB_QPT_XRC_TGT:
1053                 return "IB_QPT_XRC_TGT";
1054         case IB_QPT_RAW_PACKET:
1055                 return "IB_QPT_RAW_PACKET";
1056         case MLX5_IB_QPT_REG_UMR:
1057                 return "MLX5_IB_QPT_REG_UMR";
1058         case IB_QPT_MAX:
1059         default:
1060                 return "Invalid QP type";
1061         }
1062 }
1063
1064 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1065                                 struct ib_qp_init_attr *init_attr,
1066                                 struct ib_udata *udata)
1067 {
1068         struct mlx5_ib_dev *dev;
1069         struct mlx5_ib_qp *qp;
1070         u16 xrcdn = 0;
1071         int err;
1072
1073         if (pd) {
1074                 dev = to_mdev(pd->device);
1075         } else {
1076                 /* being cautious here */
1077                 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
1078                     init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
1079                         pr_warn("%s: no PD for transport %s\n", __func__,
1080                                 ib_qp_type_str(init_attr->qp_type));
1081                         return ERR_PTR(-EINVAL);
1082                 }
1083                 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
1084         }
1085
1086         switch (init_attr->qp_type) {
1087         case IB_QPT_XRC_TGT:
1088         case IB_QPT_XRC_INI:
1089                 if (!(dev->mdev.caps.flags & MLX5_DEV_CAP_FLAG_XRC)) {
1090                         mlx5_ib_dbg(dev, "XRC not supported\n");
1091                         return ERR_PTR(-ENOSYS);
1092                 }
1093                 init_attr->recv_cq = NULL;
1094                 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
1095                         xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1096                         init_attr->send_cq = NULL;
1097                 }
1098
1099                 /* fall through */
1100         case IB_QPT_RC:
1101         case IB_QPT_UC:
1102         case IB_QPT_UD:
1103         case IB_QPT_SMI:
1104         case IB_QPT_GSI:
1105         case MLX5_IB_QPT_REG_UMR:
1106                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1107                 if (!qp)
1108                         return ERR_PTR(-ENOMEM);
1109
1110                 err = create_qp_common(dev, pd, init_attr, udata, qp);
1111                 if (err) {
1112                         mlx5_ib_dbg(dev, "create_qp_common failed\n");
1113                         kfree(qp);
1114                         return ERR_PTR(err);
1115                 }
1116
1117                 if (is_qp0(init_attr->qp_type))
1118                         qp->ibqp.qp_num = 0;
1119                 else if (is_qp1(init_attr->qp_type))
1120                         qp->ibqp.qp_num = 1;
1121                 else
1122                         qp->ibqp.qp_num = qp->mqp.qpn;
1123
1124                 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
1125                             qp->ibqp.qp_num, qp->mqp.qpn, to_mcq(init_attr->recv_cq)->mcq.cqn,
1126                             to_mcq(init_attr->send_cq)->mcq.cqn);
1127
1128                 qp->xrcdn = xrcdn;
1129
1130                 break;
1131
1132         case IB_QPT_RAW_IPV6:
1133         case IB_QPT_RAW_ETHERTYPE:
1134         case IB_QPT_RAW_PACKET:
1135         case IB_QPT_MAX:
1136         default:
1137                 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
1138                             init_attr->qp_type);
1139                 /* Don't support raw QPs */
1140                 return ERR_PTR(-EINVAL);
1141         }
1142
1143         return &qp->ibqp;
1144 }
1145
1146 int mlx5_ib_destroy_qp(struct ib_qp *qp)
1147 {
1148         struct mlx5_ib_dev *dev = to_mdev(qp->device);
1149         struct mlx5_ib_qp *mqp = to_mqp(qp);
1150
1151         destroy_qp_common(dev, mqp);
1152
1153         kfree(mqp);
1154
1155         return 0;
1156 }
1157
1158 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
1159                                    int attr_mask)
1160 {
1161         u32 hw_access_flags = 0;
1162         u8 dest_rd_atomic;
1163         u32 access_flags;
1164
1165         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1166                 dest_rd_atomic = attr->max_dest_rd_atomic;
1167         else
1168                 dest_rd_atomic = qp->resp_depth;
1169
1170         if (attr_mask & IB_QP_ACCESS_FLAGS)
1171                 access_flags = attr->qp_access_flags;
1172         else
1173                 access_flags = qp->atomic_rd_en;
1174
1175         if (!dest_rd_atomic)
1176                 access_flags &= IB_ACCESS_REMOTE_WRITE;
1177
1178         if (access_flags & IB_ACCESS_REMOTE_READ)
1179                 hw_access_flags |= MLX5_QP_BIT_RRE;
1180         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1181                 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
1182         if (access_flags & IB_ACCESS_REMOTE_WRITE)
1183                 hw_access_flags |= MLX5_QP_BIT_RWE;
1184
1185         return cpu_to_be32(hw_access_flags);
1186 }
1187
1188 enum {
1189         MLX5_PATH_FLAG_FL       = 1 << 0,
1190         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
1191         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
1192 };
1193
1194 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
1195 {
1196         if (rate == IB_RATE_PORT_CURRENT) {
1197                 return 0;
1198         } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
1199                 return -EINVAL;
1200         } else {
1201                 while (rate != IB_RATE_2_5_GBPS &&
1202                        !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
1203                          dev->mdev.caps.stat_rate_support))
1204                         --rate;
1205         }
1206
1207         return rate + MLX5_STAT_RATE_OFFSET;
1208 }
1209
1210 static int mlx5_set_path(struct mlx5_ib_dev *dev, const struct ib_ah_attr *ah,
1211                          struct mlx5_qp_path *path, u8 port, int attr_mask,
1212                          u32 path_flags, const struct ib_qp_attr *attr)
1213 {
1214         int err;
1215
1216         path->fl = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
1217         path->free_ar = (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x80 : 0;
1218
1219         if (attr_mask & IB_QP_PKEY_INDEX)
1220                 path->pkey_index = attr->pkey_index;
1221
1222         path->grh_mlid  = ah->src_path_bits & 0x7f;
1223         path->rlid      = cpu_to_be16(ah->dlid);
1224
1225         if (ah->ah_flags & IB_AH_GRH) {
1226                 path->grh_mlid |= 1 << 7;
1227                 path->mgid_index = ah->grh.sgid_index;
1228                 path->hop_limit  = ah->grh.hop_limit;
1229                 path->tclass_flowlabel =
1230                         cpu_to_be32((ah->grh.traffic_class << 20) |
1231                                     (ah->grh.flow_label));
1232                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1233         }
1234
1235         err = ib_rate_to_mlx5(dev, ah->static_rate);
1236         if (err < 0)
1237                 return err;
1238         path->static_rate = err;
1239         path->port = port;
1240
1241         if (ah->ah_flags & IB_AH_GRH) {
1242                 if (ah->grh.sgid_index >= dev->mdev.caps.port[port - 1].gid_table_len) {
1243                         pr_err(KERN_ERR "sgid_index (%u) too large. max is %d\n",
1244                                ah->grh.sgid_index, dev->mdev.caps.port[port - 1].gid_table_len);
1245                         return -EINVAL;
1246                 }
1247
1248                 path->grh_mlid |= 1 << 7;
1249                 path->mgid_index = ah->grh.sgid_index;
1250                 path->hop_limit  = ah->grh.hop_limit;
1251                 path->tclass_flowlabel =
1252                         cpu_to_be32((ah->grh.traffic_class << 20) |
1253                                     (ah->grh.flow_label));
1254                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1255         }
1256
1257         if (attr_mask & IB_QP_TIMEOUT)
1258                 path->ackto_lt = attr->timeout << 3;
1259
1260         path->sl = ah->sl & 0xf;
1261
1262         return 0;
1263 }
1264
1265 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
1266         [MLX5_QP_STATE_INIT] = {
1267                 [MLX5_QP_STATE_INIT] = {
1268                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
1269                                           MLX5_QP_OPTPAR_RAE            |
1270                                           MLX5_QP_OPTPAR_RWE            |
1271                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
1272                                           MLX5_QP_OPTPAR_PRI_PORT,
1273                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
1274                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
1275                                           MLX5_QP_OPTPAR_PRI_PORT,
1276                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
1277                                           MLX5_QP_OPTPAR_Q_KEY          |
1278                                           MLX5_QP_OPTPAR_PRI_PORT,
1279                 },
1280                 [MLX5_QP_STATE_RTR] = {
1281                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
1282                                           MLX5_QP_OPTPAR_RRE            |
1283                                           MLX5_QP_OPTPAR_RAE            |
1284                                           MLX5_QP_OPTPAR_RWE            |
1285                                           MLX5_QP_OPTPAR_PKEY_INDEX,
1286                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
1287                                           MLX5_QP_OPTPAR_RWE            |
1288                                           MLX5_QP_OPTPAR_PKEY_INDEX,
1289                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
1290                                           MLX5_QP_OPTPAR_Q_KEY,
1291                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
1292                                            MLX5_QP_OPTPAR_Q_KEY,
1293                 },
1294         },
1295         [MLX5_QP_STATE_RTR] = {
1296                 [MLX5_QP_STATE_RTS] = {
1297                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
1298                                           MLX5_QP_OPTPAR_RRE            |
1299                                           MLX5_QP_OPTPAR_RAE            |
1300                                           MLX5_QP_OPTPAR_RWE            |
1301                                           MLX5_QP_OPTPAR_PM_STATE       |
1302                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
1303                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
1304                                           MLX5_QP_OPTPAR_RWE            |
1305                                           MLX5_QP_OPTPAR_PM_STATE,
1306                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
1307                 },
1308         },
1309         [MLX5_QP_STATE_RTS] = {
1310                 [MLX5_QP_STATE_RTS] = {
1311                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
1312                                           MLX5_QP_OPTPAR_RAE            |
1313                                           MLX5_QP_OPTPAR_RWE            |
1314                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
1315                                           MLX5_QP_OPTPAR_PM_STATE,
1316                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
1317                                           MLX5_QP_OPTPAR_PM_STATE,
1318                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
1319                                           MLX5_QP_OPTPAR_SRQN           |
1320                                           MLX5_QP_OPTPAR_CQN_RCV,
1321                 },
1322         },
1323         [MLX5_QP_STATE_SQER] = {
1324                 [MLX5_QP_STATE_RTS] = {
1325                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
1326                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
1327                 },
1328         },
1329 };
1330
1331 static int ib_nr_to_mlx5_nr(int ib_mask)
1332 {
1333         switch (ib_mask) {
1334         case IB_QP_STATE:
1335                 return 0;
1336         case IB_QP_CUR_STATE:
1337                 return 0;
1338         case IB_QP_EN_SQD_ASYNC_NOTIFY:
1339                 return 0;
1340         case IB_QP_ACCESS_FLAGS:
1341                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
1342                         MLX5_QP_OPTPAR_RAE;
1343         case IB_QP_PKEY_INDEX:
1344                 return MLX5_QP_OPTPAR_PKEY_INDEX;
1345         case IB_QP_PORT:
1346                 return MLX5_QP_OPTPAR_PRI_PORT;
1347         case IB_QP_QKEY:
1348                 return MLX5_QP_OPTPAR_Q_KEY;
1349         case IB_QP_AV:
1350                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
1351                         MLX5_QP_OPTPAR_PRI_PORT;
1352         case IB_QP_PATH_MTU:
1353                 return 0;
1354         case IB_QP_TIMEOUT:
1355                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
1356         case IB_QP_RETRY_CNT:
1357                 return MLX5_QP_OPTPAR_RETRY_COUNT;
1358         case IB_QP_RNR_RETRY:
1359                 return MLX5_QP_OPTPAR_RNR_RETRY;
1360         case IB_QP_RQ_PSN:
1361                 return 0;
1362         case IB_QP_MAX_QP_RD_ATOMIC:
1363                 return MLX5_QP_OPTPAR_SRA_MAX;
1364         case IB_QP_ALT_PATH:
1365                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
1366         case IB_QP_MIN_RNR_TIMER:
1367                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
1368         case IB_QP_SQ_PSN:
1369                 return 0;
1370         case IB_QP_MAX_DEST_RD_ATOMIC:
1371                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
1372                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
1373         case IB_QP_PATH_MIG_STATE:
1374                 return MLX5_QP_OPTPAR_PM_STATE;
1375         case IB_QP_CAP:
1376                 return 0;
1377         case IB_QP_DEST_QPN:
1378                 return 0;
1379         }
1380         return 0;
1381 }
1382
1383 static int ib_mask_to_mlx5_opt(int ib_mask)
1384 {
1385         int result = 0;
1386         int i;
1387
1388         for (i = 0; i < 8 * sizeof(int); i++) {
1389                 if ((1 << i) & ib_mask)
1390                         result |= ib_nr_to_mlx5_nr(1 << i);
1391         }
1392
1393         return result;
1394 }
1395
1396 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
1397                                const struct ib_qp_attr *attr, int attr_mask,
1398                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
1399 {
1400         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1401         struct mlx5_ib_qp *qp = to_mqp(ibqp);
1402         struct mlx5_ib_cq *send_cq, *recv_cq;
1403         struct mlx5_qp_context *context;
1404         struct mlx5_modify_qp_mbox_in *in;
1405         struct mlx5_ib_pd *pd;
1406         enum mlx5_qp_state mlx5_cur, mlx5_new;
1407         enum mlx5_qp_optpar optpar;
1408         int sqd_event;
1409         int mlx5_st;
1410         int err;
1411
1412         in = kzalloc(sizeof(*in), GFP_KERNEL);
1413         if (!in)
1414                 return -ENOMEM;
1415
1416         context = &in->ctx;
1417         err = to_mlx5_st(ibqp->qp_type);
1418         if (err < 0)
1419                 goto out;
1420
1421         context->flags = cpu_to_be32(err << 16);
1422
1423         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
1424                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
1425         } else {
1426                 switch (attr->path_mig_state) {
1427                 case IB_MIG_MIGRATED:
1428                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
1429                         break;
1430                 case IB_MIG_REARM:
1431                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
1432                         break;
1433                 case IB_MIG_ARMED:
1434                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
1435                         break;
1436                 }
1437         }
1438
1439         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) {
1440                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
1441         } else if (ibqp->qp_type == IB_QPT_UD ||
1442                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
1443                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
1444         } else if (attr_mask & IB_QP_PATH_MTU) {
1445                 if (attr->path_mtu < IB_MTU_256 ||
1446                     attr->path_mtu > IB_MTU_4096) {
1447                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
1448                         err = -EINVAL;
1449                         goto out;
1450                 }
1451                 context->mtu_msgmax = (attr->path_mtu << 5) | dev->mdev.caps.log_max_msg;
1452         }
1453
1454         if (attr_mask & IB_QP_DEST_QPN)
1455                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
1456
1457         if (attr_mask & IB_QP_PKEY_INDEX)
1458                 context->pri_path.pkey_index = attr->pkey_index;
1459
1460         /* todo implement counter_index functionality */
1461
1462         if (is_sqp(ibqp->qp_type))
1463                 context->pri_path.port = qp->port;
1464
1465         if (attr_mask & IB_QP_PORT)
1466                 context->pri_path.port = attr->port_num;
1467
1468         if (attr_mask & IB_QP_AV) {
1469                 err = mlx5_set_path(dev, &attr->ah_attr, &context->pri_path,
1470                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
1471                                     attr_mask, 0, attr);
1472                 if (err)
1473                         goto out;
1474         }
1475
1476         if (attr_mask & IB_QP_TIMEOUT)
1477                 context->pri_path.ackto_lt |= attr->timeout << 3;
1478
1479         if (attr_mask & IB_QP_ALT_PATH) {
1480                 err = mlx5_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
1481                                     attr->alt_port_num, attr_mask, 0, attr);
1482                 if (err)
1483                         goto out;
1484         }
1485
1486         pd = get_pd(qp);
1487         get_cqs(qp, &send_cq, &recv_cq);
1488
1489         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
1490         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
1491         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
1492         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
1493
1494         if (attr_mask & IB_QP_RNR_RETRY)
1495                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1496
1497         if (attr_mask & IB_QP_RETRY_CNT)
1498                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1499
1500         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1501                 if (attr->max_rd_atomic)
1502                         context->params1 |=
1503                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1504         }
1505
1506         if (attr_mask & IB_QP_SQ_PSN)
1507                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1508
1509         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1510                 if (attr->max_dest_rd_atomic)
1511                         context->params2 |=
1512                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1513         }
1514
1515         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
1516                 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
1517
1518         if (attr_mask & IB_QP_MIN_RNR_TIMER)
1519                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1520
1521         if (attr_mask & IB_QP_RQ_PSN)
1522                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1523
1524         if (attr_mask & IB_QP_QKEY)
1525                 context->qkey = cpu_to_be32(attr->qkey);
1526
1527         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1528                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1529
1530         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
1531             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1532                 sqd_event = 1;
1533         else
1534                 sqd_event = 0;
1535
1536         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1537                 context->sq_crq_size |= cpu_to_be16(1 << 4);
1538
1539
1540         mlx5_cur = to_mlx5_state(cur_state);
1541         mlx5_new = to_mlx5_state(new_state);
1542         mlx5_st = to_mlx5_st(ibqp->qp_type);
1543         if (mlx5_cur < 0 || mlx5_new < 0 || mlx5_st < 0)
1544                 goto out;
1545
1546         optpar = ib_mask_to_mlx5_opt(attr_mask);
1547         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
1548         in->optparam = cpu_to_be32(optpar);
1549         err = mlx5_core_qp_modify(&dev->mdev, to_mlx5_state(cur_state),
1550                                   to_mlx5_state(new_state), in, sqd_event,
1551                                   &qp->mqp);
1552         if (err)
1553                 goto out;
1554
1555         qp->state = new_state;
1556
1557         if (attr_mask & IB_QP_ACCESS_FLAGS)
1558                 qp->atomic_rd_en = attr->qp_access_flags;
1559         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1560                 qp->resp_depth = attr->max_dest_rd_atomic;
1561         if (attr_mask & IB_QP_PORT)
1562                 qp->port = attr->port_num;
1563         if (attr_mask & IB_QP_ALT_PATH)
1564                 qp->alt_port = attr->alt_port_num;
1565
1566         /*
1567          * If we moved a kernel QP to RESET, clean up all old CQ
1568          * entries and reinitialize the QP.
1569          */
1570         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
1571                 mlx5_ib_cq_clean(recv_cq, qp->mqp.qpn,
1572                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1573                 if (send_cq != recv_cq)
1574                         mlx5_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1575
1576                 qp->rq.head = 0;
1577                 qp->rq.tail = 0;
1578                 qp->sq.head = 0;
1579                 qp->sq.tail = 0;
1580                 qp->sq.cur_post = 0;
1581                 qp->sq.last_poll = 0;
1582                 qp->db.db[MLX5_RCV_DBR] = 0;
1583                 qp->db.db[MLX5_SND_DBR] = 0;
1584         }
1585
1586 out:
1587         kfree(in);
1588         return err;
1589 }
1590
1591 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1592                       int attr_mask, struct ib_udata *udata)
1593 {
1594         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1595         struct mlx5_ib_qp *qp = to_mqp(ibqp);
1596         enum ib_qp_state cur_state, new_state;
1597         int err = -EINVAL;
1598         int port;
1599
1600         mutex_lock(&qp->mutex);
1601
1602         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1603         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1604
1605         if (ibqp->qp_type != MLX5_IB_QPT_REG_UMR &&
1606             !ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask))
1607                 goto out;
1608
1609         if ((attr_mask & IB_QP_PORT) &&
1610             (attr->port_num == 0 || attr->port_num > dev->mdev.caps.num_ports))
1611                 goto out;
1612
1613         if (attr_mask & IB_QP_PKEY_INDEX) {
1614                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1615                 if (attr->pkey_index >= dev->mdev.caps.port[port - 1].pkey_table_len)
1616                         goto out;
1617         }
1618
1619         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1620             attr->max_rd_atomic > dev->mdev.caps.max_ra_res_qp)
1621                 goto out;
1622
1623         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1624             attr->max_dest_rd_atomic > dev->mdev.caps.max_ra_req_qp)
1625                 goto out;
1626
1627         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1628                 err = 0;
1629                 goto out;
1630         }
1631
1632         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1633
1634 out:
1635         mutex_unlock(&qp->mutex);
1636         return err;
1637 }
1638
1639 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1640 {
1641         struct mlx5_ib_cq *cq;
1642         unsigned cur;
1643
1644         cur = wq->head - wq->tail;
1645         if (likely(cur + nreq < wq->max_post))
1646                 return 0;
1647
1648         cq = to_mcq(ib_cq);
1649         spin_lock(&cq->lock);
1650         cur = wq->head - wq->tail;
1651         spin_unlock(&cq->lock);
1652
1653         return cur + nreq >= wq->max_post;
1654 }
1655
1656 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
1657                                           u64 remote_addr, u32 rkey)
1658 {
1659         rseg->raddr    = cpu_to_be64(remote_addr);
1660         rseg->rkey     = cpu_to_be32(rkey);
1661         rseg->reserved = 0;
1662 }
1663
1664 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
1665                              struct ib_send_wr *wr)
1666 {
1667         memcpy(&dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof(struct mlx5_av));
1668         dseg->av.dqp_dct = cpu_to_be32(wr->wr.ud.remote_qpn | MLX5_EXTENDED_UD_AV);
1669         dseg->av.key.qkey.qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
1670 }
1671
1672 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
1673 {
1674         dseg->byte_count = cpu_to_be32(sg->length);
1675         dseg->lkey       = cpu_to_be32(sg->lkey);
1676         dseg->addr       = cpu_to_be64(sg->addr);
1677 }
1678
1679 static __be16 get_klm_octo(int npages)
1680 {
1681         return cpu_to_be16(ALIGN(npages, 8) / 2);
1682 }
1683
1684 static __be64 frwr_mkey_mask(void)
1685 {
1686         u64 result;
1687
1688         result = MLX5_MKEY_MASK_LEN             |
1689                 MLX5_MKEY_MASK_PAGE_SIZE        |
1690                 MLX5_MKEY_MASK_START_ADDR       |
1691                 MLX5_MKEY_MASK_EN_RINVAL        |
1692                 MLX5_MKEY_MASK_KEY              |
1693                 MLX5_MKEY_MASK_LR               |
1694                 MLX5_MKEY_MASK_LW               |
1695                 MLX5_MKEY_MASK_RR               |
1696                 MLX5_MKEY_MASK_RW               |
1697                 MLX5_MKEY_MASK_A                |
1698                 MLX5_MKEY_MASK_SMALL_FENCE      |
1699                 MLX5_MKEY_MASK_FREE;
1700
1701         return cpu_to_be64(result);
1702 }
1703
1704 static void set_frwr_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
1705                                  struct ib_send_wr *wr, int li)
1706 {
1707         memset(umr, 0, sizeof(*umr));
1708
1709         if (li) {
1710                 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
1711                 umr->flags = 1 << 7;
1712                 return;
1713         }
1714
1715         umr->flags = (1 << 5); /* fail if not free */
1716         umr->klm_octowords = get_klm_octo(wr->wr.fast_reg.page_list_len);
1717         umr->mkey_mask = frwr_mkey_mask();
1718 }
1719
1720 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
1721                                 struct ib_send_wr *wr)
1722 {
1723         struct umr_wr *umrwr = (struct umr_wr *)&wr->wr.fast_reg;
1724         u64 mask;
1725
1726         memset(umr, 0, sizeof(*umr));
1727
1728         if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
1729                 umr->flags = 1 << 5; /* fail if not free */
1730                 umr->klm_octowords = get_klm_octo(umrwr->npages);
1731                 mask =  MLX5_MKEY_MASK_LEN              |
1732                         MLX5_MKEY_MASK_PAGE_SIZE        |
1733                         MLX5_MKEY_MASK_START_ADDR       |
1734                         MLX5_MKEY_MASK_PD               |
1735                         MLX5_MKEY_MASK_LR               |
1736                         MLX5_MKEY_MASK_LW               |
1737                         MLX5_MKEY_MASK_RR               |
1738                         MLX5_MKEY_MASK_RW               |
1739                         MLX5_MKEY_MASK_A                |
1740                         MLX5_MKEY_MASK_FREE;
1741                 umr->mkey_mask = cpu_to_be64(mask);
1742         } else {
1743                 umr->flags = 2 << 5; /* fail if free */
1744                 mask = MLX5_MKEY_MASK_FREE;
1745                 umr->mkey_mask = cpu_to_be64(mask);
1746         }
1747
1748         if (!wr->num_sge)
1749                 umr->flags |= (1 << 7); /* inline */
1750 }
1751
1752 static u8 get_umr_flags(int acc)
1753 {
1754         return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
1755                (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
1756                (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
1757                (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
1758                 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN | MLX5_ACCESS_MODE_MTT;
1759 }
1760
1761 static void set_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr,
1762                              int li, int *writ)
1763 {
1764         memset(seg, 0, sizeof(*seg));
1765         if (li) {
1766                 seg->status = 1 << 6;
1767                 return;
1768         }
1769
1770         seg->flags = get_umr_flags(wr->wr.fast_reg.access_flags);
1771         *writ = seg->flags & (MLX5_PERM_LOCAL_WRITE | IB_ACCESS_REMOTE_WRITE);
1772         seg->qpn_mkey7_0 = cpu_to_be32((wr->wr.fast_reg.rkey & 0xff) | 0xffffff00);
1773         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
1774         seg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start);
1775         seg->len = cpu_to_be64(wr->wr.fast_reg.length);
1776         seg->xlt_oct_size = cpu_to_be32((wr->wr.fast_reg.page_list_len + 1) / 2);
1777         seg->log2_page_size = wr->wr.fast_reg.page_shift;
1778 }
1779
1780 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
1781 {
1782         memset(seg, 0, sizeof(*seg));
1783         if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
1784                 seg->status = 1 << 6;
1785                 return;
1786         }
1787
1788         seg->flags = convert_access(wr->wr.fast_reg.access_flags);
1789         seg->flags_pd = cpu_to_be32(to_mpd((struct ib_pd *)wr->wr.fast_reg.page_list)->pdn);
1790         seg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start);
1791         seg->len = cpu_to_be64(wr->wr.fast_reg.length);
1792         seg->log2_page_size = wr->wr.fast_reg.page_shift;
1793         seg->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
1794 }
1795
1796 static void set_frwr_pages(struct mlx5_wqe_data_seg *dseg,
1797                            struct ib_send_wr *wr,
1798                            struct mlx5_core_dev *mdev,
1799                            struct mlx5_ib_pd *pd,
1800                            int writ)
1801 {
1802         struct mlx5_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
1803         u64 *page_list = wr->wr.fast_reg.page_list->page_list;
1804         u64 perm = MLX5_EN_RD | (writ ? MLX5_EN_WR : 0);
1805         int i;
1806
1807         for (i = 0; i < wr->wr.fast_reg.page_list_len; i++)
1808                 mfrpl->mapped_page_list[i] = cpu_to_be64(page_list[i] | perm);
1809         dseg->addr = cpu_to_be64(mfrpl->map);
1810         dseg->byte_count = cpu_to_be32(ALIGN(sizeof(u64) * wr->wr.fast_reg.page_list_len, 64));
1811         dseg->lkey = cpu_to_be32(pd->pa_lkey);
1812 }
1813
1814 static __be32 send_ieth(struct ib_send_wr *wr)
1815 {
1816         switch (wr->opcode) {
1817         case IB_WR_SEND_WITH_IMM:
1818         case IB_WR_RDMA_WRITE_WITH_IMM:
1819                 return wr->ex.imm_data;
1820
1821         case IB_WR_SEND_WITH_INV:
1822                 return cpu_to_be32(wr->ex.invalidate_rkey);
1823
1824         default:
1825                 return 0;
1826         }
1827 }
1828
1829 static u8 calc_sig(void *wqe, int size)
1830 {
1831         u8 *p = wqe;
1832         u8 res = 0;
1833         int i;
1834
1835         for (i = 0; i < size; i++)
1836                 res ^= p[i];
1837
1838         return ~res;
1839 }
1840
1841 static u8 wq_sig(void *wqe)
1842 {
1843         return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
1844 }
1845
1846 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
1847                             void *wqe, int *sz)
1848 {
1849         struct mlx5_wqe_inline_seg *seg;
1850         void *qend = qp->sq.qend;
1851         void *addr;
1852         int inl = 0;
1853         int copy;
1854         int len;
1855         int i;
1856
1857         seg = wqe;
1858         wqe += sizeof(*seg);
1859         for (i = 0; i < wr->num_sge; i++) {
1860                 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
1861                 len  = wr->sg_list[i].length;
1862                 inl += len;
1863
1864                 if (unlikely(inl > qp->max_inline_data))
1865                         return -ENOMEM;
1866
1867                 if (unlikely(wqe + len > qend)) {
1868                         copy = qend - wqe;
1869                         memcpy(wqe, addr, copy);
1870                         addr += copy;
1871                         len -= copy;
1872                         wqe = mlx5_get_send_wqe(qp, 0);
1873                 }
1874                 memcpy(wqe, addr, len);
1875                 wqe += len;
1876         }
1877
1878         seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
1879
1880         *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
1881
1882         return 0;
1883 }
1884
1885 static int set_frwr_li_wr(void **seg, struct ib_send_wr *wr, int *size,
1886                           struct mlx5_core_dev *mdev, struct mlx5_ib_pd *pd, struct mlx5_ib_qp *qp)
1887 {
1888         int writ = 0;
1889         int li;
1890
1891         li = wr->opcode == IB_WR_LOCAL_INV ? 1 : 0;
1892         if (unlikely(wr->send_flags & IB_SEND_INLINE))
1893                 return -EINVAL;
1894
1895         set_frwr_umr_segment(*seg, wr, li);
1896         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
1897         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
1898         if (unlikely((*seg == qp->sq.qend)))
1899                 *seg = mlx5_get_send_wqe(qp, 0);
1900         set_mkey_segment(*seg, wr, li, &writ);
1901         *seg += sizeof(struct mlx5_mkey_seg);
1902         *size += sizeof(struct mlx5_mkey_seg) / 16;
1903         if (unlikely((*seg == qp->sq.qend)))
1904                 *seg = mlx5_get_send_wqe(qp, 0);
1905         if (!li) {
1906                 set_frwr_pages(*seg, wr, mdev, pd, writ);
1907                 *seg += sizeof(struct mlx5_wqe_data_seg);
1908                 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
1909         }
1910         return 0;
1911 }
1912
1913 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
1914 {
1915         __be32 *p = NULL;
1916         int tidx = idx;
1917         int i, j;
1918
1919         pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
1920         for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
1921                 if ((i & 0xf) == 0) {
1922                         void *buf = mlx5_get_send_wqe(qp, tidx);
1923                         tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
1924                         p = buf;
1925                         j = 0;
1926                 }
1927                 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
1928                          be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
1929                          be32_to_cpu(p[j + 3]));
1930         }
1931 }
1932
1933 static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
1934                          unsigned bytecnt, struct mlx5_ib_qp *qp)
1935 {
1936         while (bytecnt > 0) {
1937                 __iowrite64_copy(dst++, src++, 8);
1938                 __iowrite64_copy(dst++, src++, 8);
1939                 __iowrite64_copy(dst++, src++, 8);
1940                 __iowrite64_copy(dst++, src++, 8);
1941                 __iowrite64_copy(dst++, src++, 8);
1942                 __iowrite64_copy(dst++, src++, 8);
1943                 __iowrite64_copy(dst++, src++, 8);
1944                 __iowrite64_copy(dst++, src++, 8);
1945                 bytecnt -= 64;
1946                 if (unlikely(src == qp->sq.qend))
1947                         src = mlx5_get_send_wqe(qp, 0);
1948         }
1949 }
1950
1951 static u8 get_fence(u8 fence, struct ib_send_wr *wr)
1952 {
1953         if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
1954                      wr->send_flags & IB_SEND_FENCE))
1955                 return MLX5_FENCE_MODE_STRONG_ORDERING;
1956
1957         if (unlikely(fence)) {
1958                 if (wr->send_flags & IB_SEND_FENCE)
1959                         return MLX5_FENCE_MODE_SMALL_AND_FENCE;
1960                 else
1961                         return fence;
1962
1963         } else {
1964                 return 0;
1965         }
1966 }
1967
1968 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1969                       struct ib_send_wr **bad_wr)
1970 {
1971         struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
1972         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1973         struct mlx5_core_dev *mdev = &dev->mdev;
1974         struct mlx5_ib_qp *qp = to_mqp(ibqp);
1975         struct mlx5_wqe_data_seg *dpseg;
1976         struct mlx5_wqe_xrc_seg *xrc;
1977         struct mlx5_bf *bf = qp->bf;
1978         int uninitialized_var(size);
1979         void *qend = qp->sq.qend;
1980         unsigned long flags;
1981         u32 mlx5_opcode;
1982         unsigned idx;
1983         int err = 0;
1984         int inl = 0;
1985         int num_sge;
1986         void *seg;
1987         int nreq;
1988         int i;
1989         u8 next_fence = 0;
1990         u8 opmod = 0;
1991         u8 fence;
1992
1993         spin_lock_irqsave(&qp->sq.lock, flags);
1994
1995         for (nreq = 0; wr; nreq++, wr = wr->next) {
1996                 if (unlikely(wr->opcode >= sizeof(mlx5_ib_opcode) / sizeof(mlx5_ib_opcode[0]))) {
1997                         mlx5_ib_warn(dev, "\n");
1998                         err = -EINVAL;
1999                         *bad_wr = wr;
2000                         goto out;
2001                 }
2002
2003                 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) {
2004                         mlx5_ib_warn(dev, "\n");
2005                         err = -ENOMEM;
2006                         *bad_wr = wr;
2007                         goto out;
2008                 }
2009
2010                 fence = qp->fm_cache;
2011                 num_sge = wr->num_sge;
2012                 if (unlikely(num_sge > qp->sq.max_gs)) {
2013                         mlx5_ib_warn(dev, "\n");
2014                         err = -ENOMEM;
2015                         *bad_wr = wr;
2016                         goto out;
2017                 }
2018
2019                 idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
2020                 seg = mlx5_get_send_wqe(qp, idx);
2021                 ctrl = seg;
2022                 *(uint32_t *)(seg + 8) = 0;
2023                 ctrl->imm = send_ieth(wr);
2024                 ctrl->fm_ce_se = qp->sq_signal_bits |
2025                         (wr->send_flags & IB_SEND_SIGNALED ?
2026                          MLX5_WQE_CTRL_CQ_UPDATE : 0) |
2027                         (wr->send_flags & IB_SEND_SOLICITED ?
2028                          MLX5_WQE_CTRL_SOLICITED : 0);
2029
2030                 seg += sizeof(*ctrl);
2031                 size = sizeof(*ctrl) / 16;
2032
2033                 switch (ibqp->qp_type) {
2034                 case IB_QPT_XRC_INI:
2035                         xrc = seg;
2036                         xrc->xrc_srqn = htonl(wr->xrc_remote_srq_num);
2037                         seg += sizeof(*xrc);
2038                         size += sizeof(*xrc) / 16;
2039                         /* fall through */
2040                 case IB_QPT_RC:
2041                         switch (wr->opcode) {
2042                         case IB_WR_RDMA_READ:
2043                         case IB_WR_RDMA_WRITE:
2044                         case IB_WR_RDMA_WRITE_WITH_IMM:
2045                                 set_raddr_seg(seg, wr->wr.rdma.remote_addr,
2046                                               wr->wr.rdma.rkey);
2047                                 seg  += sizeof(struct mlx5_wqe_raddr_seg);
2048                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
2049                                 break;
2050
2051                         case IB_WR_ATOMIC_CMP_AND_SWP:
2052                         case IB_WR_ATOMIC_FETCH_AND_ADD:
2053                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
2054                                 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
2055                                 err = -ENOSYS;
2056                                 *bad_wr = wr;
2057                                 goto out;
2058
2059                         case IB_WR_LOCAL_INV:
2060                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
2061                                 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
2062                                 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
2063                                 err = set_frwr_li_wr(&seg, wr, &size, mdev, to_mpd(ibqp->pd), qp);
2064                                 if (err) {
2065                                         mlx5_ib_warn(dev, "\n");
2066                                         *bad_wr = wr;
2067                                         goto out;
2068                                 }
2069                                 num_sge = 0;
2070                                 break;
2071
2072                         case IB_WR_FAST_REG_MR:
2073                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
2074                                 qp->sq.wr_data[idx] = IB_WR_FAST_REG_MR;
2075                                 ctrl->imm = cpu_to_be32(wr->wr.fast_reg.rkey);
2076                                 err = set_frwr_li_wr(&seg, wr, &size, mdev, to_mpd(ibqp->pd), qp);
2077                                 if (err) {
2078                                         mlx5_ib_warn(dev, "\n");
2079                                         *bad_wr = wr;
2080                                         goto out;
2081                                 }
2082                                 num_sge = 0;
2083                                 break;
2084
2085                         default:
2086                                 break;
2087                         }
2088                         break;
2089
2090                 case IB_QPT_UC:
2091                         switch (wr->opcode) {
2092                         case IB_WR_RDMA_WRITE:
2093                         case IB_WR_RDMA_WRITE_WITH_IMM:
2094                                 set_raddr_seg(seg, wr->wr.rdma.remote_addr,
2095                                               wr->wr.rdma.rkey);
2096                                 seg  += sizeof(struct mlx5_wqe_raddr_seg);
2097                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
2098                                 break;
2099
2100                         default:
2101                                 break;
2102                         }
2103                         break;
2104
2105                 case IB_QPT_UD:
2106                 case IB_QPT_SMI:
2107                 case IB_QPT_GSI:
2108                         set_datagram_seg(seg, wr);
2109                         seg  += sizeof(struct mlx5_wqe_datagram_seg);
2110                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
2111                         if (unlikely((seg == qend)))
2112                                 seg = mlx5_get_send_wqe(qp, 0);
2113                         break;
2114
2115                 case MLX5_IB_QPT_REG_UMR:
2116                         if (wr->opcode != MLX5_IB_WR_UMR) {
2117                                 err = -EINVAL;
2118                                 mlx5_ib_warn(dev, "bad opcode\n");
2119                                 goto out;
2120                         }
2121                         qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
2122                         ctrl->imm = cpu_to_be32(wr->wr.fast_reg.rkey);
2123                         set_reg_umr_segment(seg, wr);
2124                         seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
2125                         size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
2126                         if (unlikely((seg == qend)))
2127                                 seg = mlx5_get_send_wqe(qp, 0);
2128                         set_reg_mkey_segment(seg, wr);
2129                         seg += sizeof(struct mlx5_mkey_seg);
2130                         size += sizeof(struct mlx5_mkey_seg) / 16;
2131                         if (unlikely((seg == qend)))
2132                                 seg = mlx5_get_send_wqe(qp, 0);
2133                         break;
2134
2135                 default:
2136                         break;
2137                 }
2138
2139                 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
2140                         int uninitialized_var(sz);
2141
2142                         err = set_data_inl_seg(qp, wr, seg, &sz);
2143                         if (unlikely(err)) {
2144                                 mlx5_ib_warn(dev, "\n");
2145                                 *bad_wr = wr;
2146                                 goto out;
2147                         }
2148                         inl = 1;
2149                         size += sz;
2150                 } else {
2151                         dpseg = seg;
2152                         for (i = 0; i < num_sge; i++) {
2153                                 if (unlikely(dpseg == qend)) {
2154                                         seg = mlx5_get_send_wqe(qp, 0);
2155                                         dpseg = seg;
2156                                 }
2157                                 if (likely(wr->sg_list[i].length)) {
2158                                         set_data_ptr_seg(dpseg, wr->sg_list + i);
2159                                         size += sizeof(struct mlx5_wqe_data_seg) / 16;
2160                                         dpseg++;
2161                                 }
2162                         }
2163                 }
2164
2165                 mlx5_opcode = mlx5_ib_opcode[wr->opcode];
2166                 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8)      |
2167                                                      mlx5_opcode                        |
2168                                                      ((u32)opmod << 24));
2169                 ctrl->qpn_ds = cpu_to_be32(size | (qp->mqp.qpn << 8));
2170                 ctrl->fm_ce_se |= get_fence(fence, wr);
2171                 qp->fm_cache = next_fence;
2172                 if (unlikely(qp->wq_sig))
2173                         ctrl->signature = wq_sig(ctrl);
2174
2175                 qp->sq.wrid[idx] = wr->wr_id;
2176                 qp->sq.w_list[idx].opcode = mlx5_opcode;
2177                 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
2178                 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
2179                 qp->sq.w_list[idx].next = qp->sq.cur_post;
2180
2181                 if (0)
2182                         dump_wqe(qp, idx, size);
2183         }
2184
2185 out:
2186         if (likely(nreq)) {
2187                 qp->sq.head += nreq;
2188
2189                 /* Make sure that descriptors are written before
2190                  * updating doorbell record and ringing the doorbell
2191                  */
2192                 wmb();
2193
2194                 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
2195
2196                 if (bf->need_lock)
2197                         spin_lock(&bf->lock);
2198
2199                 /* TBD enable WC */
2200                 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
2201                         mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
2202                         /* wc_wmb(); */
2203                 } else {
2204                         mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
2205                                      MLX5_GET_DOORBELL_LOCK(&bf->lock32));
2206                         /* Make sure doorbells don't leak out of SQ spinlock
2207                          * and reach the HCA out of order.
2208                          */
2209                         mmiowb();
2210                 }
2211                 bf->offset ^= bf->buf_size;
2212                 if (bf->need_lock)
2213                         spin_unlock(&bf->lock);
2214         }
2215
2216         spin_unlock_irqrestore(&qp->sq.lock, flags);
2217
2218         return err;
2219 }
2220
2221 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
2222 {
2223         sig->signature = calc_sig(sig, size);
2224 }
2225
2226 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2227                       struct ib_recv_wr **bad_wr)
2228 {
2229         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2230         struct mlx5_wqe_data_seg *scat;
2231         struct mlx5_rwqe_sig *sig;
2232         unsigned long flags;
2233         int err = 0;
2234         int nreq;
2235         int ind;
2236         int i;
2237
2238         spin_lock_irqsave(&qp->rq.lock, flags);
2239
2240         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
2241
2242         for (nreq = 0; wr; nreq++, wr = wr->next) {
2243                 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2244                         err = -ENOMEM;
2245                         *bad_wr = wr;
2246                         goto out;
2247                 }
2248
2249                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2250                         err = -EINVAL;
2251                         *bad_wr = wr;
2252                         goto out;
2253                 }
2254
2255                 scat = get_recv_wqe(qp, ind);
2256                 if (qp->wq_sig)
2257                         scat++;
2258
2259                 for (i = 0; i < wr->num_sge; i++)
2260                         set_data_ptr_seg(scat + i, wr->sg_list + i);
2261
2262                 if (i < qp->rq.max_gs) {
2263                         scat[i].byte_count = 0;
2264                         scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
2265                         scat[i].addr       = 0;
2266                 }
2267
2268                 if (qp->wq_sig) {
2269                         sig = (struct mlx5_rwqe_sig *)scat;
2270                         set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
2271                 }
2272
2273                 qp->rq.wrid[ind] = wr->wr_id;
2274
2275                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
2276         }
2277
2278 out:
2279         if (likely(nreq)) {
2280                 qp->rq.head += nreq;
2281
2282                 /* Make sure that descriptors are written before
2283                  * doorbell record.
2284                  */
2285                 wmb();
2286
2287                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
2288         }
2289
2290         spin_unlock_irqrestore(&qp->rq.lock, flags);
2291
2292         return err;
2293 }
2294
2295 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
2296 {
2297         switch (mlx5_state) {
2298         case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
2299         case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
2300         case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
2301         case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
2302         case MLX5_QP_STATE_SQ_DRAINING:
2303         case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
2304         case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
2305         case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
2306         default:                     return -1;
2307         }
2308 }
2309
2310 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
2311 {
2312         switch (mlx5_mig_state) {
2313         case MLX5_QP_PM_ARMED:          return IB_MIG_ARMED;
2314         case MLX5_QP_PM_REARM:          return IB_MIG_REARM;
2315         case MLX5_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
2316         default: return -1;
2317         }
2318 }
2319
2320 static int to_ib_qp_access_flags(int mlx5_flags)
2321 {
2322         int ib_flags = 0;
2323
2324         if (mlx5_flags & MLX5_QP_BIT_RRE)
2325                 ib_flags |= IB_ACCESS_REMOTE_READ;
2326         if (mlx5_flags & MLX5_QP_BIT_RWE)
2327                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
2328         if (mlx5_flags & MLX5_QP_BIT_RAE)
2329                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
2330
2331         return ib_flags;
2332 }
2333
2334 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
2335                                 struct mlx5_qp_path *path)
2336 {
2337         struct mlx5_core_dev *dev = &ibdev->mdev;
2338
2339         memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
2340         ib_ah_attr->port_num      = path->port;
2341
2342         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
2343                 return;
2344
2345         ib_ah_attr->sl = path->sl & 0xf;
2346
2347         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
2348         ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
2349         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
2350         ib_ah_attr->ah_flags      = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
2351         if (ib_ah_attr->ah_flags) {
2352                 ib_ah_attr->grh.sgid_index = path->mgid_index;
2353                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
2354                 ib_ah_attr->grh.traffic_class =
2355                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
2356                 ib_ah_attr->grh.flow_label =
2357                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
2358                 memcpy(ib_ah_attr->grh.dgid.raw,
2359                        path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
2360         }
2361 }
2362
2363 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
2364                      struct ib_qp_init_attr *qp_init_attr)
2365 {
2366         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2367         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2368         struct mlx5_query_qp_mbox_out *outb;
2369         struct mlx5_qp_context *context;
2370         int mlx5_state;
2371         int err = 0;
2372
2373         mutex_lock(&qp->mutex);
2374         outb = kzalloc(sizeof(*outb), GFP_KERNEL);
2375         if (!outb) {
2376                 err = -ENOMEM;
2377                 goto out;
2378         }
2379         context = &outb->ctx;
2380         err = mlx5_core_qp_query(&dev->mdev, &qp->mqp, outb, sizeof(*outb));
2381         if (err)
2382                 goto out_free;
2383
2384         mlx5_state = be32_to_cpu(context->flags) >> 28;
2385
2386         qp->state                    = to_ib_qp_state(mlx5_state);
2387         qp_attr->qp_state            = qp->state;
2388         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
2389         qp_attr->path_mig_state      =
2390                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
2391         qp_attr->qkey                = be32_to_cpu(context->qkey);
2392         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
2393         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
2394         qp_attr->dest_qp_num         = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
2395         qp_attr->qp_access_flags     =
2396                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
2397
2398         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
2399                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
2400                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
2401                 qp_attr->alt_pkey_index = context->alt_path.pkey_index & 0x7f;
2402                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
2403         }
2404
2405         qp_attr->pkey_index = context->pri_path.pkey_index & 0x7f;
2406         qp_attr->port_num = context->pri_path.port;
2407
2408         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
2409         qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
2410
2411         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
2412
2413         qp_attr->max_dest_rd_atomic =
2414                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
2415         qp_attr->min_rnr_timer      =
2416                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
2417         qp_attr->timeout            = context->pri_path.ackto_lt >> 3;
2418         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
2419         qp_attr->rnr_retry          = (be32_to_cpu(context->params1) >> 13) & 0x7;
2420         qp_attr->alt_timeout        = context->alt_path.ackto_lt >> 3;
2421         qp_attr->cur_qp_state        = qp_attr->qp_state;
2422         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
2423         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
2424
2425         if (!ibqp->uobject) {
2426                 qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
2427                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
2428         } else {
2429                 qp_attr->cap.max_send_wr  = 0;
2430                 qp_attr->cap.max_send_sge = 0;
2431         }
2432
2433         /* We don't support inline sends for kernel QPs (yet), and we
2434          * don't know what userspace's value should be.
2435          */
2436         qp_attr->cap.max_inline_data = 0;
2437
2438         qp_init_attr->cap            = qp_attr->cap;
2439
2440         qp_init_attr->create_flags = 0;
2441         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
2442                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
2443
2444         qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
2445                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
2446
2447 out_free:
2448         kfree(outb);
2449
2450 out:
2451         mutex_unlock(&qp->mutex);
2452         return err;
2453 }
2454
2455 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
2456                                           struct ib_ucontext *context,
2457                                           struct ib_udata *udata)
2458 {
2459         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2460         struct mlx5_ib_xrcd *xrcd;
2461         int err;
2462
2463         if (!(dev->mdev.caps.flags & MLX5_DEV_CAP_FLAG_XRC))
2464                 return ERR_PTR(-ENOSYS);
2465
2466         xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
2467         if (!xrcd)
2468                 return ERR_PTR(-ENOMEM);
2469
2470         err = mlx5_core_xrcd_alloc(&dev->mdev, &xrcd->xrcdn);
2471         if (err) {
2472                 kfree(xrcd);
2473                 return ERR_PTR(-ENOMEM);
2474         }
2475
2476         return &xrcd->ibxrcd;
2477 }
2478
2479 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
2480 {
2481         struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
2482         u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
2483         int err;
2484
2485         err = mlx5_core_xrcd_dealloc(&dev->mdev, xrcdn);
2486         if (err) {
2487                 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
2488                 return err;
2489         }
2490
2491         kfree(xrcd);
2492
2493         return 0;
2494 }