drivers/infiniband/hw/ocrdma/ocrdma_sli.h

   1 /*******************************************************************
   2  * This file is part of the Emulex RoCE Device Driver for          *
   3  * RoCE (RDMA over Converged Ethernet) adapters.                   *
   4  * Copyright (C) 2008-2012 Emulex. All rights reserved.            *
   5  * EMULEX and SLI are trademarks of Emulex.                        *
   6  * www.emulex.com                                                  *
   7  *                                                                 *
   8  * This program is free software; you can redistribute it and/or   *
   9  * modify it under the terms of version 2 of the GNU General       *
  10  * Public License as published by the Free Software Foundation.    *
  11  * This program is distributed in the hope that it will be useful. *
  12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  16  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  17  * more details, a copy of which can be found in the file COPYING  *
  18  * included with this package.                                     *
  19  *
  20  * Contact Information:
  21  * linux-drivers@emulex.com
  22  *
  23  * Emulex
  24  * 3333 Susan Street
  25  * Costa Mesa, CA 92626
  26  *******************************************************************/
  27
  28 #ifndef __OCRDMA_SLI_H__
  29 #define __OCRDMA_SLI_H__
  30
  31 #define Bit(_b) (1 << (_b))
  32
  33 enum {
  34         OCRDMA_ASIC_GEN_SKH_R = 0x04,
  35         OCRDMA_ASIC_GEN_LANCER = 0x0B
  36 };
  37
  38 enum {
  39         OCRDMA_ASIC_REV_A0 = 0x00,
  40         OCRDMA_ASIC_REV_B0 = 0x10,
  41         OCRDMA_ASIC_REV_C0 = 0x20
  42 };
  43
  44 #define OCRDMA_SUBSYS_ROCE 10
  45 enum {
  46         OCRDMA_CMD_QUERY_CONFIG = 1,
  47         OCRDMA_CMD_ALLOC_PD = 2,
  48         OCRDMA_CMD_DEALLOC_PD = 3,
  49
  50         OCRDMA_CMD_CREATE_AH_TBL = 4,
  51         OCRDMA_CMD_DELETE_AH_TBL = 5,
  52
  53         OCRDMA_CMD_CREATE_QP = 6,
  54         OCRDMA_CMD_QUERY_QP = 7,
  55         OCRDMA_CMD_MODIFY_QP = 8 ,
  56         OCRDMA_CMD_DELETE_QP = 9,
  57
  58         OCRDMA_CMD_RSVD1 = 10,
  59         OCRDMA_CMD_ALLOC_LKEY = 11,
  60         OCRDMA_CMD_DEALLOC_LKEY = 12,
  61         OCRDMA_CMD_REGISTER_NSMR = 13,
  62         OCRDMA_CMD_REREGISTER_NSMR = 14,
  63         OCRDMA_CMD_REGISTER_NSMR_CONT = 15,
  64         OCRDMA_CMD_QUERY_NSMR = 16,
  65         OCRDMA_CMD_ALLOC_MW = 17,
  66         OCRDMA_CMD_QUERY_MW = 18,
  67
  68         OCRDMA_CMD_CREATE_SRQ = 19,
  69         OCRDMA_CMD_QUERY_SRQ = 20,
  70         OCRDMA_CMD_MODIFY_SRQ = 21,
  71         OCRDMA_CMD_DELETE_SRQ = 22,
  72
  73         OCRDMA_CMD_ATTACH_MCAST = 23,
  74         OCRDMA_CMD_DETACH_MCAST = 24,
  75
  76         OCRDMA_CMD_CREATE_RBQ = 25,
  77         OCRDMA_CMD_DESTROY_RBQ = 26,
  78
  79         OCRDMA_CMD_GET_RDMA_STATS = 27,
  80
  81         OCRDMA_CMD_MAX
  82 };
  83
  84 #define OCRDMA_SUBSYS_COMMON 1
  85 enum {
  86         OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1 = 5,
  87         OCRDMA_CMD_CREATE_CQ            = 12,
  88         OCRDMA_CMD_CREATE_EQ            = 13,
  89         OCRDMA_CMD_CREATE_MQ            = 21,
  90         OCRDMA_CMD_GET_CTRL_ATTRIBUTES  = 32,
  91         OCRDMA_CMD_GET_FW_VER           = 35,
  92         OCRDMA_CMD_DELETE_MQ            = 53,
  93         OCRDMA_CMD_DELETE_CQ            = 54,
  94         OCRDMA_CMD_DELETE_EQ            = 55,
  95         OCRDMA_CMD_GET_FW_CONFIG        = 58,
  96         OCRDMA_CMD_CREATE_MQ_EXT        = 90,
  97         OCRDMA_CMD_PHY_DETAILS          = 102
  98 };
  99
 100 enum {
 101         QTYPE_EQ        = 1,
 102         QTYPE_CQ        = 2,
 103         QTYPE_MCCQ      = 3
 104 };
 105
 106 #define OCRDMA_MAX_SGID (8)
 107
 108 #define OCRDMA_MAX_QP    2048
 109 #define OCRDMA_MAX_CQ    2048
 110 #define OCRDMA_MAX_STAG 16384
 111
 112 enum {
 113         OCRDMA_DB_RQ_OFFSET             = 0xE0,
 114         OCRDMA_DB_GEN2_RQ_OFFSET        = 0x100,
 115         OCRDMA_DB_SQ_OFFSET             = 0x60,
 116         OCRDMA_DB_GEN2_SQ_OFFSET        = 0x1C0,
 117         OCRDMA_DB_SRQ_OFFSET            = OCRDMA_DB_RQ_OFFSET,
 118         OCRDMA_DB_GEN2_SRQ_OFFSET       = OCRDMA_DB_GEN2_RQ_OFFSET,
 119         OCRDMA_DB_CQ_OFFSET             = 0x120,
 120         OCRDMA_DB_EQ_OFFSET             = OCRDMA_DB_CQ_OFFSET,
 121         OCRDMA_DB_MQ_OFFSET             = 0x140,
 122
 123         OCRDMA_DB_SQ_SHIFT              = 16,
 124         OCRDMA_DB_RQ_SHIFT              = 24
 125 };
 126
 127 #define OCRDMA_DB_CQ_RING_ID_MASK       0x3FF   /* bits 0 - 9 */
 128 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK  0x0C00   /* bits 10-11 of qid at 12-11 */
 129 /* qid #2 msbits at 12-11 */
 130 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT  0x1
 131 #define OCRDMA_DB_CQ_NUM_POPPED_SHIFT       (16)        /* bits 16 - 28 */
 132 /* Rearm bit */
 133 #define OCRDMA_DB_CQ_REARM_SHIFT        (29)    /* bit 29 */
 134 /* solicited bit */
 135 #define OCRDMA_DB_CQ_SOLICIT_SHIFT   (31)       /* bit 31 */
 136
 137 #define OCRDMA_EQ_ID_MASK               0x1FF   /* bits 0 - 8 */
 138 #define OCRDMA_EQ_ID_EXT_MASK           0x3e00  /* bits 9-13 */
 139 #define OCRDMA_EQ_ID_EXT_MASK_SHIFT     (2)     /* qid bits 9-13 at 11-15 */
 140
 141 /* Clear the interrupt for this eq */
 142 #define OCRDMA_EQ_CLR_SHIFT                     (9)     /* bit 9 */
 143 /* Must be 1 */
 144 #define OCRDMA_EQ_TYPE_SHIFT            (10)    /* bit 10 */
 145 /* Number of event entries processed */
 146 #define OCRDMA_NUM_EQE_SHIFT            (16)    /* bits 16 - 28 */
 147 /* Rearm bit */
 148 #define OCRDMA_REARM_SHIFT              (29)    /* bit 29 */
 149
 150 #define OCRDMA_MQ_ID_MASK               0x7FF   /* bits 0 - 10 */
 151 /* Number of entries posted */
 152 #define OCRDMA_MQ_NUM_MQE_SHIFT (16)    /* bits 16 - 29 */
 153
 154 #define OCRDMA_MIN_HPAGE_SIZE (4096)
 155
 156 #define OCRDMA_MIN_Q_PAGE_SIZE (4096)
 157 #define OCRDMA_MAX_Q_PAGES     (8)
 158
 159 #define OCRDMA_SLI_ASIC_ID_OFFSET       0x9C
 160 #define OCRDMA_SLI_ASIC_REV_MASK        0x000000FF
 161 #define OCRDMA_SLI_ASIC_GEN_NUM_MASK    0x0000FF00
 162 #define OCRDMA_SLI_ASIC_GEN_NUM_SHIFT   0x08
 163 /*
 164 # 0: 4K Bytes
 165 # 1: 8K Bytes
 166 # 2: 16K Bytes
 167 # 3: 32K Bytes
 168 # 4: 64K Bytes
 169 # 5: 128K Bytes
 170 # 6: 256K Bytes
 171 # 7: 512K Bytes
 172 */
 173 #define OCRDMA_MAX_Q_PAGE_SIZE_CNT (8)
 174 #define OCRDMA_Q_PAGE_BASE_SIZE (OCRDMA_MIN_Q_PAGE_SIZE * OCRDMA_MAX_Q_PAGES)
 175
 176 #define MAX_OCRDMA_QP_PAGES      (8)
 177 #define OCRDMA_MAX_WQE_MEM_SIZE (MAX_OCRDMA_QP_PAGES * OCRDMA_MIN_HQ_PAGE_SIZE)
 178
 179 #define OCRDMA_CREATE_CQ_MAX_PAGES (4)
 180 #define OCRDMA_DPP_CQE_SIZE (4)
 181
 182 #define OCRDMA_GEN2_MAX_CQE 1024
 183 #define OCRDMA_GEN2_CQ_PAGE_SIZE 4096
 184 #define OCRDMA_GEN2_WQE_SIZE 256
 185 #define OCRDMA_MAX_CQE  4095
 186 #define OCRDMA_CQ_PAGE_SIZE 16384
 187 #define OCRDMA_WQE_SIZE 128
 188 #define OCRDMA_WQE_STRIDE 8
 189 #define OCRDMA_WQE_ALIGN_BYTES 16
 190
 191 #define MAX_OCRDMA_SRQ_PAGES MAX_OCRDMA_QP_PAGES
 192
 193 enum {
 194         OCRDMA_MCH_OPCODE_SHIFT = 0,
 195         OCRDMA_MCH_OPCODE_MASK  = 0xFF,
 196         OCRDMA_MCH_SUBSYS_SHIFT = 8,
 197         OCRDMA_MCH_SUBSYS_MASK  = 0xFF00
 198 };
 199
 200 /* mailbox cmd header */
 201 struct ocrdma_mbx_hdr {
 202         u32 subsys_op;
 203         u32 timeout;            /* in seconds */
 204         u32 cmd_len;
 205         u32 rsvd_version;
 206 };
 207
 208 enum {
 209         OCRDMA_MBX_RSP_OPCODE_SHIFT     = 0,
 210         OCRDMA_MBX_RSP_OPCODE_MASK      = 0xFF,
 211         OCRDMA_MBX_RSP_SUBSYS_SHIFT     = 8,
 212         OCRDMA_MBX_RSP_SUBSYS_MASK      = 0xFF << OCRDMA_MBX_RSP_SUBSYS_SHIFT,
 213
 214         OCRDMA_MBX_RSP_STATUS_SHIFT     = 0,
 215         OCRDMA_MBX_RSP_STATUS_MASK      = 0xFF,
 216         OCRDMA_MBX_RSP_ASTATUS_SHIFT    = 8,
 217         OCRDMA_MBX_RSP_ASTATUS_MASK     = 0xFF << OCRDMA_MBX_RSP_ASTATUS_SHIFT
 218 };
 219
 220 /* mailbox cmd response */
 221 struct ocrdma_mbx_rsp {
 222         u32 subsys_op;
 223         u32 status;
 224         u32 rsp_len;
 225         u32 add_rsp_len;
 226 };
 227
 228 enum {
 229         OCRDMA_MQE_EMBEDDED     = 1,
 230         OCRDMA_MQE_NONEMBEDDED  = 0
 231 };
 232
 233 struct ocrdma_mqe_sge {
 234         u32 pa_lo;
 235         u32 pa_hi;
 236         u32 len;
 237 };
 238
 239 enum {
 240         OCRDMA_MQE_HDR_EMB_SHIFT        = 0,
 241         OCRDMA_MQE_HDR_EMB_MASK         = Bit(0),
 242         OCRDMA_MQE_HDR_SGE_CNT_SHIFT    = 3,
 243         OCRDMA_MQE_HDR_SGE_CNT_MASK     = 0x1F << OCRDMA_MQE_HDR_SGE_CNT_SHIFT,
 244         OCRDMA_MQE_HDR_SPECIAL_SHIFT    = 24,
 245         OCRDMA_MQE_HDR_SPECIAL_MASK     = 0xFF << OCRDMA_MQE_HDR_SPECIAL_SHIFT
 246 };
 247
 248 struct ocrdma_mqe_hdr {
 249         u32 spcl_sge_cnt_emb;
 250         u32 pyld_len;
 251         u32 tag_lo;
 252         u32 tag_hi;
 253         u32 rsvd3;
 254 };
 255
 256 struct ocrdma_mqe_emb_cmd {
 257         struct ocrdma_mbx_hdr mch;
 258         u8 pyld[220];
 259 };
 260
 261 struct ocrdma_mqe {
 262         struct ocrdma_mqe_hdr hdr;
 263         union {
 264                 struct ocrdma_mqe_emb_cmd emb_req;
 265                 struct {
 266                         struct ocrdma_mqe_sge sge[19];
 267                 } nonemb_req;
 268                 u8 cmd[236];
 269                 struct ocrdma_mbx_rsp rsp;
 270         } u;
 271 };
 272
 273 #define OCRDMA_EQ_LEN       4096
 274 #define OCRDMA_MQ_CQ_LEN    256
 275 #define OCRDMA_MQ_LEN       128
 276
 277 #define PAGE_SHIFT_4K           12
 278 #define PAGE_SIZE_4K            (1 << PAGE_SHIFT_4K)
 279
 280 /* Returns number of pages spanned by the data starting at the given addr */
 281 #define PAGES_4K_SPANNED(_address, size) \
 282         ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) +     \
 283                         (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
 284
 285 struct ocrdma_delete_q_req {
 286         struct ocrdma_mbx_hdr req;
 287         u32 id;
 288 };
 289
 290 struct ocrdma_pa {
 291         u32 lo;
 292         u32 hi;
 293 };
 294
 295 #define MAX_OCRDMA_EQ_PAGES (8)
 296 struct ocrdma_create_eq_req {
 297         struct ocrdma_mbx_hdr req;
 298         u32 num_pages;
 299         u32 valid;
 300         u32 cnt;
 301         u32 delay;
 302         u32 rsvd;
 303         struct ocrdma_pa pa[MAX_OCRDMA_EQ_PAGES];
 304 };
 305
 306 enum {
 307         OCRDMA_CREATE_EQ_VALID  = Bit(29),
 308         OCRDMA_CREATE_EQ_CNT_SHIFT      = 26,
 309         OCRDMA_CREATE_CQ_DELAY_SHIFT    = 13,
 310 };
 311
 312 struct ocrdma_create_eq_rsp {
 313         struct ocrdma_mbx_rsp rsp;
 314         u32 vector_eqid;
 315 };
 316
 317 #define OCRDMA_EQ_MINOR_OTHER (0x1)
 318
 319 enum {
 320         OCRDMA_MCQE_STATUS_SHIFT        = 0,
 321         OCRDMA_MCQE_STATUS_MASK         = 0xFFFF,
 322         OCRDMA_MCQE_ESTATUS_SHIFT       = 16,
 323         OCRDMA_MCQE_ESTATUS_MASK        = 0xFFFF << OCRDMA_MCQE_ESTATUS_SHIFT,
 324         OCRDMA_MCQE_CONS_SHIFT          = 27,
 325         OCRDMA_MCQE_CONS_MASK           = Bit(27),
 326         OCRDMA_MCQE_CMPL_SHIFT          = 28,
 327         OCRDMA_MCQE_CMPL_MASK           = Bit(28),
 328         OCRDMA_MCQE_AE_SHIFT            = 30,
 329         OCRDMA_MCQE_AE_MASK             = Bit(30),
 330         OCRDMA_MCQE_VALID_SHIFT         = 31,
 331         OCRDMA_MCQE_VALID_MASK          = Bit(31)
 332 };
 333
 334 struct ocrdma_mcqe {
 335         u32 status;
 336         u32 tag_lo;
 337         u32 tag_hi;
 338         u32 valid_ae_cmpl_cons;
 339 };
 340
 341 enum {
 342         OCRDMA_AE_MCQE_QPVALID          = Bit(31),
 343         OCRDMA_AE_MCQE_QPID_MASK        = 0xFFFF,
 344
 345         OCRDMA_AE_MCQE_CQVALID          = Bit(31),
 346         OCRDMA_AE_MCQE_CQID_MASK        = 0xFFFF,
 347         OCRDMA_AE_MCQE_VALID            = Bit(31),
 348         OCRDMA_AE_MCQE_AE               = Bit(30),
 349         OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT = 16,
 350         OCRDMA_AE_MCQE_EVENT_TYPE_MASK  =
 351                                         0xFF << OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT,
 352         OCRDMA_AE_MCQE_EVENT_CODE_SHIFT = 8,
 353         OCRDMA_AE_MCQE_EVENT_CODE_MASK  =
 354                                         0xFF << OCRDMA_AE_MCQE_EVENT_CODE_SHIFT
 355 };
 356 struct ocrdma_ae_mcqe {
 357         u32 qpvalid_qpid;
 358         u32 cqvalid_cqid;
 359         u32 evt_tag;
 360         u32 valid_ae_event;
 361 };
 362
 363 enum {
 364         OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT = 0,
 365         OCRDMA_AE_PVID_MCQE_ENABLED_MASK  = 0xFF,
 366         OCRDMA_AE_PVID_MCQE_TAG_SHIFT = 16,
 367         OCRDMA_AE_PVID_MCQE_TAG_MASK = 0xFFFF << OCRDMA_AE_PVID_MCQE_TAG_SHIFT
 368 };
 369
 370 struct ocrdma_ae_pvid_mcqe {
 371         u32 tag_enabled;
 372         u32 event_tag;
 373         u32 rsvd1;
 374         u32 rsvd2;
 375 };
 376
 377 enum {
 378         OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT         = 16,
 379         OCRDMA_AE_MPA_MCQE_REQ_ID_MASK          = 0xFFFF <<
 380                                         OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT,
 381
 382         OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT     = 8,
 383         OCRDMA_AE_MPA_MCQE_EVENT_CODE_MASK      = 0xFF <<
 384                                         OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT,
 385         OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT     = 16,
 386         OCRDMA_AE_MPA_MCQE_EVENT_TYPE_MASK      = 0xFF <<
 387                                         OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT,
 388         OCRDMA_AE_MPA_MCQE_EVENT_AE_SHIFT       = 30,
 389         OCRDMA_AE_MPA_MCQE_EVENT_AE_MASK        = Bit(30),
 390         OCRDMA_AE_MPA_MCQE_EVENT_VALID_SHIFT    = 31,
 391         OCRDMA_AE_MPA_MCQE_EVENT_VALID_MASK     = Bit(31)
 392 };
 393
 394 struct ocrdma_ae_mpa_mcqe {
 395         u32 req_id;
 396         u32 w1;
 397         u32 w2;
 398         u32 valid_ae_event;
 399 };
 400
 401 enum {
 402         OCRDMA_AE_QP_MCQE_NEW_QP_STATE_SHIFT    = 0,
 403         OCRDMA_AE_QP_MCQE_NEW_QP_STATE_MASK     = 0xFFFF,
 404         OCRDMA_AE_QP_MCQE_QP_ID_SHIFT           = 16,
 405         OCRDMA_AE_QP_MCQE_QP_ID_MASK            = 0xFFFF <<
 406                                                 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT,
 407
 408         OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT      = 8,
 409         OCRDMA_AE_QP_MCQE_EVENT_CODE_MASK       = 0xFF <<
 410                                 OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT,
 411         OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT      = 16,
 412         OCRDMA_AE_QP_MCQE_EVENT_TYPE_MASK       = 0xFF <<
 413                                 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT,
 414         OCRDMA_AE_QP_MCQE_EVENT_AE_SHIFT        = 30,
 415         OCRDMA_AE_QP_MCQE_EVENT_AE_MASK         = Bit(30),
 416         OCRDMA_AE_QP_MCQE_EVENT_VALID_SHIFT     = 31,
 417         OCRDMA_AE_QP_MCQE_EVENT_VALID_MASK      = Bit(31)
 418 };
 419
 420 struct ocrdma_ae_qp_mcqe {
 421         u32 qp_id_state;
 422         u32 w1;
 423         u32 w2;
 424         u32 valid_ae_event;
 425 };
 426
 427 #define OCRDMA_ASYNC_RDMA_EVE_CODE 0x14
 428 #define OCRDMA_ASYNC_GRP5_EVE_CODE 0x5
 429
 430 enum ocrdma_async_grp5_events {
 431         OCRDMA_ASYNC_EVENT_QOS_VALUE    = 0x01,
 432         OCRDMA_ASYNC_EVENT_COS_VALUE    = 0x02,
 433         OCRDMA_ASYNC_EVENT_PVID_STATE   = 0x03
 434 };
 435
 436 enum OCRDMA_ASYNC_EVENT_TYPE {
 437         OCRDMA_CQ_ERROR                 = 0x00,
 438         OCRDMA_CQ_OVERRUN_ERROR         = 0x01,
 439         OCRDMA_CQ_QPCAT_ERROR           = 0x02,
 440         OCRDMA_QP_ACCESS_ERROR          = 0x03,
 441         OCRDMA_QP_COMM_EST_EVENT        = 0x04,
 442         OCRDMA_SQ_DRAINED_EVENT         = 0x05,
 443         OCRDMA_DEVICE_FATAL_EVENT       = 0x08,
 444         OCRDMA_SRQCAT_ERROR             = 0x0E,
 445         OCRDMA_SRQ_LIMIT_EVENT          = 0x0F,
 446         OCRDMA_QP_LAST_WQE_EVENT        = 0x10
 447 };
 448
 449 /* mailbox command request and responses */
 450 enum {
 451         OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT          = 2,
 452         OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK           = Bit(2),
 453         OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT        = 3,
 454         OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK         = Bit(3),
 455         OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT               = 8,
 456         OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK                = 0xFFFFFF <<
 457                                 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT,
 458
 459         OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT               = 16,
 460         OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK                = 0xFFFF <<
 461                                         OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT,
 462         OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT         = 8,
 463         OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK          = 0xFF <<
 464                                 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT,
 465
 466         OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT         = 0,
 467         OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK          = 0xFFFF,
 468         OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT        = 16,
 469         OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK         = 0xFFFF <<
 470                                 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT,
 471
 472         OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT       = 0,
 473         OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK        = 0xFFFF,
 474         OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT       = 16,
 475         OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK        = 0xFFFF <<
 476                                 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT,
 477
 478         OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET        = 24,
 479         OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK          = 0xFF <<
 480                                 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET,
 481         OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET        = 16,
 482         OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK          = 0xFF <<
 483                                 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET,
 484         OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET        = 0,
 485         OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_MASK          = 0xFFFF <<
 486                                 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET,
 487
 488         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET             = 16,
 489         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK               = 0xFFFF <<
 490                                 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET,
 491         OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET        = 0,
 492         OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_MASK          = 0xFFFF <<
 493                                 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET,
 494
 495         OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET         = 16,
 496         OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK           = 0xFFFF <<
 497                                 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET,
 498         OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET     = 0,
 499         OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_MASK       = 0xFFFF <<
 500                                 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET,
 501
 502         OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET         = 0,
 503         OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_MASK           = 0xFFFF <<
 504                                 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET,
 505
 506         OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET     = 16,
 507         OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_MASK       = 0xFFFF <<
 508                                 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET,
 509         OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET     = 0,
 510         OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK       = 0xFFFF <<
 511                                 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET,
 512
 513         OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET              = 16,
 514         OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK                = 0xFFFF <<
 515                                 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET,
 516         OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET     = 0,
 517         OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK       = 0xFFFF <<
 518                                 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET,
 519
 520         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET         = 16,
 521         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_MASK           = 0xFFFF <<
 522                                 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET,
 523         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET         = 0,
 524         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK           = 0xFFFF <<
 525                                 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET,
 526 };
 527
 528 struct ocrdma_mbx_query_config {
 529         struct ocrdma_mqe_hdr hdr;
 530         struct ocrdma_mbx_rsp rsp;
 531         u32 qp_srq_cq_ird_ord;
 532         u32 max_pd_ca_ack_delay;
 533         u32 max_write_send_sge;
 534         u32 max_ird_ord_per_qp;
 535         u32 max_shared_ird_ord;
 536         u32 max_mr;
 537         u32 max_mr_size_hi;
 538         u32 max_mr_size_lo;
 539         u32 max_num_mr_pbl;
 540         u32 max_mw;
 541         u32 max_fmr;
 542         u32 max_pages_per_frmr;
 543         u32 max_mcast_group;
 544         u32 max_mcast_qp_attach;
 545         u32 max_total_mcast_qp_attach;
 546         u32 wqe_rqe_stride_max_dpp_cqs;
 547         u32 max_srq_rpir_qps;
 548         u32 max_dpp_pds_credits;
 549         u32 max_dpp_credits_pds_per_pd;
 550         u32 max_wqes_rqes_per_q;
 551         u32 max_cq_cqes_per_cq;
 552         u32 max_srq_rqe_sge;
 553 };
 554
 555 struct ocrdma_fw_ver_rsp {
 556         struct ocrdma_mqe_hdr hdr;
 557         struct ocrdma_mbx_rsp rsp;
 558
 559         u8 running_ver[32];
 560 };
 561
 562 struct ocrdma_fw_conf_rsp {
 563         struct ocrdma_mqe_hdr hdr;
 564         struct ocrdma_mbx_rsp rsp;
 565
 566         u32 config_num;
 567         u32 asic_revision;
 568         u32 phy_port;
 569         u32 fn_mode;
 570         struct {
 571                 u32 mode;
 572                 u32 nic_wqid_base;
 573                 u32 nic_wq_tot;
 574                 u32 prot_wqid_base;
 575                 u32 prot_wq_tot;
 576                 u32 prot_rqid_base;
 577                 u32 prot_rqid_tot;
 578                 u32 rsvd[6];
 579         } ulp[2];
 580         u32 fn_capabilities;
 581         u32 rsvd1;
 582         u32 rsvd2;
 583         u32 base_eqid;
 584         u32 max_eq;
 585
 586 };
 587
 588 enum {
 589         OCRDMA_FN_MODE_RDMA     = 0x4
 590 };
 591
 592 struct ocrdma_get_phy_info_rsp {
 593         struct ocrdma_mqe_hdr hdr;
 594         struct ocrdma_mbx_rsp rsp;
 595
 596         u16 phy_type;
 597         u16 interface_type;
 598         u32 misc_params;
 599         u16 ext_phy_details;
 600         u16 rsvd;
 601         u16 auto_speeds_supported;
 602         u16 fixed_speeds_supported;
 603         u32 future_use[2];
 604 };
 605
 606 enum {
 607         OCRDMA_PHY_SPEED_ZERO = 0x0,
 608         OCRDMA_PHY_SPEED_10MBPS = 0x1,
 609         OCRDMA_PHY_SPEED_100MBPS = 0x2,
 610         OCRDMA_PHY_SPEED_1GBPS = 0x4,
 611         OCRDMA_PHY_SPEED_10GBPS = 0x8,
 612         OCRDMA_PHY_SPEED_40GBPS = 0x20
 613 };
 614
 615
 616 struct ocrdma_get_link_speed_rsp {
 617         struct ocrdma_mqe_hdr hdr;
 618         struct ocrdma_mbx_rsp rsp;
 619
 620         u8 pt_port_num;
 621         u8 link_duplex;
 622         u8 phys_port_speed;
 623         u8 phys_port_fault;
 624         u16 rsvd1;
 625         u16 qos_lnk_speed;
 626         u8 logical_lnk_status;
 627         u8 rsvd2[3];
 628 };
 629
 630 enum {
 631         OCRDMA_PHYS_LINK_SPEED_ZERO = 0x0,
 632         OCRDMA_PHYS_LINK_SPEED_10MBPS = 0x1,
 633         OCRDMA_PHYS_LINK_SPEED_100MBPS = 0x2,
 634         OCRDMA_PHYS_LINK_SPEED_1GBPS = 0x3,
 635         OCRDMA_PHYS_LINK_SPEED_10GBPS = 0x4,
 636         OCRDMA_PHYS_LINK_SPEED_20GBPS = 0x5,
 637         OCRDMA_PHYS_LINK_SPEED_25GBPS = 0x6,
 638         OCRDMA_PHYS_LINK_SPEED_40GBPS = 0x7,
 639         OCRDMA_PHYS_LINK_SPEED_100GBPS = 0x8
 640 };
 641
 642 enum {
 643         OCRDMA_CREATE_CQ_VER2                   = 2,
 644         OCRDMA_CREATE_CQ_VER3                   = 3,
 645
 646         OCRDMA_CREATE_CQ_PAGE_CNT_MASK          = 0xFFFF,
 647         OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT        = 16,
 648         OCRDMA_CREATE_CQ_PAGE_SIZE_MASK         = 0xFF,
 649
 650         OCRDMA_CREATE_CQ_COALESCWM_SHIFT        = 12,
 651         OCRDMA_CREATE_CQ_COALESCWM_MASK         = Bit(13) | Bit(12),
 652         OCRDMA_CREATE_CQ_FLAGS_NODELAY          = Bit(14),
 653         OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID       = Bit(15),
 654
 655         OCRDMA_CREATE_CQ_EQ_ID_MASK             = 0xFFFF,
 656         OCRDMA_CREATE_CQ_CQE_COUNT_MASK         = 0xFFFF
 657 };
 658
 659 enum {
 660         OCRDMA_CREATE_CQ_VER0                   = 0,
 661         OCRDMA_CREATE_CQ_DPP                    = 1,
 662         OCRDMA_CREATE_CQ_TYPE_SHIFT             = 24,
 663         OCRDMA_CREATE_CQ_EQID_SHIFT             = 22,
 664
 665         OCRDMA_CREATE_CQ_CNT_SHIFT              = 27,
 666         OCRDMA_CREATE_CQ_FLAGS_VALID            = Bit(29),
 667         OCRDMA_CREATE_CQ_FLAGS_EVENTABLE        = Bit(31),
 668         OCRDMA_CREATE_CQ_DEF_FLAGS              = OCRDMA_CREATE_CQ_FLAGS_VALID |
 669                                         OCRDMA_CREATE_CQ_FLAGS_EVENTABLE |
 670                                         OCRDMA_CREATE_CQ_FLAGS_NODELAY
 671 };
 672
 673 struct ocrdma_create_cq_cmd {
 674         struct ocrdma_mbx_hdr req;
 675         u32 pgsz_pgcnt;
 676         u32 ev_cnt_flags;
 677         u32 eqn;
 678         u16 cqe_count;
 679         u16 pd_id;
 680         u32 rsvd6;
 681         struct ocrdma_pa pa[OCRDMA_CREATE_CQ_MAX_PAGES];
 682 };
 683
 684 struct ocrdma_create_cq {
 685         struct ocrdma_mqe_hdr hdr;
 686         struct ocrdma_create_cq_cmd cmd;
 687 };
 688
 689 enum {
 690         OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK = 0xFFFF
 691 };
 692
 693 struct ocrdma_create_cq_cmd_rsp {
 694         struct ocrdma_mbx_rsp rsp;
 695         u32 cq_id;
 696 };
 697
 698 struct ocrdma_create_cq_rsp {
 699         struct ocrdma_mqe_hdr hdr;
 700         struct ocrdma_create_cq_cmd_rsp rsp;
 701 };
 702
 703 enum {
 704         OCRDMA_CREATE_MQ_V0_CQ_ID_SHIFT         = 22,
 705         OCRDMA_CREATE_MQ_CQ_ID_SHIFT            = 16,
 706         OCRDMA_CREATE_MQ_RING_SIZE_SHIFT        = 16,
 707         OCRDMA_CREATE_MQ_VALID                  = Bit(31),
 708         OCRDMA_CREATE_MQ_ASYNC_CQ_VALID         = Bit(0)
 709 };
 710
 711 struct ocrdma_create_mq_req {
 712         struct ocrdma_mbx_hdr req;
 713         u32 cqid_pages;
 714         u32 async_event_bitmap;
 715         u32 async_cqid_ringsize;
 716         u32 valid;
 717         u32 async_cqid_valid;
 718         u32 rsvd;
 719         struct ocrdma_pa pa[8];
 720 };
 721
 722 struct ocrdma_create_mq_rsp {
 723         struct ocrdma_mbx_rsp rsp;
 724         u32 id;
 725 };
 726
 727 enum {
 728         OCRDMA_DESTROY_CQ_QID_SHIFT                     = 0,
 729         OCRDMA_DESTROY_CQ_QID_MASK                      = 0xFFFF,
 730         OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT        = 16,
 731         OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_MASK         = 0xFFFF <<
 732                                 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT
 733 };
 734
 735 struct ocrdma_destroy_cq {
 736         struct ocrdma_mqe_hdr hdr;
 737         struct ocrdma_mbx_hdr req;
 738
 739         u32 bypass_flush_qid;
 740 };
 741
 742 struct ocrdma_destroy_cq_rsp {
 743         struct ocrdma_mqe_hdr hdr;
 744         struct ocrdma_mbx_rsp rsp;
 745 };
 746
 747 enum {
 748         OCRDMA_QPT_GSI  = 1,
 749         OCRDMA_QPT_RC   = 2,
 750         OCRDMA_QPT_UD   = 4,
 751 };
 752
 753 enum {
 754         OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT        = 0,
 755         OCRDMA_CREATE_QP_REQ_PD_ID_MASK         = 0xFFFF,
 756         OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT = 16,
 757         OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT = 19,
 758         OCRDMA_CREATE_QP_REQ_QPT_SHIFT          = 29,
 759         OCRDMA_CREATE_QP_REQ_QPT_MASK           = Bit(31) | Bit(30) | Bit(29),
 760
 761         OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT      = 0,
 762         OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK       = 0xFFFF,
 763         OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT      = 16,
 764         OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK       = 0xFFFF <<
 765                                         OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT,
 766
 767         OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT        = 0,
 768         OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK         = 0xFFFF,
 769         OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT         = 16,
 770         OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK          = 0xFFFF <<
 771                                         OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT,
 772
 773         OCRDMA_CREATE_QP_REQ_FMR_EN_SHIFT               = 0,
 774         OCRDMA_CREATE_QP_REQ_FMR_EN_MASK                = Bit(0),
 775         OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_SHIFT          = 1,
 776         OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK           = Bit(1),
 777         OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_SHIFT          = 2,
 778         OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK           = Bit(2),
 779         OCRDMA_CREATE_QP_REQ_INB_WREN_SHIFT             = 3,
 780         OCRDMA_CREATE_QP_REQ_INB_WREN_MASK              = Bit(3),
 781         OCRDMA_CREATE_QP_REQ_INB_RDEN_SHIFT             = 4,
 782         OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK              = Bit(4),
 783         OCRDMA_CREATE_QP_REQ_USE_SRQ_SHIFT              = 5,
 784         OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK               = Bit(5),
 785         OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_SHIFT          = 6,
 786         OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_MASK           = Bit(6),
 787         OCRDMA_CREATE_QP_REQ_ENABLE_DPP_SHIFT           = 7,
 788         OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK            = Bit(7),
 789         OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_SHIFT        = 8,
 790         OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_MASK         = Bit(8),
 791         OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT         = 16,
 792         OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK          = 0xFFFF <<
 793                                 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT,
 794
 795         OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT              = 0,
 796         OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK               = 0xFFFF,
 797         OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT              = 16,
 798         OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK               = 0xFFFF <<
 799                                 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT,
 800
 801         OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT         = 0,
 802         OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK          = 0xFFFF,
 803         OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT         = 16,
 804         OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK          = 0xFFFF <<
 805                                 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT,
 806
 807         OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT             = 0,
 808         OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK              = 0xFFFF,
 809         OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT             = 16,
 810         OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK              = 0xFFFF <<
 811                                 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT,
 812
 813         OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT              = 0,
 814         OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK               = 0xFFFF,
 815         OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT              = 16,
 816         OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK               = 0xFFFF <<
 817                                 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT,
 818
 819         OCRDMA_CREATE_QP_REQ_DPP_CQPID_SHIFT            = 0,
 820         OCRDMA_CREATE_QP_REQ_DPP_CQPID_MASK             = 0xFFFF,
 821         OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT           = 16,
 822         OCRDMA_CREATE_QP_REQ_DPP_CREDIT_MASK            = 0xFFFF <<
 823                                 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT
 824 };
 825
 826 enum {
 827         OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT   = 16,
 828         OCRDMA_CREATE_QP_RSP_DPP_PAGE_SHIFT     = 1
 829 };
 830
 831 #define MAX_OCRDMA_IRD_PAGES 4
 832
 833 enum ocrdma_qp_flags {
 834         OCRDMA_QP_MW_BIND       = 1,
 835         OCRDMA_QP_LKEY0         = (1 << 1),
 836         OCRDMA_QP_FAST_REG      = (1 << 2),
 837         OCRDMA_QP_INB_RD        = (1 << 6),
 838         OCRDMA_QP_INB_WR        = (1 << 7),
 839 };
 840
 841 enum ocrdma_qp_state {
 842         OCRDMA_QPS_RST          = 0,
 843         OCRDMA_QPS_INIT         = 1,
 844         OCRDMA_QPS_RTR          = 2,
 845         OCRDMA_QPS_RTS          = 3,
 846         OCRDMA_QPS_SQE          = 4,
 847         OCRDMA_QPS_SQ_DRAINING  = 5,
 848         OCRDMA_QPS_ERR          = 6,
 849         OCRDMA_QPS_SQD          = 7
 850 };
 851
 852 struct ocrdma_create_qp_req {
 853         struct ocrdma_mqe_hdr hdr;
 854         struct ocrdma_mbx_hdr req;
 855
 856         u32 type_pgsz_pdn;
 857         u32 max_wqe_rqe;
 858         u32 max_sge_send_write;
 859         u32 max_sge_recv_flags;
 860         u32 max_ord_ird;
 861         u32 num_wq_rq_pages;
 862         u32 wqe_rqe_size;
 863         u32 wq_rq_cqid;
 864         struct ocrdma_pa wq_addr[MAX_OCRDMA_QP_PAGES];
 865         struct ocrdma_pa rq_addr[MAX_OCRDMA_QP_PAGES];
 866         u32 dpp_credits_cqid;
 867         u32 rpir_lkey;
 868         struct ocrdma_pa ird_addr[MAX_OCRDMA_IRD_PAGES];
 869 };
 870
 871 enum {
 872         OCRDMA_CREATE_QP_RSP_QP_ID_SHIFT                = 0,
 873         OCRDMA_CREATE_QP_RSP_QP_ID_MASK                 = 0xFFFF,
 874
 875         OCRDMA_CREATE_QP_RSP_MAX_RQE_SHIFT              = 0,
 876         OCRDMA_CREATE_QP_RSP_MAX_RQE_MASK               = 0xFFFF,
 877         OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT              = 16,
 878         OCRDMA_CREATE_QP_RSP_MAX_WQE_MASK               = 0xFFFF <<
 879                                 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT,
 880
 881         OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_SHIFT        = 0,
 882         OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_MASK         = 0xFFFF,
 883         OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT         = 16,
 884         OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_MASK          = 0xFFFF <<
 885                                 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT,
 886
 887         OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT         = 16,
 888         OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_MASK          = 0xFFFF <<
 889                                 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT,
 890
 891         OCRDMA_CREATE_QP_RSP_MAX_IRD_SHIFT              = 0,
 892         OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK               = 0xFFFF,
 893         OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT              = 16,
 894         OCRDMA_CREATE_QP_RSP_MAX_ORD_MASK               = 0xFFFF <<
 895                                 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT,
 896
 897         OCRDMA_CREATE_QP_RSP_RQ_ID_SHIFT                = 0,
 898         OCRDMA_CREATE_QP_RSP_RQ_ID_MASK                 = 0xFFFF,
 899         OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT                = 16,
 900         OCRDMA_CREATE_QP_RSP_SQ_ID_MASK                 = 0xFFFF <<
 901                                 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT,
 902
 903         OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK           = Bit(0),
 904         OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT      = 1,
 905         OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK       = 0x7FFF <<
 906                                 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT,
 907         OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT          = 16,
 908         OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK           = 0xFFFF <<
 909                                 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT,
 910 };
 911
 912 struct ocrdma_create_qp_rsp {
 913         struct ocrdma_mqe_hdr hdr;
 914         struct ocrdma_mbx_rsp rsp;
 915
 916         u32 qp_id;
 917         u32 max_wqe_rqe;
 918         u32 max_sge_send_write;
 919         u32 max_sge_recv;
 920         u32 max_ord_ird;
 921         u32 sq_rq_id;
 922         u32 dpp_response;
 923 };
 924
 925 struct ocrdma_destroy_qp {
 926         struct ocrdma_mqe_hdr hdr;
 927         struct ocrdma_mbx_hdr req;
 928         u32 qp_id;
 929 };
 930
 931 struct ocrdma_destroy_qp_rsp {
 932         struct ocrdma_mqe_hdr hdr;
 933         struct ocrdma_mbx_rsp rsp;
 934 };
 935
 936 enum {
 937         OCRDMA_MODIFY_QP_ID_SHIFT       = 0,
 938         OCRDMA_MODIFY_QP_ID_MASK        = 0xFFFF,
 939
 940         OCRDMA_QP_PARA_QPS_VALID        = Bit(0),
 941         OCRDMA_QP_PARA_SQD_ASYNC_VALID  = Bit(1),
 942         OCRDMA_QP_PARA_PKEY_VALID       = Bit(2),
 943         OCRDMA_QP_PARA_QKEY_VALID       = Bit(3),
 944         OCRDMA_QP_PARA_PMTU_VALID       = Bit(4),
 945         OCRDMA_QP_PARA_ACK_TO_VALID     = Bit(5),
 946         OCRDMA_QP_PARA_RETRY_CNT_VALID  = Bit(6),
 947         OCRDMA_QP_PARA_RRC_VALID        = Bit(7),
 948         OCRDMA_QP_PARA_RQPSN_VALID      = Bit(8),
 949         OCRDMA_QP_PARA_MAX_IRD_VALID    = Bit(9),
 950         OCRDMA_QP_PARA_MAX_ORD_VALID    = Bit(10),
 951         OCRDMA_QP_PARA_RNT_VALID        = Bit(11),
 952         OCRDMA_QP_PARA_SQPSN_VALID      = Bit(12),
 953         OCRDMA_QP_PARA_DST_QPN_VALID    = Bit(13),
 954         OCRDMA_QP_PARA_MAX_WQE_VALID    = Bit(14),
 955         OCRDMA_QP_PARA_MAX_RQE_VALID    = Bit(15),
 956         OCRDMA_QP_PARA_SGE_SEND_VALID   = Bit(16),
 957         OCRDMA_QP_PARA_SGE_RECV_VALID   = Bit(17),
 958         OCRDMA_QP_PARA_SGE_WR_VALID     = Bit(18),
 959         OCRDMA_QP_PARA_INB_RDEN_VALID   = Bit(19),
 960         OCRDMA_QP_PARA_INB_WREN_VALID   = Bit(20),
 961         OCRDMA_QP_PARA_FLOW_LBL_VALID   = Bit(21),
 962         OCRDMA_QP_PARA_BIND_EN_VALID    = Bit(22),
 963         OCRDMA_QP_PARA_ZLKEY_EN_VALID   = Bit(23),
 964         OCRDMA_QP_PARA_FMR_EN_VALID     = Bit(24),
 965         OCRDMA_QP_PARA_INBAT_EN_VALID   = Bit(25),
 966         OCRDMA_QP_PARA_VLAN_EN_VALID    = Bit(26),
 967
 968         OCRDMA_MODIFY_QP_FLAGS_RD       = Bit(0),
 969         OCRDMA_MODIFY_QP_FLAGS_WR       = Bit(1),
 970         OCRDMA_MODIFY_QP_FLAGS_SEND     = Bit(2),
 971         OCRDMA_MODIFY_QP_FLAGS_ATOMIC   = Bit(3)
 972 };
 973
 974 enum {
 975         OCRDMA_QP_PARAMS_SRQ_ID_SHIFT           = 0,
 976         OCRDMA_QP_PARAMS_SRQ_ID_MASK            = 0xFFFF,
 977
 978         OCRDMA_QP_PARAMS_MAX_RQE_SHIFT          = 0,
 979         OCRDMA_QP_PARAMS_MAX_RQE_MASK           = 0xFFFF,
 980         OCRDMA_QP_PARAMS_MAX_WQE_SHIFT          = 16,
 981         OCRDMA_QP_PARAMS_MAX_WQE_MASK           = 0xFFFF <<
 982             OCRDMA_QP_PARAMS_MAX_WQE_SHIFT,
 983
 984         OCRDMA_QP_PARAMS_MAX_SGE_WRITE_SHIFT    = 0,
 985         OCRDMA_QP_PARAMS_MAX_SGE_WRITE_MASK     = 0xFFFF,
 986         OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT     = 16,
 987         OCRDMA_QP_PARAMS_MAX_SGE_SEND_MASK      = 0xFFFF <<
 988                                         OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT,
 989
 990         OCRDMA_QP_PARAMS_FLAGS_FMR_EN           = Bit(0),
 991         OCRDMA_QP_PARAMS_FLAGS_LKEY_0_EN        = Bit(1),
 992         OCRDMA_QP_PARAMS_FLAGS_BIND_MW_EN       = Bit(2),
 993         OCRDMA_QP_PARAMS_FLAGS_INBWR_EN         = Bit(3),
 994         OCRDMA_QP_PARAMS_FLAGS_INBRD_EN         = Bit(4),
 995         OCRDMA_QP_PARAMS_STATE_SHIFT            = 5,
 996         OCRDMA_QP_PARAMS_STATE_MASK             = Bit(5) | Bit(6) | Bit(7),
 997         OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC        = Bit(8),
 998         OCRDMA_QP_PARAMS_FLAGS_INB_ATEN         = Bit(9),
 999         OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT     = 16,
1000         OCRDMA_QP_PARAMS_MAX_SGE_RECV_MASK      = 0xFFFF <<
1001                                         OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT,
1002
1003         OCRDMA_QP_PARAMS_MAX_IRD_SHIFT          = 0,
1004         OCRDMA_QP_PARAMS_MAX_IRD_MASK           = 0xFFFF,
1005         OCRDMA_QP_PARAMS_MAX_ORD_SHIFT          = 16,
1006         OCRDMA_QP_PARAMS_MAX_ORD_MASK           = 0xFFFF <<
1007                                         OCRDMA_QP_PARAMS_MAX_ORD_SHIFT,
1008
1009         OCRDMA_QP_PARAMS_RQ_CQID_SHIFT          = 0,
1010         OCRDMA_QP_PARAMS_RQ_CQID_MASK           = 0xFFFF,
1011         OCRDMA_QP_PARAMS_WQ_CQID_SHIFT          = 16,
1012         OCRDMA_QP_PARAMS_WQ_CQID_MASK           = 0xFFFF <<
1013                                         OCRDMA_QP_PARAMS_WQ_CQID_SHIFT,
1014
1015         OCRDMA_QP_PARAMS_RQ_PSN_SHIFT           = 0,
1016         OCRDMA_QP_PARAMS_RQ_PSN_MASK            = 0xFFFFFF,
1017         OCRDMA_QP_PARAMS_HOP_LMT_SHIFT          = 24,
1018         OCRDMA_QP_PARAMS_HOP_LMT_MASK           = 0xFF <<
1019                                         OCRDMA_QP_PARAMS_HOP_LMT_SHIFT,
1020
1021         OCRDMA_QP_PARAMS_SQ_PSN_SHIFT           = 0,
1022         OCRDMA_QP_PARAMS_SQ_PSN_MASK            = 0xFFFFFF,
1023         OCRDMA_QP_PARAMS_TCLASS_SHIFT           = 24,
1024         OCRDMA_QP_PARAMS_TCLASS_MASK            = 0xFF <<
1025                                         OCRDMA_QP_PARAMS_TCLASS_SHIFT,
1026
1027         OCRDMA_QP_PARAMS_DEST_QPN_SHIFT         = 0,
1028         OCRDMA_QP_PARAMS_DEST_QPN_MASK          = 0xFFFFFF,
1029         OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT    = 24,
1030         OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK     = 0x7 <<
1031                                         OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT,
1032         OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT      = 27,
1033         OCRDMA_QP_PARAMS_ACK_TIMEOUT_MASK       = 0x1F <<
1034                                         OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT,
1035
1036         OCRDMA_QP_PARAMS_PKEY_IDNEX_SHIFT       = 0,
1037         OCRDMA_QP_PARAMS_PKEY_INDEX_MASK        = 0xFFFF,
1038         OCRDMA_QP_PARAMS_PATH_MTU_SHIFT         = 18,
1039         OCRDMA_QP_PARAMS_PATH_MTU_MASK          = 0x3FFF <<
1040                                         OCRDMA_QP_PARAMS_PATH_MTU_SHIFT,
1041
1042         OCRDMA_QP_PARAMS_FLOW_LABEL_SHIFT       = 0,
1043         OCRDMA_QP_PARAMS_FLOW_LABEL_MASK        = 0xFFFFF,
1044         OCRDMA_QP_PARAMS_SL_SHIFT               = 20,
1045         OCRDMA_QP_PARAMS_SL_MASK                = 0xF <<
1046                                         OCRDMA_QP_PARAMS_SL_SHIFT,
1047         OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT        = 24,
1048         OCRDMA_QP_PARAMS_RETRY_CNT_MASK         = 0x7 <<
1049                                         OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT,
1050         OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT    = 27,
1051         OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK     = 0x1F <<
1052                                         OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT,
1053
1054         OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_SHIFT    = 0,
1055         OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_MASK     = 0xFFFF,
1056         OCRDMA_QP_PARAMS_VLAN_SHIFT             = 16,
1057         OCRDMA_QP_PARAMS_VLAN_MASK              = 0xFFFF <<
1058                                         OCRDMA_QP_PARAMS_VLAN_SHIFT
1059 };
1060
1061 struct ocrdma_qp_params {
1062         u32 id;
1063         u32 max_wqe_rqe;
1064         u32 max_sge_send_write;
1065         u32 max_sge_recv_flags;
1066         u32 max_ord_ird;
1067         u32 wq_rq_cqid;
1068         u32 hop_lmt_rq_psn;
1069         u32 tclass_sq_psn;
1070         u32 ack_to_rnr_rtc_dest_qpn;
1071         u32 path_mtu_pkey_indx;
1072         u32 rnt_rc_sl_fl;
1073         u8 sgid[16];
1074         u8 dgid[16];
1075         u32 dmac_b0_to_b3;
1076         u32 vlan_dmac_b4_to_b5;
1077         u32 qkey;
1078 };
1079
1080
1081 struct ocrdma_modify_qp {
1082         struct ocrdma_mqe_hdr hdr;
1083         struct ocrdma_mbx_hdr req;
1084
1085         struct ocrdma_qp_params params;
1086         u32 flags;
1087         u32 rdma_flags;
1088         u32 num_outstanding_atomic_rd;
1089 };
1090
1091 enum {
1092         OCRDMA_MODIFY_QP_RSP_MAX_RQE_SHIFT      = 0,
1093         OCRDMA_MODIFY_QP_RSP_MAX_RQE_MASK       = 0xFFFF,
1094         OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT      = 16,
1095         OCRDMA_MODIFY_QP_RSP_MAX_WQE_MASK       = 0xFFFF <<
1096                                         OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT,
1097
1098         OCRDMA_MODIFY_QP_RSP_MAX_IRD_SHIFT      = 0,
1099         OCRDMA_MODIFY_QP_RSP_MAX_IRD_MASK       = 0xFFFF,
1100         OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT      = 16,
1101         OCRDMA_MODIFY_QP_RSP_MAX_ORD_MASK       = 0xFFFF <<
1102                                         OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT
1103 };
1104
1105 struct ocrdma_modify_qp_rsp {
1106         struct ocrdma_mqe_hdr hdr;
1107         struct ocrdma_mbx_rsp rsp;
1108
1109         u32 max_wqe_rqe;
1110         u32 max_ord_ird;
1111 };
1112
1113 struct ocrdma_query_qp {
1114         struct ocrdma_mqe_hdr hdr;
1115         struct ocrdma_mbx_hdr req;
1116
1117 #define OCRDMA_QUERY_UP_QP_ID_SHIFT     0
1118 #define OCRDMA_QUERY_UP_QP_ID_MASK      0xFFFFFF
1119         u32 qp_id;
1120 };
1121
1122 struct ocrdma_query_qp_rsp {
1123         struct ocrdma_mqe_hdr hdr;
1124         struct ocrdma_mbx_rsp rsp;
1125         struct ocrdma_qp_params params;
1126 };
1127
1128 enum {
1129         OCRDMA_CREATE_SRQ_PD_ID_SHIFT           = 0,
1130         OCRDMA_CREATE_SRQ_PD_ID_MASK            = 0xFFFF,
1131         OCRDMA_CREATE_SRQ_PG_SZ_SHIFT           = 16,
1132         OCRDMA_CREATE_SRQ_PG_SZ_MASK            = 0x3 <<
1133                                         OCRDMA_CREATE_SRQ_PG_SZ_SHIFT,
1134
1135         OCRDMA_CREATE_SRQ_MAX_RQE_SHIFT         = 0,
1136         OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT    = 16,
1137         OCRDMA_CREATE_SRQ_MAX_SGE_RECV_MASK     = 0xFFFF <<
1138                                         OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT,
1139
1140         OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT        = 0,
1141         OCRDMA_CREATE_SRQ_RQE_SIZE_MASK         = 0xFFFF,
1142         OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT    = 16,
1143         OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_MASK     = 0xFFFF <<
1144                                         OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT
1145 };
1146
1147 struct ocrdma_create_srq {
1148         struct ocrdma_mqe_hdr hdr;
1149         struct ocrdma_mbx_hdr req;
1150
1151         u32 pgsz_pdid;
1152         u32 max_sge_rqe;
1153         u32 pages_rqe_sz;
1154         struct ocrdma_pa rq_addr[MAX_OCRDMA_SRQ_PAGES];
1155 };
1156
1157 enum {
1158         OCRDMA_CREATE_SRQ_RSP_SRQ_ID_SHIFT                      = 0,
1159         OCRDMA_CREATE_SRQ_RSP_SRQ_ID_MASK                       = 0xFFFFFF,
1160
1161         OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT           = 0,
1162         OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK            = 0xFFFF,
1163         OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT      = 16,
1164         OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK       = 0xFFFF <<
1165                         OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT
1166 };
1167
1168 struct ocrdma_create_srq_rsp {
1169         struct ocrdma_mqe_hdr hdr;
1170         struct ocrdma_mbx_rsp rsp;
1171
1172         u32 id;
1173         u32 max_sge_rqe_allocated;
1174 };
1175
1176 enum {
1177         OCRDMA_MODIFY_SRQ_ID_SHIFT      = 0,
1178         OCRDMA_MODIFY_SRQ_ID_MASK       = 0xFFFFFF,
1179
1180         OCRDMA_MODIFY_SRQ_MAX_RQE_SHIFT = 0,
1181         OCRDMA_MODIFY_SRQ_MAX_RQE_MASK  = 0xFFFF,
1182         OCRDMA_MODIFY_SRQ_LIMIT_SHIFT   = 16,
1183         OCRDMA_MODIFY_SRQ__LIMIT_MASK   = 0xFFFF <<
1184                                         OCRDMA_MODIFY_SRQ_LIMIT_SHIFT
1185 };
1186
1187 struct ocrdma_modify_srq {
1188         struct ocrdma_mqe_hdr hdr;
1189         struct ocrdma_mbx_rsp rep;
1190
1191         u32 id;
1192         u32 limit_max_rqe;
1193 };
1194
1195 enum {
1196         OCRDMA_QUERY_SRQ_ID_SHIFT       = 0,
1197         OCRDMA_QUERY_SRQ_ID_MASK        = 0xFFFFFF
1198 };
1199
1200 struct ocrdma_query_srq {
1201         struct ocrdma_mqe_hdr hdr;
1202         struct ocrdma_mbx_rsp req;
1203
1204         u32 id;
1205 };
1206
1207 enum {
1208         OCRDMA_QUERY_SRQ_RSP_PD_ID_SHIFT        = 0,
1209         OCRDMA_QUERY_SRQ_RSP_PD_ID_MASK         = 0xFFFF,
1210         OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT      = 16,
1211         OCRDMA_QUERY_SRQ_RSP_MAX_RQE_MASK       = 0xFFFF <<
1212                                         OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT,
1213
1214         OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_SHIFT = 0,
1215         OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK  = 0xFFFF,
1216         OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT    = 16,
1217         OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_MASK     = 0xFFFF <<
1218                                         OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT
1219 };
1220
1221 struct ocrdma_query_srq_rsp {
1222         struct ocrdma_mqe_hdr hdr;
1223         struct ocrdma_mbx_rsp req;
1224
1225         u32 max_rqe_pdid;
1226         u32 srq_lmt_max_sge;
1227 };
1228
1229 enum {
1230         OCRDMA_DESTROY_SRQ_ID_SHIFT     = 0,
1231         OCRDMA_DESTROY_SRQ_ID_MASK      = 0xFFFFFF
1232 };
1233
1234 struct ocrdma_destroy_srq {
1235         struct ocrdma_mqe_hdr hdr;
1236         struct ocrdma_mbx_rsp req;
1237
1238         u32 id;
1239 };
1240
1241 enum {
1242         OCRDMA_ALLOC_PD_ENABLE_DPP      = BIT(16),
1243         OCRDMA_DPP_PAGE_SIZE            = 4096
1244 };
1245
1246 struct ocrdma_alloc_pd {
1247         struct ocrdma_mqe_hdr hdr;
1248         struct ocrdma_mbx_hdr req;
1249         u32 enable_dpp_rsvd;
1250 };
1251
1252 enum {
1253         OCRDMA_ALLOC_PD_RSP_DPP                 = Bit(16),
1254         OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT      = 20,
1255         OCRDMA_ALLOC_PD_RSP_PDID_MASK           = 0xFFFF,
1256 };
1257
1258 struct ocrdma_alloc_pd_rsp {
1259         struct ocrdma_mqe_hdr hdr;
1260         struct ocrdma_mbx_rsp rsp;
1261         u32 dpp_page_pdid;
1262 };
1263
1264 struct ocrdma_dealloc_pd {
1265         struct ocrdma_mqe_hdr hdr;
1266         struct ocrdma_mbx_hdr req;
1267         u32 id;
1268 };
1269
1270 struct ocrdma_dealloc_pd_rsp {
1271         struct ocrdma_mqe_hdr hdr;
1272         struct ocrdma_mbx_rsp rsp;
1273 };
1274
1275 enum {
1276         OCRDMA_ADDR_CHECK_ENABLE        = 1,
1277         OCRDMA_ADDR_CHECK_DISABLE       = 0
1278 };
1279
1280 enum {
1281         OCRDMA_ALLOC_LKEY_PD_ID_SHIFT           = 0,
1282         OCRDMA_ALLOC_LKEY_PD_ID_MASK            = 0xFFFF,
1283
1284         OCRDMA_ALLOC_LKEY_ADDR_CHECK_SHIFT      = 0,
1285         OCRDMA_ALLOC_LKEY_ADDR_CHECK_MASK       = Bit(0),
1286         OCRDMA_ALLOC_LKEY_FMR_SHIFT             = 1,
1287         OCRDMA_ALLOC_LKEY_FMR_MASK              = Bit(1),
1288         OCRDMA_ALLOC_LKEY_REMOTE_INV_SHIFT      = 2,
1289         OCRDMA_ALLOC_LKEY_REMOTE_INV_MASK       = Bit(2),
1290         OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT       = 3,
1291         OCRDMA_ALLOC_LKEY_REMOTE_WR_MASK        = Bit(3),
1292         OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT       = 4,
1293         OCRDMA_ALLOC_LKEY_REMOTE_RD_MASK        = Bit(4),
1294         OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT        = 5,
1295         OCRDMA_ALLOC_LKEY_LOCAL_WR_MASK         = Bit(5),
1296         OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_MASK    = Bit(6),
1297         OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT   = 6,
1298         OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT        = 16,
1299         OCRDMA_ALLOC_LKEY_PBL_SIZE_MASK         = 0xFFFF <<
1300                                                 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT
1301 };
1302
1303 struct ocrdma_alloc_lkey {
1304         struct ocrdma_mqe_hdr hdr;
1305         struct ocrdma_mbx_hdr req;
1306
1307         u32 pdid;
1308         u32 pbl_sz_flags;
1309 };
1310
1311 struct ocrdma_alloc_lkey_rsp {
1312         struct ocrdma_mqe_hdr hdr;
1313         struct ocrdma_mbx_rsp rsp;
1314
1315         u32 lrkey;
1316         u32 num_pbl_rsvd;
1317 };
1318
1319 struct ocrdma_dealloc_lkey {
1320         struct ocrdma_mqe_hdr hdr;
1321         struct ocrdma_mbx_hdr req;
1322
1323         u32 lkey;
1324         u32 rsvd_frmr;
1325 };
1326
1327 struct ocrdma_dealloc_lkey_rsp {
1328         struct ocrdma_mqe_hdr hdr;
1329         struct ocrdma_mbx_rsp rsp;
1330 };
1331
1332 #define MAX_OCRDMA_NSMR_PBL    (u32)22
1333 #define MAX_OCRDMA_PBL_SIZE     65536
1334 #define MAX_OCRDMA_PBL_PER_LKEY 32767
1335
1336 enum {
1337         OCRDMA_REG_NSMR_LRKEY_INDEX_SHIFT       = 0,
1338         OCRDMA_REG_NSMR_LRKEY_INDEX_MASK        = 0xFFFFFF,
1339         OCRDMA_REG_NSMR_LRKEY_SHIFT             = 24,
1340         OCRDMA_REG_NSMR_LRKEY_MASK              = 0xFF <<
1341                                         OCRDMA_REG_NSMR_LRKEY_SHIFT,
1342
1343         OCRDMA_REG_NSMR_PD_ID_SHIFT             = 0,
1344         OCRDMA_REG_NSMR_PD_ID_MASK              = 0xFFFF,
1345         OCRDMA_REG_NSMR_NUM_PBL_SHIFT           = 16,
1346         OCRDMA_REG_NSMR_NUM_PBL_MASK            = 0xFFFF <<
1347                                         OCRDMA_REG_NSMR_NUM_PBL_SHIFT,
1348
1349         OCRDMA_REG_NSMR_PBE_SIZE_SHIFT          = 0,
1350         OCRDMA_REG_NSMR_PBE_SIZE_MASK           = 0xFFFF,
1351         OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT        = 16,
1352         OCRDMA_REG_NSMR_HPAGE_SIZE_MASK         = 0xFF <<
1353                                         OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT,
1354         OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT       = 24,
1355         OCRDMA_REG_NSMR_BIND_MEMWIN_MASK        = Bit(24),
1356         OCRDMA_REG_NSMR_ZB_SHIFT                = 25,
1357         OCRDMA_REG_NSMR_ZB_SHIFT_MASK           = Bit(25),
1358         OCRDMA_REG_NSMR_REMOTE_INV_SHIFT        = 26,
1359         OCRDMA_REG_NSMR_REMOTE_INV_MASK         = Bit(26),
1360         OCRDMA_REG_NSMR_REMOTE_WR_SHIFT         = 27,
1361         OCRDMA_REG_NSMR_REMOTE_WR_MASK          = Bit(27),
1362         OCRDMA_REG_NSMR_REMOTE_RD_SHIFT         = 28,
1363         OCRDMA_REG_NSMR_REMOTE_RD_MASK          = Bit(28),
1364         OCRDMA_REG_NSMR_LOCAL_WR_SHIFT          = 29,
1365         OCRDMA_REG_NSMR_LOCAL_WR_MASK           = Bit(29),
1366         OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT     = 30,
1367         OCRDMA_REG_NSMR_REMOTE_ATOMIC_MASK      = Bit(30),
1368         OCRDMA_REG_NSMR_LAST_SHIFT              = 31,
1369         OCRDMA_REG_NSMR_LAST_MASK               = Bit(31)
1370 };
1371
1372 struct ocrdma_reg_nsmr {
1373         struct ocrdma_mqe_hdr hdr;
1374         struct ocrdma_mbx_hdr cmd;
1375
1376         u32 fr_mr;
1377         u32 num_pbl_pdid;
1378         u32 flags_hpage_pbe_sz;
1379         u32 totlen_low;
1380         u32 totlen_high;
1381         u32 fbo_low;
1382         u32 fbo_high;
1383         u32 va_loaddr;
1384         u32 va_hiaddr;
1385         struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL];
1386 };
1387
1388 enum {
1389         OCRDMA_REG_NSMR_CONT_PBL_SHIFT          = 0,
1390         OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK     = 0xFFFF,
1391         OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT      = 16,
1392         OCRDMA_REG_NSMR_CONT_NUM_PBL_MASK       = 0xFFFF <<
1393                                         OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT,
1394
1395         OCRDMA_REG_NSMR_CONT_LAST_SHIFT         = 31,
1396         OCRDMA_REG_NSMR_CONT_LAST_MASK          = Bit(31)
1397 };
1398
1399 struct ocrdma_reg_nsmr_cont {
1400         struct ocrdma_mqe_hdr hdr;
1401         struct ocrdma_mbx_hdr cmd;
1402
1403         u32 lrkey;
1404         u32 num_pbl_offset;
1405         u32 last;
1406
1407         struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL];
1408 };
1409
1410 struct ocrdma_pbe {
1411         u32 pa_hi;
1412         u32 pa_lo;
1413 };
1414
1415 enum {
1416         OCRDMA_REG_NSMR_RSP_NUM_PBL_SHIFT       = 16,
1417         OCRDMA_REG_NSMR_RSP_NUM_PBL_MASK        = 0xFFFF0000
1418 };
1419 struct ocrdma_reg_nsmr_rsp {
1420         struct ocrdma_mqe_hdr hdr;
1421         struct ocrdma_mbx_rsp rsp;
1422
1423         u32 lrkey;
1424         u32 num_pbl;
1425 };
1426
1427 enum {
1428         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_SHIFT      = 0,
1429         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_MASK       = 0xFFFFFF,
1430         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT            = 24,
1431         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_MASK             = 0xFF <<
1432                                         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT,
1433
1434         OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT          = 16,
1435         OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_MASK           = 0xFFFF <<
1436                                         OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT
1437 };
1438
1439 struct ocrdma_reg_nsmr_cont_rsp {
1440         struct ocrdma_mqe_hdr hdr;
1441         struct ocrdma_mbx_rsp rsp;
1442
1443         u32 lrkey_key_index;
1444         u32 num_pbl;
1445 };
1446
1447 enum {
1448         OCRDMA_ALLOC_MW_PD_ID_SHIFT     = 0,
1449         OCRDMA_ALLOC_MW_PD_ID_MASK      = 0xFFFF
1450 };
1451
1452 struct ocrdma_alloc_mw {
1453         struct ocrdma_mqe_hdr hdr;
1454         struct ocrdma_mbx_hdr req;
1455
1456         u32 pdid;
1457 };
1458
1459 enum {
1460         OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_SHIFT   = 0,
1461         OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_MASK    = 0xFFFFFF
1462 };
1463
1464 struct ocrdma_alloc_mw_rsp {
1465         struct ocrdma_mqe_hdr hdr;
1466         struct ocrdma_mbx_rsp rsp;
1467
1468         u32 lrkey_index;
1469 };
1470
1471 struct ocrdma_attach_mcast {
1472         struct ocrdma_mqe_hdr hdr;
1473         struct ocrdma_mbx_hdr req;
1474         u32 qp_id;
1475         u8 mgid[16];
1476         u32 mac_b0_to_b3;
1477         u32 vlan_mac_b4_to_b5;
1478 };
1479
1480 struct ocrdma_attach_mcast_rsp {
1481         struct ocrdma_mqe_hdr hdr;
1482         struct ocrdma_mbx_rsp rsp;
1483 };
1484
1485 struct ocrdma_detach_mcast {
1486         struct ocrdma_mqe_hdr hdr;
1487         struct ocrdma_mbx_hdr req;
1488         u32 qp_id;
1489         u8 mgid[16];
1490         u32 mac_b0_to_b3;
1491         u32 vlan_mac_b4_to_b5;
1492 };
1493
1494 struct ocrdma_detach_mcast_rsp {
1495         struct ocrdma_mqe_hdr hdr;
1496         struct ocrdma_mbx_rsp rsp;
1497 };
1498
1499 enum {
1500         OCRDMA_CREATE_AH_NUM_PAGES_SHIFT        = 19,
1501         OCRDMA_CREATE_AH_NUM_PAGES_MASK         = 0xF <<
1502                                         OCRDMA_CREATE_AH_NUM_PAGES_SHIFT,
1503
1504         OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT        = 16,
1505         OCRDMA_CREATE_AH_PAGE_SIZE_MASK         = 0x7 <<
1506                                         OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT,
1507
1508         OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT       = 23,
1509         OCRDMA_CREATE_AH_ENTRY_SIZE_MASK        = 0x1FF <<
1510                                         OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT,
1511 };
1512
1513 #define OCRDMA_AH_TBL_PAGES 8
1514
1515 struct ocrdma_create_ah_tbl {
1516         struct ocrdma_mqe_hdr hdr;
1517         struct ocrdma_mbx_hdr req;
1518
1519         u32 ah_conf;
1520         struct ocrdma_pa tbl_addr[8];
1521 };
1522
1523 struct ocrdma_create_ah_tbl_rsp {
1524         struct ocrdma_mqe_hdr hdr;
1525         struct ocrdma_mbx_rsp rsp;
1526         u32 ahid;
1527 };
1528
1529 struct ocrdma_delete_ah_tbl {
1530         struct ocrdma_mqe_hdr hdr;
1531         struct ocrdma_mbx_hdr req;
1532         u32 ahid;
1533 };
1534
1535 struct ocrdma_delete_ah_tbl_rsp {
1536         struct ocrdma_mqe_hdr hdr;
1537         struct ocrdma_mbx_rsp rsp;
1538 };
1539
1540 enum {
1541         OCRDMA_EQE_VALID_SHIFT          = 0,
1542         OCRDMA_EQE_VALID_MASK           = Bit(0),
1543         OCRDMA_EQE_FOR_CQE_MASK         = 0xFFFE,
1544         OCRDMA_EQE_RESOURCE_ID_SHIFT    = 16,
1545         OCRDMA_EQE_RESOURCE_ID_MASK     = 0xFFFF <<
1546                                 OCRDMA_EQE_RESOURCE_ID_SHIFT,
1547 };
1548
1549 struct ocrdma_eqe {
1550         u32 id_valid;
1551 };
1552
1553 enum OCRDMA_CQE_STATUS {
1554         OCRDMA_CQE_SUCCESS = 0,
1555         OCRDMA_CQE_LOC_LEN_ERR,
1556         OCRDMA_CQE_LOC_QP_OP_ERR,
1557         OCRDMA_CQE_LOC_EEC_OP_ERR,
1558         OCRDMA_CQE_LOC_PROT_ERR,
1559         OCRDMA_CQE_WR_FLUSH_ERR,
1560         OCRDMA_CQE_MW_BIND_ERR,
1561         OCRDMA_CQE_BAD_RESP_ERR,
1562         OCRDMA_CQE_LOC_ACCESS_ERR,
1563         OCRDMA_CQE_REM_INV_REQ_ERR,
1564         OCRDMA_CQE_REM_ACCESS_ERR,
1565         OCRDMA_CQE_REM_OP_ERR,
1566         OCRDMA_CQE_RETRY_EXC_ERR,
1567         OCRDMA_CQE_RNR_RETRY_EXC_ERR,
1568         OCRDMA_CQE_LOC_RDD_VIOL_ERR,
1569         OCRDMA_CQE_REM_INV_RD_REQ_ERR,
1570         OCRDMA_CQE_REM_ABORT_ERR,
1571         OCRDMA_CQE_INV_EECN_ERR,
1572         OCRDMA_CQE_INV_EEC_STATE_ERR,
1573         OCRDMA_CQE_FATAL_ERR,
1574         OCRDMA_CQE_RESP_TIMEOUT_ERR,
1575         OCRDMA_CQE_GENERAL_ERR
1576 };
1577
1578 enum {
1579         /* w0 */
1580         OCRDMA_CQE_WQEIDX_SHIFT         = 0,
1581         OCRDMA_CQE_WQEIDX_MASK          = 0xFFFF,
1582
1583         /* w1 */
1584         OCRDMA_CQE_UD_XFER_LEN_SHIFT    = 16,
1585         OCRDMA_CQE_PKEY_SHIFT           = 0,
1586         OCRDMA_CQE_PKEY_MASK            = 0xFFFF,
1587
1588         /* w2 */
1589         OCRDMA_CQE_QPN_SHIFT            = 0,
1590         OCRDMA_CQE_QPN_MASK             = 0x0000FFFF,
1591
1592         OCRDMA_CQE_BUFTAG_SHIFT         = 16,
1593         OCRDMA_CQE_BUFTAG_MASK          = 0xFFFF << OCRDMA_CQE_BUFTAG_SHIFT,
1594
1595         /* w3 */
1596         OCRDMA_CQE_UD_STATUS_SHIFT      = 24,
1597         OCRDMA_CQE_UD_STATUS_MASK       = 0x7 << OCRDMA_CQE_UD_STATUS_SHIFT,
1598         OCRDMA_CQE_STATUS_SHIFT         = 16,
1599         OCRDMA_CQE_STATUS_MASK          = 0xFF << OCRDMA_CQE_STATUS_SHIFT,
1600         OCRDMA_CQE_VALID                = Bit(31),
1601         OCRDMA_CQE_INVALIDATE           = Bit(30),
1602         OCRDMA_CQE_QTYPE                = Bit(29),
1603         OCRDMA_CQE_IMM                  = Bit(28),
1604         OCRDMA_CQE_WRITE_IMM            = Bit(27),
1605         OCRDMA_CQE_QTYPE_SQ             = 0,
1606         OCRDMA_CQE_QTYPE_RQ             = 1,
1607         OCRDMA_CQE_SRCQP_MASK           = 0xFFFFFF
1608 };
1609
1610 struct ocrdma_cqe {
1611         union {
1612                 /* w0 to w2 */
1613                 struct {
1614                         u32 wqeidx;
1615                         u32 bytes_xfered;
1616                         u32 qpn;
1617                 } wq;
1618                 struct {
1619                         u32 lkey_immdt;
1620                         u32 rxlen;
1621                         u32 buftag_qpn;
1622                 } rq;
1623                 struct {
1624                         u32 lkey_immdt;
1625                         u32 rxlen_pkey;
1626                         u32 buftag_qpn;
1627                 } ud;
1628                 struct {
1629                         u32 word_0;
1630                         u32 word_1;
1631                         u32 qpn;
1632                 } cmn;
1633         };
1634         u32 flags_status_srcqpn;        /* w3 */
1635 };
1636
1637 struct ocrdma_sge {
1638         u32 addr_hi;
1639         u32 addr_lo;
1640         u32 lrkey;
1641         u32 len;
1642 };
1643
1644 enum {
1645         OCRDMA_FLAG_SIG         = 0x1,
1646         OCRDMA_FLAG_INV         = 0x2,
1647         OCRDMA_FLAG_FENCE_L     = 0x4,
1648         OCRDMA_FLAG_FENCE_R     = 0x8,
1649         OCRDMA_FLAG_SOLICIT     = 0x10,
1650         OCRDMA_FLAG_IMM         = 0x20,
1651
1652         /* Stag flags */
1653         OCRDMA_LKEY_FLAG_LOCAL_WR       = 0x1,
1654         OCRDMA_LKEY_FLAG_REMOTE_RD      = 0x2,
1655         OCRDMA_LKEY_FLAG_REMOTE_WR      = 0x4,
1656         OCRDMA_LKEY_FLAG_VATO           = 0x8,
1657 };
1658
1659 enum OCRDMA_WQE_OPCODE {
1660         OCRDMA_WRITE            = 0x06,
1661         OCRDMA_READ             = 0x0C,
1662         OCRDMA_RESV0            = 0x02,
1663         OCRDMA_SEND             = 0x00,
1664         OCRDMA_CMP_SWP          = 0x14,
1665         OCRDMA_BIND_MW          = 0x10,
1666         OCRDMA_FR_MR            = 0x11,
1667         OCRDMA_RESV1            = 0x0A,
1668         OCRDMA_LKEY_INV         = 0x15,
1669         OCRDMA_FETCH_ADD        = 0x13,
1670         OCRDMA_POST_RQ          = 0x12
1671 };
1672
1673 enum {
1674         OCRDMA_TYPE_INLINE      = 0x0,
1675         OCRDMA_TYPE_LKEY        = 0x1,
1676 };
1677
1678 enum {
1679         OCRDMA_WQE_OPCODE_SHIFT         = 0,
1680         OCRDMA_WQE_OPCODE_MASK          = 0x0000001F,
1681         OCRDMA_WQE_FLAGS_SHIFT          = 5,
1682         OCRDMA_WQE_TYPE_SHIFT           = 16,
1683         OCRDMA_WQE_TYPE_MASK            = 0x00030000,
1684         OCRDMA_WQE_SIZE_SHIFT           = 18,
1685         OCRDMA_WQE_SIZE_MASK            = 0xFF,
1686         OCRDMA_WQE_NXT_WQE_SIZE_SHIFT   = 25,
1687
1688         OCRDMA_WQE_LKEY_FLAGS_SHIFT     = 0,
1689         OCRDMA_WQE_LKEY_FLAGS_MASK      = 0xF
1690 };
1691
1692 /* header WQE for all the SQ and RQ operations */
1693 struct ocrdma_hdr_wqe {
1694         u32 cw;
1695         union {
1696                 u32 rsvd_tag;
1697                 u32 rsvd_lkey_flags;
1698         };
1699         union {
1700                 u32 immdt;
1701                 u32 lkey;
1702         };
1703         u32 total_len;
1704 };
1705
1706 struct ocrdma_ewqe_ud_hdr {
1707         u32 rsvd_dest_qpn;
1708         u32 qkey;
1709         u32 rsvd_ahid;
1710         u32 rsvd;
1711 };
1712
1713 /* extended wqe followed by hdr_wqe for Fast Memory register */
1714 struct ocrdma_ewqe_fr {
1715         u32 va_hi;
1716         u32 va_lo;
1717         u32 fbo_hi;
1718         u32 fbo_lo;
1719         u32 size_sge;
1720         u32 num_sges;
1721         u32 rsvd;
1722         u32 rsvd2;
1723 };
1724
1725 struct ocrdma_eth_basic {
1726         u8 dmac[6];
1727         u8 smac[6];
1728         __be16 eth_type;
1729 } __packed;
1730
1731 struct ocrdma_eth_vlan {
1732         u8 dmac[6];
1733         u8 smac[6];
1734         __be16 eth_type;
1735         __be16 vlan_tag;
1736 #define OCRDMA_ROCE_ETH_TYPE 0x8915
1737         __be16 roce_eth_type;
1738 } __packed;
1739
1740 struct ocrdma_grh {
1741         __be32  tclass_flow;
1742         __be32  pdid_hoplimit;
1743         u8      sgid[16];
1744         u8      dgid[16];
1745         u16     rsvd;
1746 } __packed;
1747
1748 #define OCRDMA_AV_VALID         Bit(7)
1749 #define OCRDMA_AV_VLAN_VALID    Bit(1)
1750
1751 struct ocrdma_av {
1752         struct ocrdma_eth_vlan eth_hdr;
1753         struct ocrdma_grh grh;
1754         u32 valid;
1755 } __packed;
1756
1757 struct ocrdma_rsrc_stats {
1758         u32 dpp_pds;
1759         u32 non_dpp_pds;
1760         u32 rc_dpp_qps;
1761         u32 uc_dpp_qps;
1762         u32 ud_dpp_qps;
1763         u32 rc_non_dpp_qps;
1764         u32 rsvd;
1765         u32 uc_non_dpp_qps;
1766         u32 ud_non_dpp_qps;
1767         u32 rsvd1;
1768         u32 srqs;
1769         u32 rbqs;
1770         u32 r64K_nsmr;
1771         u32 r64K_to_2M_nsmr;
1772         u32 r2M_to_44M_nsmr;
1773         u32 r44M_to_1G_nsmr;
1774         u32 r1G_to_4G_nsmr;
1775         u32 nsmr_count_4G_to_32G;
1776         u32 r32G_to_64G_nsmr;
1777         u32 r64G_to_128G_nsmr;
1778         u32 r128G_to_higher_nsmr;
1779         u32 embedded_nsmr;
1780         u32 frmr;
1781         u32 prefetch_qps;
1782         u32 ondemand_qps;
1783         u32 phy_mr;
1784         u32 mw;
1785         u32 rsvd2[7];
1786 };
1787
1788 struct ocrdma_db_err_stats {
1789         u32 sq_doorbell_errors;
1790         u32 cq_doorbell_errors;
1791         u32 rq_srq_doorbell_errors;
1792         u32 cq_overflow_errors;
1793         u32 rsvd[4];
1794 };
1795
1796 struct ocrdma_wqe_stats {
1797         u32 large_send_rc_wqes_lo;
1798         u32 large_send_rc_wqes_hi;
1799         u32 large_write_rc_wqes_lo;
1800         u32 large_write_rc_wqes_hi;
1801         u32 rsvd[4];
1802         u32 read_wqes_lo;
1803         u32 read_wqes_hi;
1804         u32 frmr_wqes_lo;
1805         u32 frmr_wqes_hi;
1806         u32 mw_bind_wqes_lo;
1807         u32 mw_bind_wqes_hi;
1808         u32 invalidate_wqes_lo;
1809         u32 invalidate_wqes_hi;
1810         u32 rsvd1[2];
1811         u32 dpp_wqe_drops;
1812         u32 rsvd2[5];
1813 };
1814
1815 struct ocrdma_tx_stats {
1816         u32 send_pkts_lo;
1817         u32 send_pkts_hi;
1818         u32 write_pkts_lo;
1819         u32 write_pkts_hi;
1820         u32 read_pkts_lo;
1821         u32 read_pkts_hi;
1822         u32 read_rsp_pkts_lo;
1823         u32 read_rsp_pkts_hi;
1824         u32 ack_pkts_lo;
1825         u32 ack_pkts_hi;
1826         u32 send_bytes_lo;
1827         u32 send_bytes_hi;
1828         u32 write_bytes_lo;
1829         u32 write_bytes_hi;
1830         u32 read_req_bytes_lo;
1831         u32 read_req_bytes_hi;
1832         u32 read_rsp_bytes_lo;
1833         u32 read_rsp_bytes_hi;
1834         u32 ack_timeouts;
1835         u32 rsvd[5];
1836 };
1837
1838
1839 struct ocrdma_tx_qp_err_stats {
1840         u32 local_length_errors;
1841         u32 local_protection_errors;
1842         u32 local_qp_operation_errors;
1843         u32 retry_count_exceeded_errors;
1844         u32 rnr_retry_count_exceeded_errors;
1845         u32 rsvd[3];
1846 };
1847
1848 struct ocrdma_rx_stats {
1849         u32 roce_frame_bytes_lo;
1850         u32 roce_frame_bytes_hi;
1851         u32 roce_frame_icrc_drops;
1852         u32 roce_frame_payload_len_drops;
1853         u32 ud_drops;
1854         u32 qp1_drops;
1855         u32 psn_error_request_packets;
1856         u32 psn_error_resp_packets;
1857         u32 rnr_nak_timeouts;
1858         u32 rnr_nak_receives;
1859         u32 roce_frame_rxmt_drops;
1860         u32 nak_count_psn_sequence_errors;
1861         u32 rc_drop_count_lookup_errors;
1862         u32 rq_rnr_naks;
1863         u32 srq_rnr_naks;
1864         u32 roce_frames_lo;
1865         u32 roce_frames_hi;
1866         u32 rsvd;
1867 };
1868
1869 struct ocrdma_rx_qp_err_stats {
1870         u32 nak_invalid_requst_errors;
1871         u32 nak_remote_operation_errors;
1872         u32 nak_count_remote_access_errors;
1873         u32 local_length_errors;
1874         u32 local_protection_errors;
1875         u32 local_qp_operation_errors;
1876         u32 rsvd[2];
1877 };
1878
1879 struct ocrdma_tx_dbg_stats {
1880         u32 data[100];
1881 };
1882
1883 struct ocrdma_rx_dbg_stats {
1884         u32 data[200];
1885 };
1886
1887 struct ocrdma_rdma_stats_req {
1888         struct ocrdma_mbx_hdr hdr;
1889         u8 reset_stats;
1890         u8 rsvd[3];
1891 } __packed;
1892
1893 struct ocrdma_rdma_stats_resp {
1894         struct ocrdma_mbx_hdr hdr;
1895         struct ocrdma_rsrc_stats act_rsrc_stats;
1896         struct ocrdma_rsrc_stats th_rsrc_stats;
1897         struct ocrdma_db_err_stats      db_err_stats;
1898         struct ocrdma_wqe_stats         wqe_stats;
1899         struct ocrdma_tx_stats          tx_stats;
1900         struct ocrdma_tx_qp_err_stats   tx_qp_err_stats;
1901         struct ocrdma_rx_stats          rx_stats;
1902         struct ocrdma_rx_qp_err_stats   rx_qp_err_stats;
1903         struct ocrdma_tx_dbg_stats      tx_dbg_stats;
1904         struct ocrdma_rx_dbg_stats      rx_dbg_stats;
1905 } __packed;
1906
1907
1908 struct mgmt_hba_attribs {
1909         u8 flashrom_version_string[32];
1910         u8 manufacturer_name[32];
1911         u32 supported_modes;
1912         u32 rsvd0[3];
1913         u8 ncsi_ver_string[12];
1914         u32 default_extended_timeout;
1915         u8 controller_model_number[32];
1916         u8 controller_description[64];
1917         u8 controller_serial_number[32];
1918         u8 ip_version_string[32];
1919         u8 firmware_version_string[32];
1920         u8 bios_version_string[32];
1921         u8 redboot_version_string[32];
1922         u8 driver_version_string[32];
1923         u8 fw_on_flash_version_string[32];
1924         u32 functionalities_supported;
1925         u16 max_cdblength;
1926         u8 asic_revision;
1927         u8 generational_guid[16];
1928         u8 hba_port_count;
1929         u16 default_link_down_timeout;
1930         u8 iscsi_ver_min_max;
1931         u8 multifunction_device;
1932         u8 cache_valid;
1933         u8 hba_status;
1934         u8 max_domains_supported;
1935         u8 phy_port;
1936         u32 firmware_post_status;
1937         u32 hba_mtu[8];
1938         u32 rsvd1[4];
1939 };
1940
1941 struct mgmt_controller_attrib {
1942         struct mgmt_hba_attribs hba_attribs;
1943         u16 pci_vendor_id;
1944         u16 pci_device_id;
1945         u16 pci_sub_vendor_id;
1946         u16 pci_sub_system_id;
1947         u8 pci_bus_number;
1948         u8 pci_device_number;
1949         u8 pci_function_number;
1950         u8 interface_type;
1951         u64 unique_identifier;
1952         u32 rsvd0[5];
1953 };
1954
1955 struct ocrdma_get_ctrl_attribs_rsp {
1956         struct ocrdma_mbx_hdr hdr;
1957         struct mgmt_controller_attrib ctrl_attribs;
1958 };
1959
1960 #define OCRDMA_SUBSYS_DCBX 0x10
1961
1962 enum OCRDMA_DCBX_OPCODE {
1963         OCRDMA_CMD_GET_DCBX_CONFIG = 0x01
1964 };
1965
1966 enum OCRDMA_DCBX_PARAM_TYPE {
1967         OCRDMA_PARAMETER_TYPE_ADMIN     = 0x00,
1968         OCRDMA_PARAMETER_TYPE_OPER      = 0x01,
1969         OCRDMA_PARAMETER_TYPE_PEER      = 0x02
1970 };
1971
1972 enum OCRDMA_DCBX_APP_PROTO {
1973         OCRDMA_APP_PROTO_ROCE   = 0x8915
1974 };
1975
1976 enum OCRDMA_DCBX_PROTO {
1977         OCRDMA_PROTO_SELECT_L2  = 0x00,
1978         OCRDMA_PROTO_SELECT_L4  = 0x01
1979 };
1980
1981 enum OCRDMA_DCBX_APP_PARAM {
1982         OCRDMA_APP_PARAM_APP_PROTO_MASK = 0xFFFF,
1983         OCRDMA_APP_PARAM_PROTO_SEL_MASK = 0xFF,
1984         OCRDMA_APP_PARAM_PROTO_SEL_SHIFT = 0x10,
1985         OCRDMA_APP_PARAM_VALID_MASK     = 0xFF,
1986         OCRDMA_APP_PARAM_VALID_SHIFT    = 0x18
1987 };
1988
1989 enum OCRDMA_DCBX_STATE_FLAGS {
1990         OCRDMA_STATE_FLAG_ENABLED       = 0x01,
1991         OCRDMA_STATE_FLAG_ADDVERTISED   = 0x02,
1992         OCRDMA_STATE_FLAG_WILLING       = 0x04,
1993         OCRDMA_STATE_FLAG_SYNC          = 0x08,
1994         OCRDMA_STATE_FLAG_UNSUPPORTED   = 0x40000000,
1995         OCRDMA_STATE_FLAG_NEG_FAILD     = 0x80000000
1996 };
1997
1998 enum OCRDMA_TCV_AEV_OPV_ST {
1999         OCRDMA_DCBX_TC_SUPPORT_MASK     = 0xFF,
2000         OCRDMA_DCBX_TC_SUPPORT_SHIFT    = 0x18,
2001         OCRDMA_DCBX_APP_ENTRY_SHIFT     = 0x10,
2002         OCRDMA_DCBX_OP_PARAM_SHIFT      = 0x08,
2003         OCRDMA_DCBX_STATE_MASK          = 0xFF
2004 };
2005
2006 struct ocrdma_app_parameter {
2007         u32 valid_proto_app;
2008         u32 oui;
2009         u32 app_prio[2];
2010 };
2011
2012 struct ocrdma_dcbx_cfg {
2013         u32 tcv_aev_opv_st;
2014         u32 tc_state;
2015         u32 pfc_state;
2016         u32 qcn_state;
2017         u32 appl_state;
2018         u32 ll_state;
2019         u32 tc_bw[2];
2020         u32 tc_prio[8];
2021         u32 pfc_prio[2];
2022         struct ocrdma_app_parameter app_param[15];
2023 };
2024
2025 struct ocrdma_get_dcbx_cfg_req {
2026         struct ocrdma_mbx_hdr hdr;
2027         u32 param_type;
2028 } __packed;
2029
2030 struct ocrdma_get_dcbx_cfg_rsp {
2031         struct ocrdma_mbx_rsp hdr;
2032         struct ocrdma_dcbx_cfg cfg;
2033 } __packed;
2034
2035 #endif                          /* __OCRDMA_SLI_H__ */