drivers/iommu/intel-iommu.c

   1 /*
   2  * Copyright © 2006-2014 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * Authors: David Woodhouse <dwmw2@infradead.org>,
  14  *          Ashok Raj <ashok.raj@intel.com>,
  15  *          Shaohua Li <shaohua.li@intel.com>,
  16  *          Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>,
  17  *          Fenghua Yu <fenghua.yu@intel.com>
  18  *          Joerg Roedel <jroedel@suse.de>
  19  */
  20
  21 #define pr_fmt(fmt)     "DMAR: " fmt
  22
  23 #include <linux/init.h>
  24 #include <linux/bitmap.h>
  25 #include <linux/debugfs.h>
  26 #include <linux/export.h>
  27 #include <linux/slab.h>
  28 #include <linux/irq.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/pci.h>
  32 #include <linux/dmar.h>
  33 #include <linux/dma-mapping.h>
  34 #include <linux/mempool.h>
  35 #include <linux/memory.h>
  36 #include <linux/timer.h>
  37 #include <linux/io.h>
  38 #include <linux/iova.h>
  39 #include <linux/iommu.h>
  40 #include <linux/intel-iommu.h>
  41 #include <linux/syscore_ops.h>
  42 #include <linux/tboot.h>
  43 #include <linux/dmi.h>
  44 #include <linux/pci-ats.h>
  45 #include <linux/memblock.h>
  46 #include <linux/dma-contiguous.h>
  47 #include <linux/crash_dump.h>
  48 #include <asm/irq_remapping.h>
  49 #include <asm/cacheflush.h>
  50 #include <asm/iommu.h>
  51
  52 #include "irq_remapping.h"
  53
  54 #define ROOT_SIZE               VTD_PAGE_SIZE
  55 #define CONTEXT_SIZE            VTD_PAGE_SIZE
  56
  57 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
  58 #define IS_USB_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_SERIAL_USB)
  59 #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
  60 #define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
  61
  62 #define IOAPIC_RANGE_START      (0xfee00000)
  63 #define IOAPIC_RANGE_END        (0xfeefffff)
  64 #define IOVA_START_ADDR         (0x1000)
  65
  66 #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
  67
  68 #define MAX_AGAW_WIDTH 64
  69 #define MAX_AGAW_PFN_WIDTH      (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT)
  70
  71 #define __DOMAIN_MAX_PFN(gaw)  ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
  72 #define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1)
  73
  74 /* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR
  75    to match. That way, we can use 'unsigned long' for PFNs with impunity. */
  76 #define DOMAIN_MAX_PFN(gaw)     ((unsigned long) min_t(uint64_t, \
  77                                 __DOMAIN_MAX_PFN(gaw), (unsigned long)-1))
  78 #define DOMAIN_MAX_ADDR(gaw)    (((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT)
  79
  80 /* IO virtual address start page frame number */
  81 #define IOVA_START_PFN          (1)
  82
  83 #define IOVA_PFN(addr)          ((addr) >> PAGE_SHIFT)
  84 #define DMA_32BIT_PFN           IOVA_PFN(DMA_BIT_MASK(32))
  85 #define DMA_64BIT_PFN           IOVA_PFN(DMA_BIT_MASK(64))
  86
  87 /* page table handling */
  88 #define LEVEL_STRIDE            (9)
  89 #define LEVEL_MASK              (((u64)1 << LEVEL_STRIDE) - 1)
  90
  91 /*
  92  * This bitmap is used to advertise the page sizes our hardware support
  93  * to the IOMMU core, which will then use this information to split
  94  * physically contiguous memory regions it is mapping into page sizes
  95  * that we support.
  96  *
  97  * Traditionally the IOMMU core just handed us the mappings directly,
  98  * after making sure the size is an order of a 4KiB page and that the
  99  * mapping has natural alignment.
 100  *
 101  * To retain this behavior, we currently advertise that we support
 102  * all page sizes that are an order of 4KiB.
 103  *
 104  * If at some point we'd like to utilize the IOMMU core's new behavior,
 105  * we could change this to advertise the real page sizes we support.
 106  */
 107 #define INTEL_IOMMU_PGSIZES     (~0xFFFUL)
 108
 109 static inline int agaw_to_level(int agaw)
 110 {
 111         return agaw + 2;
 112 }
 113
 114 static inline int agaw_to_width(int agaw)
 115 {
 116         return min_t(int, 30 + agaw * LEVEL_STRIDE, MAX_AGAW_WIDTH);
 117 }
 118
 119 static inline int width_to_agaw(int width)
 120 {
 121         return DIV_ROUND_UP(width - 30, LEVEL_STRIDE);
 122 }
 123
 124 static inline unsigned int level_to_offset_bits(int level)
 125 {
 126         return (level - 1) * LEVEL_STRIDE;
 127 }
 128
 129 static inline int pfn_level_offset(unsigned long pfn, int level)
 130 {
 131         return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
 132 }
 133
 134 static inline unsigned long level_mask(int level)
 135 {
 136         return -1UL << level_to_offset_bits(level);
 137 }
 138
 139 static inline unsigned long level_size(int level)
 140 {
 141         return 1UL << level_to_offset_bits(level);
 142 }
 143
 144 static inline unsigned long align_to_level(unsigned long pfn, int level)
 145 {
 146         return (pfn + level_size(level) - 1) & level_mask(level);
 147 }
 148
 149 static inline unsigned long lvl_to_nr_pages(unsigned int lvl)
 150 {
 151         return  1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);
 152 }
 153
 154 /* VT-d pages must always be _smaller_ than MM pages. Otherwise things
 155    are never going to work. */
 156 static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
 157 {
 158         return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
 159 }
 160
 161 static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
 162 {
 163         return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
 164 }
 165 static inline unsigned long page_to_dma_pfn(struct page *pg)
 166 {
 167         return mm_to_dma_pfn(page_to_pfn(pg));
 168 }
 169 static inline unsigned long virt_to_dma_pfn(void *p)
 170 {
 171         return page_to_dma_pfn(virt_to_page(p));
 172 }
 173
 174 /* global iommu list, set NULL for ignored DMAR units */
 175 static struct intel_iommu **g_iommus;
 176
 177 static void __init check_tylersburg_isoch(void);
 178 static int rwbf_quirk;
 179
 180 /*
 181  * set to 1 to panic kernel if can't successfully enable VT-d
 182  * (used when kernel is launched w/ TXT)
 183  */
 184 static int force_on = 0;
 185
 186 /*
 187  * 0: Present
 188  * 1-11: Reserved
 189  * 12-63: Context Ptr (12 - (haw-1))
 190  * 64-127: Reserved
 191  */
 192 struct root_entry {
 193         u64     lo;
 194         u64     hi;
 195 };
 196 #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
 197
 198 /*
 199  * Take a root_entry and return the Lower Context Table Pointer (LCTP)
 200  * if marked present.
 201  */
 202 static phys_addr_t root_entry_lctp(struct root_entry *re)
 203 {
 204         if (!(re->lo & 1))
 205                 return 0;
 206
 207         return re->lo & VTD_PAGE_MASK;
 208 }
 209
 210 /*
 211  * Take a root_entry and return the Upper Context Table Pointer (UCTP)
 212  * if marked present.
 213  */
 214 static phys_addr_t root_entry_uctp(struct root_entry *re)
 215 {
 216         if (!(re->hi & 1))
 217                 return 0;
 218
 219         return re->hi & VTD_PAGE_MASK;
 220 }
 221 /*
 222  * low 64 bits:
 223  * 0: present
 224  * 1: fault processing disable
 225  * 2-3: translation type
 226  * 12-63: address space root
 227  * high 64 bits:
 228  * 0-2: address width
 229  * 3-6: aval
 230  * 8-23: domain id
 231  */
 232 struct context_entry {
 233         u64 lo;
 234         u64 hi;
 235 };
 236
 237 static inline void context_clear_pasid_enable(struct context_entry *context)
 238 {
 239         context->lo &= ~(1ULL << 11);
 240 }
 241
 242 static inline bool context_pasid_enabled(struct context_entry *context)
 243 {
 244         return !!(context->lo & (1ULL << 11));
 245 }
 246
 247 static inline void context_set_copied(struct context_entry *context)
 248 {
 249         context->hi |= (1ull << 3);
 250 }
 251
 252 static inline bool context_copied(struct context_entry *context)
 253 {
 254         return !!(context->hi & (1ULL << 3));
 255 }
 256
 257 static inline bool __context_present(struct context_entry *context)
 258 {
 259         return (context->lo & 1);
 260 }
 261
 262 static inline bool context_present(struct context_entry *context)
 263 {
 264         return context_pasid_enabled(context) ?
 265              __context_present(context) :
 266              __context_present(context) && !context_copied(context);
 267 }
 268
 269 static inline void context_set_present(struct context_entry *context)
 270 {
 271         context->lo |= 1;
 272 }
 273
 274 static inline void context_set_fault_enable(struct context_entry *context)
 275 {
 276         context->lo &= (((u64)-1) << 2) | 1;
 277 }
 278
 279 static inline void context_set_translation_type(struct context_entry *context,
 280                                                 unsigned long value)
 281 {
 282         context->lo &= (((u64)-1) << 4) | 3;
 283         context->lo |= (value & 3) << 2;
 284 }
 285
 286 static inline void context_set_address_root(struct context_entry *context,
 287                                             unsigned long value)
 288 {
 289         context->lo &= ~VTD_PAGE_MASK;
 290         context->lo |= value & VTD_PAGE_MASK;
 291 }
 292
 293 static inline void context_set_address_width(struct context_entry *context,
 294                                              unsigned long value)
 295 {
 296         context->hi |= value & 7;
 297 }
 298
 299 static inline void context_set_domain_id(struct context_entry *context,
 300                                          unsigned long value)
 301 {
 302         context->hi |= (value & ((1 << 16) - 1)) << 8;
 303 }
 304
 305 static inline int context_domain_id(struct context_entry *c)
 306 {
 307         return((c->hi >> 8) & 0xffff);
 308 }
 309
 310 static inline void context_clear_entry(struct context_entry *context)
 311 {
 312         context->lo = 0;
 313         context->hi = 0;
 314 }
 315
 316 /*
 317  * 0: readable
 318  * 1: writable
 319  * 2-6: reserved
 320  * 7: super page
 321  * 8-10: available
 322  * 11: snoop behavior
 323  * 12-63: Host physcial address
 324  */
 325 struct dma_pte {
 326         u64 val;
 327 };
 328
 329 static inline void dma_clear_pte(struct dma_pte *pte)
 330 {
 331         pte->val = 0;
 332 }
 333
 334 static inline u64 dma_pte_addr(struct dma_pte *pte)
 335 {
 336 #ifdef CONFIG_64BIT
 337         return pte->val & VTD_PAGE_MASK;
 338 #else
 339         /* Must have a full atomic 64-bit read */
 340         return  __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
 341 #endif
 342 }
 343
 344 static inline bool dma_pte_present(struct dma_pte *pte)
 345 {
 346         return (pte->val & 3) != 0;
 347 }
 348
 349 static inline bool dma_pte_superpage(struct dma_pte *pte)
 350 {
 351         return (pte->val & DMA_PTE_LARGE_PAGE);
 352 }
 353
 354 static inline int first_pte_in_page(struct dma_pte *pte)
 355 {
 356         return !((unsigned long)pte & ~VTD_PAGE_MASK);
 357 }
 358
 359 /*
 360  * This domain is a statically identity mapping domain.
 361  *      1. This domain creats a static 1:1 mapping to all usable memory.
 362  *      2. It maps to each iommu if successful.
 363  *      3. Each iommu mapps to this domain if successful.
 364  */
 365 static struct dmar_domain *si_domain;
 366 static int hw_pass_through = 1;
 367
 368 /*
 369  * Domain represents a virtual machine, more than one devices
 370  * across iommus may be owned in one domain, e.g. kvm guest.
 371  */
 372 #define DOMAIN_FLAG_VIRTUAL_MACHINE     (1 << 0)
 373
 374 /* si_domain contains mulitple devices */
 375 #define DOMAIN_FLAG_STATIC_IDENTITY     (1 << 1)
 376
 377 #define for_each_domain_iommu(idx, domain)                      \
 378         for (idx = 0; idx < g_num_of_iommus; idx++)             \
 379                 if (domain->iommu_refcnt[idx])
 380
 381 struct dmar_domain {
 382         int     nid;                    /* node id */
 383
 384         unsigned        iommu_refcnt[DMAR_UNITS_SUPPORTED];
 385                                         /* Refcount of devices per iommu */
 386
 387
 388         u16             iommu_did[DMAR_UNITS_SUPPORTED];
 389                                         /* Domain ids per IOMMU. Use u16 since
 390                                          * domain ids are 16 bit wide according
 391                                          * to VT-d spec, section 9.3 */
 392
 393         struct list_head devices;       /* all devices' list */
 394         struct iova_domain iovad;       /* iova's that belong to this domain */
 395
 396         struct dma_pte  *pgd;           /* virtual address */
 397         int             gaw;            /* max guest address width */
 398
 399         /* adjusted guest address width, 0 is level 2 30-bit */
 400         int             agaw;
 401
 402         int             flags;          /* flags to find out type of domain */
 403
 404         int             iommu_coherency;/* indicate coherency of iommu access */
 405         int             iommu_snooping; /* indicate snooping control feature*/
 406         int             iommu_count;    /* reference count of iommu */
 407         int             iommu_superpage;/* Level of superpages supported:
 408                                            0 == 4KiB (no superpages), 1 == 2MiB,
 409                                            2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
 410         u64             max_addr;       /* maximum mapped address */
 411
 412         struct iommu_domain domain;     /* generic domain data structure for
 413                                            iommu core */
 414 };
 415
 416 /* PCI domain-device relationship */
 417 struct device_domain_info {
 418         struct list_head link;  /* link to domain siblings */
 419         struct list_head global; /* link to global list */
 420         u8 bus;                 /* PCI bus number */
 421         u8 devfn;               /* PCI devfn number */
 422         struct {
 423                 u8 enabled:1;
 424                 u8 qdep;
 425         } ats;                  /* ATS state */
 426         struct device *dev; /* it's NULL for PCIe-to-PCI bridge */
 427         struct intel_iommu *iommu; /* IOMMU used by this device */
 428         struct dmar_domain *domain; /* pointer to domain */
 429 };
 430
 431 struct dmar_rmrr_unit {
 432         struct list_head list;          /* list of rmrr units   */
 433         struct acpi_dmar_header *hdr;   /* ACPI header          */
 434         u64     base_address;           /* reserved base address*/
 435         u64     end_address;            /* reserved end address */
 436         struct dmar_dev_scope *devices; /* target devices */
 437         int     devices_cnt;            /* target device count */
 438 };
 439
 440 struct dmar_atsr_unit {
 441         struct list_head list;          /* list of ATSR units */
 442         struct acpi_dmar_header *hdr;   /* ACPI header */
 443         struct dmar_dev_scope *devices; /* target devices */
 444         int devices_cnt;                /* target device count */
 445         u8 include_all:1;               /* include all ports */
 446 };
 447
 448 static LIST_HEAD(dmar_atsr_units);
 449 static LIST_HEAD(dmar_rmrr_units);
 450
 451 #define for_each_rmrr_units(rmrr) \
 452         list_for_each_entry(rmrr, &dmar_rmrr_units, list)
 453
 454 static void flush_unmaps_timeout(unsigned long data);
 455
 456 static DEFINE_TIMER(unmap_timer,  flush_unmaps_timeout, 0, 0);
 457
 458 #define HIGH_WATER_MARK 250
 459 struct deferred_flush_tables {
 460         int next;
 461         struct iova *iova[HIGH_WATER_MARK];
 462         struct dmar_domain *domain[HIGH_WATER_MARK];
 463         struct page *freelist[HIGH_WATER_MARK];
 464 };
 465
 466 static struct deferred_flush_tables *deferred_flush;
 467
 468 /* bitmap for indexing intel_iommus */
 469 static int g_num_of_iommus;
 470
 471 static DEFINE_SPINLOCK(async_umap_flush_lock);
 472 static LIST_HEAD(unmaps_to_do);
 473
 474 static int timer_on;
 475 static long list_size;
 476
 477 static void domain_exit(struct dmar_domain *domain);
 478 static void domain_remove_dev_info(struct dmar_domain *domain);
 479 static void dmar_remove_one_dev_info(struct dmar_domain *domain,
 480                                      struct device *dev);
 481 static void __dmar_remove_one_dev_info(struct device_domain_info *info);
 482 static void domain_context_clear(struct intel_iommu *iommu,
 483                                  struct device *dev);
 484 static int domain_detach_iommu(struct dmar_domain *domain,
 485                                struct intel_iommu *iommu);
 486
 487 #ifdef CONFIG_INTEL_IOMMU_DEFAULT_ON
 488 int dmar_disabled = 0;
 489 #else
 490 int dmar_disabled = 1;
 491 #endif /*CONFIG_INTEL_IOMMU_DEFAULT_ON*/
 492
 493 int intel_iommu_enabled = 0;
 494 EXPORT_SYMBOL_GPL(intel_iommu_enabled);
 495
 496 static int dmar_map_gfx = 1;
 497 static int dmar_forcedac;
 498 static int intel_iommu_strict;
 499 static int intel_iommu_superpage = 1;
 500 static int intel_iommu_ecs = 1;
 501
 502 /* We only actually use ECS when PASID support (on the new bit 40)
 503  * is also advertised. Some early implementations — the ones with
 504  * PASID support on bit 28 — have issues even when we *only* use
 505  * extended root/context tables. */
 506 #define ecs_enabled(iommu) (intel_iommu_ecs && ecap_ecs(iommu->ecap) && \
 507                             ecap_pasid(iommu->ecap))
 508
 509 int intel_iommu_gfx_mapped;
 510 EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);
 511
 512 #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
 513 static DEFINE_SPINLOCK(device_domain_lock);
 514 static LIST_HEAD(device_domain_list);
 515
 516 static const struct iommu_ops intel_iommu_ops;
 517
 518 static bool translation_pre_enabled(struct intel_iommu *iommu)
 519 {
 520         return (iommu->flags & VTD_FLAG_TRANS_PRE_ENABLED);
 521 }
 522
 523 static void clear_translation_pre_enabled(struct intel_iommu *iommu)
 524 {
 525         iommu->flags &= ~VTD_FLAG_TRANS_PRE_ENABLED;
 526 }
 527
 528 static void init_translation_status(struct intel_iommu *iommu)
 529 {
 530         u32 gsts;
 531
 532         gsts = readl(iommu->reg + DMAR_GSTS_REG);
 533         if (gsts & DMA_GSTS_TES)
 534                 iommu->flags |= VTD_FLAG_TRANS_PRE_ENABLED;
 535 }
 536
 537 /* Convert generic 'struct iommu_domain to private struct dmar_domain */
 538 static struct dmar_domain *to_dmar_domain(struct iommu_domain *dom)
 539 {
 540         return container_of(dom, struct dmar_domain, domain);
 541 }
 542
 543 static int __init intel_iommu_setup(char *str)
 544 {
 545         if (!str)
 546                 return -EINVAL;
 547         while (*str) {
 548                 if (!strncmp(str, "on", 2)) {
 549                         dmar_disabled = 0;
 550                         pr_info("IOMMU enabled\n");
 551                 } else if (!strncmp(str, "off", 3)) {
 552                         dmar_disabled = 1;
 553                         pr_info("IOMMU disabled\n");
 554                 } else if (!strncmp(str, "igfx_off", 8)) {
 555                         dmar_map_gfx = 0;
 556                         pr_info("Disable GFX device mapping\n");
 557                 } else if (!strncmp(str, "forcedac", 8)) {
 558                         pr_info("Forcing DAC for PCI devices\n");
 559                         dmar_forcedac = 1;
 560                 } else if (!strncmp(str, "strict", 6)) {
 561                         pr_info("Disable batched IOTLB flush\n");
 562                         intel_iommu_strict = 1;
 563                 } else if (!strncmp(str, "sp_off", 6)) {
 564                         pr_info("Disable supported super page\n");
 565                         intel_iommu_superpage = 0;
 566                 } else if (!strncmp(str, "ecs_off", 7)) {
 567                         printk(KERN_INFO
 568                                 "Intel-IOMMU: disable extended context table support\n");
 569                         intel_iommu_ecs = 0;
 570                 }
 571
 572                 str += strcspn(str, ",");
 573                 while (*str == ',')
 574                         str++;
 575         }
 576         return 0;
 577 }
 578 __setup("intel_iommu=", intel_iommu_setup);
 579
 580 static struct kmem_cache *iommu_domain_cache;
 581 static struct kmem_cache *iommu_devinfo_cache;
 582
 583 static struct dmar_domain* get_iommu_domain(struct intel_iommu *iommu, u16 did)
 584 {
 585         struct dmar_domain **domains;
 586         int idx = did >> 8;
 587
 588         domains = iommu->domains[idx];
 589         if (!domains)
 590                 return NULL;
 591
 592         return domains[did & 0xff];
 593 }
 594
 595 static void set_iommu_domain(struct intel_iommu *iommu, u16 did,
 596                              struct dmar_domain *domain)
 597 {
 598         struct dmar_domain **domains;
 599         int idx = did >> 8;
 600
 601         if (!iommu->domains[idx]) {
 602                 size_t size = 256 * sizeof(struct dmar_domain *);
 603                 iommu->domains[idx] = kzalloc(size, GFP_ATOMIC);
 604         }
 605
 606         domains = iommu->domains[idx];
 607         if (WARN_ON(!domains))
 608                 return;
 609         else
 610                 domains[did & 0xff] = domain;
 611 }
 612
 613 static inline void *alloc_pgtable_page(int node)
 614 {
 615         struct page *page;
 616         void *vaddr = NULL;
 617
 618         page = alloc_pages_node(node, GFP_ATOMIC | __GFP_ZERO, 0);
 619         if (page)
 620                 vaddr = page_address(page);
 621         return vaddr;
 622 }
 623
 624 static inline void free_pgtable_page(void *vaddr)
 625 {
 626         free_page((unsigned long)vaddr);
 627 }
 628
 629 static inline void *alloc_domain_mem(void)
 630 {
 631         return kmem_cache_alloc(iommu_domain_cache, GFP_ATOMIC);
 632 }
 633
 634 static void free_domain_mem(void *vaddr)
 635 {
 636         kmem_cache_free(iommu_domain_cache, vaddr);
 637 }
 638
 639 static inline void * alloc_devinfo_mem(void)
 640 {
 641         return kmem_cache_alloc(iommu_devinfo_cache, GFP_ATOMIC);
 642 }
 643
 644 static inline void free_devinfo_mem(void *vaddr)
 645 {
 646         kmem_cache_free(iommu_devinfo_cache, vaddr);
 647 }
 648
 649 static inline int domain_type_is_vm(struct dmar_domain *domain)
 650 {
 651         return domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE;
 652 }
 653
 654 static inline int domain_type_is_si(struct dmar_domain *domain)
 655 {
 656         return domain->flags & DOMAIN_FLAG_STATIC_IDENTITY;
 657 }
 658
 659 static inline int domain_type_is_vm_or_si(struct dmar_domain *domain)
 660 {
 661         return domain->flags & (DOMAIN_FLAG_VIRTUAL_MACHINE |
 662                                 DOMAIN_FLAG_STATIC_IDENTITY);
 663 }
 664
 665 static inline int domain_pfn_supported(struct dmar_domain *domain,
 666                                        unsigned long pfn)
 667 {
 668         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
 669
 670         return !(addr_width < BITS_PER_LONG && pfn >> addr_width);
 671 }
 672
 673 static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
 674 {
 675         unsigned long sagaw;
 676         int agaw = -1;
 677
 678         sagaw = cap_sagaw(iommu->cap);
 679         for (agaw = width_to_agaw(max_gaw);
 680              agaw >= 0; agaw--) {
 681                 if (test_bit(agaw, &sagaw))
 682                         break;
 683         }
 684
 685         return agaw;
 686 }
 687
 688 /*
 689  * Calculate max SAGAW for each iommu.
 690  */
 691 int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
 692 {
 693         return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
 694 }
 695
 696 /*
 697  * calculate agaw for each iommu.
 698  * "SAGAW" may be different across iommus, use a default agaw, and
 699  * get a supported less agaw for iommus that don't support the default agaw.
 700  */
 701 int iommu_calculate_agaw(struct intel_iommu *iommu)
 702 {
 703         return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
 704 }
 705
 706 /* This functionin only returns single iommu in a domain */
 707 static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
 708 {
 709         int iommu_id;
 710
 711         /* si_domain and vm domain should not get here. */
 712         BUG_ON(domain_type_is_vm_or_si(domain));
 713         for_each_domain_iommu(iommu_id, domain)
 714                 break;
 715
 716         if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
 717                 return NULL;
 718
 719         return g_iommus[iommu_id];
 720 }
 721
 722 static void domain_update_iommu_coherency(struct dmar_domain *domain)
 723 {
 724         struct dmar_drhd_unit *drhd;
 725         struct intel_iommu *iommu;
 726         bool found = false;
 727         int i;
 728
 729         domain->iommu_coherency = 1;
 730
 731         for_each_domain_iommu(i, domain) {
 732                 found = true;
 733                 if (!ecap_coherent(g_iommus[i]->ecap)) {
 734                         domain->iommu_coherency = 0;
 735                         break;
 736                 }
 737         }
 738         if (found)
 739                 return;
 740
 741         /* No hardware attached; use lowest common denominator */
 742         rcu_read_lock();
 743         for_each_active_iommu(iommu, drhd) {
 744                 if (!ecap_coherent(iommu->ecap)) {
 745                         domain->iommu_coherency = 0;
 746                         break;
 747                 }
 748         }
 749         rcu_read_unlock();
 750 }
 751
 752 static int domain_update_iommu_snooping(struct intel_iommu *skip)
 753 {
 754         struct dmar_drhd_unit *drhd;
 755         struct intel_iommu *iommu;
 756         int ret = 1;
 757
 758         rcu_read_lock();
 759         for_each_active_iommu(iommu, drhd) {
 760                 if (iommu != skip) {
 761                         if (!ecap_sc_support(iommu->ecap)) {
 762                                 ret = 0;
 763                                 break;
 764                         }
 765                 }
 766         }
 767         rcu_read_unlock();
 768
 769         return ret;
 770 }
 771
 772 static int domain_update_iommu_superpage(struct intel_iommu *skip)
 773 {
 774         struct dmar_drhd_unit *drhd;
 775         struct intel_iommu *iommu;
 776         int mask = 0xf;
 777
 778         if (!intel_iommu_superpage) {
 779                 return 0;
 780         }
 781
 782         /* set iommu_superpage to the smallest common denominator */
 783         rcu_read_lock();
 784         for_each_active_iommu(iommu, drhd) {
 785                 if (iommu != skip) {
 786                         mask &= cap_super_page_val(iommu->cap);
 787                         if (!mask)
 788                                 break;
 789                 }
 790         }
 791         rcu_read_unlock();
 792
 793         return fls(mask);
 794 }
 795
 796 /* Some capabilities may be different across iommus */
 797 static void domain_update_iommu_cap(struct dmar_domain *domain)
 798 {
 799         domain_update_iommu_coherency(domain);
 800         domain->iommu_snooping = domain_update_iommu_snooping(NULL);
 801         domain->iommu_superpage = domain_update_iommu_superpage(NULL);
 802 }
 803
 804 static inline struct context_entry *iommu_context_addr(struct intel_iommu *iommu,
 805                                                        u8 bus, u8 devfn, int alloc)
 806 {
 807         struct root_entry *root = &iommu->root_entry[bus];
 808         struct context_entry *context;
 809         u64 *entry;
 810
 811         entry = &root->lo;
 812         if (ecs_enabled(iommu)) {
 813                 if (devfn >= 0x80) {
 814                         devfn -= 0x80;
 815                         entry = &root->hi;
 816                 }
 817                 devfn *= 2;
 818         }
 819         if (*entry & 1)
 820                 context = phys_to_virt(*entry & VTD_PAGE_MASK);
 821         else {
 822                 unsigned long phy_addr;
 823                 if (!alloc)
 824                         return NULL;
 825
 826                 context = alloc_pgtable_page(iommu->node);
 827                 if (!context)
 828                         return NULL;
 829
 830                 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
 831                 phy_addr = virt_to_phys((void *)context);
 832                 *entry = phy_addr | 1;
 833                 __iommu_flush_cache(iommu, entry, sizeof(*entry));
 834         }
 835         return &context[devfn];
 836 }
 837
 838 static int iommu_dummy(struct device *dev)
 839 {
 840         return dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
 841 }
 842
 843 static struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn)
 844 {
 845         struct dmar_drhd_unit *drhd = NULL;
 846         struct intel_iommu *iommu;
 847         struct device *tmp;
 848         struct pci_dev *ptmp, *pdev = NULL;
 849         u16 segment = 0;
 850         int i;
 851
 852         if (iommu_dummy(dev))
 853                 return NULL;
 854
 855         if (dev_is_pci(dev)) {
 856                 pdev = to_pci_dev(dev);
 857                 segment = pci_domain_nr(pdev->bus);
 858         } else if (has_acpi_companion(dev))
 859                 dev = &ACPI_COMPANION(dev)->dev;
 860
 861         rcu_read_lock();
 862         for_each_active_iommu(iommu, drhd) {
 863                 if (pdev && segment != drhd->segment)
 864                         continue;
 865
 866                 for_each_active_dev_scope(drhd->devices,
 867                                           drhd->devices_cnt, i, tmp) {
 868                         if (tmp == dev) {
 869                                 *bus = drhd->devices[i].bus;
 870                                 *devfn = drhd->devices[i].devfn;
 871                                 goto out;
 872                         }
 873
 874                         if (!pdev || !dev_is_pci(tmp))
 875                                 continue;
 876
 877                         ptmp = to_pci_dev(tmp);
 878                         if (ptmp->subordinate &&
 879                             ptmp->subordinate->number <= pdev->bus->number &&
 880                             ptmp->subordinate->busn_res.end >= pdev->bus->number)
 881                                 goto got_pdev;
 882                 }
 883
 884                 if (pdev && drhd->include_all) {
 885                 got_pdev:
 886                         *bus = pdev->bus->number;
 887                         *devfn = pdev->devfn;
 888                         goto out;
 889                 }
 890         }
 891         iommu = NULL;
 892  out:
 893         rcu_read_unlock();
 894
 895         return iommu;
 896 }
 897
 898 static void domain_flush_cache(struct dmar_domain *domain,
 899                                void *addr, int size)
 900 {
 901         if (!domain->iommu_coherency)
 902                 clflush_cache_range(addr, size);
 903 }
 904
 905 static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
 906 {
 907         struct context_entry *context;
 908         int ret = 0;
 909         unsigned long flags;
 910
 911         spin_lock_irqsave(&iommu->lock, flags);
 912         context = iommu_context_addr(iommu, bus, devfn, 0);
 913         if (context)
 914                 ret = context_present(context);
 915         spin_unlock_irqrestore(&iommu->lock, flags);
 916         return ret;
 917 }
 918
 919 static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
 920 {
 921         struct context_entry *context;
 922         unsigned long flags;
 923
 924         spin_lock_irqsave(&iommu->lock, flags);
 925         context = iommu_context_addr(iommu, bus, devfn, 0);
 926         if (context) {
 927                 context_clear_entry(context);
 928                 __iommu_flush_cache(iommu, context, sizeof(*context));
 929         }
 930         spin_unlock_irqrestore(&iommu->lock, flags);
 931 }
 932
 933 static void free_context_table(struct intel_iommu *iommu)
 934 {
 935         int i;
 936         unsigned long flags;
 937         struct context_entry *context;
 938
 939         spin_lock_irqsave(&iommu->lock, flags);
 940         if (!iommu->root_entry) {
 941                 goto out;
 942         }
 943         for (i = 0; i < ROOT_ENTRY_NR; i++) {
 944                 context = iommu_context_addr(iommu, i, 0, 0);
 945                 if (context)
 946                         free_pgtable_page(context);
 947
 948                 if (!ecs_enabled(iommu))
 949                         continue;
 950
 951                 context = iommu_context_addr(iommu, i, 0x80, 0);
 952                 if (context)
 953                         free_pgtable_page(context);
 954
 955         }
 956         free_pgtable_page(iommu->root_entry);
 957         iommu->root_entry = NULL;
 958 out:
 959         spin_unlock_irqrestore(&iommu->lock, flags);
 960 }
 961
 962 static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
 963                                       unsigned long pfn, int *target_level)
 964 {
 965         struct dma_pte *parent, *pte = NULL;
 966         int level = agaw_to_level(domain->agaw);
 967         int offset;
 968
 969         BUG_ON(!domain->pgd);
 970
 971         if (!domain_pfn_supported(domain, pfn))
 972                 /* Address beyond IOMMU's addressing capabilities. */
 973                 return NULL;
 974
 975         parent = domain->pgd;
 976
 977         while (1) {
 978                 void *tmp_page;
 979
 980                 offset = pfn_level_offset(pfn, level);
 981                 pte = &parent[offset];
 982                 if (!*target_level && (dma_pte_superpage(pte) || !dma_pte_present(pte)))
 983                         break;
 984                 if (level == *target_level)
 985                         break;
 986
 987                 if (!dma_pte_present(pte)) {
 988                         uint64_t pteval;
 989
 990                         tmp_page = alloc_pgtable_page(domain->nid);
 991
 992                         if (!tmp_page)
 993                                 return NULL;
 994
 995                         domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
 996                         pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
 997                         if (cmpxchg64(&pte->val, 0ULL, pteval))
 998                                 /* Someone else set it while we were thinking; use theirs. */
 999                                 free_pgtable_page(tmp_page);
1000                         else
1001                                 domain_flush_cache(domain, pte, sizeof(*pte));
1002                 }
1003                 if (level == 1)
1004                         break;
1005
1006                 parent = phys_to_virt(dma_pte_addr(pte));
1007                 level--;
1008         }
1009
1010         if (!*target_level)
1011                 *target_level = level;
1012
1013         return pte;
1014 }
1015
1016
1017 /* return address's pte at specific level */
1018 static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
1019                                          unsigned long pfn,
1020                                          int level, int *large_page)
1021 {
1022         struct dma_pte *parent, *pte = NULL;
1023         int total = agaw_to_level(domain->agaw);
1024         int offset;
1025
1026         parent = domain->pgd;
1027         while (level <= total) {
1028                 offset = pfn_level_offset(pfn, total);
1029                 pte = &parent[offset];
1030                 if (level == total)
1031                         return pte;
1032
1033                 if (!dma_pte_present(pte)) {
1034                         *large_page = total;
1035                         break;
1036                 }
1037
1038                 if (dma_pte_superpage(pte)) {
1039                         *large_page = total;
1040                         return pte;
1041                 }
1042
1043                 parent = phys_to_virt(dma_pte_addr(pte));
1044                 total--;
1045         }
1046         return NULL;
1047 }
1048
1049 /* clear last level pte, a tlb flush should be followed */
1050 static void dma_pte_clear_range(struct dmar_domain *domain,
1051                                 unsigned long start_pfn,
1052                                 unsigned long last_pfn)
1053 {
1054         unsigned int large_page = 1;
1055         struct dma_pte *first_pte, *pte;
1056
1057         BUG_ON(!domain_pfn_supported(domain, start_pfn));
1058         BUG_ON(!domain_pfn_supported(domain, last_pfn));
1059         BUG_ON(start_pfn > last_pfn);
1060
1061         /* we don't need lock here; nobody else touches the iova range */
1062         do {
1063                 large_page = 1;
1064                 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page);
1065                 if (!pte) {
1066                         start_pfn = align_to_level(start_pfn + 1, large_page + 1);
1067                         continue;
1068                 }
1069                 do {
1070                         dma_clear_pte(pte);
1071                         start_pfn += lvl_to_nr_pages(large_page);
1072                         pte++;
1073                 } while (start_pfn <= last_pfn && !first_pte_in_page(pte));
1074
1075                 domain_flush_cache(domain, first_pte,
1076                                    (void *)pte - (void *)first_pte);
1077
1078         } while (start_pfn && start_pfn <= last_pfn);
1079 }
1080
1081 static void dma_pte_free_level(struct dmar_domain *domain, int level,
1082                                struct dma_pte *pte, unsigned long pfn,
1083                                unsigned long start_pfn, unsigned long last_pfn)
1084 {
1085         pfn = max(start_pfn, pfn);
1086         pte = &pte[pfn_level_offset(pfn, level)];
1087
1088         do {
1089                 unsigned long level_pfn;
1090                 struct dma_pte *level_pte;
1091
1092                 if (!dma_pte_present(pte) || dma_pte_superpage(pte))
1093                         goto next;
1094
1095                 level_pfn = pfn & level_mask(level - 1);
1096                 level_pte = phys_to_virt(dma_pte_addr(pte));
1097
1098                 if (level > 2)
1099                         dma_pte_free_level(domain, level - 1, level_pte,
1100                                            level_pfn, start_pfn, last_pfn);
1101
1102                 /* If range covers entire pagetable, free it */
1103                 if (!(start_pfn > level_pfn ||
1104                       last_pfn < level_pfn + level_size(level) - 1)) {
1105                         dma_clear_pte(pte);
1106                         domain_flush_cache(domain, pte, sizeof(*pte));
1107                         free_pgtable_page(level_pte);
1108                 }
1109 next:
1110                 pfn += level_size(level);
1111         } while (!first_pte_in_page(++pte) && pfn <= last_pfn);
1112 }
1113
1114 /* free page table pages. last level pte should already be cleared */
1115 static void dma_pte_free_pagetable(struct dmar_domain *domain,
1116                                    unsigned long start_pfn,
1117                                    unsigned long last_pfn)
1118 {
1119         BUG_ON(!domain_pfn_supported(domain, start_pfn));
1120         BUG_ON(!domain_pfn_supported(domain, last_pfn));
1121         BUG_ON(start_pfn > last_pfn);
1122
1123         dma_pte_clear_range(domain, start_pfn, last_pfn);
1124
1125         /* We don't need lock here; nobody else touches the iova range */
1126         dma_pte_free_level(domain, agaw_to_level(domain->agaw),
1127                            domain->pgd, 0, start_pfn, last_pfn);
1128
1129         /* free pgd */
1130         if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
1131                 free_pgtable_page(domain->pgd);
1132                 domain->pgd = NULL;
1133         }
1134 }
1135
1136 /* When a page at a given level is being unlinked from its parent, we don't
1137    need to *modify* it at all. All we need to do is make a list of all the
1138    pages which can be freed just as soon as we've flushed the IOTLB and we
1139    know the hardware page-walk will no longer touch them.
1140    The 'pte' argument is the *parent* PTE, pointing to the page that is to
1141    be freed. */
1142 static struct page *dma_pte_list_pagetables(struct dmar_domain *domain,
1143                                             int level, struct dma_pte *pte,
1144                                             struct page *freelist)
1145 {
1146         struct page *pg;
1147
1148         pg = pfn_to_page(dma_pte_addr(pte) >> PAGE_SHIFT);
1149         pg->freelist = freelist;
1150         freelist = pg;
1151
1152         if (level == 1)
1153                 return freelist;
1154
1155         pte = page_address(pg);
1156         do {
1157                 if (dma_pte_present(pte) && !dma_pte_superpage(pte))
1158                         freelist = dma_pte_list_pagetables(domain, level - 1,
1159                                                            pte, freelist);
1160                 pte++;
1161         } while (!first_pte_in_page(pte));
1162
1163         return freelist;
1164 }
1165
1166 static struct page *dma_pte_clear_level(struct dmar_domain *domain, int level,
1167                                         struct dma_pte *pte, unsigned long pfn,
1168                                         unsigned long start_pfn,
1169                                         unsigned long last_pfn,
1170                                         struct page *freelist)
1171 {
1172         struct dma_pte *first_pte = NULL, *last_pte = NULL;
1173
1174         pfn = max(start_pfn, pfn);
1175         pte = &pte[pfn_level_offset(pfn, level)];
1176
1177         do {
1178                 unsigned long level_pfn;
1179
1180                 if (!dma_pte_present(pte))
1181                         goto next;
1182
1183                 level_pfn = pfn & level_mask(level);
1184
1185                 /* If range covers entire pagetable, free it */
1186                 if (start_pfn <= level_pfn &&
1187                     last_pfn >= level_pfn + level_size(level) - 1) {
1188                         /* These suborbinate page tables are going away entirely. Don't
1189                            bother to clear them; we're just going to *free* them. */
1190                         if (level > 1 && !dma_pte_superpage(pte))
1191                                 freelist = dma_pte_list_pagetables(domain, level - 1, pte, freelist);
1192
1193                         dma_clear_pte(pte);
1194                         if (!first_pte)
1195                                 first_pte = pte;
1196                         last_pte = pte;
1197                 } else if (level > 1) {
1198                         /* Recurse down into a level that isn't *entirely* obsolete */
1199                         freelist = dma_pte_clear_level(domain, level - 1,
1200                                                        phys_to_virt(dma_pte_addr(pte)),
1201                                                        level_pfn, start_pfn, last_pfn,
1202                                                        freelist);
1203                 }
1204 next:
1205                 pfn += level_size(level);
1206         } while (!first_pte_in_page(++pte) && pfn <= last_pfn);
1207
1208         if (first_pte)
1209                 domain_flush_cache(domain, first_pte,
1210                                    (void *)++last_pte - (void *)first_pte);
1211
1212         return freelist;
1213 }
1214
1215 /* We can't just free the pages because the IOMMU may still be walking
1216    the page tables, and may have cached the intermediate levels. The
1217    pages can only be freed after the IOTLB flush has been done. */
1218 static struct page *domain_unmap(struct dmar_domain *domain,
1219                                  unsigned long start_pfn,
1220                                  unsigned long last_pfn)
1221 {
1222         struct page *freelist = NULL;
1223
1224         BUG_ON(!domain_pfn_supported(domain, start_pfn));
1225         BUG_ON(!domain_pfn_supported(domain, last_pfn));
1226         BUG_ON(start_pfn > last_pfn);
1227
1228         /* we don't need lock here; nobody else touches the iova range */
1229         freelist = dma_pte_clear_level(domain, agaw_to_level(domain->agaw),
1230                                        domain->pgd, 0, start_pfn, last_pfn, NULL);
1231
1232         /* free pgd */
1233         if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
1234                 struct page *pgd_page = virt_to_page(domain->pgd);
1235                 pgd_page->freelist = freelist;
1236                 freelist = pgd_page;
1237
1238                 domain->pgd = NULL;
1239         }
1240
1241         return freelist;
1242 }
1243
1244 static void dma_free_pagelist(struct page *freelist)
1245 {
1246         struct page *pg;
1247
1248         while ((pg = freelist)) {
1249                 freelist = pg->freelist;
1250                 free_pgtable_page(page_address(pg));
1251         }
1252 }
1253
1254 /* iommu handling */
1255 static int iommu_alloc_root_entry(struct intel_iommu *iommu)
1256 {
1257         struct root_entry *root;
1258         unsigned long flags;
1259
1260         root = (struct root_entry *)alloc_pgtable_page(iommu->node);
1261         if (!root) {
1262                 pr_err("Allocating root entry for %s failed\n",
1263                         iommu->name);
1264                 return -ENOMEM;
1265         }
1266
1267         __iommu_flush_cache(iommu, root, ROOT_SIZE);
1268
1269         spin_lock_irqsave(&iommu->lock, flags);
1270         iommu->root_entry = root;
1271         spin_unlock_irqrestore(&iommu->lock, flags);
1272
1273         return 0;
1274 }
1275
1276 static void iommu_set_root_entry(struct intel_iommu *iommu)
1277 {
1278         u64 addr;
1279         u32 sts;
1280         unsigned long flag;
1281
1282         addr = virt_to_phys(iommu->root_entry);
1283         if (ecs_enabled(iommu))
1284                 addr |= DMA_RTADDR_RTT;
1285
1286         raw_spin_lock_irqsave(&iommu->register_lock, flag);
1287         dmar_writeq(iommu->reg + DMAR_RTADDR_REG, addr);
1288
1289         writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
1290
1291         /* Make sure hardware complete it */
1292         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1293                       readl, (sts & DMA_GSTS_RTPS), sts);
1294
1295         raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1296 }
1297
1298 static void iommu_flush_write_buffer(struct intel_iommu *iommu)
1299 {
1300         u32 val;
1301         unsigned long flag;
1302
1303         if (!rwbf_quirk && !cap_rwbf(iommu->cap))
1304                 return;
1305
1306         raw_spin_lock_irqsave(&iommu->register_lock, flag);
1307         writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
1308
1309         /* Make sure hardware complete it */
1310         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1311                       readl, (!(val & DMA_GSTS_WBFS)), val);
1312
1313         raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1314 }
1315
1316 /* return value determine if we need a write buffer flush */
1317 static void __iommu_flush_context(struct intel_iommu *iommu,
1318                                   u16 did, u16 source_id, u8 function_mask,
1319                                   u64 type)
1320 {
1321         u64 val = 0;
1322         unsigned long flag;
1323
1324         switch (type) {
1325         case DMA_CCMD_GLOBAL_INVL:
1326                 val = DMA_CCMD_GLOBAL_INVL;
1327                 break;
1328         case DMA_CCMD_DOMAIN_INVL:
1329                 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
1330                 break;
1331         case DMA_CCMD_DEVICE_INVL:
1332                 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
1333                         | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
1334                 break;
1335         default:
1336                 BUG();
1337         }
1338         val |= DMA_CCMD_ICC;
1339
1340         raw_spin_lock_irqsave(&iommu->register_lock, flag);
1341         dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
1342
1343         /* Make sure hardware complete it */
1344         IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
1345                 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
1346
1347         raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1348 }
1349
1350 /* return value determine if we need a write buffer flush */
1351 static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
1352                                 u64 addr, unsigned int size_order, u64 type)
1353 {
1354         int tlb_offset = ecap_iotlb_offset(iommu->ecap);
1355         u64 val = 0, val_iva = 0;
1356         unsigned long flag;
1357
1358         switch (type) {
1359         case DMA_TLB_GLOBAL_FLUSH:
1360                 /* global flush doesn't need set IVA_REG */
1361                 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
1362                 break;
1363         case DMA_TLB_DSI_FLUSH:
1364                 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
1365                 break;
1366         case DMA_TLB_PSI_FLUSH:
1367                 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
1368                 /* IH bit is passed in as part of address */
1369                 val_iva = size_order | addr;
1370                 break;
1371         default:
1372                 BUG();
1373         }
1374         /* Note: set drain read/write */
1375 #if 0
1376         /*
1377          * This is probably to be super secure.. Looks like we can
1378          * ignore it without any impact.
1379          */
1380         if (cap_read_drain(iommu->cap))
1381                 val |= DMA_TLB_READ_DRAIN;
1382 #endif
1383         if (cap_write_drain(iommu->cap))
1384                 val |= DMA_TLB_WRITE_DRAIN;
1385
1386         raw_spin_lock_irqsave(&iommu->register_lock, flag);
1387         /* Note: Only uses first TLB reg currently */
1388         if (val_iva)
1389                 dmar_writeq(iommu->reg + tlb_offset, val_iva);
1390         dmar_writeq(iommu->reg + tlb_offset + 8, val);
1391
1392         /* Make sure hardware complete it */
1393         IOMMU_WAIT_OP(iommu, tlb_offset + 8,
1394                 dmar_readq, (!(val & DMA_TLB_IVT)), val);
1395
1396         raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1397
1398         /* check IOTLB invalidation granularity */
1399         if (DMA_TLB_IAIG(val) == 0)
1400                 pr_err("Flush IOTLB failed\n");
1401         if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
1402                 pr_debug("TLB flush request %Lx, actual %Lx\n",
1403                         (unsigned long long)DMA_TLB_IIRG(type),
1404                         (unsigned long long)DMA_TLB_IAIG(val));
1405 }
1406
1407 static struct device_domain_info *
1408 iommu_support_dev_iotlb (struct dmar_domain *domain, struct intel_iommu *iommu,
1409                          u8 bus, u8 devfn)
1410 {
1411         bool found = false;
1412         struct device_domain_info *info;
1413         struct pci_dev *pdev;
1414
1415         assert_spin_locked(&device_domain_lock);
1416
1417         if (!ecap_dev_iotlb_support(iommu->ecap))
1418                 return NULL;
1419
1420         if (!iommu->qi)
1421                 return NULL;
1422
1423         list_for_each_entry(info, &domain->devices, link)
1424                 if (info->iommu == iommu && info->bus == bus &&
1425                     info->devfn == devfn) {
1426                         found = true;
1427                         break;
1428                 }
1429
1430         if (!found || !info->dev || !dev_is_pci(info->dev))
1431                 return NULL;
1432
1433         pdev = to_pci_dev(info->dev);
1434
1435         if (!pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS))
1436                 return NULL;
1437
1438         if (!dmar_find_matched_atsr_unit(pdev))
1439                 return NULL;
1440
1441         return info;
1442 }
1443
1444 static void iommu_enable_dev_iotlb(struct device_domain_info *info)
1445 {
1446         struct pci_dev *pdev;
1447
1448         if (!info || !dev_is_pci(info->dev))
1449                 return;
1450
1451         pdev = to_pci_dev(info->dev);
1452         if (pci_enable_ats(pdev, VTD_PAGE_SHIFT))
1453                 return;
1454
1455         info->ats.enabled = 1;
1456         info->ats.qdep = pci_ats_queue_depth(pdev);
1457 }
1458
1459 static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1460 {
1461         if (!info->ats.enabled)
1462                 return;
1463
1464         pci_disable_ats(to_pci_dev(info->dev));
1465         info->ats.enabled = 0;
1466 }
1467
1468 static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1469                                   u64 addr, unsigned mask)
1470 {
1471         u16 sid, qdep;
1472         unsigned long flags;
1473         struct device_domain_info *info;
1474
1475         spin_lock_irqsave(&device_domain_lock, flags);
1476         list_for_each_entry(info, &domain->devices, link) {
1477                 if (!info->ats.enabled)
1478                         continue;
1479
1480                 sid = info->bus << 8 | info->devfn;
1481                 qdep = info->ats.qdep;
1482                 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1483         }
1484         spin_unlock_irqrestore(&device_domain_lock, flags);
1485 }
1486
1487 static void iommu_flush_iotlb_psi(struct intel_iommu *iommu,
1488                                   struct dmar_domain *domain,
1489                                   unsigned long pfn, unsigned int pages,
1490                                   int ih, int map)
1491 {
1492         unsigned int mask = ilog2(__roundup_pow_of_two(pages));
1493         uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
1494         u16 did = domain->iommu_did[iommu->seq_id];
1495
1496         BUG_ON(pages == 0);
1497
1498         if (ih)
1499                 ih = 1 << 6;
1500         /*
1501          * Fallback to domain selective flush if no PSI support or the size is
1502          * too big.
1503          * PSI requires page size to be 2 ^ x, and the base address is naturally
1504          * aligned to the size
1505          */
1506         if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1507                 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1508                                                 DMA_TLB_DSI_FLUSH);
1509         else
1510                 iommu->flush.flush_iotlb(iommu, did, addr | ih, mask,
1511                                                 DMA_TLB_PSI_FLUSH);
1512
1513         /*
1514          * In caching mode, changes of pages from non-present to present require
1515          * flush. However, device IOTLB doesn't need to be flushed in this case.
1516          */
1517         if (!cap_caching_mode(iommu->cap) || !map)
1518                 iommu_flush_dev_iotlb(get_iommu_domain(iommu, did),
1519                                       addr, mask);
1520 }
1521
1522 static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1523 {
1524         u32 pmen;
1525         unsigned long flags;
1526
1527         raw_spin_lock_irqsave(&iommu->register_lock, flags);
1528         pmen = readl(iommu->reg + DMAR_PMEN_REG);
1529         pmen &= ~DMA_PMEN_EPM;
1530         writel(pmen, iommu->reg + DMAR_PMEN_REG);
1531
1532         /* wait for the protected region status bit to clear */
1533         IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1534                 readl, !(pmen & DMA_PMEN_PRS), pmen);
1535
1536         raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1537 }
1538
1539 static void iommu_enable_translation(struct intel_iommu *iommu)
1540 {
1541         u32 sts;
1542         unsigned long flags;
1543
1544         raw_spin_lock_irqsave(&iommu->register_lock, flags);
1545         iommu->gcmd |= DMA_GCMD_TE;
1546         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1547
1548         /* Make sure hardware complete it */
1549         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1550                       readl, (sts & DMA_GSTS_TES), sts);
1551
1552         raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1553 }
1554
1555 static void iommu_disable_translation(struct intel_iommu *iommu)
1556 {
1557         u32 sts;
1558         unsigned long flag;
1559
1560         raw_spin_lock_irqsave(&iommu->register_lock, flag);
1561         iommu->gcmd &= ~DMA_GCMD_TE;
1562         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1563
1564         /* Make sure hardware complete it */
1565         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1566                       readl, (!(sts & DMA_GSTS_TES)), sts);
1567
1568         raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1569 }
1570
1571
1572 static int iommu_init_domains(struct intel_iommu *iommu)
1573 {
1574         u32 ndomains, nlongs;
1575         size_t size;
1576
1577         ndomains = cap_ndoms(iommu->cap);
1578         pr_debug("%s: Number of Domains supported <%d>\n",
1579                  iommu->name, ndomains);
1580         nlongs = BITS_TO_LONGS(ndomains);
1581
1582         spin_lock_init(&iommu->lock);
1583
1584         iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1585         if (!iommu->domain_ids) {
1586                 pr_err("%s: Allocating domain id array failed\n",
1587                        iommu->name);
1588                 return -ENOMEM;
1589         }
1590
1591         size = ((ndomains >> 8) + 1) * sizeof(struct dmar_domain **);
1592         iommu->domains = kzalloc(size, GFP_KERNEL);
1593
1594         if (iommu->domains) {
1595                 size = 256 * sizeof(struct dmar_domain *);
1596                 iommu->domains[0] = kzalloc(size, GFP_KERNEL);
1597         }
1598
1599         if (!iommu->domains || !iommu->domains[0]) {
1600                 pr_err("%s: Allocating domain array failed\n",
1601                        iommu->name);
1602                 kfree(iommu->domain_ids);
1603                 kfree(iommu->domains);
1604                 iommu->domain_ids = NULL;
1605                 iommu->domains    = NULL;
1606                 return -ENOMEM;
1607         }
1608
1609
1610
1611         /*
1612          * If Caching mode is set, then invalid translations are tagged
1613          * with domain-id 0, hence we need to pre-allocate it. We also
1614          * use domain-id 0 as a marker for non-allocated domain-id, so
1615          * make sure it is not used for a real domain.
1616          */
1617         set_bit(0, iommu->domain_ids);
1618
1619         return 0;
1620 }
1621
1622 static void disable_dmar_iommu(struct intel_iommu *iommu)
1623 {
1624         struct device_domain_info *info, *tmp;
1625         unsigned long flags;
1626
1627         if (!iommu->domains || !iommu->domain_ids)
1628                 return;
1629
1630         spin_lock_irqsave(&device_domain_lock, flags);
1631         list_for_each_entry_safe(info, tmp, &device_domain_list, global) {
1632                 struct dmar_domain *domain;
1633
1634                 if (info->iommu != iommu)
1635                         continue;
1636
1637                 if (!info->dev || !info->domain)
1638                         continue;
1639
1640                 domain = info->domain;
1641
1642                 dmar_remove_one_dev_info(domain, info->dev);
1643
1644                 if (!domain_type_is_vm_or_si(domain))
1645                         domain_exit(domain);
1646         }
1647         spin_unlock_irqrestore(&device_domain_lock, flags);
1648
1649         if (iommu->gcmd & DMA_GCMD_TE)
1650                 iommu_disable_translation(iommu);
1651 }
1652
1653 static void free_dmar_iommu(struct intel_iommu *iommu)
1654 {
1655         if ((iommu->domains) && (iommu->domain_ids)) {
1656                 int elems = (cap_ndoms(iommu->cap) >> 8) + 1;
1657                 int i;
1658
1659                 for (i = 0; i < elems; i++)
1660                         kfree(iommu->domains[i]);
1661                 kfree(iommu->domains);
1662                 kfree(iommu->domain_ids);
1663                 iommu->domains = NULL;
1664                 iommu->domain_ids = NULL;
1665         }
1666
1667         g_iommus[iommu->seq_id] = NULL;
1668
1669         /* free context mapping */
1670         free_context_table(iommu);
1671 }
1672
1673 static struct dmar_domain *alloc_domain(int flags)
1674 {
1675         struct dmar_domain *domain;
1676
1677         domain = alloc_domain_mem();
1678         if (!domain)
1679                 return NULL;
1680
1681         memset(domain, 0, sizeof(*domain));
1682         domain->nid = -1;
1683         domain->flags = flags;
1684         INIT_LIST_HEAD(&domain->devices);
1685
1686         return domain;
1687 }
1688
1689 /* Must be called with iommu->lock */
1690 static int domain_attach_iommu(struct dmar_domain *domain,
1691                                struct intel_iommu *iommu)
1692 {
1693         unsigned long ndomains;
1694         int num;
1695
1696         assert_spin_locked(&device_domain_lock);
1697         assert_spin_locked(&iommu->lock);
1698
1699         domain->iommu_refcnt[iommu->seq_id] += 1;
1700         domain->iommu_count += 1;
1701         if (domain->iommu_refcnt[iommu->seq_id] == 1) {
1702                 ndomains = cap_ndoms(iommu->cap);
1703                 num      = find_first_zero_bit(iommu->domain_ids, ndomains);
1704
1705                 if (num >= ndomains) {
1706                         pr_err("%s: No free domain ids\n", iommu->name);
1707                         domain->iommu_refcnt[iommu->seq_id] -= 1;
1708                         domain->iommu_count -= 1;
1709                         return -ENOSPC;
1710                 }
1711
1712                 set_bit(num, iommu->domain_ids);
1713                 set_iommu_domain(iommu, num, domain);
1714
1715                 domain->iommu_did[iommu->seq_id] = num;
1716                 domain->nid                      = iommu->node;
1717
1718                 domain_update_iommu_cap(domain);
1719         }
1720
1721         return 0;
1722 }
1723
1724 static int domain_detach_iommu(struct dmar_domain *domain,
1725                                struct intel_iommu *iommu)
1726 {
1727         int num, count = INT_MAX;
1728
1729         assert_spin_locked(&device_domain_lock);
1730         assert_spin_locked(&iommu->lock);
1731
1732         domain->iommu_refcnt[iommu->seq_id] -= 1;
1733         count = --domain->iommu_count;
1734         if (domain->iommu_refcnt[iommu->seq_id] == 0) {
1735                 num = domain->iommu_did[iommu->seq_id];
1736                 clear_bit(num, iommu->domain_ids);
1737                 set_iommu_domain(iommu, num, NULL);
1738
1739                 domain_update_iommu_cap(domain);
1740                 domain->iommu_did[iommu->seq_id] = 0;
1741         }
1742
1743         return count;
1744 }
1745
1746 static struct iova_domain reserved_iova_list;
1747 static struct lock_class_key reserved_rbtree_key;
1748
1749 static int dmar_init_reserved_ranges(void)
1750 {
1751         struct pci_dev *pdev = NULL;
1752         struct iova *iova;
1753         int i;
1754
1755         init_iova_domain(&reserved_iova_list, VTD_PAGE_SIZE, IOVA_START_PFN,
1756                         DMA_32BIT_PFN);
1757
1758         lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1759                 &reserved_rbtree_key);
1760
1761         /* IOAPIC ranges shouldn't be accessed by DMA */
1762         iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1763                 IOVA_PFN(IOAPIC_RANGE_END));
1764         if (!iova) {
1765                 pr_err("Reserve IOAPIC range failed\n");
1766                 return -ENODEV;
1767         }
1768
1769         /* Reserve all PCI MMIO to avoid peer-to-peer access */
1770         for_each_pci_dev(pdev) {
1771                 struct resource *r;
1772
1773                 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1774                         r = &pdev->resource[i];
1775                         if (!r->flags || !(r->flags & IORESOURCE_MEM))
1776                                 continue;
1777                         iova = reserve_iova(&reserved_iova_list,
1778                                             IOVA_PFN(r->start),
1779                                             IOVA_PFN(r->end));
1780                         if (!iova) {
1781                                 pr_err("Reserve iova failed\n");
1782                                 return -ENODEV;
1783                         }
1784                 }
1785         }
1786         return 0;
1787 }
1788
1789 static void domain_reserve_special_ranges(struct dmar_domain *domain)
1790 {
1791         copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1792 }
1793
1794 static inline int guestwidth_to_adjustwidth(int gaw)
1795 {
1796         int agaw;
1797         int r = (gaw - 12) % 9;
1798
1799         if (r == 0)
1800                 agaw = gaw;
1801         else
1802                 agaw = gaw + 9 - r;
1803         if (agaw > 64)
1804                 agaw = 64;
1805         return agaw;
1806 }
1807
1808 static int domain_init(struct dmar_domain *domain, struct intel_iommu *iommu,
1809                        int guest_width)
1810 {
1811         int adjust_width, agaw;
1812         unsigned long sagaw;
1813
1814         init_iova_domain(&domain->iovad, VTD_PAGE_SIZE, IOVA_START_PFN,
1815                         DMA_32BIT_PFN);
1816         domain_reserve_special_ranges(domain);
1817
1818         /* calculate AGAW */
1819         if (guest_width > cap_mgaw(iommu->cap))
1820                 guest_width = cap_mgaw(iommu->cap);
1821         domain->gaw = guest_width;
1822         adjust_width = guestwidth_to_adjustwidth(guest_width);
1823         agaw = width_to_agaw(adjust_width);
1824         sagaw = cap_sagaw(iommu->cap);
1825         if (!test_bit(agaw, &sagaw)) {
1826                 /* hardware doesn't support it, choose a bigger one */
1827                 pr_debug("Hardware doesn't support agaw %d\n", agaw);
1828                 agaw = find_next_bit(&sagaw, 5, agaw);
1829                 if (agaw >= 5)
1830                         return -ENODEV;
1831         }
1832         domain->agaw = agaw;
1833
1834         if (ecap_coherent(iommu->ecap))
1835                 domain->iommu_coherency = 1;
1836         else
1837                 domain->iommu_coherency = 0;
1838
1839         if (ecap_sc_support(iommu->ecap))
1840                 domain->iommu_snooping = 1;
1841         else
1842                 domain->iommu_snooping = 0;
1843
1844         if (intel_iommu_superpage)
1845                 domain->iommu_superpage = fls(cap_super_page_val(iommu->cap));
1846         else
1847                 domain->iommu_superpage = 0;
1848
1849         domain->nid = iommu->node;
1850
1851         /* always allocate the top pgd */
1852         domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
1853         if (!domain->pgd)
1854                 return -ENOMEM;
1855         __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
1856         return 0;
1857 }
1858
1859 static void domain_exit(struct dmar_domain *domain)
1860 {
1861         struct page *freelist = NULL;
1862
1863         /* Domain 0 is reserved, so dont process it */
1864         if (!domain)
1865                 return;
1866
1867         /* Flush any lazy unmaps that may reference this domain */
1868         if (!intel_iommu_strict)
1869                 flush_unmaps_timeout(0);
1870
1871         /* Remove associated devices and clear attached or cached domains */
1872         rcu_read_lock();
1873         domain_remove_dev_info(domain);
1874         rcu_read_unlock();
1875
1876         /* destroy iovas */
1877         put_iova_domain(&domain->iovad);
1878
1879         freelist = domain_unmap(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1880
1881         dma_free_pagelist(freelist);
1882
1883         free_domain_mem(domain);
1884 }
1885
1886 static int domain_context_mapping_one(struct dmar_domain *domain,
1887                                       struct intel_iommu *iommu,
1888                                       u8 bus, u8 devfn)
1889 {
1890         u16 did = domain->iommu_did[iommu->seq_id];
1891         int translation = CONTEXT_TT_MULTI_LEVEL;
1892         struct device_domain_info *info = NULL;
1893         struct context_entry *context;
1894         unsigned long flags;
1895         struct dma_pte *pgd;
1896         int ret, agaw;
1897
1898         WARN_ON(did == 0);
1899
1900         if (hw_pass_through && domain_type_is_si(domain))
1901                 translation = CONTEXT_TT_PASS_THROUGH;
1902
1903         pr_debug("Set context mapping for %02x:%02x.%d\n",
1904                 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1905
1906         BUG_ON(!domain->pgd);
1907
1908         spin_lock_irqsave(&device_domain_lock, flags);
1909         spin_lock(&iommu->lock);
1910
1911         ret = -ENOMEM;
1912         context = iommu_context_addr(iommu, bus, devfn, 1);
1913         if (!context)
1914                 goto out_unlock;
1915
1916         ret = 0;
1917         if (context_present(context))
1918                 goto out_unlock;
1919
1920         pgd = domain->pgd;
1921
1922         context_clear_entry(context);
1923         context_set_domain_id(context, did);
1924
1925         /*
1926          * Skip top levels of page tables for iommu which has less agaw
1927          * than default.  Unnecessary for PT mode.
1928          */
1929         if (translation != CONTEXT_TT_PASS_THROUGH) {
1930                 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1931                         ret = -ENOMEM;
1932                         pgd = phys_to_virt(dma_pte_addr(pgd));
1933                         if (!dma_pte_present(pgd))
1934                                 goto out_unlock;
1935                 }
1936
1937                 info = iommu_support_dev_iotlb(domain, iommu, bus, devfn);
1938                 translation = info ? CONTEXT_TT_DEV_IOTLB :
1939                                      CONTEXT_TT_MULTI_LEVEL;
1940
1941                 context_set_address_root(context, virt_to_phys(pgd));
1942                 context_set_address_width(context, iommu->agaw);
1943         } else {
1944                 /*
1945                  * In pass through mode, AW must be programmed to
1946                  * indicate the largest AGAW value supported by
1947                  * hardware. And ASR is ignored by hardware.
1948                  */
1949                 context_set_address_width(context, iommu->msagaw);
1950         }
1951
1952         context_set_translation_type(context, translation);
1953         context_set_fault_enable(context);
1954         context_set_present(context);
1955         domain_flush_cache(domain, context, sizeof(*context));
1956
1957         /*
1958          * It's a non-present to present mapping. If hardware doesn't cache
1959          * non-present entry we only need to flush the write-buffer. If the
1960          * _does_ cache non-present entries, then it does so in the special
1961          * domain #0, which we have to flush:
1962          */
1963         if (cap_caching_mode(iommu->cap)) {
1964                 iommu->flush.flush_context(iommu, 0,
1965                                            (((u16)bus) << 8) | devfn,
1966                                            DMA_CCMD_MASK_NOBIT,
1967                                            DMA_CCMD_DEVICE_INVL);
1968                 iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH);
1969         } else {
1970                 iommu_flush_write_buffer(iommu);
1971         }
1972         iommu_enable_dev_iotlb(info);
1973
1974         ret = 0;
1975
1976 out_unlock:
1977         spin_unlock(&iommu->lock);
1978         spin_unlock_irqrestore(&device_domain_lock, flags);
1979
1980         return 0;
1981 }
1982
1983 struct domain_context_mapping_data {
1984         struct dmar_domain *domain;
1985         struct intel_iommu *iommu;
1986 };
1987
1988 static int domain_context_mapping_cb(struct pci_dev *pdev,
1989                                      u16 alias, void *opaque)
1990 {
1991         struct domain_context_mapping_data *data = opaque;
1992
1993         return domain_context_mapping_one(data->domain, data->iommu,
1994                                           PCI_BUS_NUM(alias), alias & 0xff);
1995 }
1996
1997 static int
1998 domain_context_mapping(struct dmar_domain *domain, struct device *dev)
1999 {
2000         struct intel_iommu *iommu;
2001         u8 bus, devfn;
2002         struct domain_context_mapping_data data;
2003
2004         iommu = device_to_iommu(dev, &bus, &devfn);
2005         if (!iommu)
2006                 return -ENODEV;
2007
2008         if (!dev_is_pci(dev))
2009                 return domain_context_mapping_one(domain, iommu, bus, devfn);
2010
2011         data.domain = domain;
2012         data.iommu = iommu;
2013
2014         return pci_for_each_dma_alias(to_pci_dev(dev),
2015                                       &domain_context_mapping_cb, &data);
2016 }
2017
2018 static int domain_context_mapped_cb(struct pci_dev *pdev,
2019                                     u16 alias, void *opaque)
2020 {
2021         struct intel_iommu *iommu = opaque;
2022
2023         return !device_context_mapped(iommu, PCI_BUS_NUM(alias), alias & 0xff);
2024 }
2025
2026 static int domain_context_mapped(struct device *dev)
2027 {
2028         struct intel_iommu *iommu;
2029         u8 bus, devfn;
2030
2031         iommu = device_to_iommu(dev, &bus, &devfn);
2032         if (!iommu)
2033                 return -ENODEV;
2034
2035         if (!dev_is_pci(dev))
2036                 return device_context_mapped(iommu, bus, devfn);
2037
2038         return !pci_for_each_dma_alias(to_pci_dev(dev),
2039                                        domain_context_mapped_cb, iommu);
2040 }
2041
2042 /* Returns a number of VTD pages, but aligned to MM page size */
2043 static inline unsigned long aligned_nrpages(unsigned long host_addr,
2044                                             size_t size)
2045 {
2046         host_addr &= ~PAGE_MASK;
2047         return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
2048 }
2049
2050 /* Return largest possible superpage level for a given mapping */
2051 static inline int hardware_largepage_caps(struct dmar_domain *domain,
2052                                           unsigned long iov_pfn,
2053                                           unsigned long phy_pfn,
2054                                           unsigned long pages)
2055 {
2056         int support, level = 1;
2057         unsigned long pfnmerge;
2058
2059         support = domain->iommu_superpage;
2060
2061         /* To use a large page, the virtual *and* physical addresses
2062            must be aligned to 2MiB/1GiB/etc. Lower bits set in either
2063            of them will mean we have to use smaller pages. So just
2064            merge them and check both at once. */
2065         pfnmerge = iov_pfn | phy_pfn;
2066
2067         while (support && !(pfnmerge & ~VTD_STRIDE_MASK)) {
2068                 pages >>= VTD_STRIDE_SHIFT;
2069                 if (!pages)
2070                         break;
2071                 pfnmerge >>= VTD_STRIDE_SHIFT;
2072                 level++;
2073                 support--;
2074         }
2075         return level;
2076 }
2077
2078 static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
2079                             struct scatterlist *sg, unsigned long phys_pfn,
2080                             unsigned long nr_pages, int prot)
2081 {
2082         struct dma_pte *first_pte = NULL, *pte = NULL;
2083         phys_addr_t uninitialized_var(pteval);
2084         unsigned long sg_res = 0;
2085         unsigned int largepage_lvl = 0;
2086         unsigned long lvl_pages = 0;
2087
2088         BUG_ON(!domain_pfn_supported(domain, iov_pfn + nr_pages - 1));
2089
2090         if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
2091                 return -EINVAL;
2092
2093         prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
2094
2095         if (!sg) {
2096                 sg_res = nr_pages;
2097                 pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
2098         }
2099
2100         while (nr_pages > 0) {
2101                 uint64_t tmp;
2102
2103                 if (!sg_res) {
2104                         sg_res = aligned_nrpages(sg->offset, sg->length);
2105                         sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
2106                         sg->dma_length = sg->length;
2107                         pteval = (sg_phys(sg) & PAGE_MASK) | prot;
2108                         phys_pfn = pteval >> VTD_PAGE_SHIFT;
2109                 }
2110
2111                 if (!pte) {
2112                         largepage_lvl = hardware_largepage_caps(domain, iov_pfn, phys_pfn, sg_res);
2113
2114                         first_pte = pte = pfn_to_dma_pte(domain, iov_pfn, &largepage_lvl);
2115                         if (!pte)
2116                                 return -ENOMEM;
2117                         /* It is large page*/
2118                         if (largepage_lvl > 1) {
2119                                 pteval |= DMA_PTE_LARGE_PAGE;
2120                                 lvl_pages = lvl_to_nr_pages(largepage_lvl);
2121                                 /*
2122                                  * Ensure that old small page tables are
2123                                  * removed to make room for superpage,
2124                                  * if they exist.
2125                                  */
2126                                 dma_pte_free_pagetable(domain, iov_pfn,
2127                                                        iov_pfn + lvl_pages - 1);
2128                         } else {
2129                                 pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE;
2130                         }
2131
2132                 }
2133                 /* We don't need lock here, nobody else
2134                  * touches the iova range
2135                  */
2136                 tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
2137                 if (tmp) {
2138                         static int dumps = 5;
2139                         pr_crit("ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
2140                                 iov_pfn, tmp, (unsigned long long)pteval);
2141                         if (dumps) {
2142                                 dumps--;
2143                                 debug_dma_dump_mappings(NULL);
2144                         }
2145                         WARN_ON(1);
2146                 }
2147
2148                 lvl_pages = lvl_to_nr_pages(largepage_lvl);
2149
2150                 BUG_ON(nr_pages < lvl_pages);
2151                 BUG_ON(sg_res < lvl_pages);
2152
2153                 nr_pages -= lvl_pages;
2154                 iov_pfn += lvl_pages;
2155                 phys_pfn += lvl_pages;
2156                 pteval += lvl_pages * VTD_PAGE_SIZE;
2157                 sg_res -= lvl_pages;
2158
2159                 /* If the next PTE would be the first in a new page, then we
2160                    need to flush the cache on the entries we've just written.
2161                    And then we'll need to recalculate 'pte', so clear it and
2162                    let it get set again in the if (!pte) block above.
2163
2164                    If we're done (!nr_pages) we need to flush the cache too.
2165
2166                    Also if we've been setting superpages, we may need to
2167                    recalculate 'pte' and switch back to smaller pages for the
2168                    end of the mapping, if the trailing size is not enough to
2169                    use another superpage (i.e. sg_res < lvl_pages). */
2170                 pte++;
2171                 if (!nr_pages || first_pte_in_page(pte) ||
2172                     (largepage_lvl > 1 && sg_res < lvl_pages)) {
2173                         domain_flush_cache(domain, first_pte,
2174                                            (void *)pte - (void *)first_pte);
2175                         pte = NULL;
2176                 }
2177
2178                 if (!sg_res && nr_pages)
2179                         sg = sg_next(sg);
2180         }
2181         return 0;
2182 }
2183
2184 static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
2185                                     struct scatterlist *sg, unsigned long nr_pages,
2186                                     int prot)
2187 {
2188         return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
2189 }
2190
2191 static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
2192                                      unsigned long phys_pfn, unsigned long nr_pages,
2193                                      int prot)
2194 {
2195         return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
2196 }
2197
2198 static void domain_context_clear_one(struct intel_iommu *iommu, u8 bus, u8 devfn)
2199 {
2200         if (!iommu)
2201                 return;
2202
2203         clear_context_table(iommu, bus, devfn);
2204         iommu->flush.flush_context(iommu, 0, 0, 0,
2205                                            DMA_CCMD_GLOBAL_INVL);
2206         iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
2207 }
2208
2209 static inline void unlink_domain_info(struct device_domain_info *info)
2210 {
2211         assert_spin_locked(&device_domain_lock);
2212         list_del(&info->link);
2213         list_del(&info->global);
2214         if (info->dev)
2215                 info->dev->archdata.iommu = NULL;
2216 }
2217
2218 static void domain_remove_dev_info(struct dmar_domain *domain)
2219 {
2220         struct device_domain_info *info, *tmp;
2221         unsigned long flags;
2222
2223         spin_lock_irqsave(&device_domain_lock, flags);
2224         list_for_each_entry_safe(info, tmp, &domain->devices, link)
2225                 __dmar_remove_one_dev_info(info);
2226         spin_unlock_irqrestore(&device_domain_lock, flags);
2227 }
2228
2229 /*
2230  * find_domain
2231  * Note: we use struct device->archdata.iommu stores the info
2232  */
2233 static struct dmar_domain *find_domain(struct device *dev)
2234 {
2235         struct device_domain_info *info;
2236
2237         /* No lock here, assumes no domain exit in normal case */
2238         info = dev->archdata.iommu;
2239         if (info)
2240                 return info->domain;
2241         return NULL;
2242 }
2243
2244 static inline struct device_domain_info *
2245 dmar_search_domain_by_dev_info(int segment, int bus, int devfn)
2246 {
2247         struct device_domain_info *info;
2248
2249         list_for_each_entry(info, &device_domain_list, global)
2250                 if (info->iommu->segment == segment && info->bus == bus &&
2251                     info->devfn == devfn)
2252                         return info;
2253
2254         return NULL;
2255 }
2256
2257 static struct dmar_domain *dmar_insert_one_dev_info(struct intel_iommu *iommu,
2258                                                     int bus, int devfn,
2259                                                     struct device *dev,
2260                                                     struct dmar_domain *domain)
2261 {
2262         struct dmar_domain *found = NULL;
2263         struct device_domain_info *info;
2264         unsigned long flags;
2265         int ret;
2266
2267         info = alloc_devinfo_mem();
2268         if (!info)
2269                 return NULL;
2270
2271         info->bus = bus;
2272         info->devfn = devfn;
2273         info->ats.enabled = 0;
2274         info->ats.qdep = 0;
2275         info->dev = dev;
2276         info->domain = domain;
2277         info->iommu = iommu;
2278
2279         spin_lock_irqsave(&device_domain_lock, flags);
2280         if (dev)
2281                 found = find_domain(dev);
2282
2283         if (!found) {
2284                 struct device_domain_info *info2;
2285                 info2 = dmar_search_domain_by_dev_info(iommu->segment, bus, devfn);
2286                 if (info2) {
2287                         found      = info2->domain;
2288                         info2->dev = dev;
2289                 }
2290         }
2291
2292         if (found) {
2293                 spin_unlock_irqrestore(&device_domain_lock, flags);
2294                 free_devinfo_mem(info);
2295                 /* Caller must free the original domain */
2296                 return found;
2297         }
2298
2299         spin_lock(&iommu->lock);
2300         ret = domain_attach_iommu(domain, iommu);
2301         spin_unlock(&iommu->lock);
2302
2303         if (ret) {
2304                 spin_unlock_irqrestore(&device_domain_lock, flags);
2305                 return NULL;
2306         }
2307
2308         list_add(&info->link, &domain->devices);
2309         list_add(&info->global, &device_domain_list);
2310         if (dev)
2311                 dev->archdata.iommu = info;
2312         spin_unlock_irqrestore(&device_domain_lock, flags);
2313
2314         if (dev && domain_context_mapping(domain, dev)) {
2315                 pr_err("Domain context map for %s failed\n", dev_name(dev));
2316                 dmar_remove_one_dev_info(domain, dev);
2317                 return NULL;
2318         }
2319
2320         return domain;
2321 }
2322
2323 static int get_last_alias(struct pci_dev *pdev, u16 alias, void *opaque)
2324 {
2325         *(u16 *)opaque = alias;
2326         return 0;
2327 }
2328
2329 /* domain is initialized */
2330 static struct dmar_domain *get_domain_for_dev(struct device *dev, int gaw)
2331 {
2332         struct device_domain_info *info = NULL;
2333         struct dmar_domain *domain, *tmp;
2334         struct intel_iommu *iommu;
2335         u16 req_id, dma_alias;
2336         unsigned long flags;
2337         u8 bus, devfn;
2338
2339         domain = find_domain(dev);
2340         if (domain)
2341                 return domain;
2342
2343         iommu = device_to_iommu(dev, &bus, &devfn);
2344         if (!iommu)
2345                 return NULL;
2346
2347         req_id = ((u16)bus << 8) | devfn;
2348
2349         if (dev_is_pci(dev)) {
2350                 struct pci_dev *pdev = to_pci_dev(dev);
2351
2352                 pci_for_each_dma_alias(pdev, get_last_alias, &dma_alias);
2353
2354                 spin_lock_irqsave(&device_domain_lock, flags);
2355                 info = dmar_search_domain_by_dev_info(pci_domain_nr(pdev->bus),
2356                                                       PCI_BUS_NUM(dma_alias),
2357                                                       dma_alias & 0xff);
2358                 if (info) {
2359                         iommu = info->iommu;
2360                         domain = info->domain;
2361                 }
2362                 spin_unlock_irqrestore(&device_domain_lock, flags);
2363
2364                 /* DMA alias already has a domain, uses it */
2365                 if (info)
2366                         goto found_domain;
2367         }
2368
2369         /* Allocate and initialize new domain for the device */
2370         domain = alloc_domain(0);
2371         if (!domain)
2372                 return NULL;
2373         if (domain_init(domain, iommu, gaw)) {
2374                 domain_exit(domain);
2375                 return NULL;
2376         }
2377
2378         /* register PCI DMA alias device */
2379         if (req_id != dma_alias && dev_is_pci(dev)) {
2380                 tmp = dmar_insert_one_dev_info(iommu, PCI_BUS_NUM(dma_alias),
2381                                                dma_alias & 0xff, NULL, domain);
2382
2383                 if (!tmp || tmp != domain) {
2384                         domain_exit(domain);
2385                         domain = tmp;
2386                 }
2387
2388                 if (!domain)
2389                         return NULL;
2390         }
2391
2392 found_domain:
2393         tmp = dmar_insert_one_dev_info(iommu, bus, devfn, dev, domain);
2394
2395         if (!tmp || tmp != domain) {
2396                 domain_exit(domain);
2397                 domain = tmp;
2398         }
2399
2400         return domain;
2401 }
2402
2403 static int iommu_identity_mapping;
2404 #define IDENTMAP_ALL            1
2405 #define IDENTMAP_GFX            2
2406 #define IDENTMAP_AZALIA         4
2407
2408 static int iommu_domain_identity_map(struct dmar_domain *domain,
2409                                      unsigned long long start,
2410                                      unsigned long long end)
2411 {
2412         unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
2413         unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
2414
2415         if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
2416                           dma_to_mm_pfn(last_vpfn))) {
2417                 pr_err("Reserving iova failed\n");
2418                 return -ENOMEM;
2419         }
2420
2421         pr_debug("Mapping reserved region %llx-%llx\n", start, end);
2422         /*
2423          * RMRR range might have overlap with physical memory range,
2424          * clear it first
2425          */
2426         dma_pte_clear_range(domain, first_vpfn, last_vpfn);
2427
2428         return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
2429                                   last_vpfn - first_vpfn + 1,
2430                                   DMA_PTE_READ|DMA_PTE_WRITE);
2431 }
2432
2433 static int domain_prepare_identity_map(struct device *dev,
2434                                        struct dmar_domain *domain,
2435                                        unsigned long long start,
2436                                        unsigned long long end)
2437 {
2438         /* For _hardware_ passthrough, don't bother. But for software
2439            passthrough, we do it anyway -- it may indicate a memory
2440            range which is reserved in E820, so which didn't get set
2441            up to start with in si_domain */
2442         if (domain == si_domain && hw_pass_through) {
2443                 pr_warn("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
2444                         dev_name(dev), start, end);
2445                 return 0;
2446         }
2447
2448         pr_info("Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
2449                 dev_name(dev), start, end);
2450
2451         if (end < start) {
2452                 WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n"
2453                         "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
2454                         dmi_get_system_info(DMI_BIOS_VENDOR),
2455                         dmi_get_system_info(DMI_BIOS_VERSION),
2456                      dmi_get_system_info(DMI_PRODUCT_VERSION));
2457                 return -EIO;
2458         }
2459
2460         if (end >> agaw_to_width(domain->agaw)) {
2461                 WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n"
2462                      "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
2463                      agaw_to_width(domain->agaw),
2464                      dmi_get_system_info(DMI_BIOS_VENDOR),
2465                      dmi_get_system_info(DMI_BIOS_VERSION),
2466                      dmi_get_system_info(DMI_PRODUCT_VERSION));
2467                 return -EIO;
2468         }
2469
2470         return iommu_domain_identity_map(domain, start, end);
2471 }
2472
2473 static int iommu_prepare_identity_map(struct device *dev,
2474                                       unsigned long long start,
2475                                       unsigned long long end)
2476 {
2477         struct dmar_domain *domain;
2478         int ret;
2479
2480         domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
2481         if (!domain)
2482                 return -ENOMEM;
2483
2484         ret = domain_prepare_identity_map(dev, domain, start, end);
2485         if (ret)
2486                 domain_exit(domain);
2487
2488         return ret;
2489 }
2490
2491 static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
2492                                          struct device *dev)
2493 {
2494         if (dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
2495                 return 0;
2496         return iommu_prepare_identity_map(dev, rmrr->base_address,
2497                                           rmrr->end_address);
2498 }
2499
2500 #ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA
2501 static inline void iommu_prepare_isa(void)
2502 {
2503         struct pci_dev *pdev;
2504         int ret;
2505
2506         pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
2507         if (!pdev)
2508                 return;
2509
2510         pr_info("Prepare 0-16MiB unity mapping for LPC\n");
2511         ret = iommu_prepare_identity_map(&pdev->dev, 0, 16*1024*1024 - 1);
2512
2513         if (ret)
2514                 pr_err("Failed to create 0-16MiB identity map - floppy might not work\n");
2515
2516         pci_dev_put(pdev);
2517 }
2518 #else
2519 static inline void iommu_prepare_isa(void)
2520 {
2521         return;
2522 }
2523 #endif /* !CONFIG_INTEL_IOMMU_FLPY_WA */
2524
2525 static int md_domain_init(struct dmar_domain *domain, int guest_width);
2526
2527 static int __init si_domain_init(int hw)
2528 {
2529         int nid, ret = 0;
2530
2531         si_domain = alloc_domain(DOMAIN_FLAG_STATIC_IDENTITY);
2532         if (!si_domain)
2533                 return -EFAULT;
2534
2535         if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2536                 domain_exit(si_domain);
2537                 return -EFAULT;
2538         }
2539
2540         pr_debug("Identity mapping domain allocated\n");
2541
2542         if (hw)
2543                 return 0;
2544
2545         for_each_online_node(nid) {
2546                 unsigned long start_pfn, end_pfn;
2547                 int i;
2548
2549                 for_each_mem_pfn_range(i, nid, &start_pfn, &end_pfn, NULL) {
2550                         ret = iommu_domain_identity_map(si_domain,
2551                                         PFN_PHYS(start_pfn), PFN_PHYS(end_pfn));
2552                         if (ret)
2553                                 return ret;
2554                 }
2555         }
2556
2557         return 0;
2558 }
2559
2560 static int identity_mapping(struct device *dev)
2561 {
2562         struct device_domain_info *info;
2563
2564         if (likely(!iommu_identity_mapping))
2565                 return 0;
2566
2567         info = dev->archdata.iommu;
2568         if (info && info != DUMMY_DEVICE_DOMAIN_INFO)
2569                 return (info->domain == si_domain);
2570
2571         return 0;
2572 }
2573
2574 static int domain_add_dev_info(struct dmar_domain *domain, struct device *dev)
2575 {
2576         struct dmar_domain *ndomain;
2577         struct intel_iommu *iommu;
2578         u8 bus, devfn;
2579
2580         iommu = device_to_iommu(dev, &bus, &devfn);
2581         if (!iommu)
2582                 return -ENODEV;
2583
2584         ndomain = dmar_insert_one_dev_info(iommu, bus, devfn, dev, domain);
2585         if (ndomain != domain)
2586                 return -EBUSY;
2587
2588         return 0;
2589 }
2590
2591 static bool device_has_rmrr(struct device *dev)
2592 {
2593         struct dmar_rmrr_unit *rmrr;
2594         struct device *tmp;
2595         int i;
2596
2597         rcu_read_lock();
2598         for_each_rmrr_units(rmrr) {
2599                 /*
2600                  * Return TRUE if this RMRR contains the device that
2601                  * is passed in.
2602                  */
2603                 for_each_active_dev_scope(rmrr->devices,
2604                                           rmrr->devices_cnt, i, tmp)
2605                         if (tmp == dev) {
2606                                 rcu_read_unlock();
2607                                 return true;
2608                         }
2609         }
2610         rcu_read_unlock();
2611         return false;
2612 }
2613
2614 /*
2615  * There are a couple cases where we need to restrict the functionality of
2616  * devices associated with RMRRs.  The first is when evaluating a device for
2617  * identity mapping because problems exist when devices are moved in and out
2618  * of domains and their respective RMRR information is lost.  This means that
2619  * a device with associated RMRRs will never be in a "passthrough" domain.
2620  * The second is use of the device through the IOMMU API.  This interface
2621  * expects to have full control of the IOVA space for the device.  We cannot
2622  * satisfy both the requirement that RMRR access is maintained and have an
2623  * unencumbered IOVA space.  We also have no ability to quiesce the device's
2624  * use of the RMRR space or even inform the IOMMU API user of the restriction.
2625  * We therefore prevent devices associated with an RMRR from participating in
2626  * the IOMMU API, which eliminates them from device assignment.
2627  *
2628  * In both cases we assume that PCI USB devices with RMRRs have them largely
2629  * for historical reasons and that the RMRR space is not actively used post
2630  * boot.  This exclusion may change if vendors begin to abuse it.
2631  *
2632  * The same exception is made for graphics devices, with the requirement that
2633  * any use of the RMRR regions will be torn down before assigning the device
2634  * to a guest.
2635  */
2636 static bool device_is_rmrr_locked(struct device *dev)
2637 {
2638         if (!device_has_rmrr(dev))
2639                 return false;
2640
2641         if (dev_is_pci(dev)) {
2642                 struct pci_dev *pdev = to_pci_dev(dev);
2643
2644                 if (IS_USB_DEVICE(pdev) || IS_GFX_DEVICE(pdev))
2645                         return false;
2646         }
2647
2648         return true;
2649 }
2650
2651 static int iommu_should_identity_map(struct device *dev, int startup)
2652 {
2653
2654         if (dev_is_pci(dev)) {
2655                 struct pci_dev *pdev = to_pci_dev(dev);
2656
2657                 if (device_is_rmrr_locked(dev))
2658                         return 0;
2659
2660                 if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev))
2661                         return 1;
2662
2663                 if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev))
2664                         return 1;
2665
2666                 if (!(iommu_identity_mapping & IDENTMAP_ALL))
2667                         return 0;
2668
2669                 /*
2670                  * We want to start off with all devices in the 1:1 domain, and
2671                  * take them out later if we find they can't access all of memory.
2672                  *
2673                  * However, we can't do this for PCI devices behind bridges,
2674                  * because all PCI devices behind the same bridge will end up
2675                  * with the same source-id on their transactions.
2676                  *
2677                  * Practically speaking, we can't change things around for these
2678                  * devices at run-time, because we can't be sure there'll be no
2679                  * DMA transactions in flight for any of their siblings.
2680                  *
2681                  * So PCI devices (unless they're on the root bus) as well as
2682                  * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
2683                  * the 1:1 domain, just in _case_ one of their siblings turns out
2684                  * not to be able to map all of memory.
2685                  */
2686                 if (!pci_is_pcie(pdev)) {
2687                         if (!pci_is_root_bus(pdev->bus))
2688                                 return 0;
2689                         if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
2690                                 return 0;
2691                 } else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_PCI_BRIDGE)
2692                         return 0;
2693         } else {
2694                 if (device_has_rmrr(dev))
2695                         return 0;
2696         }
2697
2698         /*
2699          * At boot time, we don't yet know if devices will be 64-bit capable.
2700          * Assume that they will — if they turn out not to be, then we can
2701          * take them out of the 1:1 domain later.
2702          */
2703         if (!startup) {
2704                 /*
2705                  * If the device's dma_mask is less than the system's memory
2706                  * size then this is not a candidate for identity mapping.
2707                  */
2708                 u64 dma_mask = *dev->dma_mask;
2709
2710                 if (dev->coherent_dma_mask &&
2711                     dev->coherent_dma_mask < dma_mask)
2712                         dma_mask = dev->coherent_dma_mask;
2713
2714                 return dma_mask >= dma_get_required_mask(dev);
2715         }
2716
2717         return 1;
2718 }
2719
2720 static int __init dev_prepare_static_identity_mapping(struct device *dev, int hw)
2721 {
2722         int ret;
2723
2724         if (!iommu_should_identity_map(dev, 1))
2725                 return 0;
2726
2727         ret = domain_add_dev_info(si_domain, dev);
2728         if (!ret)
2729                 pr_info("%s identity mapping for device %s\n",
2730                         hw ? "Hardware" : "Software", dev_name(dev));
2731         else if (ret == -ENODEV)
2732                 /* device not associated with an iommu */
2733                 ret = 0;
2734
2735         return ret;
2736 }
2737
2738
2739 static int __init iommu_prepare_static_identity_mapping(int hw)
2740 {
2741         struct pci_dev *pdev = NULL;
2742         struct dmar_drhd_unit *drhd;
2743         struct intel_iommu *iommu;
2744         struct device *dev;
2745         int i;
2746         int ret = 0;
2747
2748         for_each_pci_dev(pdev) {
2749                 ret = dev_prepare_static_identity_mapping(&pdev->dev, hw);
2750                 if (ret)
2751                         return ret;
2752         }
2753
2754         for_each_active_iommu(iommu, drhd)
2755                 for_each_active_dev_scope(drhd->devices, drhd->devices_cnt, i, dev) {
2756                         struct acpi_device_physical_node *pn;
2757                         struct acpi_device *adev;
2758
2759                         if (dev->bus != &acpi_bus_type)
2760                                 continue;
2761
2762                         adev= to_acpi_device(dev);
2763                         mutex_lock(&adev->physical_node_lock);
2764                         list_for_each_entry(pn, &adev->physical_node_list, node) {
2765                                 ret = dev_prepare_static_identity_mapping(pn->dev, hw);
2766                                 if (ret)
2767                                         break;
2768                         }
2769                         mutex_unlock(&adev->physical_node_lock);
2770                         if (ret)
2771                                 return ret;
2772                 }
2773
2774         return 0;
2775 }
2776
2777 static void intel_iommu_init_qi(struct intel_iommu *iommu)
2778 {
2779         /*
2780          * Start from the sane iommu hardware state.
2781          * If the queued invalidation is already initialized by us
2782          * (for example, while enabling interrupt-remapping) then
2783          * we got the things already rolling from a sane state.
2784          */
2785         if (!iommu->qi) {
2786                 /*
2787                  * Clear any previous faults.
2788                  */
2789                 dmar_fault(-1, iommu);
2790                 /*
2791                  * Disable queued invalidation if supported and already enabled
2792                  * before OS handover.
2793                  */
2794                 dmar_disable_qi(iommu);
2795         }
2796
2797         if (dmar_enable_qi(iommu)) {
2798                 /*
2799                  * Queued Invalidate not enabled, use Register Based Invalidate
2800                  */
2801                 iommu->flush.flush_context = __iommu_flush_context;
2802                 iommu->flush.flush_iotlb = __iommu_flush_iotlb;
2803                 pr_info("%s: Using Register based invalidation\n",
2804                         iommu->name);
2805         } else {
2806                 iommu->flush.flush_context = qi_flush_context;
2807                 iommu->flush.flush_iotlb = qi_flush_iotlb;
2808                 pr_info("%s: Using Queued invalidation\n", iommu->name);
2809         }
2810 }
2811
2812 static int copy_context_table(struct intel_iommu *iommu,
2813                               struct root_entry *old_re,
2814                               struct context_entry **tbl,
2815                               int bus, bool ext)
2816 {
2817         int tbl_idx, pos = 0, idx, devfn, ret = 0, did;
2818         struct context_entry *new_ce = NULL, ce;
2819         struct context_entry *old_ce = NULL;
2820         struct root_entry re;
2821         phys_addr_t old_ce_phys;
2822
2823         tbl_idx = ext ? bus * 2 : bus;
2824         memcpy(&re, old_re, sizeof(re));
2825
2826         for (devfn = 0; devfn < 256; devfn++) {
2827                 /* First calculate the correct index */
2828                 idx = (ext ? devfn * 2 : devfn) % 256;
2829
2830                 if (idx == 0) {
2831                         /* First save what we may have and clean up */
2832                         if (new_ce) {
2833                                 tbl[tbl_idx] = new_ce;
2834                                 __iommu_flush_cache(iommu, new_ce,
2835                                                     VTD_PAGE_SIZE);
2836                                 pos = 1;
2837                         }
2838
2839                         if (old_ce)
2840                                 iounmap(old_ce);
2841
2842                         ret = 0;
2843                         if (devfn < 0x80)
2844                                 old_ce_phys = root_entry_lctp(&re);
2845                         else
2846                                 old_ce_phys = root_entry_uctp(&re);
2847
2848                         if (!old_ce_phys) {
2849                                 if (ext && devfn == 0) {
2850                                         /* No LCTP, try UCTP */
2851                                         devfn = 0x7f;
2852                                         continue;
2853                                 } else {
2854                                         goto out;
2855                                 }
2856                         }
2857
2858                         ret = -ENOMEM;
2859                         old_ce = memremap(old_ce_phys, PAGE_SIZE,
2860                                         MEMREMAP_WB);
2861                         if (!old_ce)
2862                                 goto out;
2863
2864                         new_ce = alloc_pgtable_page(iommu->node);
2865                         if (!new_ce)
2866                                 goto out_unmap;
2867
2868                         ret = 0;
2869                 }
2870
2871                 /* Now copy the context entry */
2872                 memcpy(&ce, old_ce + idx, sizeof(ce));
2873
2874                 if (!__context_present(&ce))
2875                         continue;
2876
2877                 did = context_domain_id(&ce);
2878                 if (did >= 0 && did < cap_ndoms(iommu->cap))
2879                         set_bit(did, iommu->domain_ids);
2880
2881                 /*
2882                  * We need a marker for copied context entries. This
2883                  * marker needs to work for the old format as well as
2884                  * for extended context entries.
2885                  *
2886                  * Bit 67 of the context entry is used. In the old
2887                  * format this bit is available to software, in the
2888                  * extended format it is the PGE bit, but PGE is ignored
2889                  * by HW if PASIDs are disabled (and thus still
2890                  * available).
2891                  *
2892                  * So disable PASIDs first and then mark the entry
2893                  * copied. This means that we don't copy PASID
2894                  * translations from the old kernel, but this is fine as
2895                  * faults there are not fatal.
2896                  */
2897                 context_clear_pasid_enable(&ce);
2898                 context_set_copied(&ce);
2899
2900                 new_ce[idx] = ce;
2901         }
2902
2903         tbl[tbl_idx + pos] = new_ce;
2904
2905         __iommu_flush_cache(iommu, new_ce, VTD_PAGE_SIZE);
2906
2907 out_unmap:
2908         memunmap(old_ce);
2909
2910 out:
2911         return ret;
2912 }
2913
2914 static int copy_translation_tables(struct intel_iommu *iommu)
2915 {
2916         struct context_entry **ctxt_tbls;
2917         struct root_entry *old_rt;
2918         phys_addr_t old_rt_phys;
2919         int ctxt_table_entries;
2920         unsigned long flags;
2921         u64 rtaddr_reg;
2922         int bus, ret;
2923         bool new_ext, ext;
2924
2925         rtaddr_reg = dmar_readq(iommu->reg + DMAR_RTADDR_REG);
2926         ext        = !!(rtaddr_reg & DMA_RTADDR_RTT);
2927         new_ext    = !!ecap_ecs(iommu->ecap);
2928
2929         /*
2930          * The RTT bit can only be changed when translation is disabled,
2931          * but disabling translation means to open a window for data
2932          * corruption. So bail out and don't copy anything if we would
2933          * have to change the bit.
2934          */
2935         if (new_ext != ext)
2936                 return -EINVAL;
2937
2938         old_rt_phys = rtaddr_reg & VTD_PAGE_MASK;
2939         if (!old_rt_phys)
2940                 return -EINVAL;
2941
2942         old_rt = memremap(old_rt_phys, PAGE_SIZE, MEMREMAP_WB);
2943         if (!old_rt)
2944                 return -ENOMEM;
2945
2946         /* This is too big for the stack - allocate it from slab */
2947         ctxt_table_entries = ext ? 512 : 256;
2948         ret = -ENOMEM;
2949         ctxt_tbls = kzalloc(ctxt_table_entries * sizeof(void *), GFP_KERNEL);
2950         if (!ctxt_tbls)
2951                 goto out_unmap;
2952
2953         for (bus = 0; bus < 256; bus++) {
2954                 ret = copy_context_table(iommu, &old_rt[bus],
2955                                          ctxt_tbls, bus, ext);
2956                 if (ret) {
2957                         pr_err("%s: Failed to copy context table for bus %d\n",
2958                                 iommu->name, bus);
2959                         continue;
2960                 }
2961         }
2962
2963         spin_lock_irqsave(&iommu->lock, flags);
2964
2965         /* Context tables are copied, now write them to the root_entry table */
2966         for (bus = 0; bus < 256; bus++) {
2967                 int idx = ext ? bus * 2 : bus;
2968                 u64 val;
2969
2970                 if (ctxt_tbls[idx]) {
2971                         val = virt_to_phys(ctxt_tbls[idx]) | 1;
2972                         iommu->root_entry[bus].lo = val;
2973                 }
2974
2975                 if (!ext || !ctxt_tbls[idx + 1])
2976                         continue;
2977
2978                 val = virt_to_phys(ctxt_tbls[idx + 1]) | 1;
2979                 iommu->root_entry[bus].hi = val;
2980         }
2981
2982         spin_unlock_irqrestore(&iommu->lock, flags);
2983
2984         kfree(ctxt_tbls);
2985
2986         __iommu_flush_cache(iommu, iommu->root_entry, PAGE_SIZE);
2987
2988         ret = 0;
2989
2990 out_unmap:
2991         memunmap(old_rt);
2992
2993         return ret;
2994 }
2995
2996 static int __init init_dmars(void)
2997 {
2998         struct dmar_drhd_unit *drhd;
2999         struct dmar_rmrr_unit *rmrr;
3000         bool copied_tables = false;
3001         struct device *dev;
3002         struct intel_iommu *iommu;
3003         int i, ret;
3004
3005         /*
3006          * for each drhd
3007          *    allocate root
3008          *    initialize and program root entry to not present
3009          * endfor
3010          */
3011         for_each_drhd_unit(drhd) {
3012                 /*
3013                  * lock not needed as this is only incremented in the single
3014                  * threaded kernel __init code path all other access are read
3015                  * only
3016                  */
3017                 if (g_num_of_iommus < DMAR_UNITS_SUPPORTED) {
3018                         g_num_of_iommus++;
3019                         continue;
3020                 }
3021                 pr_err_once("Exceeded %d IOMMUs\n", DMAR_UNITS_SUPPORTED);
3022         }
3023
3024         /* Preallocate enough resources for IOMMU hot-addition */
3025         if (g_num_of_iommus < DMAR_UNITS_SUPPORTED)
3026                 g_num_of_iommus = DMAR_UNITS_SUPPORTED;
3027
3028         g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
3029                         GFP_KERNEL);
3030         if (!g_iommus) {
3031                 pr_err("Allocating global iommu array failed\n");
3032                 ret = -ENOMEM;
3033                 goto error;
3034         }
3035
3036         deferred_flush = kzalloc(g_num_of_iommus *
3037                 sizeof(struct deferred_flush_tables), GFP_KERNEL);
3038         if (!deferred_flush) {
3039                 ret = -ENOMEM;
3040                 goto free_g_iommus;
3041         }
3042
3043         for_each_active_iommu(iommu, drhd) {
3044                 g_iommus[iommu->seq_id] = iommu;
3045
3046                 intel_iommu_init_qi(iommu);
3047
3048                 ret = iommu_init_domains(iommu);
3049                 if (ret)
3050                         goto free_iommu;
3051
3052                 init_translation_status(iommu);
3053
3054                 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) {
3055                         iommu_disable_translation(iommu);
3056                         clear_translation_pre_enabled(iommu);
3057                         pr_warn("Translation was enabled for %s but we are not in kdump mode\n",
3058                                 iommu->name);
3059                 }
3060
3061                 /*
3062                  * TBD:
3063                  * we could share the same root & context tables
3064                  * among all IOMMU's. Need to Split it later.
3065                  */
3066                 ret = iommu_alloc_root_entry(iommu);
3067                 if (ret)
3068                         goto free_iommu;
3069
3070                 if (translation_pre_enabled(iommu)) {
3071                         pr_info("Translation already enabled - trying to copy translation structures\n");
3072
3073                         ret = copy_translation_tables(iommu);
3074                         if (ret) {
3075                                 /*
3076                                  * We found the IOMMU with translation
3077                                  * enabled - but failed to copy over the
3078                                  * old root-entry table. Try to proceed
3079                                  * by disabling translation now and
3080                                  * allocating a clean root-entry table.
3081                                  * This might cause DMAR faults, but
3082                                  * probably the dump will still succeed.
3083                                  */
3084                                 pr_err("Failed to copy translation tables from previous kernel for %s\n",
3085                                        iommu->name);
3086                                 iommu_disable_translation(iommu);
3087                                 clear_translation_pre_enabled(iommu);
3088                         } else {
3089                                 pr_info("Copied translation tables from previous kernel for %s\n",
3090                                         iommu->name);
3091                                 copied_tables = true;
3092                         }
3093                 }
3094
3095                 iommu_flush_write_buffer(iommu);
3096                 iommu_set_root_entry(iommu);
3097                 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
3098                 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
3099
3100                 if (!ecap_pass_through(iommu->ecap))
3101                         hw_pass_through = 0;
3102         }
3103
3104         if (iommu_pass_through)
3105                 iommu_identity_mapping |= IDENTMAP_ALL;
3106
3107 #ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA
3108         iommu_identity_mapping |= IDENTMAP_GFX;
3109 #endif
3110
3111         if (iommu_identity_mapping) {
3112                 ret = si_domain_init(hw_pass_through);
3113                 if (ret)
3114                         goto free_iommu;
3115         }
3116
3117         check_tylersburg_isoch();
3118
3119         /*
3120          * If we copied translations from a previous kernel in the kdump
3121          * case, we can not assign the devices to domains now, as that
3122          * would eliminate the old mappings. So skip this part and defer
3123          * the assignment to device driver initialization time.
3124          */
3125         if (copied_tables)
3126                 goto domains_done;
3127
3128         /*
3129          * If pass through is not set or not enabled, setup context entries for
3130          * identity mappings for rmrr, gfx, and isa and may fall back to static
3131          * identity mapping if iommu_identity_mapping is set.
3132          */
3133         if (iommu_identity_mapping) {
3134                 ret = iommu_prepare_static_identity_mapping(hw_pass_through);
3135                 if (ret) {
3136                         pr_crit("Failed to setup IOMMU pass-through\n");
3137                         goto free_iommu;
3138                 }
3139         }
3140         /*
3141          * For each rmrr
3142          *   for each dev attached to rmrr
3143          *   do
3144          *     locate drhd for dev, alloc domain for dev
3145          *     allocate free domain
3146          *     allocate page table entries for rmrr
3147          *     if context not allocated for bus
3148          *           allocate and init context
3149          *           set present in root table for this bus
3150          *     init context with domain, translation etc
3151          *    endfor
3152          * endfor
3153          */
3154         pr_info("Setting RMRR:\n");
3155         for_each_rmrr_units(rmrr) {
3156                 /* some BIOS lists non-exist devices in DMAR table. */
3157                 for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt,
3158                                           i, dev) {
3159                         ret = iommu_prepare_rmrr_dev(rmrr, dev);
3160                         if (ret)
3161                                 pr_err("Mapping reserved region failed\n");
3162                 }
3163         }
3164
3165         iommu_prepare_isa();
3166
3167 domains_done:
3168
3169         /*
3170          * for each drhd
3171          *   enable fault log
3172          *   global invalidate context cache
3173          *   global invalidate iotlb
3174          *   enable translation
3175          */
3176         for_each_iommu(iommu, drhd) {
3177                 if (drhd->ignored) {
3178                         /*
3179                          * we always have to disable PMRs or DMA may fail on
3180                          * this device
3181                          */
3182                         if (force_on)
3183                                 iommu_disable_protect_mem_regions(iommu);
3184                         continue;
3185                 }
3186
3187                 iommu_flush_write_buffer(iommu);
3188
3189                 ret = dmar_set_interrupt(iommu);
3190                 if (ret)
3191                         goto free_iommu;
3192
3193                 if (!translation_pre_enabled(iommu))
3194                         iommu_enable_translation(iommu);
3195
3196                 iommu_disable_protect_mem_regions(iommu);
3197         }
3198
3199         return 0;
3200
3201 free_iommu:
3202         for_each_active_iommu(iommu, drhd) {
3203                 disable_dmar_iommu(iommu);
3204                 free_dmar_iommu(iommu);
3205         }
3206         kfree(deferred_flush);
3207 free_g_iommus:
3208         kfree(g_iommus);
3209 error:
3210         return ret;
3211 }
3212
3213 /* This takes a number of _MM_ pages, not VTD pages */
3214 static struct iova *intel_alloc_iova(struct device *dev,
3215                                      struct dmar_domain *domain,
3216                                      unsigned long nrpages, uint64_t dma_mask)
3217 {
3218         struct iova *iova = NULL;
3219
3220         /* Restrict dma_mask to the width that the iommu can handle */
3221         dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
3222
3223         if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
3224                 /*
3225                  * First try to allocate an io virtual address in
3226                  * DMA_BIT_MASK(32) and if that fails then try allocating
3227                  * from higher range
3228                  */
3229                 iova = alloc_iova(&domain->iovad, nrpages,
3230                                   IOVA_PFN(DMA_BIT_MASK(32)), 1);
3231                 if (iova)
3232                         return iova;
3233         }
3234         iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
3235         if (unlikely(!iova)) {
3236                 pr_err("Allocating %ld-page iova for %s failed",
3237                        nrpages, dev_name(dev));
3238                 return NULL;
3239         }
3240
3241         return iova;
3242 }
3243
3244 static struct dmar_domain *__get_valid_domain_for_dev(struct device *dev)
3245 {
3246         struct dmar_rmrr_unit *rmrr;
3247         struct dmar_domain *domain;
3248         struct device *i_dev;
3249         int i, ret;
3250
3251         domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
3252         if (!domain) {
3253                 pr_err("Allocating domain for %s failed\n",
3254                        dev_name(dev));
3255                 return NULL;
3256         }
3257
3258         /* We have a new domain - setup possible RMRRs for the device */
3259         rcu_read_lock();
3260         for_each_rmrr_units(rmrr) {
3261                 for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt,
3262                                           i, i_dev) {
3263                         if (i_dev != dev)
3264                                 continue;
3265
3266                         ret = domain_prepare_identity_map(dev, domain,
3267                                                           rmrr->base_address,
3268                                                           rmrr->end_address);
3269                         if (ret)
3270                                 dev_err(dev, "Mapping reserved region failed\n");
3271                 }
3272         }
3273         rcu_read_unlock();
3274
3275         return domain;
3276 }
3277
3278 static inline struct dmar_domain *get_valid_domain_for_dev(struct device *dev)
3279 {
3280         struct device_domain_info *info;
3281
3282         /* No lock here, assumes no domain exit in normal case */
3283         info = dev->archdata.iommu;
3284         if (likely(info))
3285                 return info->domain;
3286
3287         return __get_valid_domain_for_dev(dev);
3288 }
3289
3290 /* Check if the dev needs to go through non-identity map and unmap process.*/
3291 static int iommu_no_mapping(struct device *dev)
3292 {
3293         int found;
3294
3295         if (iommu_dummy(dev))
3296                 return 1;
3297
3298         if (!iommu_identity_mapping)
3299                 return 0;
3300
3301         found = identity_mapping(dev);
3302         if (found) {
3303                 if (iommu_should_identity_map(dev, 0))
3304                         return 1;
3305                 else {
3306                         /*
3307                          * 32 bit DMA is removed from si_domain and fall back
3308                          * to non-identity mapping.
3309                          */
3310                         dmar_remove_one_dev_info(si_domain, dev);
3311                         pr_info("32bit %s uses non-identity mapping\n",
3312                                 dev_name(dev));
3313                         return 0;
3314                 }
3315         } else {
3316                 /*
3317                  * In case of a detached 64 bit DMA device from vm, the device
3318                  * is put into si_domain for identity mapping.
3319                  */
3320                 if (iommu_should_identity_map(dev, 0)) {
3321                         int ret;
3322                         ret = domain_add_dev_info(si_domain, dev);
3323                         if (!ret) {
3324                                 pr_info("64bit %s uses identity mapping\n",
3325                                         dev_name(dev));
3326                                 return 1;
3327                         }
3328                 }
3329         }
3330
3331         return 0;
3332 }
3333
3334 static dma_addr_t __intel_map_single(struct device *dev, phys_addr_t paddr,
3335                                      size_t size, int dir, u64 dma_mask)
3336 {
3337         struct dmar_domain *domain;
3338         phys_addr_t start_paddr;
3339         struct iova *iova;
3340         int prot = 0;
3341         int ret;
3342         struct intel_iommu *iommu;
3343         unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
3344
3345         BUG_ON(dir == DMA_NONE);
3346
3347         if (iommu_no_mapping(dev))
3348                 return paddr;
3349
3350         domain = get_valid_domain_for_dev(dev);
3351         if (!domain)
3352                 return 0;
3353
3354         iommu = domain_get_iommu(domain);
3355         size = aligned_nrpages(paddr, size);
3356
3357         iova = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size), dma_mask);
3358         if (!iova)
3359                 goto error;
3360
3361         /*
3362          * Check if DMAR supports zero-length reads on write only
3363          * mappings..
3364          */
3365         if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
3366                         !cap_zlr(iommu->cap))
3367                 prot |= DMA_PTE_READ;
3368         if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
3369                 prot |= DMA_PTE_WRITE;
3370         /*
3371          * paddr - (paddr + size) might be partial page, we should map the whole
3372          * page.  Note: if two part of one page are separately mapped, we
3373          * might have two guest_addr mapping to the same host paddr, but this
3374          * is not a big problem
3375          */
3376         ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
3377                                  mm_to_dma_pfn(paddr_pfn), size, prot);
3378         if (ret)
3379                 goto error;
3380
3381         /* it's a non-present to present mapping. Only flush if caching mode */
3382         if (cap_caching_mode(iommu->cap))
3383                 iommu_flush_iotlb_psi(iommu, domain,
3384                                       mm_to_dma_pfn(iova->pfn_lo),
3385                                       size, 0, 1);
3386         else
3387                 iommu_flush_write_buffer(iommu);
3388
3389         start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
3390         start_paddr += paddr & ~PAGE_MASK;
3391         return start_paddr;
3392
3393 error:
3394         if (iova)
3395                 __free_iova(&domain->iovad, iova);
3396         pr_err("Device %s request: %zx@%llx dir %d --- failed\n",
3397                 dev_name(dev), size, (unsigned long long)paddr, dir);
3398         return 0;
3399 }
3400
3401 static dma_addr_t intel_map_page(struct device *dev, struct page *page,
3402                                  unsigned long offset, size_t size,
3403                                  enum dma_data_direction dir,
3404                                  struct dma_attrs *attrs)
3405 {
3406         return __intel_map_single(dev, page_to_phys(page) + offset, size,
3407                                   dir, *dev->dma_mask);
3408 }
3409
3410 static void flush_unmaps(void)
3411 {
3412         int i, j;
3413
3414         timer_on = 0;
3415
3416         /* just flush them all */
3417         for (i = 0; i < g_num_of_iommus; i++) {
3418                 struct intel_iommu *iommu = g_iommus[i];
3419                 if (!iommu)
3420                         continue;
3421
3422                 if (!deferred_flush[i].next)
3423                         continue;
3424
3425                 /* In caching mode, global flushes turn emulation expensive */
3426                 if (!cap_caching_mode(iommu->cap))
3427                         iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3428                                          DMA_TLB_GLOBAL_FLUSH);
3429                 for (j = 0; j < deferred_flush[i].next; j++) {
3430                         unsigned long mask;
3431                         struct iova *iova = deferred_flush[i].iova[j];
3432                         struct dmar_domain *domain = deferred_flush[i].domain[j];
3433
3434                         /* On real hardware multiple invalidations are expensive */
3435                         if (cap_caching_mode(iommu->cap))
3436                                 iommu_flush_iotlb_psi(iommu, domain,
3437                                         iova->pfn_lo, iova_size(iova),
3438                                         !deferred_flush[i].freelist[j], 0);
3439                         else {
3440                                 mask = ilog2(mm_to_dma_pfn(iova_size(iova)));
3441                                 iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
3442                                                 (uint64_t)iova->pfn_lo << PAGE_SHIFT, mask);
3443                         }
3444                         __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
3445                         if (deferred_flush[i].freelist[j])
3446                                 dma_free_pagelist(deferred_flush[i].freelist[j]);
3447                 }
3448                 deferred_flush[i].next = 0;
3449         }
3450
3451         list_size = 0;
3452 }
3453
3454 static void flush_unmaps_timeout(unsigned long data)
3455 {
3456         unsigned long flags;
3457
3458         spin_lock_irqsave(&async_umap_flush_lock, flags);
3459         flush_unmaps();
3460         spin_unlock_irqrestore(&async_umap_flush_lock, flags);
3461 }
3462
3463 static void add_unmap(struct dmar_domain *dom, struct iova *iova, struct page *freelist)
3464 {
3465         unsigned long flags;
3466         int next, iommu_id;
3467         struct intel_iommu *iommu;
3468
3469         spin_lock_irqsave(&async_umap_flush_lock, flags);
3470         if (list_size == HIGH_WATER_MARK)
3471                 flush_unmaps();
3472
3473         iommu = domain_get_iommu(dom);
3474         iommu_id = iommu->seq_id;
3475
3476         next = deferred_flush[iommu_id].next;
3477         deferred_flush[iommu_id].domain[next] = dom;
3478         deferred_flush[iommu_id].iova[next] = iova;
3479         deferred_flush[iommu_id].freelist[next] = freelist;
3480         deferred_flush[iommu_id].next++;
3481
3482         if (!timer_on) {
3483                 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
3484                 timer_on = 1;
3485         }
3486         list_size++;
3487         spin_unlock_irqrestore(&async_umap_flush_lock, flags);
3488 }
3489
3490 static void intel_unmap(struct device *dev, dma_addr_t dev_addr)
3491 {
3492         struct dmar_domain *domain;
3493         unsigned long start_pfn, last_pfn;
3494         struct iova *iova;
3495         struct intel_iommu *iommu;
3496         struct page *freelist;
3497
3498         if (iommu_no_mapping(dev))
3499                 return;
3500
3501         domain = find_domain(dev);
3502         BUG_ON(!domain);
3503
3504         iommu = domain_get_iommu(domain);
3505
3506         iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
3507         if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
3508                       (unsigned long long)dev_addr))
3509                 return;
3510
3511         start_pfn = mm_to_dma_pfn(iova->pfn_lo);
3512         last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
3513
3514         pr_debug("Device %s unmapping: pfn %lx-%lx\n",
3515                  dev_name(dev), start_pfn, last_pfn);
3516
3517         freelist = domain_unmap(domain, start_pfn, last_pfn);
3518
3519         if (intel_iommu_strict) {
3520                 iommu_flush_iotlb_psi(iommu, domain, start_pfn,
3521                                       last_pfn - start_pfn + 1, !freelist, 0);
3522                 /* free iova */
3523                 __free_iova(&domain->iovad, iova);
3524                 dma_free_pagelist(freelist);
3525         } else {
3526                 add_unmap(domain, iova, freelist);
3527                 /*
3528                  * queue up the release of the unmap to save the 1/6th of the
3529                  * cpu used up by the iotlb flush operation...
3530                  */
3531         }
3532 }
3533
3534 static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
3535                              size_t size, enum dma_data_direction dir,
3536                              struct dma_attrs *attrs)
3537 {
3538         intel_unmap(dev, dev_addr);
3539 }
3540
3541 static void *intel_alloc_coherent(struct device *dev, size_t size,
3542                                   dma_addr_t *dma_handle, gfp_t flags,
3543                                   struct dma_attrs *attrs)
3544 {
3545         struct page *page = NULL;
3546         int order;
3547
3548         size = PAGE_ALIGN(size);
3549         order = get_order(size);
3550
3551         if (!iommu_no_mapping(dev))
3552                 flags &= ~(GFP_DMA | GFP_DMA32);
3553         else if (dev->coherent_dma_mask < dma_get_required_mask(dev)) {
3554                 if (dev->coherent_dma_mask < DMA_BIT_MASK(32))
3555                         flags |= GFP_DMA;
3556                 else
3557                         flags |= GFP_DMA32;
3558         }
3559
3560         if (flags & __GFP_WAIT) {
3561                 unsigned int count = size >> PAGE_SHIFT;
3562
3563                 page = dma_alloc_from_contiguous(dev, count, order);
3564                 if (page && iommu_no_mapping(dev) &&
3565                     page_to_phys(page) + size > dev->coherent_dma_mask) {
3566                         dma_release_from_contiguous(dev, page, count);
3567                         page = NULL;
3568                 }
3569         }
3570
3571         if (!page)
3572                 page = alloc_pages(flags, order);
3573         if (!page)
3574                 return NULL;
3575         memset(page_address(page), 0, size);
3576
3577         *dma_handle = __intel_map_single(dev, page_to_phys(page), size,
3578                                          DMA_BIDIRECTIONAL,
3579                                          dev->coherent_dma_mask);
3580         if (*dma_handle)
3581                 return page_address(page);
3582         if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
3583                 __free_pages(page, order);
3584
3585         return NULL;
3586 }
3587
3588 static void intel_free_coherent(struct device *dev, size_t size, void *vaddr,
3589                                 dma_addr_t dma_handle, struct dma_attrs *attrs)
3590 {
3591         int order;
3592         struct page *page = virt_to_page(vaddr);
3593
3594         size = PAGE_ALIGN(size);
3595         order = get_order(size);
3596
3597         intel_unmap(dev, dma_handle);
3598         if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
3599                 __free_pages(page, order);
3600 }
3601
3602 static void intel_unmap_sg(struct device *dev, struct scatterlist *sglist,
3603                            int nelems, enum dma_data_direction dir,
3604                            struct dma_attrs *attrs)
3605 {
3606         intel_unmap(dev, sglist[0].dma_address);
3607 }
3608
3609 static int intel_nontranslate_map_sg(struct device *hddev,
3610         struct scatterlist *sglist, int nelems, int dir)
3611 {
3612         int i;
3613         struct scatterlist *sg;
3614
3615         for_each_sg(sglist, sg, nelems, i) {
3616                 BUG_ON(!sg_page(sg));
3617                 sg->dma_address = sg_phys(sg);
3618                 sg->dma_length = sg->length;
3619         }
3620         return nelems;
3621 }
3622
3623 static int intel_map_sg(struct device *dev, struct scatterlist *sglist, int nelems,
3624                         enum dma_data_direction dir, struct dma_attrs *attrs)
3625 {
3626         int i;
3627         struct dmar_domain *domain;
3628         size_t size = 0;
3629         int prot = 0;
3630         struct iova *iova = NULL;
3631         int ret;
3632         struct scatterlist *sg;
3633         unsigned long start_vpfn;
3634         struct intel_iommu *iommu;
3635
3636         BUG_ON(dir == DMA_NONE);
3637         if (iommu_no_mapping(dev))
3638                 return intel_nontranslate_map_sg(dev, sglist, nelems, dir);
3639
3640         domain = get_valid_domain_for_dev(dev);
3641         if (!domain)
3642                 return 0;
3643
3644         iommu = domain_get_iommu(domain);
3645
3646         for_each_sg(sglist, sg, nelems, i)
3647                 size += aligned_nrpages(sg->offset, sg->length);
3648
3649         iova = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size),
3650                                 *dev->dma_mask);
3651         if (!iova) {
3652                 sglist->dma_length = 0;
3653                 return 0;
3654         }
3655
3656         /*
3657          * Check if DMAR supports zero-length reads on write only
3658          * mappings..
3659          */
3660         if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
3661                         !cap_zlr(iommu->cap))
3662                 prot |= DMA_PTE_READ;
3663         if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
3664                 prot |= DMA_PTE_WRITE;
3665
3666         start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
3667
3668         ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
3669         if (unlikely(ret)) {
3670                 dma_pte_free_pagetable(domain, start_vpfn,
3671                                        start_vpfn + size - 1);
3672                 __free_iova(&domain->iovad, iova);
3673                 return 0;
3674         }
3675
3676         /* it's a non-present to present mapping. Only flush if caching mode */
3677         if (cap_caching_mode(iommu->cap))
3678                 iommu_flush_iotlb_psi(iommu, domain, start_vpfn, size, 0, 1);
3679         else
3680                 iommu_flush_write_buffer(iommu);
3681
3682         return nelems;
3683 }
3684
3685 static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
3686 {
3687         return !dma_addr;
3688 }
3689
3690 struct dma_map_ops intel_dma_ops = {
3691         .alloc = intel_alloc_coherent,
3692         .free = intel_free_coherent,
3693         .map_sg = intel_map_sg,
3694         .unmap_sg = intel_unmap_sg,
3695         .map_page = intel_map_page,
3696         .unmap_page = intel_unmap_page,
3697         .mapping_error = intel_mapping_error,
3698 };
3699
3700 static inline int iommu_domain_cache_init(void)
3701 {
3702         int ret = 0;
3703
3704         iommu_domain_cache = kmem_cache_create("iommu_domain",
3705                                          sizeof(struct dmar_domain),
3706                                          0,
3707                                          SLAB_HWCACHE_ALIGN,
3708
3709                                          NULL);
3710         if (!iommu_domain_cache) {
3711                 pr_err("Couldn't create iommu_domain cache\n");
3712                 ret = -ENOMEM;
3713         }
3714
3715         return ret;
3716 }
3717
3718 static inline int iommu_devinfo_cache_init(void)
3719 {
3720         int ret = 0;
3721
3722         iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
3723                                          sizeof(struct device_domain_info),
3724                                          0,
3725                                          SLAB_HWCACHE_ALIGN,
3726                                          NULL);
3727         if (!iommu_devinfo_cache) {
3728                 pr_err("Couldn't create devinfo cache\n");
3729                 ret = -ENOMEM;
3730         }
3731
3732         return ret;
3733 }
3734
3735 static int __init iommu_init_mempool(void)
3736 {
3737         int ret;
3738         ret = iommu_iova_cache_init();
3739         if (ret)
3740                 return ret;
3741
3742         ret = iommu_domain_cache_init();
3743         if (ret)
3744                 goto domain_error;
3745
3746         ret = iommu_devinfo_cache_init();
3747         if (!ret)
3748                 return ret;
3749
3750         kmem_cache_destroy(iommu_domain_cache);
3751 domain_error:
3752         iommu_iova_cache_destroy();
3753
3754         return -ENOMEM;
3755 }
3756
3757 static void __init iommu_exit_mempool(void)
3758 {
3759         kmem_cache_destroy(iommu_devinfo_cache);
3760         kmem_cache_destroy(iommu_domain_cache);
3761         iommu_iova_cache_destroy();
3762 }
3763
3764 static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev)
3765 {
3766         struct dmar_drhd_unit *drhd;
3767         u32 vtbar;
3768         int rc;
3769
3770         /* We know that this device on this chipset has its own IOMMU.
3771          * If we find it under a different IOMMU, then the BIOS is lying
3772          * to us. Hope that the IOMMU for this device is actually
3773          * disabled, and it needs no translation...
3774          */
3775         rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar);
3776         if (rc) {
3777                 /* "can't" happen */
3778                 dev_info(&pdev->dev, "failed to run vt-d quirk\n");
3779                 return;
3780         }
3781         vtbar &= 0xffff0000;
3782
3783         /* we know that the this iommu should be at offset 0xa000 from vtbar */
3784         drhd = dmar_find_matched_drhd_unit(pdev);
3785         if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000,
3786                             TAINT_FIRMWARE_WORKAROUND,
3787                             "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n"))
3788                 pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3789 }
3790 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu);
3791
3792 static void __init init_no_remapping_devices(void)
3793 {
3794         struct dmar_drhd_unit *drhd;
3795         struct device *dev;
3796         int i;
3797
3798         for_each_drhd_unit(drhd) {
3799                 if (!drhd->include_all) {
3800                         for_each_active_dev_scope(drhd->devices,
3801                                                   drhd->devices_cnt, i, dev)
3802                                 break;
3803                         /* ignore DMAR unit if no devices exist */
3804                         if (i == drhd->devices_cnt)
3805                                 drhd->ignored = 1;
3806                 }
3807         }
3808
3809         for_each_active_drhd_unit(drhd) {
3810                 if (drhd->include_all)
3811                         continue;
3812
3813                 for_each_active_dev_scope(drhd->devices,
3814                                           drhd->devices_cnt, i, dev)
3815                         if (!dev_is_pci(dev) || !IS_GFX_DEVICE(to_pci_dev(dev)))
3816                                 break;
3817                 if (i < drhd->devices_cnt)
3818                         continue;
3819
3820                 /* This IOMMU has *only* gfx devices. Either bypass it or
3821                    set the gfx_mapped flag, as appropriate */
3822                 if (dmar_map_gfx) {
3823                         intel_iommu_gfx_mapped = 1;
3824                 } else {
3825                         drhd->ignored = 1;
3826                         for_each_active_dev_scope(drhd->devices,
3827                                                   drhd->devices_cnt, i, dev)
3828                                 dev->archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3829                 }
3830         }
3831 }
3832
3833 #ifdef CONFIG_SUSPEND
3834 static int init_iommu_hw(void)
3835 {
3836         struct dmar_drhd_unit *drhd;
3837         struct intel_iommu *iommu = NULL;
3838
3839         for_each_active_iommu(iommu, drhd)
3840                 if (iommu->qi)
3841                         dmar_reenable_qi(iommu);
3842
3843         for_each_iommu(iommu, drhd) {
3844                 if (drhd->ignored) {
3845                         /*
3846                          * we always have to disable PMRs or DMA may fail on
3847                          * this device
3848                          */
3849                         if (force_on)
3850                                 iommu_disable_protect_mem_regions(iommu);
3851                         continue;
3852                 }
3853
3854                 iommu_flush_write_buffer(iommu);
3855
3856                 iommu_set_root_entry(iommu);
3857
3858                 iommu->flush.flush_context(iommu, 0, 0, 0,
3859                                            DMA_CCMD_GLOBAL_INVL);
3860                 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
3861                 iommu_enable_translation(iommu);
3862                 iommu_disable_protect_mem_regions(iommu);
3863         }
3864
3865         return 0;
3866 }
3867
3868 static void iommu_flush_all(void)
3869 {
3870         struct dmar_drhd_unit *drhd;
3871         struct intel_iommu *iommu;
3872
3873         for_each_active_iommu(iommu, drhd) {
3874                 iommu->flush.flush_context(iommu, 0, 0, 0,
3875                                            DMA_CCMD_GLOBAL_INVL);
3876                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3877                                          DMA_TLB_GLOBAL_FLUSH);
3878         }
3879 }
3880
3881 static int iommu_suspend(void)
3882 {
3883         struct dmar_drhd_unit *drhd;
3884         struct intel_iommu *iommu = NULL;
3885         unsigned long flag;
3886
3887         for_each_active_iommu(iommu, drhd) {
3888                 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3889                                                  GFP_ATOMIC);
3890                 if (!iommu->iommu_state)
3891                         goto nomem;
3892         }
3893
3894         iommu_flush_all();
3895
3896         for_each_active_iommu(iommu, drhd) {
3897                 iommu_disable_translation(iommu);
3898
3899                 raw_spin_lock_irqsave(&iommu->register_lock, flag);
3900
3901                 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3902                         readl(iommu->reg + DMAR_FECTL_REG);
3903                 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3904                         readl(iommu->reg + DMAR_FEDATA_REG);
3905                 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3906                         readl(iommu->reg + DMAR_FEADDR_REG);
3907                 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3908                         readl(iommu->reg + DMAR_FEUADDR_REG);
3909
3910                 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
3911         }
3912         return 0;
3913
3914 nomem:
3915         for_each_active_iommu(iommu, drhd)
3916                 kfree(iommu->iommu_state);
3917
3918         return -ENOMEM;
3919 }
3920
3921 static void iommu_resume(void)
3922 {
3923         struct dmar_drhd_unit *drhd;
3924         struct intel_iommu *iommu = NULL;
3925         unsigned long flag;
3926
3927         if (init_iommu_hw()) {
3928                 if (force_on)
3929                         panic("tboot: IOMMU setup failed, DMAR can not resume!\n");
3930                 else
3931                         WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3932                 return;
3933         }
3934
3935         for_each_active_iommu(iommu, drhd) {
3936
3937                 raw_spin_lock_irqsave(&iommu->register_lock, flag);
3938
3939                 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3940                         iommu->reg + DMAR_FECTL_REG);
3941                 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3942                         iommu->reg + DMAR_FEDATA_REG);
3943                 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3944                         iommu->reg + DMAR_FEADDR_REG);
3945                 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3946                         iommu->reg + DMAR_FEUADDR_REG);
3947
3948                 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
3949         }
3950
3951         for_each_active_iommu(iommu, drhd)
3952                 kfree(iommu->iommu_state);
3953 }
3954
3955 static struct syscore_ops iommu_syscore_ops = {
3956         .resume         = iommu_resume,
3957         .suspend        = iommu_suspend,
3958 };
3959
3960 static void __init init_iommu_pm_ops(void)
3961 {
3962         register_syscore_ops(&iommu_syscore_ops);
3963 }
3964
3965 #else
3966 static inline void init_iommu_pm_ops(void) {}
3967 #endif  /* CONFIG_PM */
3968
3969
3970 int __init dmar_parse_one_rmrr(struct acpi_dmar_header *header, void *arg)
3971 {
3972         struct acpi_dmar_reserved_memory *rmrr;
3973         struct dmar_rmrr_unit *rmrru;
3974
3975         rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL);
3976         if (!rmrru)
3977                 return -ENOMEM;
3978
3979         rmrru->hdr = header;
3980         rmrr = (struct acpi_dmar_reserved_memory *)header;
3981         rmrru->base_address = rmrr->base_address;
3982         rmrru->end_address = rmrr->end_address;
3983         rmrru->devices = dmar_alloc_dev_scope((void *)(rmrr + 1),
3984                                 ((void *)rmrr) + rmrr->header.length,
3985                                 &rmrru->devices_cnt);
3986         if (rmrru->devices_cnt && rmrru->devices == NULL) {
3987                 kfree(rmrru);
3988                 return -ENOMEM;
3989         }
3990
3991         list_add(&rmrru->list, &dmar_rmrr_units);
3992
3993         return 0;
3994 }
3995
3996 static struct dmar_atsr_unit *dmar_find_atsr(struct acpi_dmar_atsr *atsr)
3997 {
3998         struct dmar_atsr_unit *atsru;
3999         struct acpi_dmar_atsr *tmp;
4000
4001         list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) {
4002                 tmp = (struct acpi_dmar_atsr *)atsru->hdr;
4003                 if (atsr->segment != tmp->segment)
4004                         continue;
4005                 if (atsr->header.length != tmp->header.length)
4006                         continue;
4007                 if (memcmp(atsr, tmp, atsr->header.length) == 0)
4008                         return atsru;
4009         }
4010
4011         return NULL;
4012 }
4013
4014 int dmar_parse_one_atsr(struct acpi_dmar_header *hdr, void *arg)
4015 {
4016         struct acpi_dmar_atsr *atsr;
4017         struct dmar_atsr_unit *atsru;
4018
4019         if (system_state != SYSTEM_BOOTING && !intel_iommu_enabled)
4020                 return 0;
4021
4022         atsr = container_of(hdr, struct acpi_dmar_atsr, header);
4023         atsru = dmar_find_atsr(atsr);
4024         if (atsru)
4025                 return 0;
4026
4027         atsru = kzalloc(sizeof(*atsru) + hdr->length, GFP_KERNEL);
4028         if (!atsru)
4029                 return -ENOMEM;
4030
4031         /*
4032          * If memory is allocated from slab by ACPI _DSM method, we need to
4033          * copy the memory content because the memory buffer will be freed
4034          * on return.
4035          */
4036         atsru->hdr = (void *)(atsru + 1);
4037         memcpy(atsru->hdr, hdr, hdr->length);
4038         atsru->include_all = atsr->flags & 0x1;
4039         if (!atsru->include_all) {
4040                 atsru->devices = dmar_alloc_dev_scope((void *)(atsr + 1),
4041                                 (void *)atsr + atsr->header.length,
4042                                 &atsru->devices_cnt);
4043                 if (atsru->devices_cnt && atsru->devices == NULL) {
4044                         kfree(atsru);
4045                         return -ENOMEM;
4046                 }
4047         }
4048
4049         list_add_rcu(&atsru->list, &dmar_atsr_units);
4050
4051         return 0;
4052 }
4053
4054 static void intel_iommu_free_atsr(struct dmar_atsr_unit *atsru)
4055 {
4056         dmar_free_dev_scope(&atsru->devices, &atsru->devices_cnt);
4057         kfree(atsru);
4058 }
4059
4060 int dmar_release_one_atsr(struct acpi_dmar_header *hdr, void *arg)
4061 {
4062         struct acpi_dmar_atsr *atsr;
4063         struct dmar_atsr_unit *atsru;
4064
4065         atsr = container_of(hdr, struct acpi_dmar_atsr, header);
4066         atsru = dmar_find_atsr(atsr);
4067         if (atsru) {
4068                 list_del_rcu(&atsru->list);
4069                 synchronize_rcu();
4070                 intel_iommu_free_atsr(atsru);
4071         }
4072
4073         return 0;
4074 }
4075
4076 int dmar_check_one_atsr(struct acpi_dmar_header *hdr, void *arg)
4077 {
4078         int i;
4079         struct device *dev;
4080         struct acpi_dmar_atsr *atsr;
4081         struct dmar_atsr_unit *atsru;
4082
4083         atsr = container_of(hdr, struct acpi_dmar_atsr, header);
4084         atsru = dmar_find_atsr(atsr);
4085         if (!atsru)
4086                 return 0;
4087
4088         if (!atsru->include_all && atsru->devices && atsru->devices_cnt)
4089                 for_each_active_dev_scope(atsru->devices, atsru->devices_cnt,
4090                                           i, dev)
4091                         return -EBUSY;
4092
4093         return 0;
4094 }
4095
4096 static int intel_iommu_add(struct dmar_drhd_unit *dmaru)
4097 {
4098         int sp, ret = 0;
4099         struct intel_iommu *iommu = dmaru->iommu;
4100
4101         if (g_iommus[iommu->seq_id])
4102                 return 0;
4103
4104         if (hw_pass_through && !ecap_pass_through(iommu->ecap)) {
4105                 pr_warn("%s: Doesn't support hardware pass through.\n",
4106                         iommu->name);
4107                 return -ENXIO;
4108         }
4109         if (!ecap_sc_support(iommu->ecap) &&
4110             domain_update_iommu_snooping(iommu)) {
4111                 pr_warn("%s: Doesn't support snooping.\n",
4112                         iommu->name);
4113                 return -ENXIO;
4114         }
4115         sp = domain_update_iommu_superpage(iommu) - 1;
4116         if (sp >= 0 && !(cap_super_page_val(iommu->cap) & (1 << sp))) {
4117                 pr_warn("%s: Doesn't support large page.\n",
4118                         iommu->name);
4119                 return -ENXIO;
4120         }
4121
4122         /*
4123          * Disable translation if already enabled prior to OS handover.
4124          */
4125         if (iommu->gcmd & DMA_GCMD_TE)
4126                 iommu_disable_translation(iommu);
4127
4128         g_iommus[iommu->seq_id] = iommu;
4129         ret = iommu_init_domains(iommu);
4130         if (ret == 0)
4131                 ret = iommu_alloc_root_entry(iommu);
4132         if (ret)
4133                 goto out;
4134
4135         if (dmaru->ignored) {
4136                 /*
4137                  * we always have to disable PMRs or DMA may fail on this device
4138                  */
4139                 if (force_on)
4140                         iommu_disable_protect_mem_regions(iommu);
4141                 return 0;
4142         }
4143
4144         intel_iommu_init_qi(iommu);
4145         iommu_flush_write_buffer(iommu);
4146         ret = dmar_set_interrupt(iommu);
4147         if (ret)
4148                 goto disable_iommu;
4149
4150         iommu_set_root_entry(iommu);
4151         iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
4152         iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
4153         iommu_enable_translation(iommu);
4154
4155         iommu_disable_protect_mem_regions(iommu);
4156         return 0;
4157
4158 disable_iommu:
4159         disable_dmar_iommu(iommu);
4160 out:
4161         free_dmar_iommu(iommu);
4162         return ret;
4163 }
4164
4165 int dmar_iommu_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
4166 {
4167         int ret = 0;
4168         struct intel_iommu *iommu = dmaru->iommu;
4169
4170         if (!intel_iommu_enabled)
4171                 return 0;
4172         if (iommu == NULL)
4173                 return -EINVAL;
4174
4175         if (insert) {
4176                 ret = intel_iommu_add(dmaru);
4177         } else {
4178                 disable_dmar_iommu(iommu);
4179                 free_dmar_iommu(iommu);
4180         }
4181
4182         return ret;
4183 }
4184
4185 static void intel_iommu_free_dmars(void)
4186 {
4187         struct dmar_rmrr_unit *rmrru, *rmrr_n;
4188         struct dmar_atsr_unit *atsru, *atsr_n;
4189
4190         list_for_each_entry_safe(rmrru, rmrr_n, &dmar_rmrr_units, list) {
4191                 list_del(&rmrru->list);
4192                 dmar_free_dev_scope(&rmrru->devices, &rmrru->devices_cnt);
4193                 kfree(rmrru);
4194         }
4195
4196         list_for_each_entry_safe(atsru, atsr_n, &dmar_atsr_units, list) {
4197                 list_del(&atsru->list);
4198                 intel_iommu_free_atsr(atsru);
4199         }
4200 }
4201
4202 int dmar_find_matched_atsr_unit(struct pci_dev *dev)
4203 {
4204         int i, ret = 1;
4205         struct pci_bus *bus;
4206         struct pci_dev *bridge = NULL;
4207         struct device *tmp;
4208         struct acpi_dmar_atsr *atsr;
4209         struct dmar_atsr_unit *atsru;
4210
4211         dev = pci_physfn(dev);
4212         for (bus = dev->bus; bus; bus = bus->parent) {
4213                 bridge = bus->self;
4214                 if (!bridge || !pci_is_pcie(bridge) ||
4215                     pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)
4216                         return 0;
4217                 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT)
4218                         break;
4219         }
4220         if (!bridge)
4221                 return 0;
4222
4223         rcu_read_lock();
4224         list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) {
4225                 atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
4226                 if (atsr->segment != pci_domain_nr(dev->bus))
4227                         continue;
4228
4229                 for_each_dev_scope(atsru->devices, atsru->devices_cnt, i, tmp)
4230                         if (tmp == &bridge->dev)
4231                                 goto out;
4232
4233                 if (atsru->include_all)
4234                         goto out;
4235         }
4236         ret = 0;
4237 out:
4238         rcu_read_unlock();
4239
4240         return ret;
4241 }
4242
4243 int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info)
4244 {
4245         int ret = 0;
4246         struct dmar_rmrr_unit *rmrru;
4247         struct dmar_atsr_unit *atsru;
4248         struct acpi_dmar_atsr *atsr;
4249         struct acpi_dmar_reserved_memory *rmrr;
4250
4251         if (!intel_iommu_enabled && system_state != SYSTEM_BOOTING)
4252                 return 0;
4253
4254         list_for_each_entry(rmrru, &dmar_rmrr_units, list) {
4255                 rmrr = container_of(rmrru->hdr,
4256                                     struct acpi_dmar_reserved_memory, header);
4257                 if (info->event == BUS_NOTIFY_ADD_DEVICE) {
4258                         ret = dmar_insert_dev_scope(info, (void *)(rmrr + 1),
4259                                 ((void *)rmrr) + rmrr->header.length,
4260                                 rmrr->segment, rmrru->devices,
4261                                 rmrru->devices_cnt);
4262                         if(ret < 0)
4263                                 return ret;
4264                 } else if (info->event == BUS_NOTIFY_DEL_DEVICE) {
4265                         dmar_remove_dev_scope(info, rmrr->segment,
4266                                 rmrru->devices, rmrru->devices_cnt);
4267                 }
4268         }
4269
4270         list_for_each_entry(atsru, &dmar_atsr_units, list) {
4271                 if (atsru->include_all)
4272                         continue;
4273
4274                 atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
4275                 if (info->event == BUS_NOTIFY_ADD_DEVICE) {
4276                         ret = dmar_insert_dev_scope(info, (void *)(atsr + 1),
4277                                         (void *)atsr + atsr->header.length,
4278                                         atsr->segment, atsru->devices,
4279                                         atsru->devices_cnt);
4280                         if (ret > 0)
4281                                 break;
4282                         else if(ret < 0)
4283                                 return ret;
4284                 } else if (info->event == BUS_NOTIFY_DEL_DEVICE) {
4285                         if (dmar_remove_dev_scope(info, atsr->segment,
4286                                         atsru->devices, atsru->devices_cnt))
4287                                 break;
4288                 }
4289         }
4290
4291         return 0;
4292 }
4293
4294 /*
4295  * Here we only respond to action of unbound device from driver.
4296  *
4297  * Added device is not attached to its DMAR domain here yet. That will happen
4298  * when mapping the device to iova.
4299  */
4300 static int device_notifier(struct notifier_block *nb,
4301                                   unsigned long action, void *data)
4302 {
4303         struct device *dev = data;
4304         struct dmar_domain *domain;
4305
4306         if (iommu_dummy(dev))
4307                 return 0;
4308
4309         if (action != BUS_NOTIFY_REMOVED_DEVICE)
4310                 return 0;
4311
4312         domain = find_domain(dev);
4313         if (!domain)
4314                 return 0;
4315
4316         dmar_remove_one_dev_info(domain, dev);
4317         if (!domain_type_is_vm_or_si(domain) && list_empty(&domain->devices))
4318                 domain_exit(domain);
4319
4320         return 0;
4321 }
4322
4323 static struct notifier_block device_nb = {
4324         .notifier_call = device_notifier,
4325 };
4326
4327 static int intel_iommu_memory_notifier(struct notifier_block *nb,
4328                                        unsigned long val, void *v)
4329 {
4330         struct memory_notify *mhp = v;
4331         unsigned long long start, end;
4332         unsigned long start_vpfn, last_vpfn;
4333
4334         switch (val) {
4335         case MEM_GOING_ONLINE:
4336                 start = mhp->start_pfn << PAGE_SHIFT;
4337                 end = ((mhp->start_pfn + mhp->nr_pages) << PAGE_SHIFT) - 1;
4338                 if (iommu_domain_identity_map(si_domain, start, end)) {
4339                         pr_warn("Failed to build identity map for [%llx-%llx]\n",
4340                                 start, end);
4341                         return NOTIFY_BAD;
4342                 }
4343                 break;
4344
4345         case MEM_OFFLINE:
4346         case MEM_CANCEL_ONLINE:
4347                 start_vpfn = mm_to_dma_pfn(mhp->start_pfn);
4348                 last_vpfn = mm_to_dma_pfn(mhp->start_pfn + mhp->nr_pages - 1);
4349                 while (start_vpfn <= last_vpfn) {
4350                         struct iova *iova;
4351                         struct dmar_drhd_unit *drhd;
4352                         struct intel_iommu *iommu;
4353                         struct page *freelist;
4354
4355                         iova = find_iova(&si_domain->iovad, start_vpfn);
4356                         if (iova == NULL) {
4357                                 pr_debug("Failed get IOVA for PFN %lx\n",
4358                                          start_vpfn);
4359                                 break;
4360                         }
4361
4362                         iova = split_and_remove_iova(&si_domain->iovad, iova,
4363                                                      start_vpfn, last_vpfn);
4364                         if (iova == NULL) {
4365                                 pr_warn("Failed to split IOVA PFN [%lx-%lx]\n",
4366                                         start_vpfn, last_vpfn);
4367                                 return NOTIFY_BAD;
4368                         }
4369
4370                         freelist = domain_unmap(si_domain, iova->pfn_lo,
4371                                                iova->pfn_hi);
4372
4373                         rcu_read_lock();
4374                         for_each_active_iommu(iommu, drhd)
4375                                 iommu_flush_iotlb_psi(iommu, si_domain,
4376                                         iova->pfn_lo, iova_size(iova),
4377                                         !freelist, 0);
4378                         rcu_read_unlock();
4379                         dma_free_pagelist(freelist);
4380
4381                         start_vpfn = iova->pfn_hi + 1;
4382                         free_iova_mem(iova);
4383                 }
4384                 break;
4385         }
4386
4387         return NOTIFY_OK;
4388 }
4389
4390 static struct notifier_block intel_iommu_memory_nb = {
4391         .notifier_call = intel_iommu_memory_notifier,
4392         .priority = 0
4393 };
4394
4395
4396 static ssize_t intel_iommu_show_version(struct device *dev,
4397                                         struct device_attribute *attr,
4398                                         char *buf)
4399 {
4400         struct intel_iommu *iommu = dev_get_drvdata(dev);
4401         u32 ver = readl(iommu->reg + DMAR_VER_REG);
4402         return sprintf(buf, "%d:%d\n",
4403                        DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver));
4404 }
4405 static DEVICE_ATTR(version, S_IRUGO, intel_iommu_show_version, NULL);
4406
4407 static ssize_t intel_iommu_show_address(struct device *dev,
4408                                         struct device_attribute *attr,
4409                                         char *buf)
4410 {
4411         struct intel_iommu *iommu = dev_get_drvdata(dev);
4412         return sprintf(buf, "%llx\n", iommu->reg_phys);
4413 }
4414 static DEVICE_ATTR(address, S_IRUGO, intel_iommu_show_address, NULL);
4415
4416 static ssize_t intel_iommu_show_cap(struct device *dev,
4417                                     struct device_attribute *attr,
4418                                     char *buf)
4419 {
4420         struct intel_iommu *iommu = dev_get_drvdata(dev);
4421         return sprintf(buf, "%llx\n", iommu->cap);
4422 }
4423 static DEVICE_ATTR(cap, S_IRUGO, intel_iommu_show_cap, NULL);
4424
4425 static ssize_t intel_iommu_show_ecap(struct device *dev,
4426                                     struct device_attribute *attr,
4427                                     char *buf)
4428 {
4429         struct intel_iommu *iommu = dev_get_drvdata(dev);
4430         return sprintf(buf, "%llx\n", iommu->ecap);
4431 }
4432 static DEVICE_ATTR(ecap, S_IRUGO, intel_iommu_show_ecap, NULL);
4433
4434 static ssize_t intel_iommu_show_ndoms(struct device *dev,
4435                                       struct device_attribute *attr,
4436                                       char *buf)
4437 {
4438         struct intel_iommu *iommu = dev_get_drvdata(dev);
4439         return sprintf(buf, "%ld\n", cap_ndoms(iommu->cap));
4440 }
4441 static DEVICE_ATTR(domains_supported, S_IRUGO, intel_iommu_show_ndoms, NULL);
4442
4443 static ssize_t intel_iommu_show_ndoms_used(struct device *dev,
4444                                            struct device_attribute *attr,
4445                                            char *buf)
4446 {
4447         struct intel_iommu *iommu = dev_get_drvdata(dev);
4448         return sprintf(buf, "%d\n", bitmap_weight(iommu->domain_ids,
4449                                                   cap_ndoms(iommu->cap)));
4450 }
4451 static DEVICE_ATTR(domains_used, S_IRUGO, intel_iommu_show_ndoms_used, NULL);
4452
4453 static struct attribute *intel_iommu_attrs[] = {
4454         &dev_attr_version.attr,
4455         &dev_attr_address.attr,
4456         &dev_attr_cap.attr,
4457         &dev_attr_ecap.attr,
4458         &dev_attr_domains_supported.attr,
4459         &dev_attr_domains_used.attr,
4460         NULL,
4461 };
4462
4463 static struct attribute_group intel_iommu_group = {
4464         .name = "intel-iommu",
4465         .attrs = intel_iommu_attrs,
4466 };
4467
4468 const struct attribute_group *intel_iommu_groups[] = {
4469         &intel_iommu_group,
4470         NULL,
4471 };
4472
4473 int __init intel_iommu_init(void)
4474 {
4475         int ret = -ENODEV;
4476         struct dmar_drhd_unit *drhd;
4477         struct intel_iommu *iommu;
4478
4479         /* VT-d is required for a TXT/tboot launch, so enforce that */
4480         force_on = tboot_force_iommu();
4481
4482         if (iommu_init_mempool()) {
4483                 if (force_on)
4484                         panic("tboot: Failed to initialize iommu memory\n");
4485                 return -ENOMEM;
4486         }
4487
4488         down_write(&dmar_global_lock);
4489         if (dmar_table_init()) {
4490                 if (force_on)
4491                         panic("tboot: Failed to initialize DMAR table\n");
4492                 goto out_free_dmar;
4493         }
4494
4495         if (dmar_dev_scope_init() < 0) {
4496                 if (force_on)
4497                         panic("tboot: Failed to initialize DMAR device scope\n");
4498                 goto out_free_dmar;
4499         }
4500
4501         if (no_iommu || dmar_disabled)
4502                 goto out_free_dmar;
4503
4504         if (list_empty(&dmar_rmrr_units))
4505                 pr_info("No RMRR found\n");
4506
4507         if (list_empty(&dmar_atsr_units))
4508                 pr_info("No ATSR found\n");
4509
4510         if (dmar_init_reserved_ranges()) {
4511                 if (force_on)
4512                         panic("tboot: Failed to reserve iommu ranges\n");
4513                 goto out_free_reserved_range;
4514         }
4515
4516         init_no_remapping_devices();
4517
4518         ret = init_dmars();
4519         if (ret) {
4520                 if (force_on)
4521                         panic("tboot: Failed to initialize DMARs\n");
4522                 pr_err("Initialization failed\n");
4523                 goto out_free_reserved_range;
4524         }
4525         up_write(&dmar_global_lock);
4526         pr_info("Intel(R) Virtualization Technology for Directed I/O\n");
4527
4528         init_timer(&unmap_timer);
4529 #ifdef CONFIG_SWIOTLB
4530         swiotlb = 0;
4531 #endif
4532         dma_ops = &intel_dma_ops;
4533
4534         init_iommu_pm_ops();
4535
4536         for_each_active_iommu(iommu, drhd)
4537                 iommu->iommu_dev = iommu_device_create(NULL, iommu,
4538                                                        intel_iommu_groups,
4539                                                        "%s", iommu->name);
4540
4541         bus_set_iommu(&pci_bus_type, &intel_iommu_ops);
4542         bus_register_notifier(&pci_bus_type, &device_nb);
4543         if (si_domain && !hw_pass_through)
4544                 register_memory_notifier(&intel_iommu_memory_nb);
4545
4546         intel_iommu_enabled = 1;
4547
4548         return 0;
4549
4550 out_free_reserved_range:
4551         put_iova_domain(&reserved_iova_list);
4552 out_free_dmar:
4553         intel_iommu_free_dmars();
4554         up_write(&dmar_global_lock);
4555         iommu_exit_mempool();
4556         return ret;
4557 }
4558
4559 static int domain_context_clear_one_cb(struct pci_dev *pdev, u16 alias, void *opaque)
4560 {
4561         struct intel_iommu *iommu = opaque;
4562
4563         domain_context_clear_one(iommu, PCI_BUS_NUM(alias), alias & 0xff);
4564         return 0;
4565 }
4566
4567 /*
4568  * NB - intel-iommu lacks any sort of reference counting for the users of
4569  * dependent devices.  If multiple endpoints have intersecting dependent
4570  * devices, unbinding the driver from any one of them will possibly leave
4571  * the others unable to operate.
4572  */
4573 static void domain_context_clear(struct intel_iommu *iommu, struct device *dev)
4574 {
4575         if (!iommu || !dev || !dev_is_pci(dev))
4576                 return;
4577
4578         pci_for_each_dma_alias(to_pci_dev(dev), &domain_context_clear_one_cb, iommu);
4579 }
4580
4581 static void __dmar_remove_one_dev_info(struct device_domain_info *info)
4582 {
4583         struct intel_iommu *iommu;
4584         unsigned long flags;
4585
4586         assert_spin_locked(&device_domain_lock);
4587
4588         if (WARN_ON(!info))
4589                 return;
4590
4591         iommu = info->iommu;
4592
4593         if (info->dev) {
4594                 iommu_disable_dev_iotlb(info);
4595                 domain_context_clear(iommu, info->dev);
4596         }
4597
4598         unlink_domain_info(info);
4599
4600         spin_lock_irqsave(&iommu->lock, flags);
4601         domain_detach_iommu(info->domain, iommu);
4602         spin_unlock_irqrestore(&iommu->lock, flags);
4603
4604         free_devinfo_mem(info);
4605 }
4606
4607 static void dmar_remove_one_dev_info(struct dmar_domain *domain,
4608                                      struct device *dev)
4609 {
4610         struct device_domain_info *info;
4611         unsigned long flags;
4612
4613         spin_lock_irqsave(&device_domain_lock, flags);
4614         info = dev->archdata.iommu;
4615         __dmar_remove_one_dev_info(info);
4616         spin_unlock_irqrestore(&device_domain_lock, flags);
4617 }
4618
4619 static int md_domain_init(struct dmar_domain *domain, int guest_width)
4620 {
4621         int adjust_width;
4622
4623         init_iova_domain(&domain->iovad, VTD_PAGE_SIZE, IOVA_START_PFN,
4624                         DMA_32BIT_PFN);
4625         domain_reserve_special_ranges(domain);
4626
4627         /* calculate AGAW */
4628         domain->gaw = guest_width;
4629         adjust_width = guestwidth_to_adjustwidth(guest_width);
4630         domain->agaw = width_to_agaw(adjust_width);
4631
4632         domain->iommu_coherency = 0;
4633         domain->iommu_snooping = 0;
4634         domain->iommu_superpage = 0;
4635         domain->max_addr = 0;
4636
4637         /* always allocate the top pgd */
4638         domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
4639         if (!domain->pgd)
4640                 return -ENOMEM;
4641         domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
4642         return 0;
4643 }
4644
4645 static struct iommu_domain *intel_iommu_domain_alloc(unsigned type)
4646 {
4647         struct dmar_domain *dmar_domain;
4648         struct iommu_domain *domain;
4649
4650         if (type != IOMMU_DOMAIN_UNMANAGED)
4651                 return NULL;
4652
4653         dmar_domain = alloc_domain(DOMAIN_FLAG_VIRTUAL_MACHINE);
4654         if (!dmar_domain) {
4655                 pr_err("Can't allocate dmar_domain\n");
4656                 return NULL;
4657         }
4658         if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
4659                 pr_err("Domain initialization failed\n");
4660                 domain_exit(dmar_domain);
4661                 return NULL;
4662         }
4663         domain_update_iommu_cap(dmar_domain);
4664
4665         domain = &dmar_domain->domain;
4666         domain->geometry.aperture_start = 0;
4667         domain->geometry.aperture_end   = __DOMAIN_MAX_ADDR(dmar_domain->gaw);
4668         domain->geometry.force_aperture = true;
4669
4670         return domain;
4671 }
4672
4673 static void intel_iommu_domain_free(struct iommu_domain *domain)
4674 {
4675         domain_exit(to_dmar_domain(domain));
4676 }
4677
4678 static int intel_iommu_attach_device(struct iommu_domain *domain,
4679                                      struct device *dev)
4680 {
4681         struct dmar_domain *dmar_domain = to_dmar_domain(domain);
4682         struct intel_iommu *iommu;
4683         int addr_width;
4684         u8 bus, devfn;
4685
4686         if (device_is_rmrr_locked(dev)) {
4687                 dev_warn(dev, "Device is ineligible for IOMMU domain attach due to platform RMRR requirement.  Contact your platform vendor.\n");
4688                 return -EPERM;
4689         }
4690
4691         /* normally dev is not mapped */
4692         if (unlikely(domain_context_mapped(dev))) {
4693                 struct dmar_domain *old_domain;
4694
4695                 old_domain = find_domain(dev);
4696                 if (old_domain) {
4697                         rcu_read_lock();
4698                         dmar_remove_one_dev_info(old_domain, dev);
4699                         rcu_read_unlock();
4700
4701                         if (!domain_type_is_vm_or_si(old_domain) &&
4702                              list_empty(&old_domain->devices))
4703                                 domain_exit(old_domain);
4704                 }
4705         }
4706
4707         iommu = device_to_iommu(dev, &bus, &devfn);
4708         if (!iommu)
4709                 return -ENODEV;
4710
4711         /* check if this iommu agaw is sufficient for max mapped address */
4712         addr_width = agaw_to_width(iommu->agaw);
4713         if (addr_width > cap_mgaw(iommu->cap))
4714                 addr_width = cap_mgaw(iommu->cap);
4715
4716         if (dmar_domain->max_addr > (1LL << addr_width)) {
4717                 pr_err("%s: iommu width (%d) is not "
4718                        "sufficient for the mapped address (%llx)\n",
4719                        __func__, addr_width, dmar_domain->max_addr);
4720                 return -EFAULT;
4721         }
4722         dmar_domain->gaw = addr_width;
4723
4724         /*
4725          * Knock out extra levels of page tables if necessary
4726          */
4727         while (iommu->agaw < dmar_domain->agaw) {
4728                 struct dma_pte *pte;
4729
4730                 pte = dmar_domain->pgd;
4731                 if (dma_pte_present(pte)) {
4732                         dmar_domain->pgd = (struct dma_pte *)
4733                                 phys_to_virt(dma_pte_addr(pte));
4734                         free_pgtable_page(pte);
4735                 }
4736                 dmar_domain->agaw--;
4737         }
4738
4739         return domain_add_dev_info(dmar_domain, dev);
4740 }
4741
4742 static void intel_iommu_detach_device(struct iommu_domain *domain,
4743                                       struct device *dev)
4744 {
4745         dmar_remove_one_dev_info(to_dmar_domain(domain), dev);
4746 }
4747
4748 static int intel_iommu_map(struct iommu_domain *domain,
4749                            unsigned long iova, phys_addr_t hpa,
4750                            size_t size, int iommu_prot)
4751 {
4752         struct dmar_domain *dmar_domain = to_dmar_domain(domain);
4753         u64 max_addr;
4754         int prot = 0;
4755         int ret;
4756
4757         if (iommu_prot & IOMMU_READ)
4758                 prot |= DMA_PTE_READ;
4759         if (iommu_prot & IOMMU_WRITE)
4760                 prot |= DMA_PTE_WRITE;
4761         if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
4762                 prot |= DMA_PTE_SNP;
4763
4764         max_addr = iova + size;
4765         if (dmar_domain->max_addr < max_addr) {
4766                 u64 end;
4767
4768                 /* check if minimum agaw is sufficient for mapped address */
4769                 end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1;
4770                 if (end < max_addr) {
4771                         pr_err("%s: iommu width (%d) is not "
4772                                "sufficient for the mapped address (%llx)\n",
4773                                __func__, dmar_domain->gaw, max_addr);
4774                         return -EFAULT;
4775                 }
4776                 dmar_domain->max_addr = max_addr;
4777         }
4778         /* Round up size to next multiple of PAGE_SIZE, if it and
4779            the low bits of hpa would take us onto the next page */
4780         size = aligned_nrpages(hpa, size);
4781         ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
4782                                  hpa >> VTD_PAGE_SHIFT, size, prot);
4783         return ret;
4784 }
4785
4786 static size_t intel_iommu_unmap(struct iommu_domain *domain,
4787                                 unsigned long iova, size_t size)
4788 {
4789         struct dmar_domain *dmar_domain = to_dmar_domain(domain);
4790         struct page *freelist = NULL;
4791         struct intel_iommu *iommu;
4792         unsigned long start_pfn, last_pfn;
4793         unsigned int npages;
4794         int iommu_id, level = 0;
4795
4796         /* Cope with horrid API which requires us to unmap more than the
4797            size argument if it happens to be a large-page mapping. */
4798         BUG_ON(!pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level));
4799
4800         if (size < VTD_PAGE_SIZE << level_to_offset_bits(level))
4801                 size = VTD_PAGE_SIZE << level_to_offset_bits(level);
4802
4803         start_pfn = iova >> VTD_PAGE_SHIFT;
4804         last_pfn = (iova + size - 1) >> VTD_PAGE_SHIFT;
4805
4806         freelist = domain_unmap(dmar_domain, start_pfn, last_pfn);
4807
4808         npages = last_pfn - start_pfn + 1;
4809
4810         for_each_domain_iommu(iommu_id, dmar_domain) {
4811                 iommu = g_iommus[iommu_id];
4812
4813                 iommu_flush_iotlb_psi(g_iommus[iommu_id], dmar_domain,
4814                                       start_pfn, npages, !freelist, 0);
4815         }
4816
4817         dma_free_pagelist(freelist);
4818
4819         if (dmar_domain->max_addr == iova + size)
4820                 dmar_domain->max_addr = iova;
4821
4822         return size;
4823 }
4824
4825 static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
4826                                             dma_addr_t iova)
4827 {
4828         struct dmar_domain *dmar_domain = to_dmar_domain(domain);
4829         struct dma_pte *pte;
4830         int level = 0;
4831         u64 phys = 0;
4832
4833         pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level);
4834         if (pte)
4835                 phys = dma_pte_addr(pte);
4836
4837         return phys;
4838 }
4839
4840 static bool intel_iommu_capable(enum iommu_cap cap)
4841 {
4842         if (cap == IOMMU_CAP_CACHE_COHERENCY)
4843                 return domain_update_iommu_snooping(NULL) == 1;
4844         if (cap == IOMMU_CAP_INTR_REMAP)
4845                 return irq_remapping_enabled == 1;
4846
4847         return false;
4848 }
4849
4850 static int intel_iommu_add_device(struct device *dev)
4851 {
4852         struct intel_iommu *iommu;
4853         struct iommu_group *group;
4854         u8 bus, devfn;
4855
4856         iommu = device_to_iommu(dev, &bus, &devfn);
4857         if (!iommu)
4858                 return -ENODEV;
4859
4860         iommu_device_link(iommu->iommu_dev, dev);
4861
4862         group = iommu_group_get_for_dev(dev);
4863
4864         if (IS_ERR(group))
4865                 return PTR_ERR(group);
4866
4867         iommu_group_put(group);
4868         return 0;
4869 }
4870
4871 static void intel_iommu_remove_device(struct device *dev)
4872 {
4873         struct intel_iommu *iommu;
4874         u8 bus, devfn;
4875
4876         iommu = device_to_iommu(dev, &bus, &devfn);
4877         if (!iommu)
4878                 return;
4879
4880         iommu_group_remove_device(dev);
4881
4882         iommu_device_unlink(iommu->iommu_dev, dev);
4883 }
4884
4885 static const struct iommu_ops intel_iommu_ops = {
4886         .capable        = intel_iommu_capable,
4887         .domain_alloc   = intel_iommu_domain_alloc,
4888         .domain_free    = intel_iommu_domain_free,
4889         .attach_dev     = intel_iommu_attach_device,
4890         .detach_dev     = intel_iommu_detach_device,
4891         .map            = intel_iommu_map,
4892         .unmap          = intel_iommu_unmap,
4893         .map_sg         = default_iommu_map_sg,
4894         .iova_to_phys   = intel_iommu_iova_to_phys,
4895         .add_device     = intel_iommu_add_device,
4896         .remove_device  = intel_iommu_remove_device,
4897         .pgsize_bitmap  = INTEL_IOMMU_PGSIZES,
4898 };
4899
4900 static void quirk_iommu_g4x_gfx(struct pci_dev *dev)
4901 {
4902         /* G4x/GM45 integrated gfx dmar support is totally busted. */
4903         pr_info("Disabling IOMMU for graphics on this chipset\n");
4904         dmar_map_gfx = 0;
4905 }
4906
4907 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx);
4908 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx);
4909 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx);
4910 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx);
4911 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx);
4912 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx);
4913 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx);
4914
4915 static void quirk_iommu_rwbf(struct pci_dev *dev)
4916 {
4917         /*
4918          * Mobile 4 Series Chipset neglects to set RWBF capability,
4919          * but needs it. Same seems to hold for the desktop versions.
4920          */
4921         pr_info("Forcing write-buffer flush capability\n");
4922         rwbf_quirk = 1;
4923 }
4924
4925 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
4926 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf);
4927 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf);
4928 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf);
4929 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf);
4930 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf);
4931 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf);
4932
4933 #define GGC 0x52
4934 #define GGC_MEMORY_SIZE_MASK    (0xf << 8)
4935 #define GGC_MEMORY_SIZE_NONE    (0x0 << 8)
4936 #define GGC_MEMORY_SIZE_1M      (0x1 << 8)
4937 #define GGC_MEMORY_SIZE_2M      (0x3 << 8)
4938 #define GGC_MEMORY_VT_ENABLED   (0x8 << 8)
4939 #define GGC_MEMORY_SIZE_2M_VT   (0x9 << 8)
4940 #define GGC_MEMORY_SIZE_3M_VT   (0xa << 8)
4941 #define GGC_MEMORY_SIZE_4M_VT   (0xb << 8)
4942
4943 static void quirk_calpella_no_shadow_gtt(struct pci_dev *dev)
4944 {
4945         unsigned short ggc;
4946
4947         if (pci_read_config_word(dev, GGC, &ggc))
4948                 return;
4949
4950         if (!(ggc & GGC_MEMORY_VT_ENABLED)) {
4951                 pr_info("BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n");
4952                 dmar_map_gfx = 0;
4953         } else if (dmar_map_gfx) {
4954                 /* we have to ensure the gfx device is idle before we flush */
4955                 pr_info("Disabling batched IOTLB flush on Ironlake\n");
4956                 intel_iommu_strict = 1;
4957        }
4958 }
4959 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt);
4960 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt);
4961 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0062, quirk_calpella_no_shadow_gtt);
4962 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x006a, quirk_calpella_no_shadow_gtt);
4963
4964 /* On Tylersburg chipsets, some BIOSes have been known to enable the
4965    ISOCH DMAR unit for the Azalia sound device, but not give it any
4966    TLB entries, which causes it to deadlock. Check for that.  We do
4967    this in a function called from init_dmars(), instead of in a PCI
4968    quirk, because we don't want to print the obnoxious "BIOS broken"
4969    message if VT-d is actually disabled.
4970 */
4971 static void __init check_tylersburg_isoch(void)
4972 {
4973         struct pci_dev *pdev;
4974         uint32_t vtisochctrl;
4975
4976         /* If there's no Azalia in the system anyway, forget it. */
4977         pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x3a3e, NULL);
4978         if (!pdev)
4979                 return;
4980         pci_dev_put(pdev);
4981
4982         /* System Management Registers. Might be hidden, in which case
4983            we can't do the sanity check. But that's OK, because the
4984            known-broken BIOSes _don't_ actually hide it, so far. */
4985         pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x342e, NULL);
4986         if (!pdev)
4987                 return;
4988
4989         if (pci_read_config_dword(pdev, 0x188, &vtisochctrl)) {
4990                 pci_dev_put(pdev);
4991                 return;
4992         }
4993
4994         pci_dev_put(pdev);
4995
4996         /* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */
4997         if (vtisochctrl & 1)
4998                 return;
4999
5000         /* Drop all bits other than the number of TLB entries */
5001         vtisochctrl &= 0x1c;
5002
5003         /* If we have the recommended number of TLB entries (16), fine. */
5004         if (vtisochctrl == 0x10)
5005                 return;
5006
5007         /* Zero TLB entries? You get to ride the short bus to school. */
5008         if (!vtisochctrl) {
5009                 WARN(1, "Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space.\n"
5010                      "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
5011                      dmi_get_system_info(DMI_BIOS_VENDOR),
5012                      dmi_get_system_info(DMI_BIOS_VERSION),
5013                      dmi_get_system_info(DMI_PRODUCT_VERSION));
5014                 iommu_identity_mapping |= IDENTMAP_AZALIA;
5015                 return;
5016         }
5017
5018         pr_warn("Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n",
5019                vtisochctrl);
5020 }