2 * Renesas INTC External IRQ Pin Driver
4 * Copyright (C) 2013 Magnus Damm
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/ioport.h>
27 #include <linux/irq.h>
28 #include <linux/irqdomain.h>
29 #include <linux/err.h>
30 #include <linux/slab.h>
31 #include <linux/module.h>
32 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
34 #define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
36 #define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
37 #define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
38 #define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
39 #define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
40 #define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
41 #define INTC_IRQPIN_REG_NR 5
43 /* INTC external IRQ PIN hardware register access:
45 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
46 * PRIO is read-write 32-bit with 4-bits per IRQ (**)
47 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
48 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
49 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
51 * (*) May be accessed by more than one driver instance - lock needed
52 * (**) Read-modify-write access by one driver instance - lock needed
53 * (***) Accessed by one driver instance only - no locking needed
56 struct intc_irqpin_iomem {
58 unsigned long (*read)(void __iomem *iomem);
59 void (*write)(void __iomem *iomem, unsigned long data);
63 struct intc_irqpin_irq {
67 struct intc_irqpin_priv *p;
70 struct intc_irqpin_priv {
71 struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
72 struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
73 struct renesas_intc_irqpin_config config;
74 unsigned int number_of_irqs;
75 struct platform_device *pdev;
76 struct irq_chip irq_chip;
77 struct irq_domain *irq_domain;
82 static unsigned long intc_irqpin_read32(void __iomem *iomem)
84 return ioread32(iomem);
87 static unsigned long intc_irqpin_read8(void __iomem *iomem)
89 return ioread8(iomem);
92 static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
94 iowrite32(data, iomem);
97 static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
99 iowrite8(data, iomem);
102 static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
105 struct intc_irqpin_iomem *i = &p->iomem[reg];
107 return i->read(i->iomem);
110 static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
111 int reg, unsigned long data)
113 struct intc_irqpin_iomem *i = &p->iomem[reg];
115 i->write(i->iomem, data);
118 static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
121 return BIT((p->iomem[reg].width - 1) - hw_irq);
124 static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
127 intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
130 static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
132 static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
134 int width, int value)
139 raw_spin_lock_irqsave(&intc_irqpin_lock, flags);
141 tmp = intc_irqpin_read(p, reg);
142 tmp &= ~(((1 << width) - 1) << shift);
143 tmp |= value << shift;
144 intc_irqpin_write(p, reg, tmp);
146 raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
149 static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
150 int irq, int do_mask)
152 int bitfield_width = 4; /* PRIO assumed to have fixed bitfield width */
153 int shift = (7 - irq) * bitfield_width; /* PRIO assumed to be 32-bit */
155 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
156 shift, bitfield_width,
157 do_mask ? 0 : (1 << bitfield_width) - 1);
160 static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
162 int bitfield_width = p->config.sense_bitfield_width;
163 int shift = (7 - irq) * bitfield_width; /* SENSE assumed to be 32-bit */
165 dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
167 if (value >= (1 << bitfield_width))
170 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
171 bitfield_width, value);
175 static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str)
177 dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
178 str, i->requested_irq, i->hw_irq, i->domain_irq);
181 static void intc_irqpin_irq_enable(struct irq_data *d)
183 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
184 int hw_irq = irqd_to_hwirq(d);
186 intc_irqpin_dbg(&p->irq[hw_irq], "enable");
187 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
190 static void intc_irqpin_irq_disable(struct irq_data *d)
192 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
193 int hw_irq = irqd_to_hwirq(d);
195 intc_irqpin_dbg(&p->irq[hw_irq], "disable");
196 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
199 static void intc_irqpin_shared_irq_enable(struct irq_data *d)
201 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
202 int hw_irq = irqd_to_hwirq(d);
204 intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");
205 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
207 p->shared_irq_mask &= ~BIT(hw_irq);
210 static void intc_irqpin_shared_irq_disable(struct irq_data *d)
212 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
213 int hw_irq = irqd_to_hwirq(d);
215 intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");
216 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
218 p->shared_irq_mask |= BIT(hw_irq);
221 static void intc_irqpin_irq_enable_force(struct irq_data *d)
223 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
224 int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
226 intc_irqpin_irq_enable(d);
228 /* enable interrupt through parent interrupt controller,
229 * assumes non-shared interrupt with 1:1 mapping
230 * needed for busted IRQs on some SoCs like sh73a0
232 irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
235 static void intc_irqpin_irq_disable_force(struct irq_data *d)
237 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
238 int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
240 /* disable interrupt through parent interrupt controller,
241 * assumes non-shared interrupt with 1:1 mapping
242 * needed for busted IRQs on some SoCs like sh73a0
244 irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
245 intc_irqpin_irq_disable(d);
248 #define INTC_IRQ_SENSE_VALID 0x10
249 #define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
251 static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
252 [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
253 [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
254 [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
255 [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
256 [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
259 static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
261 unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
262 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
264 if (!(value & INTC_IRQ_SENSE_VALID))
267 return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
268 value ^ INTC_IRQ_SENSE_VALID);
271 static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
273 struct intc_irqpin_irq *i = dev_id;
274 struct intc_irqpin_priv *p = i->p;
277 intc_irqpin_dbg(i, "demux1");
278 bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);
280 if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
281 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
282 intc_irqpin_dbg(i, "demux2");
283 generic_handle_irq(i->domain_irq);
289 static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id)
291 struct intc_irqpin_priv *p = dev_id;
292 unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE);
293 irqreturn_t status = IRQ_NONE;
296 for (k = 0; k < 8; k++) {
297 if (reg_source & BIT(7 - k)) {
298 if (BIT(k) & p->shared_irq_mask)
301 status |= intc_irqpin_irq_handler(irq, &p->irq[k]);
308 static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
311 struct intc_irqpin_priv *p = h->host_data;
313 p->irq[hw].domain_irq = virq;
314 p->irq[hw].hw_irq = hw;
316 intc_irqpin_dbg(&p->irq[hw], "map");
317 irq_set_chip_data(virq, h->host_data);
318 irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
319 set_irq_flags(virq, IRQF_VALID); /* kill me now */
323 static struct irq_domain_ops intc_irqpin_irq_domain_ops = {
324 .map = intc_irqpin_irq_domain_map,
325 .xlate = irq_domain_xlate_twocell,
328 static int intc_irqpin_probe(struct platform_device *pdev)
330 struct renesas_intc_irqpin_config *pdata = pdev->dev.platform_data;
331 struct intc_irqpin_priv *p;
332 struct intc_irqpin_iomem *i;
333 struct resource *io[INTC_IRQPIN_REG_NR];
334 struct resource *irq;
335 struct irq_chip *irq_chip;
336 void (*enable_fn)(struct irq_data *d);
337 void (*disable_fn)(struct irq_data *d);
338 const char *name = dev_name(&pdev->dev);
343 p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
345 dev_err(&pdev->dev, "failed to allocate driver data\n");
350 /* deal with driver instance configuration */
352 memcpy(&p->config, pdata, sizeof(*pdata));
354 of_property_read_u32(pdev->dev.of_node, "sense-bitfield-width",
355 &p->config.sense_bitfield_width);
356 p->config.control_parent = of_property_read_bool(pdev->dev.of_node,
359 if (!p->config.sense_bitfield_width)
360 p->config.sense_bitfield_width = 4; /* default to 4 bits */
363 platform_set_drvdata(pdev, p);
365 /* get hold of manadatory IOMEM */
366 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
367 io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
369 dev_err(&pdev->dev, "not enough IOMEM resources\n");
375 /* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
376 for (k = 0; k < INTC_IRQPIN_MAX; k++) {
377 irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
382 p->irq[k].requested_irq = irq->start;
385 p->number_of_irqs = k;
386 if (p->number_of_irqs < 1) {
387 dev_err(&pdev->dev, "not enough IRQ resources\n");
392 /* ioremap IOMEM and setup read/write callbacks */
393 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
396 switch (resource_size(io[k])) {
399 i->read = intc_irqpin_read8;
400 i->write = intc_irqpin_write8;
404 i->read = intc_irqpin_read32;
405 i->write = intc_irqpin_write32;
408 dev_err(&pdev->dev, "IOMEM size mismatch\n");
413 i->iomem = devm_ioremap_nocache(&pdev->dev, io[k]->start,
414 resource_size(io[k]));
416 dev_err(&pdev->dev, "failed to remap IOMEM\n");
422 /* mask all interrupts using priority */
423 for (k = 0; k < p->number_of_irqs; k++)
424 intc_irqpin_mask_unmask_prio(p, k, 1);
426 /* clear all pending interrupts */
427 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0);
429 /* scan for shared interrupt lines */
430 ref_irq = p->irq[0].requested_irq;
431 p->shared_irqs = true;
432 for (k = 1; k < p->number_of_irqs; k++) {
433 if (ref_irq != p->irq[k].requested_irq) {
434 p->shared_irqs = false;
439 /* use more severe masking method if requested */
440 if (p->config.control_parent) {
441 enable_fn = intc_irqpin_irq_enable_force;
442 disable_fn = intc_irqpin_irq_disable_force;
443 } else if (!p->shared_irqs) {
444 enable_fn = intc_irqpin_irq_enable;
445 disable_fn = intc_irqpin_irq_disable;
447 enable_fn = intc_irqpin_shared_irq_enable;
448 disable_fn = intc_irqpin_shared_irq_disable;
451 irq_chip = &p->irq_chip;
452 irq_chip->name = name;
453 irq_chip->irq_mask = disable_fn;
454 irq_chip->irq_unmask = enable_fn;
455 irq_chip->irq_enable = enable_fn;
456 irq_chip->irq_disable = disable_fn;
457 irq_chip->irq_set_type = intc_irqpin_irq_set_type;
458 irq_chip->flags = IRQCHIP_SKIP_SET_WAKE;
460 p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
463 &intc_irqpin_irq_domain_ops, p);
464 if (!p->irq_domain) {
466 dev_err(&pdev->dev, "cannot initialize irq domain\n");
470 if (p->shared_irqs) {
471 /* request one shared interrupt */
472 if (devm_request_irq(&pdev->dev, p->irq[0].requested_irq,
473 intc_irqpin_shared_irq_handler,
474 IRQF_SHARED, name, p)) {
475 dev_err(&pdev->dev, "failed to request low IRQ\n");
480 /* request interrupts one by one */
481 for (k = 0; k < p->number_of_irqs; k++) {
482 if (devm_request_irq(&pdev->dev,
483 p->irq[k].requested_irq,
484 intc_irqpin_irq_handler,
485 0, name, &p->irq[k])) {
487 "failed to request low IRQ\n");
494 /* unmask all interrupts on prio level */
495 for (k = 0; k < p->number_of_irqs; k++)
496 intc_irqpin_mask_unmask_prio(p, k, 0);
498 dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs);
500 /* warn in case of mismatch if irq base is specified */
501 if (p->config.irq_base) {
502 if (p->config.irq_base != p->irq[0].domain_irq)
503 dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n",
504 p->config.irq_base, p->irq[0].domain_irq);
510 irq_domain_remove(p->irq_domain);
515 static int intc_irqpin_remove(struct platform_device *pdev)
517 struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
519 irq_domain_remove(p->irq_domain);
524 static const struct of_device_id intc_irqpin_dt_ids[] = {
525 { .compatible = "renesas,intc-irqpin", },
528 MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);
530 static struct platform_driver intc_irqpin_device_driver = {
531 .probe = intc_irqpin_probe,
532 .remove = intc_irqpin_remove,
534 .name = "renesas_intc_irqpin",
535 .of_match_table = intc_irqpin_dt_ids,
536 .owner = THIS_MODULE,
540 static int __init intc_irqpin_init(void)
542 return platform_driver_register(&intc_irqpin_device_driver);
544 postcore_initcall(intc_irqpin_init);
546 static void __exit intc_irqpin_exit(void)
548 platform_driver_unregister(&intc_irqpin_device_driver);
550 module_exit(intc_irqpin_exit);
552 MODULE_AUTHOR("Magnus Damm");
553 MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
554 MODULE_LICENSE("GPL v2");