drivers/mmc/dw_mmc.c

   1 /*
   2  * (C) Copyright 2012 SAMSUNG Electronics
   3  * Jaehoon Chung <jh80.chung@samsung.com>
   4  * Rajeshawari Shinde <rajeshwari.s@samsung.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <bouncebuf.h>
  10 #include <common.h>
  11 #include <malloc.h>
  12 #include <mmc.h>
  13 #include <dwmmc.h>
  14 #include <asm-generic/errno.h>
  15
  16 #define PAGE_SIZE 4096
  17
  18 static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
  19 {
  20         unsigned long timeout = 1000;
  21         u32 ctrl;
  22
  23         dwmci_writel(host, DWMCI_CTRL, value);
  24
  25         while (timeout--) {
  26                 ctrl = dwmci_readl(host, DWMCI_CTRL);
  27                 if (!(ctrl & DWMCI_RESET_ALL))
  28                         return 1;
  29         }
  30         return 0;
  31 }
  32
  33 static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
  34                 u32 desc0, u32 desc1, u32 desc2)
  35 {
  36         struct dwmci_idmac *desc = idmac;
  37
  38         desc->flags = desc0;
  39         desc->cnt = desc1;
  40         desc->addr = desc2;
  41         desc->next_addr = (unsigned int)desc + sizeof(struct dwmci_idmac);
  42 }
  43
  44 static void dwmci_prepare_data(struct dwmci_host *host,
  45                                struct mmc_data *data,
  46                                struct dwmci_idmac *cur_idmac,
  47                                void *bounce_buffer)
  48 {
  49         unsigned long ctrl;
  50         unsigned int i = 0, flags, cnt, blk_cnt;
  51         ulong data_start, data_end;
  52
  53
  54         blk_cnt = data->blocks;
  55
  56         dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
  57
  58         data_start = (ulong)cur_idmac;
  59         dwmci_writel(host, DWMCI_DBADDR, (unsigned int)cur_idmac);
  60
  61         do {
  62                 flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
  63                 flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
  64                 if (blk_cnt <= 8) {
  65                         flags |= DWMCI_IDMAC_LD;
  66                         cnt = data->blocksize * blk_cnt;
  67                 } else
  68                         cnt = data->blocksize * 8;
  69
  70                 dwmci_set_idma_desc(cur_idmac, flags, cnt,
  71                                     (u32)bounce_buffer + (i * PAGE_SIZE));
  72
  73                 if (blk_cnt <= 8)
  74                         break;
  75                 blk_cnt -= 8;
  76                 cur_idmac++;
  77                 i++;
  78         } while(1);
  79
  80         data_end = (ulong)cur_idmac;
  81         flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
  82
  83         ctrl = dwmci_readl(host, DWMCI_CTRL);
  84         ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
  85         dwmci_writel(host, DWMCI_CTRL, ctrl);
  86
  87         ctrl = dwmci_readl(host, DWMCI_BMOD);
  88         ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
  89         dwmci_writel(host, DWMCI_BMOD, ctrl);
  90
  91         dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
  92         dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
  93 }
  94
  95 static int dwmci_set_transfer_mode(struct dwmci_host *host,
  96                 struct mmc_data *data)
  97 {
  98         unsigned long mode;
  99
 100         mode = DWMCI_CMD_DATA_EXP;
 101         if (data->flags & MMC_DATA_WRITE)
 102                 mode |= DWMCI_CMD_RW;
 103
 104         return mode;
 105 }
 106
 107 static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 108                 struct mmc_data *data)
 109 {
 110         struct dwmci_host *host = mmc->priv;
 111         ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
 112                                  data ? DIV_ROUND_UP(data->blocks, 8) : 0);
 113         int flags = 0, i;
 114         unsigned int timeout = 100000;
 115         u32 retry = 10000;
 116         u32 mask, ctrl;
 117         ulong start = get_timer(0);
 118         struct bounce_buffer bbstate;
 119
 120         while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
 121                 if (get_timer(start) > timeout) {
 122                         printf("Timeout on data busy\n");
 123                         return TIMEOUT;
 124                 }
 125         }
 126
 127         dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
 128
 129         if (data) {
 130                 if (data->flags == MMC_DATA_READ) {
 131                         bounce_buffer_start(&bbstate, (void*)data->dest,
 132                                             data->blocksize *
 133                                             data->blocks, GEN_BB_WRITE);
 134                 } else {
 135                         bounce_buffer_start(&bbstate, (void*)data->src,
 136                                             data->blocksize *
 137                                             data->blocks, GEN_BB_READ);
 138                 }
 139                 dwmci_prepare_data(host, data, cur_idmac,
 140                                    bbstate.bounce_buffer);
 141         }
 142
 143         dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
 144
 145         if (data)
 146                 flags = dwmci_set_transfer_mode(host, data);
 147
 148         if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
 149                 return -1;
 150
 151         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 152                 flags |= DWMCI_CMD_ABORT_STOP;
 153         else
 154                 flags |= DWMCI_CMD_PRV_DAT_WAIT;
 155
 156         if (cmd->resp_type & MMC_RSP_PRESENT) {
 157                 flags |= DWMCI_CMD_RESP_EXP;
 158                 if (cmd->resp_type & MMC_RSP_136)
 159                         flags |= DWMCI_CMD_RESP_LENGTH;
 160         }
 161
 162         if (cmd->resp_type & MMC_RSP_CRC)
 163                 flags |= DWMCI_CMD_CHECK_CRC;
 164
 165         flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);
 166
 167         debug("Sending CMD%d\n",cmd->cmdidx);
 168
 169         dwmci_writel(host, DWMCI_CMD, flags);
 170
 171         for (i = 0; i < retry; i++) {
 172                 mask = dwmci_readl(host, DWMCI_RINTSTS);
 173                 if (mask & DWMCI_INTMSK_CDONE) {
 174                         if (!data)
 175                                 dwmci_writel(host, DWMCI_RINTSTS, mask);
 176                         break;
 177                 }
 178         }
 179
 180         if (i == retry) {
 181                 printf("dwmci_send_cmd: timeout..\n");
 182                 return TIMEOUT;
 183         }
 184
 185         if (mask & DWMCI_INTMSK_RTO) {
 186                 printf("dwmci_send_cmd: Response Timeout..\n");
 187                 return TIMEOUT;
 188         } else if (mask & DWMCI_INTMSK_RE) {
 189                 printf("dwmci_send_cmd: Response Error..\n");
 190                 return -1;
 191         }
 192
 193
 194         if (cmd->resp_type & MMC_RSP_PRESENT) {
 195                 if (cmd->resp_type & MMC_RSP_136) {
 196                         cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
 197                         cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
 198                         cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
 199                         cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
 200                 } else {
 201                         cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
 202                 }
 203         }
 204
 205         if (data) {
 206                 do {
 207                         mask = dwmci_readl(host, DWMCI_RINTSTS);
 208                         if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
 209                                 printf("dwmci_send_cmd: DATA ERROR!\n");
 210                                 return -1;
 211                         }
 212                 } while (!(mask & DWMCI_INTMSK_DTO));
 213
 214                 dwmci_writel(host, DWMCI_RINTSTS, mask);
 215
 216                 ctrl = dwmci_readl(host, DWMCI_CTRL);
 217                 ctrl &= ~(DWMCI_DMA_EN);
 218                 dwmci_writel(host, DWMCI_CTRL, ctrl);
 219
 220                 bounce_buffer_stop(&bbstate);
 221         }
 222
 223         udelay(100);
 224
 225         return 0;
 226 }
 227
 228 static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
 229 {
 230         u32 div, status;
 231         int timeout = 10000;
 232         unsigned long sclk;
 233
 234         if ((freq == host->clock) || (freq == 0))
 235                 return 0;
 236         /*
 237          * If host->get_mmc_clk isn't defined,
 238          * then assume that host->bus_hz is source clock value.
 239          * host->bus_hz should be set by user.
 240          */
 241         if (host->get_mmc_clk)
 242                 sclk = host->get_mmc_clk(host);
 243         else if (host->bus_hz)
 244                 sclk = host->bus_hz;
 245         else {
 246                 printf("dwmci_setup_bus: Didn't get source clock value..\n");
 247                 return -EINVAL;
 248         }
 249
 250         if (sclk == freq)
 251                 div = 0;        /* bypass mode */
 252         else
 253                 div = DIV_ROUND_UP(sclk, 2 * freq);
 254
 255         dwmci_writel(host, DWMCI_CLKENA, 0);
 256         dwmci_writel(host, DWMCI_CLKSRC, 0);
 257
 258         dwmci_writel(host, DWMCI_CLKDIV, div);
 259         dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
 260                         DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
 261
 262         do {
 263                 status = dwmci_readl(host, DWMCI_CMD);
 264                 if (timeout-- < 0) {
 265                         printf("dwmci_setup_bus: timeout!\n");
 266                         return -ETIMEDOUT;
 267                 }
 268         } while (status & DWMCI_CMD_START);
 269
 270         dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
 271                         DWMCI_CLKEN_LOW_PWR);
 272
 273         dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
 274                         DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
 275
 276         timeout = 10000;
 277         do {
 278                 status = dwmci_readl(host, DWMCI_CMD);
 279                 if (timeout-- < 0) {
 280                         printf("dwmci_setup_bus: timeout!\n");
 281                         return -ETIMEDOUT;
 282                 }
 283         } while (status & DWMCI_CMD_START);
 284
 285         host->clock = freq;
 286
 287         return 0;
 288 }
 289
 290 static void dwmci_set_ios(struct mmc *mmc)
 291 {
 292         struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
 293         u32 ctype, regs;
 294
 295         debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);
 296
 297         dwmci_setup_bus(host, mmc->clock);
 298         switch (mmc->bus_width) {
 299         case 8:
 300                 ctype = DWMCI_CTYPE_8BIT;
 301                 break;
 302         case 4:
 303                 ctype = DWMCI_CTYPE_4BIT;
 304                 break;
 305         default:
 306                 ctype = DWMCI_CTYPE_1BIT;
 307                 break;
 308         }
 309
 310         dwmci_writel(host, DWMCI_CTYPE, ctype);
 311
 312         regs = dwmci_readl(host, DWMCI_UHS_REG);
 313         if (mmc->card_caps & MMC_MODE_DDR_52MHz)
 314                 regs |= DWMCI_DDR_MODE;
 315         else
 316                 regs &= DWMCI_DDR_MODE;
 317
 318         dwmci_writel(host, DWMCI_UHS_REG, regs);
 319
 320         if (host->clksel)
 321                 host->clksel(host);
 322 }
 323
 324 static int dwmci_init(struct mmc *mmc)
 325 {
 326         struct dwmci_host *host = mmc->priv;
 327
 328         if (host->board_init)
 329                 host->board_init(host);
 330
 331         dwmci_writel(host, DWMCI_PWREN, 1);
 332
 333         if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
 334                 printf("%s[%d] Fail-reset!!\n", __func__, __LINE__);
 335                 return -1;
 336         }
 337
 338         /* Enumerate at 400KHz */
 339         dwmci_setup_bus(host, mmc->cfg->f_min);
 340
 341         dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
 342         dwmci_writel(host, DWMCI_INTMASK, 0);
 343
 344         dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
 345
 346         dwmci_writel(host, DWMCI_IDINTEN, 0);
 347         dwmci_writel(host, DWMCI_BMOD, 1);
 348
 349         if (host->fifoth_val) {
 350                 dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
 351         }
 352
 353         dwmci_writel(host, DWMCI_CLKENA, 0);
 354         dwmci_writel(host, DWMCI_CLKSRC, 0);
 355
 356         return 0;
 357 }
 358
 359 static const struct mmc_ops dwmci_ops = {
 360         .send_cmd       = dwmci_send_cmd,
 361         .set_ios        = dwmci_set_ios,
 362         .init           = dwmci_init,
 363 };
 364
 365 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
 366 {
 367         host->cfg.name = host->name;
 368         host->cfg.ops = &dwmci_ops;
 369         host->cfg.f_min = min_clk;
 370         host->cfg.f_max = max_clk;
 371
 372         host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 373
 374         host->cfg.host_caps = host->caps;
 375
 376         if (host->buswidth == 8) {
 377                 host->cfg.host_caps |= MMC_MODE_8BIT;
 378                 host->cfg.host_caps &= ~MMC_MODE_4BIT;
 379         } else {
 380                 host->cfg.host_caps |= MMC_MODE_4BIT;
 381                 host->cfg.host_caps &= ~MMC_MODE_8BIT;
 382         }
 383         host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC;
 384
 385         host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 386
 387         host->mmc = mmc_create(&host->cfg, host);
 388         if (host->mmc == NULL)
 389                 return -1;
 390
 391         return 0;
 392 }