2 * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
4 * Copyright (C) 2012, Samsung Electronics Co., Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/clk.h>
15 #include <linux/mmc/host.h>
16 #include <linux/mmc/dw_mmc.h>
18 #include <linux/of_gpio.h>
21 #include "dw_mmc-pltfm.h"
23 #define NUM_PINS(x) (x + 2)
25 #define SDMMC_CLKSEL 0x09C
26 #define SDMMC_CLKSEL_CCLK_SAMPLE(x) (((x) & 7) << 0)
27 #define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16)
28 #define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24)
29 #define SDMMC_CLKSEL_GET_DRV_WD3(x) (((x) >> 16) & 0x7)
30 #define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \
31 SDMMC_CLKSEL_CCLK_DRIVE(y) | \
32 SDMMC_CLKSEL_CCLK_DIVIDER(z))
34 #define SDMMC_CMD_USE_HOLD_REG BIT(29)
36 #define EXYNOS4210_FIXED_CIU_CLK_DIV 2
37 #define EXYNOS4412_FIXED_CIU_CLK_DIV 4
39 /* Variations in Exynos specific dw-mshc controller */
40 enum dw_mci_exynos_type {
41 DW_MCI_TYPE_EXYNOS4210,
42 DW_MCI_TYPE_EXYNOS4412,
43 DW_MCI_TYPE_EXYNOS5250,
46 /* Exynos implementation specific driver private data */
47 struct dw_mci_exynos_priv_data {
48 enum dw_mci_exynos_type ctrl_type;
54 static struct dw_mci_exynos_compatible {
56 enum dw_mci_exynos_type ctrl_type;
59 .compatible = "samsung,exynos4210-dw-mshc",
60 .ctrl_type = DW_MCI_TYPE_EXYNOS4210,
62 .compatible = "samsung,exynos4412-dw-mshc",
63 .ctrl_type = DW_MCI_TYPE_EXYNOS4412,
65 .compatible = "samsung,exynos5250-dw-mshc",
66 .ctrl_type = DW_MCI_TYPE_EXYNOS5250,
70 static int dw_mci_exynos_priv_init(struct dw_mci *host)
72 struct dw_mci_exynos_priv_data *priv;
75 priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
77 dev_err(host->dev, "mem alloc failed for private data\n");
81 for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
82 if (of_device_is_compatible(host->dev->of_node,
83 exynos_compat[idx].compatible))
84 priv->ctrl_type = exynos_compat[idx].ctrl_type;
91 static int dw_mci_exynos_setup_clock(struct dw_mci *host)
93 struct dw_mci_exynos_priv_data *priv = host->priv;
95 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5250)
96 host->bus_hz /= (priv->ciu_div + 1);
97 else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
98 host->bus_hz /= EXYNOS4412_FIXED_CIU_CLK_DIV;
99 else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
100 host->bus_hz /= EXYNOS4210_FIXED_CIU_CLK_DIV;
105 static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr)
108 * Exynos4412 and Exynos5250 extends the use of CMD register with the
109 * use of bit 29 (which is reserved on standard MSHC controllers) for
110 * optionally bypassing the HOLD register for command and data. The
111 * HOLD register should be bypassed in case there is no phase shift
112 * applied on CMD/DATA that is sent to the card.
114 if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL)))
115 *cmdr |= SDMMC_CMD_USE_HOLD_REG;
118 static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
120 struct dw_mci_exynos_priv_data *priv = host->priv;
122 if (ios->timing == MMC_TIMING_UHS_DDR50)
123 mci_writel(host, CLKSEL, priv->ddr_timing);
125 mci_writel(host, CLKSEL, priv->sdr_timing);
128 static int dw_mci_exynos_parse_dt(struct dw_mci *host)
130 struct dw_mci_exynos_priv_data *priv = host->priv;
131 struct device_node *np = host->dev->of_node;
136 of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
139 ret = of_property_read_u32_array(np,
140 "samsung,dw-mshc-sdr-timing", timing, 2);
144 priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
146 ret = of_property_read_u32_array(np,
147 "samsung,dw-mshc-ddr-timing", timing, 2);
151 priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
155 static int dw_mci_exynos_setup_bus(struct dw_mci *host,
156 struct device_node *slot_np, u8 bus_width)
163 /* cmd + clock + bus-width pins */
164 for (idx = 0; idx < NUM_PINS(bus_width); idx++) {
165 gpio = of_get_gpio(slot_np, idx);
166 if (!gpio_is_valid(gpio)) {
167 dev_err(host->dev, "invalid gpio: %d\n", gpio);
171 ret = devm_gpio_request(host->dev, gpio, "dw-mci-bus");
173 dev_err(host->dev, "gpio [%d] request failed\n", gpio);
178 gpio = of_get_named_gpio(slot_np, "wp-gpios", 0);
179 if (gpio_is_valid(gpio)) {
180 if (devm_gpio_request(host->dev, gpio, "dw-mci-wp"))
181 dev_info(host->dev, "gpio [%d] request failed\n",
184 dev_info(host->dev, "wp gpio not available");
185 host->pdata->quirks |= DW_MCI_QUIRK_NO_WRITE_PROTECT;
188 if (host->pdata->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
191 gpio = of_get_named_gpio(slot_np, "samsung,cd-pinmux-gpio", 0);
192 if (gpio_is_valid(gpio)) {
193 if (devm_gpio_request(host->dev, gpio, "dw-mci-cd"))
194 dev_err(host->dev, "gpio [%d] request failed\n", gpio);
196 dev_info(host->dev, "cd gpio not available");
202 /* Exynos5250 controller specific capabilities */
203 static unsigned long exynos5250_dwmmc_caps[4] = {
204 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
205 MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
211 static struct dw_mci_drv_data exynos5250_drv_data = {
212 .caps = exynos5250_dwmmc_caps,
213 .init = dw_mci_exynos_priv_init,
214 .setup_clock = dw_mci_exynos_setup_clock,
215 .prepare_command = dw_mci_exynos_prepare_command,
216 .set_ios = dw_mci_exynos_set_ios,
217 .parse_dt = dw_mci_exynos_parse_dt,
218 .setup_bus = dw_mci_exynos_setup_bus,
221 static const struct of_device_id dw_mci_exynos_match[] = {
222 { .compatible = "samsung,exynos5250-dw-mshc",
223 .data = (void *)&exynos5250_drv_data, },
226 MODULE_DEVICE_TABLE(of, dw_mci_pltfm_match);
228 int dw_mci_exynos_probe(struct platform_device *pdev)
230 struct dw_mci_drv_data *drv_data;
231 const struct of_device_id *match;
233 match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node);
234 drv_data = match->data;
235 return dw_mci_pltfm_register(pdev, drv_data);
238 static struct platform_driver dw_mci_exynos_pltfm_driver = {
239 .probe = dw_mci_exynos_probe,
240 .remove = __exit_p(dw_mci_pltfm_remove),
242 .name = "dwmmc_exynos",
243 .of_match_table = of_match_ptr(dw_mci_exynos_match),
244 .pm = &dw_mci_pltfm_pmops,
248 module_platform_driver(dw_mci_exynos_pltfm_driver);
250 MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension");
251 MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com");
252 MODULE_LICENSE("GPL v2");
253 MODULE_ALIAS("platform:dwmmc-exynos");