drivers/mmc/host/sdhci-pci-o2micro.c

   1 /*
   2  * Copyright (C) 2013 BayHub Technology Ltd.
   3  *
   4  * Authors: Peter Guo <peter.guo@bayhubtech.com>
   5  *          Adam Lee <adam.lee@canonical.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/pci.h>
  19
  20 #include "sdhci.h"
  21 #include "sdhci-pci.h"
  22 #include "sdhci-pci-o2micro.h"
  23
  24 static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
  25 {
  26         u32 scratch_32;
  27         pci_read_config_dword(chip->pdev,
  28                               O2_SD_PLL_SETTING, &scratch_32);
  29
  30         scratch_32 &= 0x0000FFFF;
  31         scratch_32 |= value;
  32
  33         pci_write_config_dword(chip->pdev,
  34                                O2_SD_PLL_SETTING, scratch_32);
  35 }
  36
  37 static void o2_pci_led_enable(struct sdhci_pci_chip *chip)
  38 {
  39         int ret;
  40         u32 scratch_32;
  41
  42         /* Set led of SD host function enable */
  43         ret = pci_read_config_dword(chip->pdev,
  44                                     O2_SD_FUNC_REG0, &scratch_32);
  45         if (ret)
  46                 return;
  47
  48         scratch_32 &= ~O2_SD_FREG0_LEDOFF;
  49         pci_write_config_dword(chip->pdev,
  50                                O2_SD_FUNC_REG0, scratch_32);
  51
  52         ret = pci_read_config_dword(chip->pdev,
  53                                     O2_SD_TEST_REG, &scratch_32);
  54         if (ret)
  55                 return;
  56
  57         scratch_32 |= O2_SD_LED_ENABLE;
  58         pci_write_config_dword(chip->pdev,
  59                                O2_SD_TEST_REG, scratch_32);
  60
  61 }
  62
  63 void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
  64 {
  65         u32 scratch_32;
  66         int ret;
  67         /* Improve write performance for SD3.0 */
  68         ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
  69         if (ret)
  70                 return;
  71         scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
  72         pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
  73
  74         /* Enable Link abnormal reset generating Reset */
  75         ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
  76         if (ret)
  77                 return;
  78         scratch_32 &= ~((1 << 19) | (1 << 11));
  79         scratch_32 |= (1 << 10);
  80         pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
  81
  82         /* set card power over current protection */
  83         ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
  84         if (ret)
  85                 return;
  86         scratch_32 |= (1 << 4);
  87         pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
  88
  89         /* adjust the output delay for SD mode */
  90         pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);
  91
  92         /* Set the output voltage setting of Aux 1.2v LDO */
  93         ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
  94         if (ret)
  95                 return;
  96         scratch_32 &= ~(3 << 12);
  97         pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
  98
  99         /* Set Max power supply capability of SD host */
 100         ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
 101         if (ret)
 102                 return;
 103         scratch_32 &= ~(0x01FE);
 104         scratch_32 |= 0x00CC;
 105         pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
 106         /* Set DLL Tuning Window */
 107         ret = pci_read_config_dword(chip->pdev,
 108                                     O2_SD_TUNING_CTRL, &scratch_32);
 109         if (ret)
 110                 return;
 111         scratch_32 &= ~(0x000000FF);
 112         scratch_32 |= 0x00000066;
 113         pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
 114
 115         /* Set UHS2 T_EIDLE */
 116         ret = pci_read_config_dword(chip->pdev,
 117                                     O2_SD_UHS2_L1_CTRL, &scratch_32);
 118         if (ret)
 119                 return;
 120         scratch_32 &= ~(0x000000FC);
 121         scratch_32 |= 0x00000084;
 122         pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
 123
 124         /* Set UHS2 Termination */
 125         ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
 126         if (ret)
 127                 return;
 128         scratch_32 &= ~((1 << 21) | (1 << 30));
 129
 130         /* Set RTD3 function disabled */
 131         scratch_32 |= ((1 << 29) | (1 << 28));
 132         pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
 133
 134         /* Set L1 Entrance Timer */
 135         ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
 136         if (ret)
 137                 return;
 138         scratch_32 &= ~(0xf0000000);
 139         scratch_32 |= 0x30000000;
 140         pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
 141
 142         ret = pci_read_config_dword(chip->pdev,
 143                                     O2_SD_MISC_CTRL4, &scratch_32);
 144         if (ret)
 145                 return;
 146         scratch_32 &= ~(0x000f0000);
 147         scratch_32 |= 0x00080000;
 148         pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
 149 }
 150 EXPORT_SYMBOL_GPL(sdhci_pci_o2_fujin2_pci_init);
 151
 152 int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
 153 {
 154         struct sdhci_pci_chip *chip;
 155         struct sdhci_host *host;
 156         u32 reg;
 157
 158         chip = slot->chip;
 159         host = slot->host;
 160         switch (chip->pdev->device) {
 161         case PCI_DEVICE_ID_O2_SDS0:
 162         case PCI_DEVICE_ID_O2_SEABIRD0:
 163         case PCI_DEVICE_ID_O2_SEABIRD1:
 164         case PCI_DEVICE_ID_O2_SDS1:
 165         case PCI_DEVICE_ID_O2_FUJIN2:
 166                 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
 167                 if (reg & 0x1)
 168                         host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
 169
 170                 if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
 171                         break;
 172                 /* set dll watch dog timer */
 173                 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
 174                 reg |= (1 << 12);
 175                 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);
 176
 177                 break;
 178         default:
 179                 break;
 180         }
 181
 182         return 0;
 183 }
 184 EXPORT_SYMBOL_GPL(sdhci_pci_o2_probe_slot);
 185
 186 int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
 187 {
 188         int ret;
 189         u8 scratch;
 190         u32 scratch_32;
 191
 192         switch (chip->pdev->device) {
 193         case PCI_DEVICE_ID_O2_8220:
 194         case PCI_DEVICE_ID_O2_8221:
 195         case PCI_DEVICE_ID_O2_8320:
 196         case PCI_DEVICE_ID_O2_8321:
 197                 /* This extra setup is required due to broken ADMA. */
 198                 ret = pci_read_config_byte(chip->pdev,
 199                                 O2_SD_LOCK_WP, &scratch);
 200                 if (ret)
 201                         return ret;
 202                 scratch &= 0x7f;
 203                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 204
 205                 /* Set Multi 3 to VCC3V# */
 206                 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
 207
 208                 /* Disable CLK_REQ# support after media DET */
 209                 ret = pci_read_config_byte(chip->pdev,
 210                                 O2_SD_CLKREQ, &scratch);
 211                 if (ret)
 212                         return ret;
 213                 scratch |= 0x20;
 214                 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
 215
 216                 /* Choose capabilities, enable SDMA.  We have to write 0x01
 217                  * to the capabilities register first to unlock it.
 218                  */
 219                 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
 220                 if (ret)
 221                         return ret;
 222                 scratch |= 0x01;
 223                 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
 224                 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
 225
 226                 /* Disable ADMA1/2 */
 227                 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
 228                 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
 229
 230                 /* Disable the infinite transfer mode */
 231                 ret = pci_read_config_byte(chip->pdev,
 232                                 O2_SD_INF_MOD, &scratch);
 233                 if (ret)
 234                         return ret;
 235                 scratch |= 0x08;
 236                 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
 237
 238                 /* Lock WP */
 239                 ret = pci_read_config_byte(chip->pdev,
 240                                 O2_SD_LOCK_WP, &scratch);
 241                 if (ret)
 242                         return ret;
 243                 scratch |= 0x80;
 244                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 245                 break;
 246         case PCI_DEVICE_ID_O2_SDS0:
 247         case PCI_DEVICE_ID_O2_SDS1:
 248         case PCI_DEVICE_ID_O2_FUJIN2:
 249                 /* UnLock WP */
 250                 ret = pci_read_config_byte(chip->pdev,
 251                                 O2_SD_LOCK_WP, &scratch);
 252                 if (ret)
 253                         return ret;
 254
 255                 scratch &= 0x7f;
 256                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 257
 258                 /* DevId=8520 subId= 0x11 or 0x12  Type Chip support */
 259                 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) {
 260                         ret = pci_read_config_dword(chip->pdev,
 261                                                     O2_SD_FUNC_REG0,
 262                                                     &scratch_32);
 263                         scratch_32 = ((scratch_32 & 0xFF000000) >> 24);
 264
 265                         /* Check Whether subId is 0x11 or 0x12 */
 266                         if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {
 267                                 scratch_32 = 0x2c280000;
 268
 269                                 /* Set Base Clock to 208MZ */
 270                                 o2_pci_set_baseclk(chip, scratch_32);
 271                                 ret = pci_read_config_dword(chip->pdev,
 272                                                             O2_SD_FUNC_REG4,
 273                                                             &scratch_32);
 274
 275                                 /* Enable Base Clk setting change */
 276                                 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
 277                                 pci_write_config_dword(chip->pdev,
 278                                                        O2_SD_FUNC_REG4,
 279                                                        scratch_32);
 280
 281                                 /* Set Tuning Window to 4 */
 282                                 pci_write_config_byte(chip->pdev,
 283                                                       O2_SD_TUNING_CTRL, 0x44);
 284
 285                                 break;
 286                         }
 287                 }
 288
 289                 /* Enable 8520 led function */
 290                 o2_pci_led_enable(chip);
 291
 292                 /* Set timeout CLK */
 293                 ret = pci_read_config_dword(chip->pdev,
 294                                             O2_SD_CLK_SETTING, &scratch_32);
 295                 if (ret)
 296                         return ret;
 297
 298                 scratch_32 &= ~(0xFF00);
 299                 scratch_32 |= 0x07E0C800;
 300                 pci_write_config_dword(chip->pdev,
 301                                        O2_SD_CLK_SETTING, scratch_32);
 302
 303                 ret = pci_read_config_dword(chip->pdev,
 304                                             O2_SD_CLKREQ, &scratch_32);
 305                 if (ret)
 306                         return ret;
 307                 scratch_32 |= 0x3;
 308                 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
 309
 310                 ret = pci_read_config_dword(chip->pdev,
 311                                             O2_SD_PLL_SETTING, &scratch_32);
 312                 if (ret)
 313                         return ret;
 314
 315                 scratch_32 &= ~(0x1F3F070E);
 316                 scratch_32 |= 0x18270106;
 317                 pci_write_config_dword(chip->pdev,
 318                                        O2_SD_PLL_SETTING, scratch_32);
 319
 320                 /* Disable UHS1 funciton */
 321                 ret = pci_read_config_dword(chip->pdev,
 322                                             O2_SD_CAP_REG2, &scratch_32);
 323                 if (ret)
 324                         return ret;
 325                 scratch_32 &= ~(0xE0);
 326                 pci_write_config_dword(chip->pdev,
 327                                        O2_SD_CAP_REG2, scratch_32);
 328
 329                 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
 330                         sdhci_pci_o2_fujin2_pci_init(chip);
 331
 332                 /* Lock WP */
 333                 ret = pci_read_config_byte(chip->pdev,
 334                                            O2_SD_LOCK_WP, &scratch);
 335                 if (ret)
 336                         return ret;
 337                 scratch |= 0x80;
 338                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 339                 break;
 340         case PCI_DEVICE_ID_O2_SEABIRD0:
 341         case PCI_DEVICE_ID_O2_SEABIRD1:
 342                 /* UnLock WP */
 343                 ret = pci_read_config_byte(chip->pdev,
 344                                 O2_SD_LOCK_WP, &scratch);
 345                 if (ret)
 346                         return ret;
 347
 348                 scratch &= 0x7f;
 349                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 350
 351                 ret = pci_read_config_dword(chip->pdev,
 352                                             O2_SD_PLL_SETTING, &scratch_32);
 353
 354                 if ((scratch_32 & 0xff000000) == 0x01000000) {
 355                         scratch_32 &= 0x0000FFFF;
 356                         scratch_32 |= 0x1F340000;
 357
 358                         pci_write_config_dword(chip->pdev,
 359                                                O2_SD_PLL_SETTING, scratch_32);
 360                 } else {
 361                         scratch_32 &= 0x0000FFFF;
 362                         scratch_32 |= 0x2c280000;
 363
 364                         pci_write_config_dword(chip->pdev,
 365                                                O2_SD_PLL_SETTING, scratch_32);
 366
 367                         ret = pci_read_config_dword(chip->pdev,
 368                                                     O2_SD_FUNC_REG4,
 369                                                     &scratch_32);
 370                         scratch_32 |= (1 << 22);
 371                         pci_write_config_dword(chip->pdev,
 372                                                O2_SD_FUNC_REG4, scratch_32);
 373                 }
 374
 375                 /* Set Tuning Windows to 5 */
 376                 pci_write_config_byte(chip->pdev,
 377                                 O2_SD_TUNING_CTRL, 0x55);
 378                 /* Lock WP */
 379                 ret = pci_read_config_byte(chip->pdev,
 380                                            O2_SD_LOCK_WP, &scratch);
 381                 if (ret)
 382                         return ret;
 383                 scratch |= 0x80;
 384                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 385                 break;
 386         }
 387
 388         return 0;
 389 }
 390 EXPORT_SYMBOL_GPL(sdhci_pci_o2_probe);
 391
 392 int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
 393 {
 394         sdhci_pci_o2_probe(chip);
 395         return 0;
 396 }
 397 EXPORT_SYMBOL_GPL(sdhci_pci_o2_resume);