drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/slab.h>
  22 #include <linux/scatterlist.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/pm_runtime.h>
  25
  26 #include <linux/leds.h>
  27
  28 #include <linux/mmc/mmc.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/card.h>
  31 #include <linux/mmc/sdio.h>
  32 #include <linux/mmc/slot-gpio.h>
  33
  34 #include "sdhci.h"
  35
  36 #define DRIVER_NAME "sdhci"
  37
  38 #define DBG(f, x...) \
  39         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  40
  41 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  42         defined(CONFIG_MMC_SDHCI_MODULE))
  43 #define SDHCI_USE_LEDS_CLASS
  44 #endif
  45
  46 #define MAX_TUNING_LOOP 40
  47
  48 static unsigned int debug_quirks = 0;
  49 static unsigned int debug_quirks2;
  50
  51 static void sdhci_finish_data(struct sdhci_host *);
  52
  53 static void sdhci_finish_command(struct sdhci_host *);
  54 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
  55 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
  56 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
  57                                         struct mmc_data *data);
  58 static int sdhci_do_get_cd(struct sdhci_host *host);
  59
  60 #ifdef CONFIG_PM
  61 static int sdhci_runtime_pm_get(struct sdhci_host *host);
  62 static int sdhci_runtime_pm_put(struct sdhci_host *host);
  63 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
  64 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
  65 #else
  66 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
  67 {
  68         return 0;
  69 }
  70 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
  71 {
  72         return 0;
  73 }
  74 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
  75 {
  76 }
  77 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
  78 {
  79 }
  80 #endif
  81
  82 static void sdhci_dumpregs(struct sdhci_host *host)
  83 {
  84         pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
  85                 mmc_hostname(host->mmc));
  86
  87         pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  88                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  89                 sdhci_readw(host, SDHCI_HOST_VERSION));
  90         pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  91                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  92                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  93         pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  94                 sdhci_readl(host, SDHCI_ARGUMENT),
  95                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
  96         pr_debug(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  97                 sdhci_readl(host, SDHCI_PRESENT_STATE),
  98                 sdhci_readb(host, SDHCI_HOST_CONTROL));
  99         pr_debug(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
 100                 sdhci_readb(host, SDHCI_POWER_CONTROL),
 101                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
 102         pr_debug(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
 103                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
 104                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
 105         pr_debug(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
 106                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
 107                 sdhci_readl(host, SDHCI_INT_STATUS));
 108         pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
 109                 sdhci_readl(host, SDHCI_INT_ENABLE),
 110                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
 111         pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
 112                 sdhci_readw(host, SDHCI_ACMD12_ERR),
 113                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
 114         pr_debug(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
 115                 sdhci_readl(host, SDHCI_CAPABILITIES),
 116                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
 117         pr_debug(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
 118                 sdhci_readw(host, SDHCI_COMMAND),
 119                 sdhci_readl(host, SDHCI_MAX_CURRENT));
 120         pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
 121                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
 122
 123         if (host->flags & SDHCI_USE_ADMA) {
 124                 if (host->flags & SDHCI_USE_64_BIT_DMA)
 125                         pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
 126                                  readl(host->ioaddr + SDHCI_ADMA_ERROR),
 127                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
 128                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 129                 else
 130                         pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
 131                                  readl(host->ioaddr + SDHCI_ADMA_ERROR),
 132                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 133         }
 134
 135         pr_debug(DRIVER_NAME ": ===========================================\n");
 136 }
 137
 138 /*****************************************************************************\
 139  *                                                                           *
 140  * Low level functions                                                       *
 141  *                                                                           *
 142 \*****************************************************************************/
 143
 144 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 145 {
 146         u32 present;
 147
 148         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
 149             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
 150                 return;
 151
 152         if (enable) {
 153                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 154                                       SDHCI_CARD_PRESENT;
 155
 156                 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
 157                                        SDHCI_INT_CARD_INSERT;
 158         } else {
 159                 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
 160         }
 161
 162         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 163         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 164 }
 165
 166 static void sdhci_enable_card_detection(struct sdhci_host *host)
 167 {
 168         sdhci_set_card_detection(host, true);
 169 }
 170
 171 static void sdhci_disable_card_detection(struct sdhci_host *host)
 172 {
 173         sdhci_set_card_detection(host, false);
 174 }
 175
 176 void sdhci_reset(struct sdhci_host *host, u8 mask)
 177 {
 178         unsigned long timeout;
 179
 180         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 181
 182         if (mask & SDHCI_RESET_ALL) {
 183                 host->clock = 0;
 184                 /* Reset-all turns off SD Bus Power */
 185                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
 186                         sdhci_runtime_pm_bus_off(host);
 187         }
 188
 189         /* Wait max 100 ms */
 190         timeout = 100;
 191
 192         /* hw clears the bit when it's done */
 193         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 194                 if (timeout == 0) {
 195                         pr_err("%s: Reset 0x%x never completed.\n",
 196                                 mmc_hostname(host->mmc), (int)mask);
 197                         sdhci_dumpregs(host);
 198                         return;
 199                 }
 200                 timeout--;
 201                 mdelay(1);
 202         }
 203 }
 204 EXPORT_SYMBOL_GPL(sdhci_reset);
 205
 206 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
 207 {
 208         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 209                 if (!sdhci_do_get_cd(host))
 210                         return;
 211         }
 212
 213         host->ops->reset(host, mask);
 214
 215         if (mask & SDHCI_RESET_ALL) {
 216                 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
 217                         if (host->ops->enable_dma)
 218                                 host->ops->enable_dma(host);
 219                 }
 220
 221                 /* Resetting the controller clears many */
 222                 host->preset_enabled = false;
 223         }
 224 }
 225
 226 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 227
 228 static void sdhci_init(struct sdhci_host *host, int soft)
 229 {
 230         if (soft)
 231                 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 232         else
 233                 sdhci_do_reset(host, SDHCI_RESET_ALL);
 234
 235         host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 236                     SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
 237                     SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
 238                     SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
 239                     SDHCI_INT_RESPONSE;
 240
 241         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 242         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 243
 244         if (soft) {
 245                 /* force clock reconfiguration */
 246                 host->clock = 0;
 247                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 248         }
 249 }
 250
 251 static void sdhci_reinit(struct sdhci_host *host)
 252 {
 253         sdhci_init(host, 0);
 254         sdhci_enable_card_detection(host);
 255 }
 256
 257 static void sdhci_activate_led(struct sdhci_host *host)
 258 {
 259         u8 ctrl;
 260
 261         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 262         ctrl |= SDHCI_CTRL_LED;
 263         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 264 }
 265
 266 static void sdhci_deactivate_led(struct sdhci_host *host)
 267 {
 268         u8 ctrl;
 269
 270         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 271         ctrl &= ~SDHCI_CTRL_LED;
 272         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 273 }
 274
 275 #ifdef SDHCI_USE_LEDS_CLASS
 276 static void sdhci_led_control(struct led_classdev *led,
 277         enum led_brightness brightness)
 278 {
 279         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 280         unsigned long flags;
 281
 282         spin_lock_irqsave(&host->lock, flags);
 283
 284         if (host->runtime_suspended)
 285                 goto out;
 286
 287         if (brightness == LED_OFF)
 288                 sdhci_deactivate_led(host);
 289         else
 290                 sdhci_activate_led(host);
 291 out:
 292         spin_unlock_irqrestore(&host->lock, flags);
 293 }
 294 #endif
 295
 296 /*****************************************************************************\
 297  *                                                                           *
 298  * Core functions                                                            *
 299  *                                                                           *
 300 \*****************************************************************************/
 301
 302 static void sdhci_read_block_pio(struct sdhci_host *host)
 303 {
 304         unsigned long flags;
 305         size_t blksize, len, chunk;
 306         u32 uninitialized_var(scratch);
 307         u8 *buf;
 308
 309         DBG("PIO reading\n");
 310
 311         blksize = host->data->blksz;
 312         chunk = 0;
 313
 314         local_irq_save(flags);
 315
 316         while (blksize) {
 317                 BUG_ON(!sg_miter_next(&host->sg_miter));
 318
 319                 len = min(host->sg_miter.length, blksize);
 320
 321                 blksize -= len;
 322                 host->sg_miter.consumed = len;
 323
 324                 buf = host->sg_miter.addr;
 325
 326                 while (len) {
 327                         if (chunk == 0) {
 328                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 329                                 chunk = 4;
 330                         }
 331
 332                         *buf = scratch & 0xFF;
 333
 334                         buf++;
 335                         scratch >>= 8;
 336                         chunk--;
 337                         len--;
 338                 }
 339         }
 340
 341         sg_miter_stop(&host->sg_miter);
 342
 343         local_irq_restore(flags);
 344 }
 345
 346 static void sdhci_write_block_pio(struct sdhci_host *host)
 347 {
 348         unsigned long flags;
 349         size_t blksize, len, chunk;
 350         u32 scratch;
 351         u8 *buf;
 352
 353         DBG("PIO writing\n");
 354
 355         blksize = host->data->blksz;
 356         chunk = 0;
 357         scratch = 0;
 358
 359         local_irq_save(flags);
 360
 361         while (blksize) {
 362                 BUG_ON(!sg_miter_next(&host->sg_miter));
 363
 364                 len = min(host->sg_miter.length, blksize);
 365
 366                 blksize -= len;
 367                 host->sg_miter.consumed = len;
 368
 369                 buf = host->sg_miter.addr;
 370
 371                 while (len) {
 372                         scratch |= (u32)*buf << (chunk * 8);
 373
 374                         buf++;
 375                         chunk++;
 376                         len--;
 377
 378                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 379                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 380                                 chunk = 0;
 381                                 scratch = 0;
 382                         }
 383                 }
 384         }
 385
 386         sg_miter_stop(&host->sg_miter);
 387
 388         local_irq_restore(flags);
 389 }
 390
 391 static void sdhci_transfer_pio(struct sdhci_host *host)
 392 {
 393         u32 mask;
 394
 395         BUG_ON(!host->data);
 396
 397         if (host->blocks == 0)
 398                 return;
 399
 400         if (host->data->flags & MMC_DATA_READ)
 401                 mask = SDHCI_DATA_AVAILABLE;
 402         else
 403                 mask = SDHCI_SPACE_AVAILABLE;
 404
 405         /*
 406          * Some controllers (JMicron JMB38x) mess up the buffer bits
 407          * for transfers < 4 bytes. As long as it is just one block,
 408          * we can ignore the bits.
 409          */
 410         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 411                 (host->data->blocks == 1))
 412                 mask = ~0;
 413
 414         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 415                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 416                         udelay(100);
 417
 418                 if (host->data->flags & MMC_DATA_READ)
 419                         sdhci_read_block_pio(host);
 420                 else
 421                         sdhci_write_block_pio(host);
 422
 423                 host->blocks--;
 424                 if (host->blocks == 0)
 425                         break;
 426         }
 427
 428         DBG("PIO transfer complete.\n");
 429 }
 430
 431 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 432 {
 433         local_irq_save(*flags);
 434         return kmap_atomic(sg_page(sg)) + sg->offset;
 435 }
 436
 437 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 438 {
 439         kunmap_atomic(buffer);
 440         local_irq_restore(*flags);
 441 }
 442
 443 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
 444                                   dma_addr_t addr, int len, unsigned cmd)
 445 {
 446         struct sdhci_adma2_64_desc *dma_desc = desc;
 447
 448         /* 32-bit and 64-bit descriptors have these members in same position */
 449         dma_desc->cmd = cpu_to_le16(cmd);
 450         dma_desc->len = cpu_to_le16(len);
 451         dma_desc->addr_lo = cpu_to_le32((u32)addr);
 452
 453         if (host->flags & SDHCI_USE_64_BIT_DMA)
 454                 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
 455 }
 456
 457 static void sdhci_adma_mark_end(void *desc)
 458 {
 459         struct sdhci_adma2_64_desc *dma_desc = desc;
 460
 461         /* 32-bit and 64-bit descriptors have 'cmd' in same position */
 462         dma_desc->cmd |= cpu_to_le16(ADMA2_END);
 463 }
 464
 465 static int sdhci_adma_table_pre(struct sdhci_host *host,
 466         struct mmc_data *data)
 467 {
 468         int direction;
 469
 470         void *desc;
 471         void *align;
 472         dma_addr_t addr;
 473         dma_addr_t align_addr;
 474         int len, offset;
 475
 476         struct scatterlist *sg;
 477         int i;
 478         char *buffer;
 479         unsigned long flags;
 480
 481         /*
 482          * The spec does not specify endianness of descriptor table.
 483          * We currently guess that it is LE.
 484          */
 485
 486         if (data->flags & MMC_DATA_READ)
 487                 direction = DMA_FROM_DEVICE;
 488         else
 489                 direction = DMA_TO_DEVICE;
 490
 491         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 492                 host->align_buffer, host->align_buffer_sz, direction);
 493         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 494                 goto fail;
 495         BUG_ON(host->align_addr & host->align_mask);
 496
 497         host->sg_count = sdhci_pre_dma_transfer(host, data);
 498         if (host->sg_count < 0)
 499                 goto unmap_align;
 500
 501         desc = host->adma_table;
 502         align = host->align_buffer;
 503
 504         align_addr = host->align_addr;
 505
 506         for_each_sg(data->sg, sg, host->sg_count, i) {
 507                 addr = sg_dma_address(sg);
 508                 len = sg_dma_len(sg);
 509
 510                 /*
 511                  * The SDHCI specification states that ADMA
 512                  * addresses must be 32-bit aligned. If they
 513                  * aren't, then we use a bounce buffer for
 514                  * the (up to three) bytes that screw up the
 515                  * alignment.
 516                  */
 517                 offset = (host->align_sz - (addr & host->align_mask)) &
 518                          host->align_mask;
 519                 if (offset) {
 520                         if (data->flags & MMC_DATA_WRITE) {
 521                                 buffer = sdhci_kmap_atomic(sg, &flags);
 522                                 memcpy(align, buffer, offset);
 523                                 sdhci_kunmap_atomic(buffer, &flags);
 524                         }
 525
 526                         /* tran, valid */
 527                         sdhci_adma_write_desc(host, desc, align_addr, offset,
 528                                               ADMA2_TRAN_VALID);
 529
 530                         BUG_ON(offset > 65536);
 531
 532                         align += host->align_sz;
 533                         align_addr += host->align_sz;
 534
 535                         desc += host->desc_sz;
 536
 537                         addr += offset;
 538                         len -= offset;
 539                 }
 540
 541                 BUG_ON(len > 65536);
 542
 543                 /* tran, valid */
 544                 sdhci_adma_write_desc(host, desc, addr, len, ADMA2_TRAN_VALID);
 545                 desc += host->desc_sz;
 546
 547                 /*
 548                  * If this triggers then we have a calculation bug
 549                  * somewhere. :/
 550                  */
 551                 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
 552         }
 553
 554         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 555                 /*
 556                 * Mark the last descriptor as the terminating descriptor
 557                 */
 558                 if (desc != host->adma_table) {
 559                         desc -= host->desc_sz;
 560                         sdhci_adma_mark_end(desc);
 561                 }
 562         } else {
 563                 /*
 564                 * Add a terminating entry.
 565                 */
 566
 567                 /* nop, end, valid */
 568                 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
 569         }
 570
 571         /*
 572          * Resync align buffer as we might have changed it.
 573          */
 574         if (data->flags & MMC_DATA_WRITE) {
 575                 dma_sync_single_for_device(mmc_dev(host->mmc),
 576                         host->align_addr, host->align_buffer_sz, direction);
 577         }
 578
 579         return 0;
 580
 581 unmap_align:
 582         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 583                 host->align_buffer_sz, direction);
 584 fail:
 585         return -EINVAL;
 586 }
 587
 588 static void sdhci_adma_table_post(struct sdhci_host *host,
 589         struct mmc_data *data)
 590 {
 591         int direction;
 592
 593         struct scatterlist *sg;
 594         int i, size;
 595         void *align;
 596         char *buffer;
 597         unsigned long flags;
 598         bool has_unaligned;
 599
 600         if (data->flags & MMC_DATA_READ)
 601                 direction = DMA_FROM_DEVICE;
 602         else
 603                 direction = DMA_TO_DEVICE;
 604
 605         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 606                 host->align_buffer_sz, direction);
 607
 608         /* Do a quick scan of the SG list for any unaligned mappings */
 609         has_unaligned = false;
 610         for_each_sg(data->sg, sg, host->sg_count, i)
 611                 if (sg_dma_address(sg) & host->align_mask) {
 612                         has_unaligned = true;
 613                         break;
 614                 }
 615
 616         if (has_unaligned && data->flags & MMC_DATA_READ) {
 617                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 618                         data->sg_len, direction);
 619
 620                 align = host->align_buffer;
 621
 622                 for_each_sg(data->sg, sg, host->sg_count, i) {
 623                         if (sg_dma_address(sg) & host->align_mask) {
 624                                 size = host->align_sz -
 625                                        (sg_dma_address(sg) & host->align_mask);
 626
 627                                 buffer = sdhci_kmap_atomic(sg, &flags);
 628                                 memcpy(buffer, align, size);
 629                                 sdhci_kunmap_atomic(buffer, &flags);
 630
 631                                 align += host->align_sz;
 632                         }
 633                 }
 634         }
 635
 636         if (data->host_cookie == COOKIE_MAPPED) {
 637                 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 638                         data->sg_len, direction);
 639                 data->host_cookie = COOKIE_UNMAPPED;
 640         }
 641 }
 642
 643 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 644 {
 645         u8 count;
 646         struct mmc_data *data = cmd->data;
 647         unsigned target_timeout, current_timeout;
 648
 649         /*
 650          * If the host controller provides us with an incorrect timeout
 651          * value, just skip the check and use 0xE.  The hardware may take
 652          * longer to time out, but that's much better than having a too-short
 653          * timeout value.
 654          */
 655         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 656                 return 0xE;
 657
 658         /* Unspecified timeout, assume max */
 659         if (!data && !cmd->busy_timeout)
 660                 return 0xE;
 661
 662         /* timeout in us */
 663         if (!data)
 664                 target_timeout = cmd->busy_timeout * 1000;
 665         else {
 666                 target_timeout = data->timeout_ns / 1000;
 667                 if (host->clock)
 668                         target_timeout += data->timeout_clks / host->clock;
 669         }
 670
 671         /*
 672          * Figure out needed cycles.
 673          * We do this in steps in order to fit inside a 32 bit int.
 674          * The first step is the minimum timeout, which will have a
 675          * minimum resolution of 6 bits:
 676          * (1) 2^13*1000 > 2^22,
 677          * (2) host->timeout_clk < 2^16
 678          *     =>
 679          *     (1) / (2) > 2^6
 680          */
 681         count = 0;
 682         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 683         while (current_timeout < target_timeout) {
 684                 count++;
 685                 current_timeout <<= 1;
 686                 if (count >= 0xF)
 687                         break;
 688         }
 689
 690         if (count >= 0xF) {
 691                 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
 692                     mmc_hostname(host->mmc), count, cmd->opcode);
 693                 count = 0xE;
 694         }
 695
 696         return count;
 697 }
 698
 699 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 700 {
 701         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 702         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 703
 704         if (host->flags & SDHCI_REQ_USE_DMA)
 705                 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
 706         else
 707                 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
 708
 709         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 710         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 711 }
 712
 713 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 714 {
 715         u8 count;
 716
 717         if (host->ops->set_timeout) {
 718                 host->ops->set_timeout(host, cmd);
 719         } else {
 720                 count = sdhci_calc_timeout(host, cmd);
 721                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 722         }
 723 }
 724
 725 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 726 {
 727         u8 ctrl;
 728         struct mmc_data *data = cmd->data;
 729         int ret;
 730
 731         WARN_ON(host->data);
 732
 733         if (data || (cmd->flags & MMC_RSP_BUSY))
 734                 sdhci_set_timeout(host, cmd);
 735
 736         if (!data)
 737                 return;
 738
 739         /* Sanity checks */
 740         BUG_ON(data->blksz * data->blocks > 524288);
 741         BUG_ON(data->blksz > host->mmc->max_blk_size);
 742         BUG_ON(data->blocks > 65535);
 743
 744         host->data = data;
 745         host->data_early = 0;
 746         host->data->bytes_xfered = 0;
 747
 748         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 749                 host->flags |= SDHCI_REQ_USE_DMA;
 750
 751         /*
 752          * FIXME: This doesn't account for merging when mapping the
 753          * scatterlist.
 754          */
 755         if (host->flags & SDHCI_REQ_USE_DMA) {
 756                 int broken, i;
 757                 struct scatterlist *sg;
 758
 759                 broken = 0;
 760                 if (host->flags & SDHCI_USE_ADMA) {
 761                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 762                                 broken = 1;
 763                 } else {
 764                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 765                                 broken = 1;
 766                 }
 767
 768                 if (unlikely(broken)) {
 769                         for_each_sg(data->sg, sg, data->sg_len, i) {
 770                                 if (sg->length & 0x3) {
 771                                         DBG("Reverting to PIO because of transfer size (%d)\n",
 772                                                 sg->length);
 773                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 774                                         break;
 775                                 }
 776                         }
 777                 }
 778         }
 779
 780         /*
 781          * The assumption here being that alignment is the same after
 782          * translation to device address space.
 783          */
 784         if (host->flags & SDHCI_REQ_USE_DMA) {
 785                 int broken, i;
 786                 struct scatterlist *sg;
 787
 788                 broken = 0;
 789                 if (host->flags & SDHCI_USE_ADMA) {
 790                         /*
 791                          * As we use 3 byte chunks to work around
 792                          * alignment problems, we need to check this
 793                          * quirk.
 794                          */
 795                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 796                                 broken = 1;
 797                 } else {
 798                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 799                                 broken = 1;
 800                 }
 801
 802                 if (unlikely(broken)) {
 803                         for_each_sg(data->sg, sg, data->sg_len, i) {
 804                                 if (sg->offset & 0x3) {
 805                                         DBG("Reverting to PIO because of bad alignment\n");
 806                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 807                                         break;
 808                                 }
 809                         }
 810                 }
 811         }
 812
 813         if (host->flags & SDHCI_REQ_USE_DMA) {
 814                 if (host->flags & SDHCI_USE_ADMA) {
 815                         ret = sdhci_adma_table_pre(host, data);
 816                         if (ret) {
 817                                 /*
 818                                  * This only happens when someone fed
 819                                  * us an invalid request.
 820                                  */
 821                                 WARN_ON(1);
 822                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 823                         } else {
 824                                 sdhci_writel(host, host->adma_addr,
 825                                         SDHCI_ADMA_ADDRESS);
 826                                 if (host->flags & SDHCI_USE_64_BIT_DMA)
 827                                         sdhci_writel(host,
 828                                                      (u64)host->adma_addr >> 32,
 829                                                      SDHCI_ADMA_ADDRESS_HI);
 830                         }
 831                 } else {
 832                         int sg_cnt;
 833
 834                         sg_cnt = sdhci_pre_dma_transfer(host, data);
 835                         if (sg_cnt <= 0) {
 836                                 /*
 837                                  * This only happens when someone fed
 838                                  * us an invalid request.
 839                                  */
 840                                 WARN_ON(1);
 841                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 842                         } else {
 843                                 WARN_ON(sg_cnt != 1);
 844                                 sdhci_writel(host, sg_dma_address(data->sg),
 845                                         SDHCI_DMA_ADDRESS);
 846                         }
 847                 }
 848         }
 849
 850         /*
 851          * Always adjust the DMA selection as some controllers
 852          * (e.g. JMicron) can't do PIO properly when the selection
 853          * is ADMA.
 854          */
 855         if (host->version >= SDHCI_SPEC_200) {
 856                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 857                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 858                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 859                         (host->flags & SDHCI_USE_ADMA)) {
 860                         if (host->flags & SDHCI_USE_64_BIT_DMA)
 861                                 ctrl |= SDHCI_CTRL_ADMA64;
 862                         else
 863                                 ctrl |= SDHCI_CTRL_ADMA32;
 864                 } else {
 865                         ctrl |= SDHCI_CTRL_SDMA;
 866                 }
 867                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 868         }
 869
 870         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 871                 int flags;
 872
 873                 flags = SG_MITER_ATOMIC;
 874                 if (host->data->flags & MMC_DATA_READ)
 875                         flags |= SG_MITER_TO_SG;
 876                 else
 877                         flags |= SG_MITER_FROM_SG;
 878                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 879                 host->blocks = data->blocks;
 880         }
 881
 882         sdhci_set_transfer_irqs(host);
 883
 884         /* Set the DMA boundary value and block size */
 885         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 886                 data->blksz), SDHCI_BLOCK_SIZE);
 887         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 888 }
 889
 890 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 891         struct mmc_command *cmd)
 892 {
 893         u16 mode = 0;
 894         struct mmc_data *data = cmd->data;
 895
 896         if (data == NULL) {
 897                 if (host->quirks2 &
 898                         SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
 899                         sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
 900                 } else {
 901                 /* clear Auto CMD settings for no data CMDs */
 902                         mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
 903                         sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
 904                                 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
 905                 }
 906                 return;
 907         }
 908
 909         WARN_ON(!host->data);
 910
 911         if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
 912                 mode = SDHCI_TRNS_BLK_CNT_EN;
 913
 914         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 915                 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
 916                 /*
 917                  * If we are sending CMD23, CMD12 never gets sent
 918                  * on successful completion (so no Auto-CMD12).
 919                  */
 920                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
 921                     (cmd->opcode != SD_IO_RW_EXTENDED))
 922                         mode |= SDHCI_TRNS_AUTO_CMD12;
 923                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 924                         mode |= SDHCI_TRNS_AUTO_CMD23;
 925                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
 926                 }
 927         }
 928
 929         if (data->flags & MMC_DATA_READ)
 930                 mode |= SDHCI_TRNS_READ;
 931         if (host->flags & SDHCI_REQ_USE_DMA)
 932                 mode |= SDHCI_TRNS_DMA;
 933
 934         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 935 }
 936
 937 static void sdhci_finish_data(struct sdhci_host *host)
 938 {
 939         struct mmc_data *data;
 940
 941         BUG_ON(!host->data);
 942
 943         data = host->data;
 944         host->data = NULL;
 945
 946         if (host->flags & SDHCI_REQ_USE_DMA) {
 947                 if (host->flags & SDHCI_USE_ADMA)
 948                         sdhci_adma_table_post(host, data);
 949                 else {
 950                         if (data->host_cookie == COOKIE_MAPPED) {
 951                                 dma_unmap_sg(mmc_dev(host->mmc),
 952                                         data->sg, data->sg_len,
 953                                         (data->flags & MMC_DATA_READ) ?
 954                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 955                                 data->host_cookie = COOKIE_UNMAPPED;
 956                         }
 957                 }
 958         }
 959
 960         /*
 961          * The specification states that the block count register must
 962          * be updated, but it does not specify at what point in the
 963          * data flow. That makes the register entirely useless to read
 964          * back so we have to assume that nothing made it to the card
 965          * in the event of an error.
 966          */
 967         if (data->error)
 968                 data->bytes_xfered = 0;
 969         else
 970                 data->bytes_xfered = data->blksz * data->blocks;
 971
 972         /*
 973          * Need to send CMD12 if -
 974          * a) open-ended multiblock transfer (no CMD23)
 975          * b) error in multiblock transfer
 976          */
 977         if (data->stop &&
 978             (data->error ||
 979              !host->mrq->sbc)) {
 980
 981                 /*
 982                  * The controller needs a reset of internal state machines
 983                  * upon error conditions.
 984                  */
 985                 if (data->error) {
 986                         sdhci_do_reset(host, SDHCI_RESET_CMD);
 987                         sdhci_do_reset(host, SDHCI_RESET_DATA);
 988                 }
 989
 990                 sdhci_send_command(host, data->stop);
 991         } else
 992                 tasklet_schedule(&host->finish_tasklet);
 993 }
 994
 995 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 996 {
 997         int flags;
 998         u32 mask;
 999         unsigned long timeout;
1000
1001         WARN_ON(host->cmd);
1002
1003         /* Wait max 10 ms */
1004         timeout = 10;
1005
1006         mask = SDHCI_CMD_INHIBIT;
1007         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1008                 mask |= SDHCI_DATA_INHIBIT;
1009
1010         /* We shouldn't wait for data inihibit for stop commands, even
1011            though they might use busy signaling */
1012         if (host->mrq->data && (cmd == host->mrq->data->stop))
1013                 mask &= ~SDHCI_DATA_INHIBIT;
1014
1015         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1016                 if (timeout == 0) {
1017                         pr_err("%s: Controller never released inhibit bit(s).\n",
1018                                mmc_hostname(host->mmc));
1019                         sdhci_dumpregs(host);
1020                         cmd->error = -EIO;
1021                         tasklet_schedule(&host->finish_tasklet);
1022                         return;
1023                 }
1024                 timeout--;
1025                 mdelay(1);
1026         }
1027
1028         timeout = jiffies;
1029         if (!cmd->data && cmd->busy_timeout > 9000)
1030                 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1031         else
1032                 timeout += 10 * HZ;
1033         mod_timer(&host->timer, timeout);
1034
1035         host->cmd = cmd;
1036         host->busy_handle = 0;
1037
1038         sdhci_prepare_data(host, cmd);
1039
1040         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1041
1042         sdhci_set_transfer_mode(host, cmd);
1043
1044         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1045                 pr_err("%s: Unsupported response type!\n",
1046                         mmc_hostname(host->mmc));
1047                 cmd->error = -EINVAL;
1048                 tasklet_schedule(&host->finish_tasklet);
1049                 return;
1050         }
1051
1052         if (!(cmd->flags & MMC_RSP_PRESENT))
1053                 flags = SDHCI_CMD_RESP_NONE;
1054         else if (cmd->flags & MMC_RSP_136)
1055                 flags = SDHCI_CMD_RESP_LONG;
1056         else if (cmd->flags & MMC_RSP_BUSY)
1057                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1058         else
1059                 flags = SDHCI_CMD_RESP_SHORT;
1060
1061         if (cmd->flags & MMC_RSP_CRC)
1062                 flags |= SDHCI_CMD_CRC;
1063         if (cmd->flags & MMC_RSP_OPCODE)
1064                 flags |= SDHCI_CMD_INDEX;
1065
1066         /* CMD19 is special in that the Data Present Select should be set */
1067         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1068             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1069                 flags |= SDHCI_CMD_DATA;
1070
1071         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1072 }
1073 EXPORT_SYMBOL_GPL(sdhci_send_command);
1074
1075 static void sdhci_finish_command(struct sdhci_host *host)
1076 {
1077         int i;
1078
1079         BUG_ON(host->cmd == NULL);
1080
1081         if (host->cmd->flags & MMC_RSP_PRESENT) {
1082                 if (host->cmd->flags & MMC_RSP_136) {
1083                         /* CRC is stripped so we need to do some shifting. */
1084                         for (i = 0;i < 4;i++) {
1085                                 host->cmd->resp[i] = sdhci_readl(host,
1086                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1087                                 if (i != 3)
1088                                         host->cmd->resp[i] |=
1089                                                 sdhci_readb(host,
1090                                                 SDHCI_RESPONSE + (3-i)*4-1);
1091                         }
1092                 } else {
1093                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1094                 }
1095         }
1096
1097         host->cmd->error = 0;
1098
1099         /* Finished CMD23, now send actual command. */
1100         if (host->cmd == host->mrq->sbc) {
1101                 host->cmd = NULL;
1102                 sdhci_send_command(host, host->mrq->cmd);
1103         } else {
1104
1105                 /* Processed actual command. */
1106                 if (host->data && host->data_early)
1107                         sdhci_finish_data(host);
1108
1109                 if (!host->cmd->data)
1110                         tasklet_schedule(&host->finish_tasklet);
1111
1112                 host->cmd = NULL;
1113         }
1114 }
1115
1116 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1117 {
1118         u16 preset = 0;
1119
1120         switch (host->timing) {
1121         case MMC_TIMING_UHS_SDR12:
1122                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1123                 break;
1124         case MMC_TIMING_UHS_SDR25:
1125                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1126                 break;
1127         case MMC_TIMING_UHS_SDR50:
1128                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1129                 break;
1130         case MMC_TIMING_UHS_SDR104:
1131         case MMC_TIMING_MMC_HS200:
1132                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1133                 break;
1134         case MMC_TIMING_UHS_DDR50:
1135         case MMC_TIMING_MMC_DDR52:
1136                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1137                 break;
1138         case MMC_TIMING_MMC_HS400:
1139                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1140                 break;
1141         default:
1142                 pr_warn("%s: Invalid UHS-I mode selected\n",
1143                         mmc_hostname(host->mmc));
1144                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1145                 break;
1146         }
1147         return preset;
1148 }
1149
1150 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1151 {
1152         int div = 0; /* Initialized for compiler warning */
1153         int real_div = div, clk_mul = 1;
1154         u16 clk = 0;
1155         unsigned long timeout;
1156         bool switch_base_clk = false;
1157
1158         host->mmc->actual_clock = 0;
1159
1160         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1161         if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST)
1162                 mdelay(1);
1163
1164         if (clock == 0)
1165                 return;
1166
1167         if (host->version >= SDHCI_SPEC_300) {
1168                 if (host->preset_enabled) {
1169                         u16 pre_val;
1170
1171                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1172                         pre_val = sdhci_get_preset_value(host);
1173                         div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1174                                 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1175                         if (host->clk_mul &&
1176                                 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1177                                 clk = SDHCI_PROG_CLOCK_MODE;
1178                                 real_div = div + 1;
1179                                 clk_mul = host->clk_mul;
1180                         } else {
1181                                 real_div = max_t(int, 1, div << 1);
1182                         }
1183                         goto clock_set;
1184                 }
1185
1186                 /*
1187                  * Check if the Host Controller supports Programmable Clock
1188                  * Mode.
1189                  */
1190                 if (host->clk_mul) {
1191                         for (div = 1; div <= 1024; div++) {
1192                                 if ((host->max_clk * host->clk_mul / div)
1193                                         <= clock)
1194                                         break;
1195                         }
1196                         if ((host->max_clk * host->clk_mul / div) <= clock) {
1197                                 /*
1198                                  * Set Programmable Clock Mode in the Clock
1199                                  * Control register.
1200                                  */
1201                                 clk = SDHCI_PROG_CLOCK_MODE;
1202                                 real_div = div;
1203                                 clk_mul = host->clk_mul;
1204                                 div--;
1205                         } else {
1206                                 /*
1207                                  * Divisor can be too small to reach clock
1208                                  * speed requirement. Then use the base clock.
1209                                  */
1210                                 switch_base_clk = true;
1211                         }
1212                 }
1213
1214                 if (!host->clk_mul || switch_base_clk) {
1215                         /* Version 3.00 divisors must be a multiple of 2. */
1216                         if (host->max_clk <= clock)
1217                                 div = 1;
1218                         else {
1219                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1220                                      div += 2) {
1221                                         if ((host->max_clk / div) <= clock)
1222                                                 break;
1223                                 }
1224                         }
1225                         real_div = div;
1226                         div >>= 1;
1227                         if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1228                                 && !div && host->max_clk <= 25000000)
1229                                 div = 1;
1230                 }
1231         } else {
1232                 /* Version 2.00 divisors must be a power of 2. */
1233                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1234                         if ((host->max_clk / div) <= clock)
1235                                 break;
1236                 }
1237                 real_div = div;
1238                 div >>= 1;
1239         }
1240
1241 clock_set:
1242         if (real_div)
1243                 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1244         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1245         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1246                 << SDHCI_DIVIDER_HI_SHIFT;
1247         clk |= SDHCI_CLOCK_INT_EN;
1248         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1249
1250         /* Wait max 20 ms */
1251         timeout = 20;
1252         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1253                 & SDHCI_CLOCK_INT_STABLE)) {
1254                 if (timeout == 0) {
1255                         pr_err("%s: Internal clock never stabilised.\n",
1256                                mmc_hostname(host->mmc));
1257                         sdhci_dumpregs(host);
1258                         return;
1259                 }
1260                 timeout--;
1261                 mdelay(1);
1262         }
1263
1264         clk |= SDHCI_CLOCK_CARD_EN;
1265         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1266 }
1267 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1268
1269 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1270                             unsigned short vdd)
1271 {
1272         struct mmc_host *mmc = host->mmc;
1273         u8 pwr = 0;
1274
1275         if (!IS_ERR(mmc->supply.vmmc)) {
1276                 spin_unlock_irq(&host->lock);
1277                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1278                 spin_lock_irq(&host->lock);
1279
1280                 if (mode != MMC_POWER_OFF)
1281                         sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1282                 else
1283                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1284
1285                 return;
1286         }
1287
1288         if (mode != MMC_POWER_OFF) {
1289                 switch (1 << vdd) {
1290                 case MMC_VDD_165_195:
1291                         pwr = SDHCI_POWER_180;
1292                         break;
1293                 case MMC_VDD_29_30:
1294                 case MMC_VDD_30_31:
1295                         pwr = SDHCI_POWER_300;
1296                         break;
1297                 case MMC_VDD_32_33:
1298                 case MMC_VDD_33_34:
1299                         pwr = SDHCI_POWER_330;
1300                         break;
1301                 default:
1302                         BUG();
1303                 }
1304         }
1305
1306         if (host->pwr == pwr)
1307                 return;
1308
1309         host->pwr = pwr;
1310
1311         if (pwr == 0) {
1312                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1313                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1314                         sdhci_runtime_pm_bus_off(host);
1315                 vdd = 0;
1316         } else {
1317                 /*
1318                  * Spec says that we should clear the power reg before setting
1319                  * a new value. Some controllers don't seem to like this though.
1320                  */
1321                 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1322                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1323
1324                 /*
1325                  * At least the Marvell CaFe chip gets confused if we set the
1326                  * voltage and set turn on power at the same time, so set the
1327                  * voltage first.
1328                  */
1329                 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1330                         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1331
1332                 pwr |= SDHCI_POWER_ON;
1333
1334                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1335
1336                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1337                         sdhci_runtime_pm_bus_on(host);
1338
1339                 /*
1340                  * Some controllers need an extra 10ms delay of 10ms before
1341                  * they can apply clock after applying power
1342                  */
1343                 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1344                         mdelay(10);
1345         }
1346 }
1347
1348 /*****************************************************************************\
1349  *                                                                           *
1350  * MMC callbacks                                                             *
1351  *                                                                           *
1352 \*****************************************************************************/
1353
1354 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1355 {
1356         struct sdhci_host *host;
1357         int present;
1358         unsigned long flags;
1359
1360         host = mmc_priv(mmc);
1361
1362         sdhci_runtime_pm_get(host);
1363
1364         /* Firstly check card presence */
1365         present = sdhci_do_get_cd(host);
1366
1367         spin_lock_irqsave(&host->lock, flags);
1368
1369         WARN_ON(host->mrq != NULL);
1370
1371 #ifndef SDHCI_USE_LEDS_CLASS
1372         sdhci_activate_led(host);
1373 #endif
1374
1375         /*
1376          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1377          * requests if Auto-CMD12 is enabled.
1378          */
1379         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1380                 if (mrq->stop) {
1381                         mrq->data->stop = NULL;
1382                         mrq->stop = NULL;
1383                 }
1384         }
1385
1386         host->mrq = mrq;
1387
1388         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1389                 host->mrq->cmd->error = -ENOMEDIUM;
1390                 tasklet_schedule(&host->finish_tasklet);
1391         } else {
1392                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1393                         sdhci_send_command(host, mrq->sbc);
1394                 else
1395                         sdhci_send_command(host, mrq->cmd);
1396         }
1397
1398         mmiowb();
1399         spin_unlock_irqrestore(&host->lock, flags);
1400 }
1401
1402 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1403 {
1404         u8 ctrl;
1405
1406         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1407         if (width == MMC_BUS_WIDTH_8) {
1408                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1409                 if (host->version >= SDHCI_SPEC_300)
1410                         ctrl |= SDHCI_CTRL_8BITBUS;
1411         } else {
1412                 if (host->version >= SDHCI_SPEC_300)
1413                         ctrl &= ~SDHCI_CTRL_8BITBUS;
1414                 if (width == MMC_BUS_WIDTH_4)
1415                         ctrl |= SDHCI_CTRL_4BITBUS;
1416                 else
1417                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1418         }
1419         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1420 }
1421 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1422
1423 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1424 {
1425         u16 ctrl_2;
1426
1427         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1428         /* Select Bus Speed Mode for host */
1429         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1430         if ((timing == MMC_TIMING_MMC_HS200) ||
1431             (timing == MMC_TIMING_UHS_SDR104))
1432                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1433         else if (timing == MMC_TIMING_UHS_SDR12)
1434                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1435         else if (timing == MMC_TIMING_UHS_SDR25)
1436                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1437         else if (timing == MMC_TIMING_UHS_SDR50)
1438                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1439         else if ((timing == MMC_TIMING_UHS_DDR50) ||
1440                  (timing == MMC_TIMING_MMC_DDR52))
1441                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1442         else if (timing == MMC_TIMING_MMC_HS400)
1443                 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1444         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1445 }
1446 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1447
1448 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1449 {
1450         unsigned long flags;
1451         u8 ctrl;
1452         struct mmc_host *mmc = host->mmc;
1453
1454         spin_lock_irqsave(&host->lock, flags);
1455
1456         if (host->flags & SDHCI_DEVICE_DEAD) {
1457                 spin_unlock_irqrestore(&host->lock, flags);
1458                 if (!IS_ERR(mmc->supply.vmmc) &&
1459                     ios->power_mode == MMC_POWER_OFF)
1460                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1461                 return;
1462         }
1463
1464         /*
1465          * Reset the chip on each power off.
1466          * Should clear out any weird states.
1467          */
1468         if (ios->power_mode == MMC_POWER_OFF) {
1469                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1470                 sdhci_reinit(host);
1471         }
1472
1473         if (host->version >= SDHCI_SPEC_300 &&
1474                 (ios->power_mode == MMC_POWER_UP) &&
1475                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1476                 sdhci_enable_preset_value(host, false);
1477
1478         if (!ios->clock || ios->clock != host->clock) {
1479                 host->ops->set_clock(host, ios->clock);
1480                 host->clock = ios->clock;
1481
1482                 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1483                     host->clock) {
1484                         host->timeout_clk = host->mmc->actual_clock ?
1485                                                 host->mmc->actual_clock / 1000 :
1486                                                 host->clock / 1000;
1487                         host->mmc->max_busy_timeout =
1488                                 host->ops->get_max_timeout_count ?
1489                                 host->ops->get_max_timeout_count(host) :
1490                                 1 << 27;
1491                         host->mmc->max_busy_timeout /= host->timeout_clk;
1492                 }
1493         }
1494
1495         sdhci_set_power(host, ios->power_mode, ios->vdd);
1496
1497         if (host->ops->platform_send_init_74_clocks)
1498                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1499
1500         host->ops->set_bus_width(host, ios->bus_width);
1501
1502         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1503
1504         if ((ios->timing == MMC_TIMING_SD_HS ||
1505              ios->timing == MMC_TIMING_MMC_HS)
1506             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1507                 ctrl |= SDHCI_CTRL_HISPD;
1508         else
1509                 ctrl &= ~SDHCI_CTRL_HISPD;
1510
1511         if (host->version >= SDHCI_SPEC_300) {
1512                 u16 clk, ctrl_2;
1513
1514                 /* In case of UHS-I modes, set High Speed Enable */
1515                 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1516                     (ios->timing == MMC_TIMING_MMC_HS200) ||
1517                     (ios->timing == MMC_TIMING_MMC_DDR52) ||
1518                     (ios->timing == MMC_TIMING_UHS_SDR50) ||
1519                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1520                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1521                     (ios->timing == MMC_TIMING_UHS_SDR25))
1522                         ctrl |= SDHCI_CTRL_HISPD;
1523
1524                 if (!host->preset_enabled) {
1525                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1526                         /*
1527                          * We only need to set Driver Strength if the
1528                          * preset value enable is not set.
1529                          */
1530                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1531                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1532                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1533                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1534                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1535                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1536                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1537                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1538                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1539                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1540                         else {
1541                                 pr_warn("%s: invalid driver type, default to driver type B\n",
1542                                         mmc_hostname(mmc));
1543                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1544                         }
1545
1546                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1547                 } else {
1548                         /*
1549                          * According to SDHC Spec v3.00, if the Preset Value
1550                          * Enable in the Host Control 2 register is set, we
1551                          * need to reset SD Clock Enable before changing High
1552                          * Speed Enable to avoid generating clock gliches.
1553                          */
1554
1555                         /* Reset SD Clock Enable */
1556                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1557                         clk &= ~SDHCI_CLOCK_CARD_EN;
1558                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1559
1560                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1561
1562                         /* Re-enable SD Clock */
1563                         host->ops->set_clock(host, host->clock);
1564                 }
1565
1566                 /* Reset SD Clock Enable */
1567                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1568                 clk &= ~SDHCI_CLOCK_CARD_EN;
1569                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1570
1571                 host->ops->set_uhs_signaling(host, ios->timing);
1572                 host->timing = ios->timing;
1573
1574                 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1575                                 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1576                                  (ios->timing == MMC_TIMING_UHS_SDR25) ||
1577                                  (ios->timing == MMC_TIMING_UHS_SDR50) ||
1578                                  (ios->timing == MMC_TIMING_UHS_SDR104) ||
1579                                  (ios->timing == MMC_TIMING_UHS_DDR50) ||
1580                                  (ios->timing == MMC_TIMING_MMC_DDR52))) {
1581                         u16 preset;
1582
1583                         sdhci_enable_preset_value(host, true);
1584                         preset = sdhci_get_preset_value(host);
1585                         ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1586                                 >> SDHCI_PRESET_DRV_SHIFT;
1587                 }
1588
1589                 /* Re-enable SD Clock */
1590                 host->ops->set_clock(host, host->clock);
1591         } else
1592                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1593
1594         /*
1595          * Some (ENE) controllers go apeshit on some ios operation,
1596          * signalling timeout and CRC errors even on CMD0. Resetting
1597          * it on each ios seems to solve the problem.
1598          */
1599         if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1600                 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1601
1602         mmiowb();
1603         spin_unlock_irqrestore(&host->lock, flags);
1604 }
1605
1606 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1607 {
1608         struct sdhci_host *host = mmc_priv(mmc);
1609
1610         sdhci_runtime_pm_get(host);
1611         sdhci_do_set_ios(host, ios);
1612         sdhci_runtime_pm_put(host);
1613 }
1614
1615 static int sdhci_do_get_cd(struct sdhci_host *host)
1616 {
1617         int gpio_cd = mmc_gpio_get_cd(host->mmc);
1618
1619         if (host->flags & SDHCI_DEVICE_DEAD)
1620                 return 0;
1621
1622         /* If nonremovable, assume that the card is always present. */
1623         if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
1624                 return 1;
1625
1626         /*
1627          * Try slot gpio detect, if defined it take precedence
1628          * over build in controller functionality
1629          */
1630         if (!IS_ERR_VALUE(gpio_cd))
1631                 return !!gpio_cd;
1632
1633         /* If polling, assume that the card is always present. */
1634         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1635                 return 1;
1636
1637         /* Host native card detect */
1638         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1639 }
1640
1641 static int sdhci_get_cd(struct mmc_host *mmc)
1642 {
1643         struct sdhci_host *host = mmc_priv(mmc);
1644         int ret;
1645
1646         sdhci_runtime_pm_get(host);
1647         ret = sdhci_do_get_cd(host);
1648         sdhci_runtime_pm_put(host);
1649         return ret;
1650 }
1651
1652 static int sdhci_check_ro(struct sdhci_host *host)
1653 {
1654         unsigned long flags;
1655         int is_readonly;
1656
1657         spin_lock_irqsave(&host->lock, flags);
1658
1659         if (host->flags & SDHCI_DEVICE_DEAD)
1660                 is_readonly = 0;
1661         else if (host->ops->get_ro)
1662                 is_readonly = host->ops->get_ro(host);
1663         else
1664                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1665                                 & SDHCI_WRITE_PROTECT);
1666
1667         spin_unlock_irqrestore(&host->lock, flags);
1668
1669         /* This quirk needs to be replaced by a callback-function later */
1670         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1671                 !is_readonly : is_readonly;
1672 }
1673
1674 #define SAMPLE_COUNT    5
1675
1676 static int sdhci_do_get_ro(struct sdhci_host *host)
1677 {
1678         int i, ro_count;
1679
1680         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1681                 return sdhci_check_ro(host);
1682
1683         ro_count = 0;
1684         for (i = 0; i < SAMPLE_COUNT; i++) {
1685                 if (sdhci_check_ro(host)) {
1686                         if (++ro_count > SAMPLE_COUNT / 2)
1687                                 return 1;
1688                 }
1689                 msleep(30);
1690         }
1691         return 0;
1692 }
1693
1694 static void sdhci_hw_reset(struct mmc_host *mmc)
1695 {
1696         struct sdhci_host *host = mmc_priv(mmc);
1697
1698         if (host->ops && host->ops->hw_reset)
1699                 host->ops->hw_reset(host);
1700 }
1701
1702 static int sdhci_get_ro(struct mmc_host *mmc)
1703 {
1704         struct sdhci_host *host = mmc_priv(mmc);
1705         int ret;
1706
1707         sdhci_runtime_pm_get(host);
1708         ret = sdhci_do_get_ro(host);
1709         sdhci_runtime_pm_put(host);
1710         return ret;
1711 }
1712
1713 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1714 {
1715         if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1716                 if (enable)
1717                         host->ier |= SDHCI_INT_CARD_INT;
1718                 else
1719                         host->ier &= ~SDHCI_INT_CARD_INT;
1720
1721                 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1722                 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1723                 mmiowb();
1724         }
1725 }
1726
1727 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1728 {
1729         struct sdhci_host *host = mmc_priv(mmc);
1730         unsigned long flags;
1731
1732         sdhci_runtime_pm_get(host);
1733
1734         spin_lock_irqsave(&host->lock, flags);
1735         if (enable)
1736                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1737         else
1738                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1739
1740         sdhci_enable_sdio_irq_nolock(host, enable);
1741         spin_unlock_irqrestore(&host->lock, flags);
1742
1743         sdhci_runtime_pm_put(host);
1744 }
1745
1746 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1747                                                 struct mmc_ios *ios)
1748 {
1749         struct mmc_host *mmc = host->mmc;
1750         u16 ctrl;
1751         int ret;
1752
1753         /*
1754          * Signal Voltage Switching is only applicable for Host Controllers
1755          * v3.00 and above.
1756          */
1757         if (host->version < SDHCI_SPEC_300)
1758                 return 0;
1759
1760         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1761
1762         switch (ios->signal_voltage) {
1763         case MMC_SIGNAL_VOLTAGE_330:
1764                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1765                 ctrl &= ~SDHCI_CTRL_VDD_180;
1766                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1767
1768                 if (!IS_ERR(mmc->supply.vqmmc)) {
1769                         ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1770                                                     3600000);
1771                         if (ret) {
1772                                 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1773                                         mmc_hostname(mmc));
1774                                 return -EIO;
1775                         }
1776                 }
1777                 /* Wait for 5ms */
1778                 usleep_range(5000, 5500);
1779
1780                 /* 3.3V regulator output should be stable within 5 ms */
1781                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1782                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1783                         return 0;
1784
1785                 pr_warn("%s: 3.3V regulator output did not became stable\n",
1786                         mmc_hostname(mmc));
1787
1788                 return -EAGAIN;
1789         case MMC_SIGNAL_VOLTAGE_180:
1790                 if (!IS_ERR(mmc->supply.vqmmc)) {
1791                         ret = regulator_set_voltage(mmc->supply.vqmmc,
1792                                         1700000, 1950000);
1793                         if (ret) {
1794                                 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1795                                         mmc_hostname(mmc));
1796                                 return -EIO;
1797                         }
1798                 }
1799
1800                 /*
1801                  * Enable 1.8V Signal Enable in the Host Control2
1802                  * register
1803                  */
1804                 ctrl |= SDHCI_CTRL_VDD_180;
1805                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1806
1807                 /* Some controller need to do more when switching */
1808                 if (host->ops->voltage_switch)
1809                         host->ops->voltage_switch(host);
1810
1811                 /* 1.8V regulator output should be stable within 5 ms */
1812                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1813                 if (ctrl & SDHCI_CTRL_VDD_180)
1814                         return 0;
1815
1816                 pr_warn("%s: 1.8V regulator output did not became stable\n",
1817                         mmc_hostname(mmc));
1818
1819                 return -EAGAIN;
1820         case MMC_SIGNAL_VOLTAGE_120:
1821                 if (!IS_ERR(mmc->supply.vqmmc)) {
1822                         ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1823                                                     1300000);
1824                         if (ret) {
1825                                 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1826                                         mmc_hostname(mmc));
1827                                 return -EIO;
1828                         }
1829                 }
1830                 return 0;
1831         default:
1832                 /* No signal voltage switch required */
1833                 return 0;
1834         }
1835 }
1836
1837 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1838         struct mmc_ios *ios)
1839 {
1840         struct sdhci_host *host = mmc_priv(mmc);
1841         int err;
1842
1843         if (host->version < SDHCI_SPEC_300)
1844                 return 0;
1845         sdhci_runtime_pm_get(host);
1846         err = sdhci_do_start_signal_voltage_switch(host, ios);
1847         sdhci_runtime_pm_put(host);
1848         return err;
1849 }
1850
1851 static int sdhci_card_busy(struct mmc_host *mmc)
1852 {
1853         struct sdhci_host *host = mmc_priv(mmc);
1854         u32 present_state;
1855
1856         sdhci_runtime_pm_get(host);
1857         /* Check whether DAT[3:0] is 0000 */
1858         present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1859         sdhci_runtime_pm_put(host);
1860
1861         return !(present_state & SDHCI_DATA_LVL_MASK);
1862 }
1863
1864 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1865 {
1866         struct sdhci_host *host = mmc_priv(mmc);
1867         unsigned long flags;
1868
1869         spin_lock_irqsave(&host->lock, flags);
1870         host->flags |= SDHCI_HS400_TUNING;
1871         spin_unlock_irqrestore(&host->lock, flags);
1872
1873         return 0;
1874 }
1875
1876 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1877 {
1878         struct sdhci_host *host = mmc_priv(mmc);
1879         u16 ctrl;
1880         int tuning_loop_counter = MAX_TUNING_LOOP;
1881         int err = 0;
1882         unsigned long flags;
1883         unsigned int tuning_count = 0;
1884         bool hs400_tuning;
1885
1886         sdhci_runtime_pm_get(host);
1887         spin_lock_irqsave(&host->lock, flags);
1888
1889         hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1890         host->flags &= ~SDHCI_HS400_TUNING;
1891
1892         if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1893                 tuning_count = host->tuning_count;
1894
1895         /*
1896          * The Host Controller needs tuning in case of SDR104 and DDR50
1897          * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1898          * the Capabilities register.
1899          * If the Host Controller supports the HS200 mode then the
1900          * tuning function has to be executed.
1901          */
1902         switch (host->timing) {
1903         /* HS400 tuning is done in HS200 mode */
1904         case MMC_TIMING_MMC_HS400:
1905                 err = -EINVAL;
1906                 goto out_unlock;
1907
1908         case MMC_TIMING_MMC_HS200:
1909                 /*
1910                  * Periodic re-tuning for HS400 is not expected to be needed, so
1911                  * disable it here.
1912                  */
1913                 if (hs400_tuning)
1914                         tuning_count = 0;
1915                 break;
1916
1917         case MMC_TIMING_UHS_SDR104:
1918         case MMC_TIMING_UHS_DDR50:
1919                 break;
1920
1921         case MMC_TIMING_UHS_SDR50:
1922                 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1923                     host->flags & SDHCI_SDR104_NEEDS_TUNING)
1924                         break;
1925                 /* FALLTHROUGH */
1926
1927         default:
1928                 goto out_unlock;
1929         }
1930
1931         if (host->ops->platform_execute_tuning) {
1932                 spin_unlock_irqrestore(&host->lock, flags);
1933                 err = host->ops->platform_execute_tuning(host, opcode);
1934                 sdhci_runtime_pm_put(host);
1935                 return err;
1936         }
1937
1938         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1939         ctrl |= SDHCI_CTRL_EXEC_TUNING;
1940         if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1941                 ctrl |= SDHCI_CTRL_TUNED_CLK;
1942         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1943
1944         /*
1945          * As per the Host Controller spec v3.00, tuning command
1946          * generates Buffer Read Ready interrupt, so enable that.
1947          *
1948          * Note: The spec clearly says that when tuning sequence
1949          * is being performed, the controller does not generate
1950          * interrupts other than Buffer Read Ready interrupt. But
1951          * to make sure we don't hit a controller bug, we _only_
1952          * enable Buffer Read Ready interrupt here.
1953          */
1954         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1955         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1956
1957         /*
1958          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1959          * of loops reaches 40 times or a timeout of 150ms occurs.
1960          */
1961         do {
1962                 struct mmc_command cmd = {0};
1963                 struct mmc_request mrq = {NULL};
1964
1965                 cmd.opcode = opcode;
1966                 cmd.arg = 0;
1967                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1968                 cmd.retries = 0;
1969                 cmd.data = NULL;
1970                 cmd.error = 0;
1971
1972                 if (tuning_loop_counter-- == 0)
1973                         break;
1974
1975                 mrq.cmd = &cmd;
1976                 host->mrq = &mrq;
1977
1978                 /*
1979                  * In response to CMD19, the card sends 64 bytes of tuning
1980                  * block to the Host Controller. So we set the block size
1981                  * to 64 here.
1982                  */
1983                 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1984                         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1985                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1986                                              SDHCI_BLOCK_SIZE);
1987                         else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1988                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1989                                              SDHCI_BLOCK_SIZE);
1990                 } else {
1991                         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1992                                      SDHCI_BLOCK_SIZE);
1993                 }
1994
1995                 /*
1996                  * The tuning block is sent by the card to the host controller.
1997                  * So we set the TRNS_READ bit in the Transfer Mode register.
1998                  * This also takes care of setting DMA Enable and Multi Block
1999                  * Select in the same register to 0.
2000                  */
2001                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2002
2003                 sdhci_send_command(host, &cmd);
2004
2005                 host->cmd = NULL;
2006                 host->mrq = NULL;
2007
2008                 spin_unlock_irqrestore(&host->lock, flags);
2009                 /* Wait for Buffer Read Ready interrupt */
2010                 wait_event_interruptible_timeout(host->buf_ready_int,
2011                                         (host->tuning_done == 1),
2012                                         msecs_to_jiffies(50));
2013                 spin_lock_irqsave(&host->lock, flags);
2014
2015                 if (!host->tuning_done) {
2016                         pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
2017                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2018                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2019                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2020                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2021
2022                         err = -EIO;
2023                         goto out;
2024                 }
2025
2026                 host->tuning_done = 0;
2027
2028                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2029
2030                 /* eMMC spec does not require a delay between tuning cycles */
2031                 if (opcode == MMC_SEND_TUNING_BLOCK)
2032                         mdelay(1);
2033         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2034
2035         /*
2036          * The Host Driver has exhausted the maximum number of loops allowed,
2037          * so use fixed sampling frequency.
2038          */
2039         if (tuning_loop_counter < 0) {
2040                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2041                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2042         }
2043         if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2044                 pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n");
2045                 err = -EIO;
2046         }
2047
2048 out:
2049         if (tuning_count) {
2050                 /*
2051                  * In case tuning fails, host controllers which support
2052                  * re-tuning can try tuning again at a later time, when the
2053                  * re-tuning timer expires.  So for these controllers, we
2054                  * return 0. Since there might be other controllers who do not
2055                  * have this capability, we return error for them.
2056                  */
2057                 err = 0;
2058         }
2059
2060         host->mmc->retune_period = err ? 0 : tuning_count;
2061
2062         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2063         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2064 out_unlock:
2065         spin_unlock_irqrestore(&host->lock, flags);
2066         sdhci_runtime_pm_put(host);
2067
2068         return err;
2069 }
2070
2071 static int sdhci_select_drive_strength(struct mmc_card *card,
2072                                        unsigned int max_dtr, int host_drv,
2073                                        int card_drv, int *drv_type)
2074 {
2075         struct sdhci_host *host = mmc_priv(card->host);
2076
2077         if (!host->ops->select_drive_strength)
2078                 return 0;
2079
2080         return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2081                                                 card_drv, drv_type);
2082 }
2083
2084 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2085 {
2086         /* Host Controller v3.00 defines preset value registers */
2087         if (host->version < SDHCI_SPEC_300)
2088                 return;
2089
2090         /*
2091          * We only enable or disable Preset Value if they are not already
2092          * enabled or disabled respectively. Otherwise, we bail out.
2093          */
2094         if (host->preset_enabled != enable) {
2095                 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2096
2097                 if (enable)
2098                         ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2099                 else
2100                         ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2101
2102                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2103
2104                 if (enable)
2105                         host->flags |= SDHCI_PV_ENABLED;
2106                 else
2107                         host->flags &= ~SDHCI_PV_ENABLED;
2108
2109                 host->preset_enabled = enable;
2110         }
2111 }
2112
2113 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2114                                 int err)
2115 {
2116         struct sdhci_host *host = mmc_priv(mmc);
2117         struct mmc_data *data = mrq->data;
2118
2119         if (host->flags & SDHCI_REQ_USE_DMA) {
2120                 if (data->host_cookie == COOKIE_GIVEN ||
2121                                 data->host_cookie == COOKIE_MAPPED)
2122                         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2123                                          data->flags & MMC_DATA_WRITE ?
2124                                          DMA_TO_DEVICE : DMA_FROM_DEVICE);
2125                 data->host_cookie = COOKIE_UNMAPPED;
2126         }
2127 }
2128
2129 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
2130                                        struct mmc_data *data)
2131 {
2132         int sg_count;
2133
2134         if (data->host_cookie == COOKIE_MAPPED) {
2135                 data->host_cookie = COOKIE_GIVEN;
2136                 return data->sg_count;
2137         }
2138
2139         WARN_ON(data->host_cookie == COOKIE_GIVEN);
2140
2141         sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2142                                 data->flags & MMC_DATA_WRITE ?
2143                                 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2144
2145         if (sg_count == 0)
2146                 return -ENOSPC;
2147
2148         data->sg_count = sg_count;
2149         data->host_cookie = COOKIE_MAPPED;
2150
2151         return sg_count;
2152 }
2153
2154 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2155                                bool is_first_req)
2156 {
2157         struct sdhci_host *host = mmc_priv(mmc);
2158
2159         mrq->data->host_cookie = COOKIE_UNMAPPED;
2160
2161         if (host->flags & SDHCI_REQ_USE_DMA)
2162                 sdhci_pre_dma_transfer(host, mrq->data);
2163 }
2164
2165 static void sdhci_card_event(struct mmc_host *mmc)
2166 {
2167         struct sdhci_host *host = mmc_priv(mmc);
2168         unsigned long flags;
2169         int present;
2170
2171         /* First check if client has provided their own card event */
2172         if (host->ops->card_event)
2173                 host->ops->card_event(host);
2174
2175         present = sdhci_do_get_cd(host);
2176
2177         spin_lock_irqsave(&host->lock, flags);
2178
2179         /* Check host->mrq first in case we are runtime suspended */
2180         if (host->mrq && !present) {
2181                 pr_err("%s: Card removed during transfer!\n",
2182                         mmc_hostname(host->mmc));
2183                 pr_err("%s: Resetting controller.\n",
2184                         mmc_hostname(host->mmc));
2185
2186                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2187                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2188
2189                 host->mrq->cmd->error = -ENOMEDIUM;
2190                 tasklet_schedule(&host->finish_tasklet);
2191         }
2192
2193         spin_unlock_irqrestore(&host->lock, flags);
2194 }
2195
2196 static const struct mmc_host_ops sdhci_ops = {
2197         .request        = sdhci_request,
2198         .post_req       = sdhci_post_req,
2199         .pre_req        = sdhci_pre_req,
2200         .set_ios        = sdhci_set_ios,
2201         .get_cd         = sdhci_get_cd,
2202         .get_ro         = sdhci_get_ro,
2203         .hw_reset       = sdhci_hw_reset,
2204         .enable_sdio_irq = sdhci_enable_sdio_irq,
2205         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2206         .prepare_hs400_tuning           = sdhci_prepare_hs400_tuning,
2207         .execute_tuning                 = sdhci_execute_tuning,
2208         .select_drive_strength          = sdhci_select_drive_strength,
2209         .card_event                     = sdhci_card_event,
2210         .card_busy      = sdhci_card_busy,
2211 };
2212
2213 /*****************************************************************************\
2214  *                                                                           *
2215  * Tasklets                                                                  *
2216  *                                                                           *
2217 \*****************************************************************************/
2218
2219 static void sdhci_tasklet_finish(unsigned long param)
2220 {
2221         struct sdhci_host *host;
2222         unsigned long flags;
2223         struct mmc_request *mrq;
2224
2225         host = (struct sdhci_host*)param;
2226
2227         spin_lock_irqsave(&host->lock, flags);
2228
2229         /*
2230          * If this tasklet gets rescheduled while running, it will
2231          * be run again afterwards but without any active request.
2232          */
2233         if (!host->mrq) {
2234                 spin_unlock_irqrestore(&host->lock, flags);
2235                 return;
2236         }
2237
2238         del_timer(&host->timer);
2239
2240         mrq = host->mrq;
2241
2242         /*
2243          * The controller needs a reset of internal state machines
2244          * upon error conditions.
2245          */
2246         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2247             ((mrq->cmd && mrq->cmd->error) ||
2248              (mrq->sbc && mrq->sbc->error) ||
2249              (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2250                             (mrq->data->stop && mrq->data->stop->error))) ||
2251              (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2252
2253                 /* Some controllers need this kick or reset won't work here */
2254                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2255                         /* This is to force an update */
2256                         host->ops->set_clock(host, host->clock);
2257
2258                 /* Spec says we should do both at the same time, but Ricoh
2259                    controllers do not like that. */
2260                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2261                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2262         }
2263
2264         host->mrq = NULL;
2265         host->cmd = NULL;
2266         host->data = NULL;
2267
2268 #ifndef SDHCI_USE_LEDS_CLASS
2269         sdhci_deactivate_led(host);
2270 #endif
2271
2272         mmiowb();
2273         spin_unlock_irqrestore(&host->lock, flags);
2274
2275         mmc_request_done(host->mmc, mrq);
2276         sdhci_runtime_pm_put(host);
2277 }
2278
2279 static void sdhci_timeout_timer(unsigned long data)
2280 {
2281         struct sdhci_host *host;
2282         unsigned long flags;
2283
2284         host = (struct sdhci_host*)data;
2285
2286         spin_lock_irqsave(&host->lock, flags);
2287
2288         if (host->mrq) {
2289                 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2290                        mmc_hostname(host->mmc));
2291                 sdhci_dumpregs(host);
2292
2293                 if (host->data) {
2294                         host->data->error = -ETIMEDOUT;
2295                         sdhci_finish_data(host);
2296                 } else {
2297                         if (host->cmd)
2298                                 host->cmd->error = -ETIMEDOUT;
2299                         else
2300                                 host->mrq->cmd->error = -ETIMEDOUT;
2301
2302                         tasklet_schedule(&host->finish_tasklet);
2303                 }
2304         }
2305
2306         mmiowb();
2307         spin_unlock_irqrestore(&host->lock, flags);
2308 }
2309
2310 /*****************************************************************************\
2311  *                                                                           *
2312  * Interrupt handling                                                        *
2313  *                                                                           *
2314 \*****************************************************************************/
2315
2316 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2317 {
2318         BUG_ON(intmask == 0);
2319
2320         if (!host->cmd) {
2321                 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2322                        mmc_hostname(host->mmc), (unsigned)intmask);
2323                 sdhci_dumpregs(host);
2324                 return;
2325         }
2326
2327         if (intmask & SDHCI_INT_TIMEOUT)
2328                 host->cmd->error = -ETIMEDOUT;
2329         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2330                         SDHCI_INT_INDEX))
2331                 host->cmd->error = -EILSEQ;
2332
2333         if (host->cmd->error) {
2334                 tasklet_schedule(&host->finish_tasklet);
2335                 return;
2336         }
2337
2338         /*
2339          * The host can send and interrupt when the busy state has
2340          * ended, allowing us to wait without wasting CPU cycles.
2341          * Unfortunately this is overloaded on the "data complete"
2342          * interrupt, so we need to take some care when handling
2343          * it.
2344          *
2345          * Note: The 1.0 specification is a bit ambiguous about this
2346          *       feature so there might be some problems with older
2347          *       controllers.
2348          */
2349         if (host->cmd->flags & MMC_RSP_BUSY) {
2350                 if (host->cmd->data)
2351                         DBG("Cannot wait for busy signal when also doing a data transfer");
2352                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2353                                 && !host->busy_handle) {
2354                         /* Mark that command complete before busy is ended */
2355                         host->busy_handle = 1;
2356                         return;
2357                 }
2358
2359                 /* The controller does not support the end-of-busy IRQ,
2360                  * fall through and take the SDHCI_INT_RESPONSE */
2361         } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2362                    host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2363                 *mask &= ~SDHCI_INT_DATA_END;
2364         }
2365
2366         if (intmask & SDHCI_INT_RESPONSE)
2367                 sdhci_finish_command(host);
2368 }
2369
2370 #ifdef CONFIG_MMC_DEBUG
2371 static void sdhci_adma_show_error(struct sdhci_host *host)
2372 {
2373         const char *name = mmc_hostname(host->mmc);
2374         void *desc = host->adma_table;
2375
2376         sdhci_dumpregs(host);
2377
2378         while (true) {
2379                 struct sdhci_adma2_64_desc *dma_desc = desc;
2380
2381                 if (host->flags & SDHCI_USE_64_BIT_DMA)
2382                         DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2383                             name, desc, le32_to_cpu(dma_desc->addr_hi),
2384                             le32_to_cpu(dma_desc->addr_lo),
2385                             le16_to_cpu(dma_desc->len),
2386                             le16_to_cpu(dma_desc->cmd));
2387                 else
2388                         DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2389                             name, desc, le32_to_cpu(dma_desc->addr_lo),
2390                             le16_to_cpu(dma_desc->len),
2391                             le16_to_cpu(dma_desc->cmd));
2392
2393                 desc += host->desc_sz;
2394
2395                 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2396                         break;
2397         }
2398 }
2399 #else
2400 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2401 #endif
2402
2403 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2404 {
2405         u32 command;
2406         BUG_ON(intmask == 0);
2407
2408         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2409         if (intmask & SDHCI_INT_DATA_AVAIL) {
2410                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2411                 if (command == MMC_SEND_TUNING_BLOCK ||
2412                     command == MMC_SEND_TUNING_BLOCK_HS200) {
2413                         host->tuning_done = 1;
2414                         wake_up(&host->buf_ready_int);
2415                         return;
2416                 }
2417         }
2418
2419         if (!host->data) {
2420                 /*
2421                  * The "data complete" interrupt is also used to
2422                  * indicate that a busy state has ended. See comment
2423                  * above in sdhci_cmd_irq().
2424                  */
2425                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2426                         if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2427                                 host->cmd->error = -ETIMEDOUT;
2428                                 tasklet_schedule(&host->finish_tasklet);
2429                                 return;
2430                         }
2431                         if (intmask & SDHCI_INT_DATA_END) {
2432                                 /*
2433                                  * Some cards handle busy-end interrupt
2434                                  * before the command completed, so make
2435                                  * sure we do things in the proper order.
2436                                  */
2437                                 if (host->busy_handle)
2438                                         sdhci_finish_command(host);
2439                                 else
2440                                         host->busy_handle = 1;
2441                                 return;
2442                         }
2443                 }
2444
2445                 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2446                        mmc_hostname(host->mmc), (unsigned)intmask);
2447                 sdhci_dumpregs(host);
2448
2449                 return;
2450         }
2451
2452         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2453                 host->data->error = -ETIMEDOUT;
2454         else if (intmask & SDHCI_INT_DATA_END_BIT)
2455                 host->data->error = -EILSEQ;
2456         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2457                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2458                         != MMC_BUS_TEST_R)
2459                 host->data->error = -EILSEQ;
2460         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2461                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2462                 sdhci_adma_show_error(host);
2463                 host->data->error = -EIO;
2464                 if (host->ops->adma_workaround)
2465                         host->ops->adma_workaround(host, intmask);
2466         }
2467
2468         if (host->data->error)
2469                 sdhci_finish_data(host);
2470         else {
2471                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2472                         sdhci_transfer_pio(host);
2473
2474                 /*
2475                  * We currently don't do anything fancy with DMA
2476                  * boundaries, but as we can't disable the feature
2477                  * we need to at least restart the transfer.
2478                  *
2479                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2480                  * should return a valid address to continue from, but as
2481                  * some controllers are faulty, don't trust them.
2482                  */
2483                 if (intmask & SDHCI_INT_DMA_END) {
2484                         u32 dmastart, dmanow;
2485                         dmastart = sg_dma_address(host->data->sg);
2486                         dmanow = dmastart + host->data->bytes_xfered;
2487                         /*
2488                          * Force update to the next DMA block boundary.
2489                          */
2490                         dmanow = (dmanow &
2491                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2492                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2493                         host->data->bytes_xfered = dmanow - dmastart;
2494                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2495                                 " next 0x%08x\n",
2496                                 mmc_hostname(host->mmc), dmastart,
2497                                 host->data->bytes_xfered, dmanow);
2498                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2499                 }
2500
2501                 if (intmask & SDHCI_INT_DATA_END) {
2502                         if (host->cmd) {
2503                                 /*
2504                                  * Data managed to finish before the
2505                                  * command completed. Make sure we do
2506                                  * things in the proper order.
2507                                  */
2508                                 host->data_early = 1;
2509                         } else {
2510                                 sdhci_finish_data(host);
2511                         }
2512                 }
2513         }
2514 }
2515
2516 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2517 {
2518         irqreturn_t result = IRQ_NONE;
2519         struct sdhci_host *host = dev_id;
2520         u32 intmask, mask, unexpected = 0;
2521         int max_loops = 16;
2522
2523         spin_lock(&host->lock);
2524
2525         if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2526                 spin_unlock(&host->lock);
2527                 return IRQ_NONE;
2528         }
2529
2530         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2531         if (!intmask || intmask == 0xffffffff) {
2532                 result = IRQ_NONE;
2533                 goto out;
2534         }
2535
2536         do {
2537                 /* Clear selected interrupts. */
2538                 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2539                                   SDHCI_INT_BUS_POWER);
2540                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2541
2542                 DBG("*** %s got interrupt: 0x%08x\n",
2543                         mmc_hostname(host->mmc), intmask);
2544
2545                 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2546                         u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2547                                       SDHCI_CARD_PRESENT;
2548
2549                         /*
2550                          * There is a observation on i.mx esdhc.  INSERT
2551                          * bit will be immediately set again when it gets
2552                          * cleared, if a card is inserted.  We have to mask
2553                          * the irq to prevent interrupt storm which will
2554                          * freeze the system.  And the REMOVE gets the
2555                          * same situation.
2556                          *
2557                          * More testing are needed here to ensure it works
2558                          * for other platforms though.
2559                          */
2560                         host->ier &= ~(SDHCI_INT_CARD_INSERT |
2561                                        SDHCI_INT_CARD_REMOVE);
2562                         host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2563                                                SDHCI_INT_CARD_INSERT;
2564                         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2565                         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2566
2567                         sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2568                                      SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2569
2570                         host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2571                                                        SDHCI_INT_CARD_REMOVE);
2572                         result = IRQ_WAKE_THREAD;
2573                 }
2574
2575                 if (intmask & SDHCI_INT_CMD_MASK)
2576                         sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2577                                       &intmask);
2578
2579                 if (intmask & SDHCI_INT_DATA_MASK)
2580                         sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2581
2582                 if (intmask & SDHCI_INT_BUS_POWER)
2583                         pr_err("%s: Card is consuming too much power!\n",
2584                                 mmc_hostname(host->mmc));
2585
2586                 if (intmask & SDHCI_INT_CARD_INT) {
2587                         sdhci_enable_sdio_irq_nolock(host, false);
2588                         host->thread_isr |= SDHCI_INT_CARD_INT;
2589                         result = IRQ_WAKE_THREAD;
2590                 }
2591
2592                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2593                              SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2594                              SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2595                              SDHCI_INT_CARD_INT);
2596
2597                 if (intmask) {
2598                         unexpected |= intmask;
2599                         sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2600                 }
2601
2602                 if (result == IRQ_NONE)
2603                         result = IRQ_HANDLED;
2604
2605                 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2606         } while (intmask && --max_loops);
2607 out:
2608         spin_unlock(&host->lock);
2609
2610         if (unexpected) {
2611                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2612                            mmc_hostname(host->mmc), unexpected);
2613                 sdhci_dumpregs(host);
2614         }
2615
2616         return result;
2617 }
2618
2619 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2620 {
2621         struct sdhci_host *host = dev_id;
2622         unsigned long flags;
2623         u32 isr;
2624
2625         spin_lock_irqsave(&host->lock, flags);
2626         isr = host->thread_isr;
2627         host->thread_isr = 0;
2628         spin_unlock_irqrestore(&host->lock, flags);
2629
2630         if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2631                 sdhci_card_event(host->mmc);
2632                 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2633         }
2634
2635         if (isr & SDHCI_INT_CARD_INT) {
2636                 sdio_run_irqs(host->mmc);
2637
2638                 spin_lock_irqsave(&host->lock, flags);
2639                 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2640                         sdhci_enable_sdio_irq_nolock(host, true);
2641                 spin_unlock_irqrestore(&host->lock, flags);
2642         }
2643
2644         return isr ? IRQ_HANDLED : IRQ_NONE;
2645 }
2646
2647 /*****************************************************************************\
2648  *                                                                           *
2649  * Suspend/resume                                                            *
2650  *                                                                           *
2651 \*****************************************************************************/
2652
2653 #ifdef CONFIG_PM
2654 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2655 {
2656         u8 val;
2657         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2658                         | SDHCI_WAKE_ON_INT;
2659
2660         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2661         val |= mask ;
2662         /* Avoid fake wake up */
2663         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2664                 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2665         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2666 }
2667 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2668
2669 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2670 {
2671         u8 val;
2672         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2673                         | SDHCI_WAKE_ON_INT;
2674
2675         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2676         val &= ~mask;
2677         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2678 }
2679
2680 int sdhci_suspend_host(struct sdhci_host *host)
2681 {
2682         sdhci_disable_card_detection(host);
2683
2684         mmc_retune_timer_stop(host->mmc);
2685         mmc_retune_needed(host->mmc);
2686
2687         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2688                 host->ier = 0;
2689                 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2690                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2691                 free_irq(host->irq, host);
2692         } else {
2693                 sdhci_enable_irq_wakeups(host);
2694                 enable_irq_wake(host->irq);
2695         }
2696         return 0;
2697 }
2698
2699 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2700
2701 int sdhci_resume_host(struct sdhci_host *host)
2702 {
2703         int ret = 0;
2704
2705         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2706                 if (host->ops->enable_dma)
2707                         host->ops->enable_dma(host);
2708         }
2709
2710         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2711             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2712                 /* Card keeps power but host controller does not */
2713                 sdhci_init(host, 0);
2714                 host->pwr = 0;
2715                 host->clock = 0;
2716                 sdhci_do_set_ios(host, &host->mmc->ios);
2717         } else {
2718                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2719                 mmiowb();
2720         }
2721
2722         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2723                 ret = request_threaded_irq(host->irq, sdhci_irq,
2724                                            sdhci_thread_irq, IRQF_SHARED,
2725                                            mmc_hostname(host->mmc), host);
2726                 if (ret)
2727                         return ret;
2728         } else {
2729                 sdhci_disable_irq_wakeups(host);
2730                 disable_irq_wake(host->irq);
2731         }
2732
2733         sdhci_enable_card_detection(host);
2734
2735         return ret;
2736 }
2737
2738 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2739
2740 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2741 {
2742         return pm_runtime_get_sync(host->mmc->parent);
2743 }
2744
2745 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2746 {
2747         pm_runtime_mark_last_busy(host->mmc->parent);
2748         return pm_runtime_put_autosuspend(host->mmc->parent);
2749 }
2750
2751 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2752 {
2753         if (host->runtime_suspended || host->bus_on)
2754                 return;
2755         host->bus_on = true;
2756         pm_runtime_get_noresume(host->mmc->parent);
2757 }
2758
2759 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2760 {
2761         if (host->runtime_suspended || !host->bus_on)
2762                 return;
2763         host->bus_on = false;
2764         pm_runtime_put_noidle(host->mmc->parent);
2765 }
2766
2767 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2768 {
2769         unsigned long flags;
2770
2771         mmc_retune_timer_stop(host->mmc);
2772         mmc_retune_needed(host->mmc);
2773
2774         spin_lock_irqsave(&host->lock, flags);
2775         host->ier &= SDHCI_INT_CARD_INT;
2776         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2777         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2778         spin_unlock_irqrestore(&host->lock, flags);
2779
2780         synchronize_hardirq(host->irq);
2781
2782         spin_lock_irqsave(&host->lock, flags);
2783         host->runtime_suspended = true;
2784         spin_unlock_irqrestore(&host->lock, flags);
2785
2786         return 0;
2787 }
2788 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2789
2790 int sdhci_runtime_resume_host(struct sdhci_host *host)
2791 {
2792         unsigned long flags;
2793         int host_flags = host->flags;
2794
2795         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2796                 if (host->ops->enable_dma)
2797                         host->ops->enable_dma(host);
2798         }
2799
2800         sdhci_init(host, 0);
2801
2802         /* Force clock and power re-program */
2803         host->pwr = 0;
2804         host->clock = 0;
2805         sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2806         sdhci_do_set_ios(host, &host->mmc->ios);
2807
2808         if ((host_flags & SDHCI_PV_ENABLED) &&
2809                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2810                 spin_lock_irqsave(&host->lock, flags);
2811                 sdhci_enable_preset_value(host, true);
2812                 spin_unlock_irqrestore(&host->lock, flags);
2813         }
2814
2815         spin_lock_irqsave(&host->lock, flags);
2816
2817         host->runtime_suspended = false;
2818
2819         /* Enable SDIO IRQ */
2820         if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2821                 sdhci_enable_sdio_irq_nolock(host, true);
2822
2823         /* Enable Card Detection */
2824         sdhci_enable_card_detection(host);
2825
2826         spin_unlock_irqrestore(&host->lock, flags);
2827
2828         return 0;
2829 }
2830 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2831
2832 #endif /* CONFIG_PM */
2833
2834 /*****************************************************************************\
2835  *                                                                           *
2836  * Device allocation/registration                                            *
2837  *                                                                           *
2838 \*****************************************************************************/
2839
2840 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2841         size_t priv_size)
2842 {
2843         struct mmc_host *mmc;
2844         struct sdhci_host *host;
2845
2846         WARN_ON(dev == NULL);
2847
2848         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2849         if (!mmc)
2850                 return ERR_PTR(-ENOMEM);
2851
2852         host = mmc_priv(mmc);
2853         host->mmc = mmc;
2854
2855         return host;
2856 }
2857
2858 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2859
2860 int sdhci_add_host(struct sdhci_host *host)
2861 {
2862         struct mmc_host *mmc;
2863         u32 caps[2] = {0, 0};
2864         u32 max_current_caps;
2865         unsigned int ocr_avail;
2866         unsigned int override_timeout_clk;
2867         u32 max_clk;
2868         int ret;
2869
2870         WARN_ON(host == NULL);
2871         if (host == NULL)
2872                 return -EINVAL;
2873
2874         mmc = host->mmc;
2875
2876         if (debug_quirks)
2877                 host->quirks = debug_quirks;
2878         if (debug_quirks2)
2879                 host->quirks2 = debug_quirks2;
2880
2881         override_timeout_clk = host->timeout_clk;
2882
2883         sdhci_do_reset(host, SDHCI_RESET_ALL);
2884
2885         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2886         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2887                                 >> SDHCI_SPEC_VER_SHIFT;
2888         if (host->version > SDHCI_SPEC_300) {
2889                 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
2890                        mmc_hostname(mmc), host->version);
2891         }
2892
2893         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2894                 sdhci_readl(host, SDHCI_CAPABILITIES);
2895
2896         if (host->version >= SDHCI_SPEC_300)
2897                 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2898                         host->caps1 :
2899                         sdhci_readl(host, SDHCI_CAPABILITIES_1);
2900
2901         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2902                 host->flags |= SDHCI_USE_SDMA;
2903         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2904                 DBG("Controller doesn't have SDMA capability\n");
2905         else
2906                 host->flags |= SDHCI_USE_SDMA;
2907
2908         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2909                 (host->flags & SDHCI_USE_SDMA)) {
2910                 DBG("Disabling DMA as it is marked broken\n");
2911                 host->flags &= ~SDHCI_USE_SDMA;
2912         }
2913
2914         if ((host->version >= SDHCI_SPEC_200) &&
2915                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2916                 host->flags |= SDHCI_USE_ADMA;
2917
2918         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2919                 (host->flags & SDHCI_USE_ADMA)) {
2920                 DBG("Disabling ADMA as it is marked broken\n");
2921                 host->flags &= ~SDHCI_USE_ADMA;
2922         }
2923
2924         /*
2925          * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2926          * and *must* do 64-bit DMA.  A driver has the opportunity to change
2927          * that during the first call to ->enable_dma().  Similarly
2928          * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2929          * implement.
2930          */
2931         if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT)
2932                 host->flags |= SDHCI_USE_64_BIT_DMA;
2933
2934         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2935                 if (host->ops->enable_dma) {
2936                         if (host->ops->enable_dma(host)) {
2937                                 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2938                                         mmc_hostname(mmc));
2939                                 host->flags &=
2940                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2941                         }
2942                 }
2943         }
2944
2945         /* SDMA does not support 64-bit DMA */
2946         if (host->flags & SDHCI_USE_64_BIT_DMA)
2947                 host->flags &= ~SDHCI_USE_SDMA;
2948
2949         if (host->flags & SDHCI_USE_ADMA) {
2950                 /*
2951                  * The DMA descriptor table size is calculated as the maximum
2952                  * number of segments times 2, to allow for an alignment
2953                  * descriptor for each segment, plus 1 for a nop end descriptor,
2954                  * all multipled by the descriptor size.
2955                  */
2956                 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2957                         host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2958                                               SDHCI_ADMA2_64_DESC_SZ;
2959                         host->align_buffer_sz = SDHCI_MAX_SEGS *
2960                                                 SDHCI_ADMA2_64_ALIGN;
2961                         host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
2962                         host->align_sz = SDHCI_ADMA2_64_ALIGN;
2963                         host->align_mask = SDHCI_ADMA2_64_ALIGN - 1;
2964                 } else {
2965                         host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2966                                               SDHCI_ADMA2_32_DESC_SZ;
2967                         host->align_buffer_sz = SDHCI_MAX_SEGS *
2968                                                 SDHCI_ADMA2_32_ALIGN;
2969                         host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
2970                         host->align_sz = SDHCI_ADMA2_32_ALIGN;
2971                         host->align_mask = SDHCI_ADMA2_32_ALIGN - 1;
2972                 }
2973                 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
2974                                                       host->adma_table_sz,
2975                                                       &host->adma_addr,
2976                                                       GFP_KERNEL);
2977                 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
2978                 if (!host->adma_table || !host->align_buffer) {
2979                         if (host->adma_table)
2980                                 dma_free_coherent(mmc_dev(mmc),
2981                                                   host->adma_table_sz,
2982                                                   host->adma_table,
2983                                                   host->adma_addr);
2984                         kfree(host->align_buffer);
2985                         pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2986                                 mmc_hostname(mmc));
2987                         host->flags &= ~SDHCI_USE_ADMA;
2988                         host->adma_table = NULL;
2989                         host->align_buffer = NULL;
2990                 } else if (host->adma_addr & host->align_mask) {
2991                         pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2992                                 mmc_hostname(mmc));
2993                         host->flags &= ~SDHCI_USE_ADMA;
2994                         dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
2995                                           host->adma_table, host->adma_addr);
2996                         kfree(host->align_buffer);
2997                         host->adma_table = NULL;
2998                         host->align_buffer = NULL;
2999                 }
3000         }
3001
3002         /*
3003          * If we use DMA, then it's up to the caller to set the DMA
3004          * mask, but PIO does not need the hw shim so we set a new
3005          * mask here in that case.
3006          */
3007         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3008                 host->dma_mask = DMA_BIT_MASK(64);
3009                 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3010         }
3011
3012         if (host->version >= SDHCI_SPEC_300)
3013                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
3014                         >> SDHCI_CLOCK_BASE_SHIFT;
3015         else
3016                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
3017                         >> SDHCI_CLOCK_BASE_SHIFT;
3018
3019         host->max_clk *= 1000000;
3020         if (host->max_clk == 0 || host->quirks &
3021                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3022                 if (!host->ops->get_max_clock) {
3023                         pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3024                                mmc_hostname(mmc));
3025                         return -ENODEV;
3026                 }
3027                 host->max_clk = host->ops->get_max_clock(host);
3028         }
3029
3030         /*
3031          * In case of Host Controller v3.00, find out whether clock
3032          * multiplier is supported.
3033          */
3034         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3035                         SDHCI_CLOCK_MUL_SHIFT;
3036
3037         /*
3038          * In case the value in Clock Multiplier is 0, then programmable
3039          * clock mode is not supported, otherwise the actual clock
3040          * multiplier is one more than the value of Clock Multiplier
3041          * in the Capabilities Register.
3042          */
3043         if (host->clk_mul)
3044                 host->clk_mul += 1;
3045
3046         /*
3047          * Set host parameters.
3048          */
3049         mmc->ops = &sdhci_ops;
3050         max_clk = host->max_clk;
3051
3052         if (host->ops->get_min_clock)
3053                 mmc->f_min = host->ops->get_min_clock(host);
3054         else if (host->version >= SDHCI_SPEC_300) {
3055                 if (host->clk_mul) {
3056                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3057                         max_clk = host->max_clk * host->clk_mul;
3058                 } else
3059                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3060         } else
3061                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3062
3063         if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk)))
3064                 mmc->f_max = max_clk;
3065
3066         if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3067                 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3068                                         SDHCI_TIMEOUT_CLK_SHIFT;
3069                 if (host->timeout_clk == 0) {
3070                         if (host->ops->get_timeout_clock) {
3071                                 host->timeout_clk =
3072                                         host->ops->get_timeout_clock(host);
3073                         } else {
3074                                 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3075                                         mmc_hostname(mmc));
3076                                 return -ENODEV;
3077                         }
3078                 }
3079
3080                 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3081                         host->timeout_clk *= 1000;
3082
3083                 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3084                         host->ops->get_max_timeout_count(host) : 1 << 27;
3085                 mmc->max_busy_timeout /= host->timeout_clk;
3086         }
3087
3088         if (override_timeout_clk)
3089                 host->timeout_clk = override_timeout_clk;
3090
3091         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3092         mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3093
3094         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3095                 host->flags |= SDHCI_AUTO_CMD12;
3096
3097         /* Auto-CMD23 stuff only works in ADMA or PIO. */
3098         if ((host->version >= SDHCI_SPEC_300) &&
3099             ((host->flags & SDHCI_USE_ADMA) ||
3100              !(host->flags & SDHCI_USE_SDMA)) &&
3101              !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3102                 host->flags |= SDHCI_AUTO_CMD23;
3103                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3104         } else {
3105                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3106         }
3107
3108         /*
3109          * A controller may support 8-bit width, but the board itself
3110          * might not have the pins brought out.  Boards that support
3111          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3112          * their platform code before calling sdhci_add_host(), and we
3113          * won't assume 8-bit width for hosts without that CAP.
3114          */
3115         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3116                 mmc->caps |= MMC_CAP_4_BIT_DATA;
3117
3118         if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3119                 mmc->caps &= ~MMC_CAP_CMD23;
3120
3121         if (caps[0] & SDHCI_CAN_DO_HISPD)
3122                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3123
3124         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3125             !(mmc->caps & MMC_CAP_NONREMOVABLE) &&
3126             IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
3127                 mmc->caps |= MMC_CAP_NEEDS_POLL;
3128
3129         /* If there are external regulators, get them */
3130         if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3131                 return -EPROBE_DEFER;
3132
3133         /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3134         if (!IS_ERR(mmc->supply.vqmmc)) {
3135                 ret = regulator_enable(mmc->supply.vqmmc);
3136                 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3137                                                     1950000))
3138                         caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3139                                         SDHCI_SUPPORT_SDR50 |
3140                                         SDHCI_SUPPORT_DDR50);
3141                 if (ret) {
3142                         pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3143                                 mmc_hostname(mmc), ret);
3144                         mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3145                 }
3146         }
3147
3148         if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3149                 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3150                        SDHCI_SUPPORT_DDR50);
3151
3152         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3153         if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3154                        SDHCI_SUPPORT_DDR50))
3155                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3156
3157         /* SDR104 supports also implies SDR50 support */
3158         if (caps[1] & SDHCI_SUPPORT_SDR104) {
3159                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3160                 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3161                  * field can be promoted to support HS200.
3162                  */
3163                 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3164                         mmc->caps2 |= MMC_CAP2_HS200;
3165         } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3166                 mmc->caps |= MMC_CAP_UHS_SDR50;
3167
3168         if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3169             (caps[1] & SDHCI_SUPPORT_HS400))
3170                 mmc->caps2 |= MMC_CAP2_HS400;
3171
3172         if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3173             (IS_ERR(mmc->supply.vqmmc) ||
3174              !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3175                                              1300000)))
3176                 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3177
3178         if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3179                 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3180                 mmc->caps |= MMC_CAP_UHS_DDR50;
3181
3182         /* Does the host need tuning for SDR50? */
3183         if (caps[1] & SDHCI_USE_SDR50_TUNING)
3184                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3185
3186         /* Does the host need tuning for SDR104 / HS200? */
3187         if (mmc->caps2 & MMC_CAP2_HS200)
3188                 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3189
3190         /* Driver Type(s) (A, C, D) supported by the host */
3191         if (caps[1] & SDHCI_DRIVER_TYPE_A)
3192                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3193         if (caps[1] & SDHCI_DRIVER_TYPE_C)
3194                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3195         if (caps[1] & SDHCI_DRIVER_TYPE_D)
3196                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3197
3198         /* Initial value for re-tuning timer count */
3199         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3200                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3201
3202         /*
3203          * In case Re-tuning Timer is not disabled, the actual value of
3204          * re-tuning timer will be 2 ^ (n - 1).
3205          */
3206         if (host->tuning_count)
3207                 host->tuning_count = 1 << (host->tuning_count - 1);
3208
3209         /* Re-tuning mode supported by the Host Controller */
3210         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3211                              SDHCI_RETUNING_MODE_SHIFT;
3212
3213         ocr_avail = 0;
3214
3215         /*
3216          * According to SD Host Controller spec v3.00, if the Host System
3217          * can afford more than 150mA, Host Driver should set XPC to 1. Also
3218          * the value is meaningful only if Voltage Support in the Capabilities
3219          * register is set. The actual current value is 4 times the register
3220          * value.
3221          */
3222         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3223         if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3224                 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3225                 if (curr > 0) {
3226
3227                         /* convert to SDHCI_MAX_CURRENT format */
3228                         curr = curr/1000;  /* convert to mA */
3229                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3230
3231                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3232                         max_current_caps =
3233                                 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3234                                 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3235                                 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3236                 }
3237         }
3238
3239         if (caps[0] & SDHCI_CAN_VDD_330) {
3240                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3241
3242                 mmc->max_current_330 = ((max_current_caps &
3243                                    SDHCI_MAX_CURRENT_330_MASK) >>
3244                                    SDHCI_MAX_CURRENT_330_SHIFT) *
3245                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3246         }
3247         if (caps[0] & SDHCI_CAN_VDD_300) {
3248                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3249
3250                 mmc->max_current_300 = ((max_current_caps &
3251                                    SDHCI_MAX_CURRENT_300_MASK) >>
3252                                    SDHCI_MAX_CURRENT_300_SHIFT) *
3253                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3254         }
3255         if (caps[0] & SDHCI_CAN_VDD_180) {
3256                 ocr_avail |= MMC_VDD_165_195;
3257
3258                 mmc->max_current_180 = ((max_current_caps &
3259                                    SDHCI_MAX_CURRENT_180_MASK) >>
3260                                    SDHCI_MAX_CURRENT_180_SHIFT) *
3261                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3262         }
3263
3264         /* If OCR set by host, use it instead. */
3265         if (host->ocr_mask)
3266                 ocr_avail = host->ocr_mask;
3267
3268         /* If OCR set by external regulators, give it highest prio. */
3269         if (mmc->ocr_avail)
3270                 ocr_avail = mmc->ocr_avail;
3271
3272         mmc->ocr_avail = ocr_avail;
3273         mmc->ocr_avail_sdio = ocr_avail;
3274         if (host->ocr_avail_sdio)
3275                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3276         mmc->ocr_avail_sd = ocr_avail;
3277         if (host->ocr_avail_sd)
3278                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3279         else /* normal SD controllers don't support 1.8V */
3280                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3281         mmc->ocr_avail_mmc = ocr_avail;
3282         if (host->ocr_avail_mmc)
3283                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3284
3285         if (mmc->ocr_avail == 0) {
3286                 pr_err("%s: Hardware doesn't report any support voltages.\n",
3287                        mmc_hostname(mmc));
3288                 return -ENODEV;
3289         }
3290
3291         spin_lock_init(&host->lock);
3292
3293         /*
3294          * Maximum number of segments. Depends on if the hardware
3295          * can do scatter/gather or not.
3296          */
3297         if (host->flags & SDHCI_USE_ADMA)
3298                 mmc->max_segs = SDHCI_MAX_SEGS;
3299         else if (host->flags & SDHCI_USE_SDMA)
3300                 mmc->max_segs = 1;
3301         else /* PIO */
3302                 mmc->max_segs = SDHCI_MAX_SEGS;
3303
3304         /*
3305          * Maximum number of sectors in one transfer. Limited by SDMA boundary
3306          * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3307          * is less anyway.
3308          */
3309         mmc->max_req_size = 524288;
3310
3311         /*
3312          * Maximum segment size. Could be one segment with the maximum number
3313          * of bytes. When doing hardware scatter/gather, each entry cannot
3314          * be larger than 64 KiB though.
3315          */
3316         if (host->flags & SDHCI_USE_ADMA) {
3317                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3318                         mmc->max_seg_size = 65535;
3319                 else
3320                         mmc->max_seg_size = 65536;
3321         } else {
3322                 mmc->max_seg_size = mmc->max_req_size;
3323         }
3324
3325         /*
3326          * Maximum block size. This varies from controller to controller and
3327          * is specified in the capabilities register.
3328          */
3329         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3330                 mmc->max_blk_size = 2;
3331         } else {
3332                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3333                                 SDHCI_MAX_BLOCK_SHIFT;
3334                 if (mmc->max_blk_size >= 3) {
3335                         pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3336                                 mmc_hostname(mmc));
3337                         mmc->max_blk_size = 0;
3338                 }
3339         }
3340
3341         mmc->max_blk_size = 512 << mmc->max_blk_size;
3342
3343         /*
3344          * Maximum block count.
3345          */
3346         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3347
3348         /*
3349          * Init tasklets.
3350          */
3351         tasklet_init(&host->finish_tasklet,
3352                 sdhci_tasklet_finish, (unsigned long)host);
3353
3354         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3355
3356         init_waitqueue_head(&host->buf_ready_int);
3357
3358         sdhci_init(host, 0);
3359
3360         ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3361                                    IRQF_SHARED, mmc_hostname(mmc), host);
3362         if (ret) {
3363                 pr_err("%s: Failed to request IRQ %d: %d\n",
3364                        mmc_hostname(mmc), host->irq, ret);
3365                 goto untasklet;
3366         }
3367
3368 #ifdef CONFIG_MMC_DEBUG
3369         sdhci_dumpregs(host);
3370 #endif
3371
3372 #ifdef SDHCI_USE_LEDS_CLASS
3373         snprintf(host->led_name, sizeof(host->led_name),
3374                 "%s::", mmc_hostname(mmc));
3375         host->led.name = host->led_name;
3376         host->led.brightness = LED_OFF;
3377         host->led.default_trigger = mmc_hostname(mmc);
3378         host->led.brightness_set = sdhci_led_control;
3379
3380         ret = led_classdev_register(mmc_dev(mmc), &host->led);
3381         if (ret) {
3382                 pr_err("%s: Failed to register LED device: %d\n",
3383                        mmc_hostname(mmc), ret);
3384                 goto reset;
3385         }
3386 #endif
3387
3388         mmiowb();
3389
3390         mmc_add_host(mmc);
3391
3392         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3393                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3394                 (host->flags & SDHCI_USE_ADMA) ?
3395                 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3396                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3397
3398         sdhci_enable_card_detection(host);
3399
3400         return 0;
3401
3402 #ifdef SDHCI_USE_LEDS_CLASS
3403 reset:
3404         sdhci_do_reset(host, SDHCI_RESET_ALL);
3405         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3406         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3407         free_irq(host->irq, host);
3408 #endif
3409 untasklet:
3410         tasklet_kill(&host->finish_tasklet);
3411
3412         return ret;
3413 }
3414
3415 EXPORT_SYMBOL_GPL(sdhci_add_host);
3416
3417 void sdhci_remove_host(struct sdhci_host *host, int dead)
3418 {
3419         struct mmc_host *mmc = host->mmc;
3420         unsigned long flags;
3421
3422         if (dead) {
3423                 spin_lock_irqsave(&host->lock, flags);
3424
3425                 host->flags |= SDHCI_DEVICE_DEAD;
3426
3427                 if (host->mrq) {
3428                         pr_err("%s: Controller removed during "
3429                                 " transfer!\n", mmc_hostname(mmc));
3430
3431                         host->mrq->cmd->error = -ENOMEDIUM;
3432                         tasklet_schedule(&host->finish_tasklet);
3433                 }
3434
3435                 spin_unlock_irqrestore(&host->lock, flags);
3436         }
3437
3438         sdhci_disable_card_detection(host);
3439
3440         mmc_remove_host(mmc);
3441
3442 #ifdef SDHCI_USE_LEDS_CLASS
3443         led_classdev_unregister(&host->led);
3444 #endif
3445
3446         if (!dead)
3447                 sdhci_do_reset(host, SDHCI_RESET_ALL);
3448
3449         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3450         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3451         free_irq(host->irq, host);
3452
3453         del_timer_sync(&host->timer);
3454
3455         tasklet_kill(&host->finish_tasklet);
3456
3457         if (!IS_ERR(mmc->supply.vqmmc))
3458                 regulator_disable(mmc->supply.vqmmc);
3459
3460         if (host->adma_table)
3461                 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3462                                   host->adma_table, host->adma_addr);
3463         kfree(host->align_buffer);
3464
3465         host->adma_table = NULL;
3466         host->align_buffer = NULL;
3467 }
3468
3469 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3470
3471 void sdhci_free_host(struct sdhci_host *host)
3472 {
3473         mmc_free_host(host->mmc);
3474 }
3475
3476 EXPORT_SYMBOL_GPL(sdhci_free_host);
3477
3478 /*****************************************************************************\
3479  *                                                                           *
3480  * Driver init/exit                                                          *
3481  *                                                                           *
3482 \*****************************************************************************/
3483
3484 static int __init sdhci_drv_init(void)
3485 {
3486         pr_info(DRIVER_NAME
3487                 ": Secure Digital Host Controller Interface driver\n");
3488         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3489
3490         return 0;
3491 }
3492
3493 static void __exit sdhci_drv_exit(void)
3494 {
3495 }
3496
3497 module_init(sdhci_drv_init);
3498 module_exit(sdhci_drv_exit);
3499
3500 module_param(debug_quirks, uint, 0444);
3501 module_param(debug_quirks2, uint, 0444);
3502
3503 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3504 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3505 MODULE_LICENSE("GPL");
3506
3507 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3508 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");