2 * Copyright 2011, Marvell Semiconductor Inc.
3 * Lei Wen <leiwen@marvell.com>
5 * SPDX-License-Identifier: GPL-2.0+
7 * Back ported to the 8xx platform (from the 8260 platform) by
8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
18 static void sdhci_reset(struct sdhci_host *host, u8 mask)
20 unsigned long timeout;
24 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
25 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
27 printf("%s: Reset 0x%x never completed.\n",
36 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
39 if (cmd->resp_type & MMC_RSP_136) {
40 /* CRC is stripped so we need to do some shifting. */
41 for (i = 0; i < 4; i++) {
42 cmd->response[i] = sdhci_readl(host,
43 SDHCI_RESPONSE + (3-i)*4) << 8;
45 cmd->response[i] |= sdhci_readb(host,
46 SDHCI_RESPONSE + (3-i)*4-1);
49 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
53 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
57 for (i = 0; i < data->blocksize; i += 4) {
58 offs = data->dest + i;
59 if (data->flags == MMC_DATA_READ)
60 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
62 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
66 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
67 unsigned int start_addr)
69 unsigned int stat, rdy, mask, timeout, block = 0;
70 #ifdef CONFIG_MMC_SDMA
72 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
73 ctrl &= ~SDHCI_CTRL_DMA_MASK;
74 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
78 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
79 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
81 stat = sdhci_readl(host, SDHCI_INT_STATUS);
82 if (stat & SDHCI_INT_ERROR) {
83 printf("%s: Error detected in status(0x%X)!\n",
88 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
90 sdhci_writel(host, rdy, SDHCI_INT_STATUS);
91 sdhci_transfer_pio(host, data);
92 data->dest += data->blocksize;
93 if (++block >= data->blocks)
96 #ifdef CONFIG_MMC_SDMA
97 if (stat & SDHCI_INT_DMA_END) {
98 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
99 start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
100 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
101 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
107 printf("%s: Transfer data timeout\n", __func__);
110 } while (!(stat & SDHCI_INT_DATA_END));
115 * No command will be sent by driver if card is busy, so driver must wait
116 * for card ready state.
117 * Every time when card is busy after timeout then (last) timeout value will be
118 * increased twice but only if it doesn't exceed global defined maximum.
119 * Each function call will use last timeout value. Max timeout can be redefined
120 * in board config file.
122 #ifndef CONFIG_SDHCI_CMD_MAX_TIMEOUT
123 #define CONFIG_SDHCI_CMD_MAX_TIMEOUT 3200
125 #define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT 100
127 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
128 struct mmc_data *data)
130 struct sdhci_host *host = mmc->priv;
131 unsigned int stat = 0;
133 int trans_bytes = 0, is_aligned = 1;
134 u32 mask, flags, mode;
135 unsigned int time = 0, start_addr = 0;
136 unsigned int retry = 10000;
137 int mmc_dev = mmc->block_dev.dev;
139 /* Timeout unit - ms */
140 static unsigned int cmd_timeout = CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT;
142 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
143 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
145 /* We shouldn't wait for data inihibit for stop commands, even
146 though they might use busy signaling */
147 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
148 mask &= ~SDHCI_DATA_INHIBIT;
150 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
151 if (time >= cmd_timeout) {
152 printf("%s: MMC: %d busy ", __func__, mmc_dev);
153 if (2 * cmd_timeout <= CONFIG_SDHCI_CMD_MAX_TIMEOUT) {
154 cmd_timeout += cmd_timeout;
155 printf("timeout increasing to: %u ms.\n",
166 mask = SDHCI_INT_RESPONSE;
167 if (!(cmd->resp_type & MMC_RSP_PRESENT))
168 flags = SDHCI_CMD_RESP_NONE;
169 else if (cmd->resp_type & MMC_RSP_136)
170 flags = SDHCI_CMD_RESP_LONG;
171 else if (cmd->resp_type & MMC_RSP_BUSY) {
172 flags = SDHCI_CMD_RESP_SHORT_BUSY;
173 mask |= SDHCI_INT_DATA_END;
175 flags = SDHCI_CMD_RESP_SHORT;
177 if (cmd->resp_type & MMC_RSP_CRC)
178 flags |= SDHCI_CMD_CRC;
179 if (cmd->resp_type & MMC_RSP_OPCODE)
180 flags |= SDHCI_CMD_INDEX;
182 flags |= SDHCI_CMD_DATA;
184 /* Set Transfer mode regarding to data flag */
186 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
187 mode = SDHCI_TRNS_BLK_CNT_EN;
188 trans_bytes = data->blocks * data->blocksize;
189 if (data->blocks > 1)
190 mode |= SDHCI_TRNS_MULTI;
192 if (data->flags == MMC_DATA_READ)
193 mode |= SDHCI_TRNS_READ;
195 #ifdef CONFIG_MMC_SDMA
196 if (data->flags == MMC_DATA_READ)
197 start_addr = (unsigned int)data->dest;
199 start_addr = (unsigned int)data->src;
200 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
201 (start_addr & 0x7) != 0x0) {
203 start_addr = (unsigned int)aligned_buffer;
204 if (data->flags != MMC_DATA_READ)
205 memcpy(aligned_buffer, data->src, trans_bytes);
208 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
209 mode |= SDHCI_TRNS_DMA;
211 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
214 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
215 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
218 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
219 #ifdef CONFIG_MMC_SDMA
220 flush_cache(start_addr, trans_bytes);
222 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
224 stat = sdhci_readl(host, SDHCI_INT_STATUS);
225 if (stat & SDHCI_INT_ERROR)
229 } while ((stat & mask) != mask);
232 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B)
235 printf("%s: Timeout for status update!\n", __func__);
240 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
241 sdhci_cmd_done(host, cmd);
242 sdhci_writel(host, mask, SDHCI_INT_STATUS);
247 ret = sdhci_transfer_data(host, data, start_addr);
249 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
252 stat = sdhci_readl(host, SDHCI_INT_STATUS);
253 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
255 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
256 !is_aligned && (data->flags == MMC_DATA_READ))
257 memcpy(data->dest, aligned_buffer, trans_bytes);
261 sdhci_reset(host, SDHCI_RESET_CMD);
262 sdhci_reset(host, SDHCI_RESET_DATA);
263 if (stat & SDHCI_INT_TIMEOUT)
269 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
271 struct sdhci_host *host = mmc->priv;
272 unsigned int div, clk, timeout;
274 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
279 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
280 /* Version 3.00 divisors must be a multiple of 2. */
281 if (mmc->cfg->f_max <= clock)
284 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
285 if ((mmc->cfg->f_max / div) <= clock)
290 /* Version 2.00 divisors must be a power of 2. */
291 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
292 if ((mmc->cfg->f_max / div) <= clock)
299 host->set_clock(host->index, div);
301 clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
302 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
303 << SDHCI_DIVIDER_HI_SHIFT;
304 clk |= SDHCI_CLOCK_INT_EN;
305 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
309 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
310 & SDHCI_CLOCK_INT_STABLE)) {
312 printf("%s: Internal clock never stabilised.\n",
320 clk |= SDHCI_CLOCK_CARD_EN;
321 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
325 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
329 if (power != (unsigned short)-1) {
330 switch (1 << power) {
331 case MMC_VDD_165_195:
332 pwr = SDHCI_POWER_180;
336 pwr = SDHCI_POWER_300;
340 pwr = SDHCI_POWER_330;
346 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
350 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
351 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
353 pwr |= SDHCI_POWER_ON;
355 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
358 static void sdhci_set_ios(struct mmc *mmc)
361 struct sdhci_host *host = mmc->priv;
363 if (host->set_control_reg)
364 host->set_control_reg(host);
366 if (mmc->clock != host->clock)
367 sdhci_set_clock(mmc, mmc->clock);
370 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
371 if (mmc->bus_width == 8) {
372 ctrl &= ~SDHCI_CTRL_4BITBUS;
373 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
374 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
375 ctrl |= SDHCI_CTRL_8BITBUS;
377 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
378 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
379 ctrl &= ~SDHCI_CTRL_8BITBUS;
380 if (mmc->bus_width == 4)
381 ctrl |= SDHCI_CTRL_4BITBUS;
383 ctrl &= ~SDHCI_CTRL_4BITBUS;
386 if (mmc->clock > 26000000)
387 ctrl |= SDHCI_CTRL_HISPD;
389 ctrl &= ~SDHCI_CTRL_HISPD;
391 if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
392 ctrl &= ~SDHCI_CTRL_HISPD;
394 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
397 static int sdhci_init(struct mmc *mmc)
399 struct sdhci_host *host = mmc->priv;
401 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
402 aligned_buffer = memalign(8, 512*1024);
403 if (!aligned_buffer) {
404 printf("%s: Aligned buffer alloc failed!!!\n",
410 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
412 if (host->quirks & SDHCI_QUIRK_NO_CD) {
415 sdhci_writeb(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST,
418 status = sdhci_readl(host, SDHCI_PRESENT_STATE);
419 while ((!(status & SDHCI_CARD_PRESENT)) ||
420 (!(status & SDHCI_CARD_STATE_STABLE)) ||
421 (!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
422 status = sdhci_readl(host, SDHCI_PRESENT_STATE);
425 /* Enable only interrupts served by the SD controller */
426 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
428 /* Mask all sdhci interrupt sources */
429 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
435 static const struct mmc_ops sdhci_ops = {
436 .send_cmd = sdhci_send_command,
437 .set_ios = sdhci_set_ios,
441 int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
445 host->cfg.name = host->name;
446 host->cfg.ops = &sdhci_ops;
448 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
449 #ifdef CONFIG_MMC_SDMA
450 if (!(caps & SDHCI_CAN_DO_SDMA)) {
451 printf("%s: Your controller doesn't support SDMA!!\n",
458 host->cfg.f_max = max_clk;
460 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
461 host->cfg.f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK)
462 >> SDHCI_CLOCK_BASE_SHIFT;
464 host->cfg.f_max = (caps & SDHCI_CLOCK_BASE_MASK)
465 >> SDHCI_CLOCK_BASE_SHIFT;
466 host->cfg.f_max *= 1000000;
468 if (host->cfg.f_max == 0) {
469 printf("%s: Hardware doesn't specify base clock frequency\n",
474 host->cfg.f_min = min_clk;
476 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
477 host->cfg.f_min = host->cfg.f_max /
478 SDHCI_MAX_DIV_SPEC_300;
480 host->cfg.f_min = host->cfg.f_max /
481 SDHCI_MAX_DIV_SPEC_200;
484 host->cfg.voltages = 0;
485 if (caps & SDHCI_CAN_VDD_330)
486 host->cfg.voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
487 if (caps & SDHCI_CAN_VDD_300)
488 host->cfg.voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
489 if (caps & SDHCI_CAN_VDD_180)
490 host->cfg.voltages |= MMC_VDD_165_195;
492 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
493 host->cfg.voltages |= host->voltages;
495 host->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
496 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
497 if (caps & SDHCI_CAN_DO_8BIT)
498 host->cfg.host_caps |= MMC_MODE_8BIT;
501 host->cfg.host_caps |= host->host_caps;
503 host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
505 sdhci_reset(host, SDHCI_RESET_ALL);
507 host->mmc = mmc_create(&host->cfg, host);
508 if (host->mmc == NULL) {
509 printf("%s: mmc create fail!\n", __func__);