drivers/mtd/nand/gpmi-nfc/hal-mx50.c

   1 /*
   2  * Freescale GPMI NFC NAND Flash Driver
   3  *
   4  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   5  * Copyright (C) 2008 Embedded Alley Solutions, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  20  */
  21 #include "gpmi-nfc.h"
  22 #include "gpmi-regs-mx50.h"
  23 #include "bch-regs-mx50.h"
  24
  25 #define FEATURE_SIZE            4       /* p1, p2, p3, p4 */
  26 #define NAND_CMD_SET_FEATURE    0xef
  27
  28 /*
  29  * How many clocks do we need in low power mode?
  30  * We try to list them :
  31  *      GMPI            : gpmi_apb_clk, gpmi_io_clk
  32  *      BCH             : bch_clk, bch_apb_clk
  33  *      DMA(RAM)        : apbh_dma_clk, ddr_clk(RAM), ahb_max_clk(RAM)
  34  *                        (APBHDMA fetches DMA descriptors from DDR
  35  *                         through AHB-MAX/PL301)
  36  *      NAND            :
  37  *      ONFI NAND       : pll1_main_clk
  38  */
  39 static struct clk *ddr_clk;
  40 static struct clk *ahb_max_clk;
  41
  42 static void setup_ddr_timing_onfi(struct gpmi_nfc_data *this)
  43 {
  44         uint32_t value;
  45         struct resources  *resources = &this->resources;
  46
  47         /* set timing 2 register */
  48         value = BF_GPMI_TIMING2_DATA_PAUSE(0x6)
  49                 | BF_GPMI_TIMING2_CMDADD_PAUSE(0x4)
  50                 | BF_GPMI_TIMING2_POSTAMBLE_DELAY(0x2)
  51                 | BF_GPMI_TIMING2_PREAMBLE_DELAY(0x4)
  52                 | BF_GPMI_TIMING2_CE_DELAY(0x2)
  53                 | BF_GPMI_TIMING2_READ_LATENCY(0x2);
  54
  55         __raw_writel(value, resources->gpmi_regs + HW_GPMI_TIMING2);
  56
  57         /* set timing 1 register */
  58         __raw_writel(BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(0x500),
  59                         resources->gpmi_regs + HW_GPMI_TIMING1);
  60
  61         /* Put GPMI in NAND mode, disable device reset, and make certain
  62            IRQRDY polarity is active high. */
  63         value = BV_GPMI_CTRL1_GPMI_MODE__NAND
  64                 | BM_GPMI_CTRL1_GANGED_RDYBUSY
  65                 | BF_GPMI_CTRL1_WRN_DLY_SEL(0x3)
  66                 | (BV_GPMI_CTRL1_DEV_RESET__DISABLED << 3)
  67                 | (BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH << 2);
  68
  69         __raw_writel(value, resources->gpmi_regs + HW_GPMI_CTRL1_SET);
  70 }
  71
  72 /* This must be called in the context of enabling necessary clocks */
  73 static void common_ddr_init(struct resources *resources)
  74 {
  75         uint32_t value;
  76
  77         /* [6] enable both write & read DDR DLLs */
  78         value = BM_GPMI_READ_DDR_DLL_CTRL_REFCLK_ON |
  79                 BM_GPMI_READ_DDR_DLL_CTRL_ENABLE |
  80                 BF_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(0x2) |
  81                 BF_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(0x7);
  82
  83         __raw_writel(value, resources->gpmi_regs + HW_GPMI_READ_DDR_DLL_CTRL);
  84
  85         /* [7] reset read */
  86         __raw_writel(value | BM_GPMI_READ_DDR_DLL_CTRL_RESET,
  87                         resources->gpmi_regs + HW_GPMI_READ_DDR_DLL_CTRL);
  88         value = value & ~BM_GPMI_READ_DDR_DLL_CTRL_RESET;
  89         __raw_writel(value, resources->gpmi_regs + HW_GPMI_READ_DDR_DLL_CTRL);
  90
  91         value = BM_GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON |
  92                 BM_GPMI_WRITE_DDR_DLL_CTRL_ENABLE    |
  93                 BF_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT(0x2) |
  94                 BF_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET(0x7) ,
  95
  96         __raw_writel(value, resources->gpmi_regs + HW_GPMI_WRITE_DDR_DLL_CTRL);
  97
  98         /* [8] reset write */
  99         __raw_writel(value | BM_GPMI_WRITE_DDR_DLL_CTRL_RESET,
 100                         resources->gpmi_regs + HW_GPMI_WRITE_DDR_DLL_CTRL);
 101         __raw_writel(value, resources->gpmi_regs + HW_GPMI_WRITE_DDR_DLL_CTRL);
 102
 103         /* [9] wait for locks for read and write  */
 104         do {
 105                 uint32_t read_status, write_status;
 106                 uint32_t r_mask, w_mask;
 107
 108                 read_status = __raw_readl(resources->gpmi_regs
 109                                         + HW_GPMI_READ_DDR_DLL_STS);
 110                 write_status = __raw_readl(resources->gpmi_regs
 111                                         + HW_GPMI_WRITE_DDR_DLL_STS);
 112
 113                 r_mask = (BM_GPMI_READ_DDR_DLL_STS_REF_LOCK |
 114                                 BM_GPMI_READ_DDR_DLL_STS_SLV_LOCK);
 115                 w_mask = (BM_GPMI_WRITE_DDR_DLL_STS_REF_LOCK |
 116                                 BM_GPMI_WRITE_DDR_DLL_STS_SLV_LOCK);
 117
 118                 if (((read_status & r_mask) == r_mask)
 119                         && ((write_status & w_mask) == w_mask))
 120                                 break;
 121         } while (1);
 122
 123         /* [10] force update of read/write */
 124         value = __raw_readl(resources->gpmi_regs + HW_GPMI_READ_DDR_DLL_CTRL);
 125         __raw_writel(value | BM_GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD,
 126                         resources->gpmi_regs + HW_GPMI_READ_DDR_DLL_CTRL);
 127         __raw_writel(value, resources->gpmi_regs + HW_GPMI_READ_DDR_DLL_CTRL);
 128
 129         value = __raw_readl(resources->gpmi_regs + HW_GPMI_WRITE_DDR_DLL_CTRL);
 130         __raw_writel(value | BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD,
 131                         resources->gpmi_regs + HW_GPMI_WRITE_DDR_DLL_CTRL);
 132         __raw_writel(value, resources->gpmi_regs + HW_GPMI_WRITE_DDR_DLL_CTRL);
 133
 134         /* [11] set gate update */
 135         value = __raw_readl(resources->gpmi_regs + HW_GPMI_READ_DDR_DLL_CTRL);
 136         value |= BM_GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE;
 137         __raw_writel(value, resources->gpmi_regs + HW_GPMI_READ_DDR_DLL_CTRL);
 138
 139         value = __raw_readl(resources->gpmi_regs + HW_GPMI_WRITE_DDR_DLL_CTRL);
 140         value |= BM_GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE;
 141         __raw_writel(value, resources->gpmi_regs + HW_GPMI_WRITE_DDR_DLL_CTRL);
 142 }
 143
 144 static int enable_ddr_onfi(struct gpmi_nfc_data *this)
 145 {
 146         struct resources  *resources = &this->resources;
 147         struct mil *mil = &this->mil;
 148         struct nand_chip *nand = &this->mil.nand;
 149         struct mtd_info  *mtd = &mil->mtd;
 150         int saved_chip_number = 0;
 151         uint8_t device_feature[FEATURE_SIZE];
 152         int mode = 0;/* there is 5 mode available, default is 0 */
 153
 154         saved_chip_number = mil->current_chip;
 155         nand->select_chip(mtd, 0);
 156
 157         /* [0] set proper timing */
 158         __raw_writel(BF_GPMI_TIMING0_ADDRESS_SETUP(0x1)
 159                         | BF_GPMI_TIMING0_DATA_HOLD(0x3)
 160                         | BF_GPMI_TIMING0_DATA_SETUP(0x3),
 161                         resources->gpmi_regs + HW_GPMI_TIMING0);
 162
 163         /* [1] send SET FEATURE commond to NAND */
 164         memset(device_feature, 0, sizeof(device_feature));
 165         device_feature[0] = (0x1 << 4) | (mode & 0x7);
 166
 167         nand->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
 168         nand->cmdfunc(mtd, NAND_CMD_SET_FEATURE, 1, -1);
 169         nand->write_buf(mtd, device_feature, FEATURE_SIZE);
 170
 171         /* [2] set clk divider */
 172         __raw_writel(BM_GPMI_CTRL1_GPMI_CLK_DIV2_EN,
 173                         resources->gpmi_regs + HW_GPMI_CTRL1_SET);
 174
 175         /* [3] about the clock, pay attention! */
 176         nand->select_chip(mtd, saved_chip_number);
 177         {
 178                 struct clk *pll1;
 179                 pll1 = clk_get(NULL, "pll1_main_clk");
 180                 if (IS_ERR(pll1)) {
 181                         printk(KERN_INFO "No PLL1 clock\n");
 182                         return -EINVAL;
 183                 }
 184                 clk_set_parent(resources->clock, pll1);
 185                 clk_set_rate(resources->clock, 20000000);
 186         }
 187         nand->select_chip(mtd, 0);
 188
 189         /* [4] setup timing */
 190         setup_ddr_timing_onfi(this);
 191
 192         /* [5] set to SYNC mode */
 193         __raw_writel(BM_GPMI_CTRL1_TOGGLE_MODE,
 194                             resources->gpmi_regs + HW_GPMI_CTRL1_CLR);
 195         __raw_writel(BM_GPMI_CTRL1_SSYNCMODE | BM_GPMI_CTRL1_GANGED_RDYBUSY,
 196                             resources->gpmi_regs + HW_GPMI_CTRL1_SET);
 197
 198         /* common DDR initialization */
 199         common_ddr_init(resources);
 200
 201         nand->select_chip(mtd, saved_chip_number);
 202
 203         printk(KERN_INFO "Micron ONFI NAND enters synchronous mode %d\n", mode);
 204         return 0;
 205 }
 206
 207 static void setup_ddr_timing_toggle(struct gpmi_nfc_data *this)
 208 {
 209         uint32_t value;
 210         struct resources  *resources = &this->resources;
 211
 212         /* set timing 2 register */
 213         value = BF_GPMI_TIMING2_DATA_PAUSE(0x6)
 214                 | BF_GPMI_TIMING2_CMDADD_PAUSE(0x4)
 215                 | BF_GPMI_TIMING2_POSTAMBLE_DELAY(0x3)
 216                 | BF_GPMI_TIMING2_PREAMBLE_DELAY(0x2)
 217                 | BF_GPMI_TIMING2_CE_DELAY(0x2)
 218                 | BF_GPMI_TIMING2_READ_LATENCY(0x2);
 219
 220         __raw_writel(value, resources->gpmi_regs + HW_GPMI_TIMING2);
 221
 222         /* set timing 1 register */
 223         __raw_writel(BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(0x500),
 224                         resources->gpmi_regs + HW_GPMI_TIMING1);
 225
 226         /* Put GPMI in NAND mode, disable device reset, and make certain
 227            IRQRDY polarity is active high. */
 228         value = BV_GPMI_CTRL1_GPMI_MODE__NAND
 229                 | BM_GPMI_CTRL1_GANGED_RDYBUSY
 230                 | (BV_GPMI_CTRL1_DEV_RESET__DISABLED << 3)
 231                 | (BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH << 2);
 232
 233         __raw_writel(value, resources->gpmi_regs + HW_GPMI_CTRL1_SET);
 234 }
 235
 236 static int enable_ddr_toggle(struct gpmi_nfc_data *this)
 237 {
 238         struct resources  *resources = &this->resources;
 239         struct mil *mil = &this->mil;
 240         struct nand_chip *nand = &this->mil.nand;
 241         struct mtd_info  *mtd = &mil->mtd;
 242         int saved_chip_number = mil->current_chip;
 243
 244         nand->select_chip(mtd, 0);
 245
 246         /* [0] set proper timing */
 247         __raw_writel(BF_GPMI_TIMING0_ADDRESS_SETUP(0x5)
 248                         | BF_GPMI_TIMING0_DATA_HOLD(0xa)
 249                         | BF_GPMI_TIMING0_DATA_SETUP(0xa),
 250                         resources->gpmi_regs + HW_GPMI_TIMING0);
 251
 252         /* [2] set clk divider */
 253         __raw_writel(BM_GPMI_CTRL1_GPMI_CLK_DIV2_EN,
 254                         resources->gpmi_regs + HW_GPMI_CTRL1_SET);
 255
 256         /* [3] about the clock, pay attention! */
 257         nand->select_chip(mtd, saved_chip_number);
 258         {
 259                 struct clk *pll1;
 260                 unsigned long rate;
 261
 262                 pll1 = clk_get(NULL, "pll1_main_clk");
 263                 if (IS_ERR(pll1)) {
 264                         printk(KERN_INFO "No PLL1 clock\n");
 265                         return -EINVAL;
 266                 }
 267
 268                 /* toggle nand : 133/66 MHz */
 269                 rate = 33000000;
 270                 clk_set_parent(resources->clock, pll1);
 271                 clk_set_rate(resources->clock, rate);
 272         }
 273         nand->select_chip(mtd, 0);
 274
 275         /* [4] setup timing */
 276         setup_ddr_timing_toggle(this);
 277
 278         /* [5] set to TOGGLE mode */
 279         __raw_writel(BM_GPMI_CTRL1_SSYNCMODE,
 280                             resources->gpmi_regs + HW_GPMI_CTRL1_CLR);
 281         __raw_writel(BM_GPMI_CTRL1_TOGGLE_MODE | BM_GPMI_CTRL1_GANGED_RDYBUSY,
 282                             resources->gpmi_regs + HW_GPMI_CTRL1_SET);
 283
 284         /* common DDR initialization */
 285         common_ddr_init(resources);
 286
 287         nand->select_chip(mtd, saved_chip_number);
 288
 289         printk(KERN_INFO "-- Sumsung TOGGLE NAND is enabled now. --\n");
 290         return 0;
 291 }
 292
 293 static inline bool is_board_support_ddr(struct gpmi_nfc_data *this)
 294 {
 295         /* Only arm2 board supports the DDR, the rdp board does not. */
 296         return false;
 297 }
 298
 299 /* To check if we need to initialize something else*/
 300 static int extra_init(struct gpmi_nfc_data *this)
 301 {
 302         /* mx6q do not need the extra clocks, while the mx50 needs. */
 303         if (GPMI_IS_MX6Q(this))
 304                 return 0;
 305
 306         ddr_clk = clk_get(NULL, "ddr_clk");
 307         if (IS_ERR(ddr_clk)) {
 308                 printk(KERN_ERR "The ddr clock is gone!");
 309                 ddr_clk = NULL;
 310                 return -ENOENT;
 311         }
 312
 313         ahb_max_clk = clk_get(NULL, "ahb_max_clk");
 314         if (IS_ERR(ahb_max_clk)) {
 315                 printk(KERN_ERR "The APBH_DMA clock is gone!");
 316                 ahb_max_clk = NULL;
 317                 return -ENOENT;
 318         }
 319
 320         if (is_board_support_ddr(this)) {
 321                 if (0)
 322                         return enable_ddr_onfi(this);
 323                 if (0)
 324                         return enable_ddr_toggle(this);
 325         }
 326         return 0;
 327 }
 328
 329 /**
 330  * init() - Initializes the NFC hardware.
 331  *
 332  * @this:  Per-device data.
 333  */
 334 static int init(struct gpmi_nfc_data *this)
 335 {
 336         struct resources  *resources = &this->resources;
 337
 338         /* Enable the clock. */
 339         clk_enable(resources->clock);
 340
 341         /* Reset the GPMI block. */
 342         mxs_reset_block(resources->gpmi_regs + HW_GPMI_CTRL0, true);
 343
 344         /* Choose NAND mode. */
 345         __raw_writel(BM_GPMI_CTRL1_GPMI_MODE,
 346                                 resources->gpmi_regs + HW_GPMI_CTRL1_CLR);
 347
 348         /* Set the IRQ polarity. */
 349         __raw_writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
 350                                 resources->gpmi_regs + HW_GPMI_CTRL1_SET);
 351
 352         /* Disable write protection. */
 353         __raw_writel(BM_GPMI_CTRL1_DEV_RESET,
 354                                 resources->gpmi_regs + HW_GPMI_CTRL1_SET);
 355
 356         /* Select BCH ECC. */
 357         __raw_writel(BM_GPMI_CTRL1_BCH_MODE,
 358                                 resources->gpmi_regs + HW_GPMI_CTRL1_SET);
 359
 360         /* Disable the clock. */
 361         clk_disable(resources->clock);
 362
 363         return 0;
 364 }
 365
 366 /**
 367  * set_geometry() - Configures the NFC geometry.
 368  *
 369  * @this:  Per-device data.
 370  */
 371 static int set_geometry(struct gpmi_nfc_data *this)
 372 {
 373         struct resources     *resources = &this->resources;
 374         struct nfc_geometry  *nfc       = &this->nfc_geometry;
 375         unsigned int         block_count;
 376         unsigned int         block_size;
 377         unsigned int         metadata_size;
 378         unsigned int         ecc_strength;
 379         unsigned int         page_size;
 380         uint32_t                value;
 381
 382         /* We make the abstract choices in a common function. */
 383         if (common_nfc_set_geometry(this))
 384                 return !0;
 385
 386         /* Translate the abstract choices into register fields. */
 387         block_count   = nfc->ecc_chunk_count - 1;
 388         block_size    = nfc->ecc_chunk_size_in_bytes >> 2;
 389         metadata_size = nfc->metadata_size_in_bytes;
 390         ecc_strength  = nfc->ecc_strength >> 1;
 391         page_size     = nfc->page_size_in_bytes;
 392
 393         /* Enable the clock. */
 394         clk_enable(resources->clock);
 395
 396         /*
 397          * Reset the BCH block. Notice that we pass in true for the just_enable
 398          * flag. This is because the soft reset for the version 0 BCH block
 399          * doesn't work and the version 1 BCH block is similar enough that we
 400          * suspect the same (though this has not been officially tested). If you
 401          * try to soft reset a version 0 BCH block, it becomes unusable until
 402          * the next hard reset.
 403          */
 404         mxs_reset_block(resources->bch_regs, false);
 405
 406         /* Configure layout 0. */
 407         value = BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count)     |
 408                 BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size) |
 409                 BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength)       |
 410                 BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size);
 411         if (is_ddr_nand(this))
 412                 value |= BM_BCH_FLASH0LAYOUT0_GF13_0_GF14_1;
 413
 414         __raw_writel(value, resources->bch_regs + HW_BCH_FLASH0LAYOUT0);
 415
 416         value = BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size)   |
 417                 BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength)     |
 418                 BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size);
 419         if (is_ddr_nand(this))
 420                 value |= BM_BCH_FLASH0LAYOUT1_GF13_0_GF14_1;
 421
 422         __raw_writel(value, resources->bch_regs + HW_BCH_FLASH0LAYOUT1);
 423
 424         /* Set *all* chip selects to use layout 0. */
 425         __raw_writel(0, resources->bch_regs + HW_BCH_LAYOUTSELECT);
 426
 427         /* Enable interrupts. */
 428         __raw_writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
 429                                 resources->bch_regs + HW_BCH_CTRL_SET);
 430
 431         /* Disable the clock. */
 432         clk_disable(resources->clock);
 433
 434         return 0;
 435 }
 436
 437 /**
 438  * set_timing() - Configures the NFC timing.
 439  *
 440  * @this:    Per-device data.
 441  * @timing:  The timing of interest.
 442  */
 443 static int set_timing(struct gpmi_nfc_data *this,
 444                         const struct nand_timing *timing)
 445 {
 446         struct nfc_hal *nfc = this->nfc;
 447
 448         /* Accept the new timing. */
 449         nfc->timing = *timing;
 450         return 0;
 451 }
 452
 453 /**
 454  * get_timing() - Retrieves the NFC hardware timing.
 455  *
 456  * @this:                    Per-device data.
 457  * @clock_frequency_in_hz:   The clock frequency, in Hz, during the current
 458  *                           I/O transaction. If no I/O transaction is in
 459  *                           progress, this is the clock frequency during the
 460  *                           most recent I/O transaction.
 461  * @hardware_timing:         The hardware timing configuration in effect during
 462  *                           the current I/O transaction. If no I/O transaction
 463  *                           is in progress, this is the hardware timing
 464  *                           configuration during the most recent I/O
 465  *                           transaction.
 466  */
 467 static void get_timing(struct gpmi_nfc_data *this,
 468                         unsigned long *clock_frequency_in_hz,
 469                         struct gpmi_nfc_hardware_timing *hardware_timing)
 470 {
 471         struct resources                 *resources = &this->resources;
 472         struct nfc_hal                   *nfc       =  this->nfc;
 473         unsigned char                    *gpmi_regs = resources->gpmi_regs;
 474         uint32_t                         register_image;
 475
 476         /* Return the clock frequency. */
 477         *clock_frequency_in_hz = nfc->clock_frequency_in_hz;
 478
 479         /* We'll be reading the hardware, so let's enable the clock. */
 480         clk_enable(resources->clock);
 481
 482         /* Retrieve the hardware timing. */
 483         register_image = __raw_readl(gpmi_regs + HW_GPMI_TIMING0);
 484
 485         hardware_timing->data_setup_in_cycles =
 486                 (register_image & BM_GPMI_TIMING0_DATA_SETUP) >>
 487                                                 BP_GPMI_TIMING0_DATA_SETUP;
 488
 489         hardware_timing->data_hold_in_cycles =
 490                 (register_image & BM_GPMI_TIMING0_DATA_HOLD) >>
 491                                                 BP_GPMI_TIMING0_DATA_HOLD;
 492
 493         hardware_timing->address_setup_in_cycles =
 494                 (register_image & BM_GPMI_TIMING0_ADDRESS_SETUP) >>
 495                                                 BP_GPMI_TIMING0_ADDRESS_SETUP;
 496
 497         register_image = __raw_readl(gpmi_regs + HW_GPMI_CTRL1);
 498
 499         hardware_timing->use_half_periods =
 500                 (register_image & BM_GPMI_CTRL1_HALF_PERIOD) >>
 501                                                 BP_GPMI_CTRL1_HALF_PERIOD;
 502
 503         hardware_timing->sample_delay_factor =
 504                 (register_image & BM_GPMI_CTRL1_RDN_DELAY) >>
 505                                                 BP_GPMI_CTRL1_RDN_DELAY;
 506
 507         /* We're done reading the hardware, so disable the clock. */
 508         clk_disable(resources->clock);
 509 }
 510
 511 static void exit(struct gpmi_nfc_data *this)
 512 {
 513 }
 514
 515 static void begin(struct gpmi_nfc_data *this)
 516 {
 517         struct resources                 *resources = &this->resources;
 518         struct nfc_hal                   *nfc       =  this->nfc;
 519         struct gpmi_nfc_hardware_timing  hw;
 520
 521         /* Enable the clock. */
 522         if (ddr_clk)
 523                 clk_enable(ddr_clk);
 524         if (ahb_max_clk)
 525                 clk_enable(ahb_max_clk);
 526         clk_enable(resources->clock);
 527
 528         /* Get the timing information we need. */
 529         nfc->clock_frequency_in_hz = clk_get_rate(resources->clock);
 530         gpmi_nfc_compute_hardware_timing(this, &hw);
 531
 532         /* Apply the hardware timing. */
 533
 534         /* Coming soon - the clock handling code isn't ready yet. */
 535
 536 }
 537
 538 /**
 539  * end() - End NFC I/O.
 540  *
 541  * @this:  Per-device data.
 542  */
 543 static void end(struct gpmi_nfc_data *this)
 544 {
 545         struct resources  *resources = &this->resources;
 546
 547         clk_disable(resources->clock);
 548         if (ahb_max_clk)
 549                 clk_disable(ahb_max_clk);
 550         if (ddr_clk)
 551                 clk_disable(ddr_clk);
 552 }
 553
 554 /**
 555  * clear_bch() - Clears a BCH interrupt.
 556  *
 557  * @this:  Per-device data.
 558  */
 559 static void clear_bch(struct gpmi_nfc_data *this)
 560 {
 561         struct resources  *resources = &this->resources;
 562         __raw_writel(BM_BCH_CTRL_COMPLETE_IRQ,
 563                                 resources->bch_regs + HW_BCH_CTRL_CLR);
 564 }
 565
 566 /**
 567  * is_ready() - Returns the ready/busy status of the given chip.
 568  *
 569  * @this:  Per-device data.
 570  * @chip:  The chip of interest.
 571  */
 572 static int is_ready(struct gpmi_nfc_data *this, unsigned chip)
 573 {
 574         struct resources  *resources = &this->resources;
 575         uint32_t          mask;
 576         uint32_t          register_image;
 577
 578         /* Extract and return the status. */
 579         mask = BF_GPMI_STAT_READY_BUSY(1 << 0);
 580         register_image = __raw_readl(resources->gpmi_regs + HW_GPMI_STAT);
 581         return !!(register_image & mask);
 582 }
 583
 584 /* The DMA may need the NAND-LOCK bit set to work properly. */
 585 static int send_command(struct gpmi_nfc_data *this)
 586 {
 587         struct dma_chan *channel = get_dma_chan(this);
 588         struct mil *mil = &this->mil;
 589         struct dma_async_tx_descriptor *desc;
 590         struct scatterlist *sgl;
 591         u32 pio[3];
 592
 593         /* [1] send out the PIO words */
 594         pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__WRITE)
 595                 | BM_GPMI_CTRL0_WORD_LENGTH
 596                 | BF_GPMI_CTRL0_CS(mil->current_chip)
 597                 | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_CLE)
 598                 | BM_GPMI_CTRL0_ADDRESS_INCREMENT
 599                 | BF_GPMI_CTRL0_XFER_COUNT(mil->command_length);
 600         pio[1] = pio[2] = 0;
 601         desc = channel->device->device_prep_slave_sg(channel,
 602                                         (struct scatterlist *)pio,
 603                                         ARRAY_SIZE(pio), DMA_NONE, 0);
 604         if (!desc) {
 605                 pr_info("step 1 error");
 606                 return -1;
 607         }
 608
 609         /* [2] send out the COMMAND + ADDRESS string stored in @buffer */
 610         sgl = &mil->cmd_sgl;
 611
 612         sg_init_one(sgl, mil->cmd_buffer, mil->command_length);
 613         dma_map_sg(this->dev, sgl, 1, DMA_TO_DEVICE);
 614         desc = channel->device->device_prep_slave_sg(channel,
 615                                         sgl, 1, DMA_TO_DEVICE, 1);
 616         if (!desc) {
 617                 pr_info("error");
 618                 return -1;
 619         }
 620
 621         /* [3] submit the DMA */
 622         this->dma_type = DMA_FOR_COMMAND;
 623         start_dma_without_bch_irq(this, desc);
 624         return 0;
 625 }
 626
 627 static int send_data(struct gpmi_nfc_data *this)
 628 {
 629         struct dma_async_tx_descriptor *desc;
 630         struct dma_chan *channel = get_dma_chan(this);
 631         struct mil *mil = &this->mil;
 632         uint32_t command_mode;
 633         uint32_t address;
 634         u32 pio[2];
 635
 636         /* [1] PIO */
 637         command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
 638         address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
 639
 640         pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
 641                 | BM_GPMI_CTRL0_WORD_LENGTH
 642                 | BF_GPMI_CTRL0_CS(mil->current_chip)
 643                 | BF_GPMI_CTRL0_ADDRESS(address)
 644                 | BF_GPMI_CTRL0_XFER_COUNT(mil->upper_len);
 645         pio[1] = 0;
 646         desc = channel->device->device_prep_slave_sg(channel,
 647                                         (struct scatterlist *)pio,
 648                                         ARRAY_SIZE(pio), DMA_NONE, 0);
 649         if (!desc) {
 650                 pr_info("step 1 error");
 651                 return -1;
 652         }
 653
 654         /* [2]  send DMA request */
 655         prepare_data_dma(this, DMA_TO_DEVICE);
 656         desc = channel->device->device_prep_slave_sg(channel, &mil->data_sgl,
 657                                                 1, DMA_TO_DEVICE, 1);
 658         if (!desc) {
 659                 pr_info("step 2 error");
 660                 return -1;
 661         }
 662         /* [3] submit the DMA */
 663         this->dma_type = DMA_FOR_WRITE_DATA;
 664         start_dma_without_bch_irq(this, desc);
 665         return 0;
 666 }
 667
 668 static int read_data(struct gpmi_nfc_data *this)
 669 {
 670         struct dma_async_tx_descriptor *desc;
 671         struct dma_chan *channel = get_dma_chan(this);
 672         struct mil *mil = &this->mil;
 673         u32 pio[2];
 674
 675         /* [1] : send PIO */
 676         pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__READ)
 677                 | BM_GPMI_CTRL0_WORD_LENGTH
 678                 | BF_GPMI_CTRL0_CS(mil->current_chip)
 679                 | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_DATA)
 680                 | BF_GPMI_CTRL0_XFER_COUNT(mil->upper_len);
 681         pio[1] = 0;
 682         desc = channel->device->device_prep_slave_sg(channel,
 683                                         (struct scatterlist *)pio,
 684                                         ARRAY_SIZE(pio), DMA_NONE, 0);
 685         if (!desc) {
 686                 pr_info("step 1 error");
 687                 return -1;
 688         }
 689
 690         /* [2] : send DMA request */
 691         prepare_data_dma(this, DMA_FROM_DEVICE);
 692         desc = channel->device->device_prep_slave_sg(channel, &mil->data_sgl,
 693                                                 1, DMA_FROM_DEVICE, 1);
 694         if (!desc) {
 695                 pr_info("step 2 error");
 696                 return -1;
 697         }
 698
 699         /* [3] : submit the DMA */
 700         this->dma_type = DMA_FOR_READ_DATA;
 701         start_dma_without_bch_irq(this, desc);
 702         return 0;
 703 }
 704
 705 static int send_page(struct gpmi_nfc_data *this,
 706                         dma_addr_t payload, dma_addr_t auxiliary)
 707 {
 708         struct nfc_geometry *geo = &this->nfc_geometry;
 709         uint32_t command_mode;
 710         uint32_t address;
 711         uint32_t ecc_command;
 712         uint32_t buffer_mask;
 713         uint32_t busw;
 714         uint32_t page_size;
 715         struct dma_async_tx_descriptor *desc;
 716         struct dma_chan *channel = get_dma_chan(this);
 717         struct mil *mil = &this->mil;
 718         int chip = mil->current_chip;
 719         u32 pio[6];
 720
 721         /* DDR use the 16-bit for DATA transmission! */
 722         if (is_board_support_ddr(this) && is_ddr_nand(this)) {
 723                 busw            = BV_GPMI_CTRL0_WORD_LENGTH__16_BIT;
 724                 page_size       = geo->page_size_in_bytes >> 1;
 725         } else {
 726                 busw            = BM_GPMI_CTRL0_WORD_LENGTH;
 727                 page_size       = geo->page_size_in_bytes;
 728         }
 729
 730         /* A DMA descriptor that does an ECC page read. */
 731         command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
 732         address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
 733         ecc_command  = BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE;
 734         buffer_mask  = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
 735                                 BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
 736
 737         pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
 738                 | busw
 739                 | BF_GPMI_CTRL0_CS(chip)
 740                 | BF_GPMI_CTRL0_ADDRESS(address)
 741                 | BF_GPMI_CTRL0_XFER_COUNT(0);
 742         pio[1] = 0;
 743         pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
 744                 | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
 745                 | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
 746         pio[3] = page_size;
 747         pio[4] = payload;
 748         pio[5] = auxiliary;
 749
 750         desc = channel->device->device_prep_slave_sg(channel,
 751                                         (struct scatterlist *)pio,
 752                                         ARRAY_SIZE(pio), DMA_NONE, 0);
 753         if (!desc) {
 754                 pr_info("step 2 error");
 755                 return -1;
 756         }
 757         this->dma_type = DMA_FOR_WRITE_ECC_PAGE;
 758         return start_dma_with_bch_irq(this, desc);
 759 }
 760
 761 static int read_page(struct gpmi_nfc_data *this,
 762                                 dma_addr_t payload, dma_addr_t auxiliary)
 763 {
 764         struct nfc_geometry *geo = &this->nfc_geometry;
 765         uint32_t command_mode;
 766         uint32_t address;
 767         uint32_t ecc_command;
 768         uint32_t buffer_mask;
 769         uint32_t page_size;
 770         uint32_t busw;
 771         struct dma_async_tx_descriptor *desc;
 772         struct dma_chan *channel = get_dma_chan(this);
 773         struct mil *mil = &this->mil;
 774         int chip = mil->current_chip;
 775         u32 pio[6];
 776
 777         /* DDR use the 16-bit for DATA transmission! */
 778         if (is_board_support_ddr(this) && is_ddr_nand(this)) {
 779                 busw            = BV_GPMI_CTRL0_WORD_LENGTH__16_BIT;
 780                 page_size       = geo->page_size_in_bytes >> 1;
 781         } else {
 782                 busw            = BM_GPMI_CTRL0_WORD_LENGTH;
 783                 page_size       = geo->page_size_in_bytes;
 784         }
 785
 786         /* [1] Wait for the chip to report ready. */
 787         command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
 788         address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
 789
 790         pio[0] =  BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
 791                 | busw
 792                 | BF_GPMI_CTRL0_CS(chip)
 793                 | BF_GPMI_CTRL0_ADDRESS(address)
 794                 | BF_GPMI_CTRL0_XFER_COUNT(0);
 795         pio[1] = 0;
 796         desc = channel->device->device_prep_slave_sg(channel,
 797                                 (struct scatterlist *)pio, 2, DMA_NONE, 0);
 798         if (!desc) {
 799                 pr_info("step 1 error");
 800                 return -1;
 801         }
 802
 803         /* [2] Enable the BCH block and read. */
 804         command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
 805         address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
 806         ecc_command  = BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE;
 807         buffer_mask  = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE
 808                         | BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
 809
 810         pio[0] =  BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
 811                 | busw
 812                 | BF_GPMI_CTRL0_CS(chip)
 813                 | BF_GPMI_CTRL0_ADDRESS(address)
 814                 | BF_GPMI_CTRL0_XFER_COUNT(page_size);
 815
 816         pio[1] = 0;
 817         pio[2] =  BM_GPMI_ECCCTRL_ENABLE_ECC
 818                 | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
 819                 | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
 820         pio[3] = page_size;
 821         pio[4] = payload;
 822         pio[5] = auxiliary;
 823         desc = channel->device->device_prep_slave_sg(channel,
 824                                         (struct scatterlist *)pio,
 825                                         ARRAY_SIZE(pio), DMA_NONE, 1);
 826         if (!desc) {
 827                 pr_info("step 2 error");
 828                 return -1;
 829         }
 830
 831         /* [3] Disable the BCH block */
 832         command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
 833         address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
 834
 835         pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
 836                 | busw
 837                 | BF_GPMI_CTRL0_CS(chip)
 838                 | BF_GPMI_CTRL0_ADDRESS(address)
 839                 | BF_GPMI_CTRL0_XFER_COUNT(page_size);
 840         pio[1] = 0;
 841         desc = channel->device->device_prep_slave_sg(channel,
 842                                 (struct scatterlist *)pio, 2, DMA_NONE, 1);
 843         if (!desc) {
 844                 pr_info("step 3 error");
 845                 return -1;
 846         }
 847
 848         /* [4] submit the DMA */
 849         this->dma_type = DMA_FOR_READ_ECC_PAGE;
 850         return start_dma_with_bch_irq(this, desc);
 851 }
 852
 853 /* This structure represents the NFC HAL for this version of the hardware. */
 854 struct nfc_hal  gpmi_nfc_hal_mx50 = {
 855         .description                 = "8-chip GPMI and BCH",
 856         .max_chip_count              = 8,
 857         .max_data_setup_cycles       = (BM_GPMI_TIMING0_DATA_SETUP >>
 858                                                 BP_GPMI_TIMING0_DATA_SETUP),
 859         .internal_data_setup_in_ns   = 0,
 860         .max_sample_delay_factor     = (BM_GPMI_CTRL1_RDN_DELAY >>
 861                                                 BP_GPMI_CTRL1_RDN_DELAY),
 862         .max_dll_clock_period_in_ns  = 32,
 863         .max_dll_delay_in_ns         = 16,
 864         .init                        = init,
 865         .extra_init                  = extra_init,
 866         .set_geometry                = set_geometry,
 867         .set_timing                  = set_timing,
 868         .get_timing                  = get_timing,
 869         .exit                        = exit,
 870         .begin                       = begin,
 871         .end                         = end,
 872         .clear_bch                   = clear_bch,
 873         .is_ready                    = is_ready,
 874         .send_command                = send_command,
 875         .send_data                   = send_data,
 876         .read_data                   = read_data,
 877         .send_page                   = send_page,
 878         .read_page                   = read_page,
 879 };