drivers/mxc/ipu3/ipu_common.c

   1 /*
   2  * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
   3  */
   4
   5 /*
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /*!
  15  * @file ipu_common.c
  16  *
  17  * @brief This file contains the IPU driver common API functions.
  18  *
  19  * @ingroup IPU
  20  */
  21 #include <linux/types.h>
  22 #include <linux/init.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/err.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/delay.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/io.h>
  29 #include <linux/ipu.h>
  30 #include <linux/clk.h>
  31 #include <linux/clkdev.h>
  32 #include <mach/clock.h>
  33 #include <mach/hardware.h>
  34 #include <mach/ipu-v3.h>
  35 #include <mach/devices-common.h>
  36
  37 #include "ipu_prv.h"
  38 #include "ipu_regs.h"
  39 #include "ipu_param_mem.h"
  40
  41 struct ipu_irq_node {
  42         irqreturn_t(*handler) (int, void *);    /*!< the ISR */
  43         const char *name;       /*!< device associated with the interrupt */
  44         void *dev_id;           /*!< some unique information for the ISR */
  45         __u32 flags;            /*!< not used */
  46 };
  47
  48 /* Globals */
  49 struct clk *g_ipu_clk;
  50 bool g_ipu_clk_enabled;
  51 struct clk *g_di_clk[2];
  52 struct clk *g_pixel_clk[2];
  53 struct clk *g_csi_clk[2];
  54 unsigned char g_dc_di_assignment[10];
  55 ipu_channel_t g_ipu_csi_channel[2];
  56 int g_ipu_irq[2];
  57 int g_ipu_hw_rev;
  58 bool g_sec_chan_en[24];
  59 bool g_thrd_chan_en[24];
  60 bool g_chan_is_interlaced[52];
  61 uint32_t g_channel_init_mask;
  62 uint32_t g_channel_enable_mask;
  63 DEFINE_SPINLOCK(ipu_lock);
  64 struct device *g_ipu_dev;
  65
  66 static struct ipu_irq_node ipu_irq_list[IPU_IRQ_COUNT];
  67
  68 static int ipu_dc_use_count;
  69 static int ipu_dp_use_count;
  70 static int ipu_dmfc_use_count;
  71 static int ipu_smfc_use_count;
  72 static int ipu_ic_use_count;
  73 static int ipu_rot_use_count;
  74 static int ipu_vdi_use_count;
  75 static int ipu_di_use_count[2];
  76 static int ipu_csi_use_count[2];
  77 /* Set to the follow using IC direct channel, default non */
  78 static ipu_channel_t using_ic_dirct_ch;
  79
  80 /* for power gating */
  81 static uint32_t ipu_conf_reg;
  82 static uint32_t ic_conf_reg;
  83 static uint32_t ipu_cha_db_mode_reg[4];
  84 static uint32_t ipu_cha_trb_mode_reg[2];
  85 static uint32_t ipu_cha_cur_buf_reg[4];
  86 static uint32_t ipu_cha_triple_cur_buf_reg[4];
  87 static uint32_t idma_sub_addr_reg[5];
  88 static uint32_t idma_enable_reg[2];
  89 static uint32_t buf_ready_reg[10];
  90
  91 u32 *ipu_cm_reg;
  92 u32 *ipu_idmac_reg;
  93 u32 *ipu_dp_reg;
  94 u32 *ipu_ic_reg;
  95 u32 *ipu_dc_reg;
  96 u32 *ipu_dc_tmpl_reg;
  97 u32 *ipu_dmfc_reg;
  98 u32 *ipu_di_reg[2];
  99 u32 *ipu_smfc_reg;
 100 u32 *ipu_csi_reg[2];
 101 u32 *ipu_cpmem_base;
 102 u32 *ipu_tpmem_base;
 103 u32 *ipu_disp_base[2];
 104 u32 *ipu_vdi_reg;
 105
 106 /* Static functions */
 107 static irqreturn_t ipu_irq_handler(int irq, void *desc);
 108
 109 static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)
 110 {
 111         return ((uint32_t) ch >> (6 * type)) & 0x3F;
 112 };
 113
 114 static inline int _ipu_is_ic_chan(uint32_t dma_chan)
 115 {
 116         return ((dma_chan >= 11) && (dma_chan <= 22) && (dma_chan != 17) && (dma_chan != 18));
 117 }
 118
 119 static inline int _ipu_is_ic_graphic_chan(uint32_t dma_chan)
 120 {
 121         return (dma_chan == 14 || dma_chan == 15);
 122 }
 123
 124 /* Either DP BG or DP FG can be graphic window */
 125 static inline int _ipu_is_dp_graphic_chan(uint32_t dma_chan)
 126 {
 127         return (dma_chan == 23 || dma_chan == 27);
 128 }
 129
 130 static inline int _ipu_is_irt_chan(uint32_t dma_chan)
 131 {
 132         return ((dma_chan >= 45) && (dma_chan <= 50));
 133 }
 134
 135 static inline int _ipu_is_dmfc_chan(uint32_t dma_chan)
 136 {
 137         return ((dma_chan >= 23) && (dma_chan <= 29));
 138 }
 139
 140 static inline int _ipu_is_smfc_chan(uint32_t dma_chan)
 141 {
 142         return ((dma_chan >= 0) && (dma_chan <= 3));
 143 }
 144
 145 static inline int _ipu_is_trb_chan(uint32_t dma_chan)
 146 {
 147         return (((dma_chan == 8) || (dma_chan == 9) ||
 148                  (dma_chan == 10) || (dma_chan == 13) ||
 149                  (dma_chan == 21) || (dma_chan == 23) ||
 150                  (dma_chan == 27) || (dma_chan == 28)) &&
 151                 (g_ipu_hw_rev >= 2));
 152 }
 153
 154 #define idma_is_valid(ch)       (ch != NO_DMA)
 155 #define idma_mask(ch)           (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)
 156 #define idma_is_set(reg, dma)   (__raw_readl(reg(dma)) & idma_mask(dma))
 157 #define tri_cur_buf_mask(ch)    (idma_mask(ch*2) * 3)
 158 #define tri_cur_buf_shift(ch)   (ffs(idma_mask(ch*2)) - 1)
 159
 160 static unsigned long _ipu_pixel_clk_get_rate(struct clk *clk)
 161 {
 162         u32 div = __raw_readl(DI_BS_CLKGEN0(clk->id));
 163         if (div == 0)
 164                 return 0;
 165         return  (clk_get_rate(clk->parent) * 16) / div;
 166 }
 167
 168 static unsigned long _ipu_pixel_clk_round_rate(struct clk *clk, unsigned long rate)
 169 {
 170         u32 div, div1;
 171         u32 parent_rate = clk_get_rate(clk->parent) * 16;
 172         /*
 173          * Calculate divider
 174          * Fractional part is 4 bits,
 175          * so simply multiply by 2^4 to get fractional part.
 176          */
 177         div = parent_rate / rate;
 178
 179         if (div < 0x10)            /* Min DI disp clock divider is 1 */
 180                 div = 0x10;
 181         if (div & ~0xFEF)
 182                 div &= 0xFF8;
 183         else {
 184                 div1 = div & 0xFE0;
 185                 if ((parent_rate / div1 - parent_rate / div) < rate / 4)
 186                         div = div1;
 187                 else
 188                         div &= 0xFF8;
 189         }
 190         return parent_rate / div;
 191 }
 192
 193 static int _ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)
 194 {
 195         u32 div = (clk_get_rate(clk->parent) * 16) / rate;
 196
 197         __raw_writel(div, DI_BS_CLKGEN0(clk->id));
 198
 199         /* Setup pixel clock timing */
 200         /* FIXME: needs to be more flexible */
 201         /* Down time is half of period */
 202         __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));
 203
 204         return 0;
 205 }
 206
 207 static int _ipu_pixel_clk_enable(struct clk *clk)
 208 {
 209         u32 disp_gen = __raw_readl(IPU_DISP_GEN);
 210         disp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE;
 211         __raw_writel(disp_gen, IPU_DISP_GEN);
 212
 213         return 0;
 214 }
 215
 216 static void _ipu_pixel_clk_disable(struct clk *clk)
 217 {
 218         u32 disp_gen = __raw_readl(IPU_DISP_GEN);
 219         disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;
 220         __raw_writel(disp_gen, IPU_DISP_GEN);
 221 }
 222
 223 static int _ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)
 224 {
 225         u32 di_gen = __raw_readl(DI_GENERAL(clk->id));
 226
 227         if (parent == g_ipu_clk)
 228                 di_gen &= ~DI_GEN_DI_CLK_EXT;
 229         else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_di_clk[clk->id])
 230                 di_gen |= DI_GEN_DI_CLK_EXT;
 231         else
 232                 return -EINVAL;
 233
 234         __raw_writel(di_gen, DI_GENERAL(clk->id));
 235         return 0;
 236 }
 237
 238 #ifdef CONFIG_CLK_DEBUG
 239 #define __INIT_CLK_DEBUG(n)     .name = #n,
 240 #else
 241 #define __INIT_CLK_DEBUG(n)
 242 #endif
 243 static struct clk pixel_clk[] = {
 244         {
 245         __INIT_CLK_DEBUG(pixel_clk_0)
 246         .id = 0,
 247         .get_rate = _ipu_pixel_clk_get_rate,
 248         .set_rate = _ipu_pixel_clk_set_rate,
 249         .round_rate = _ipu_pixel_clk_round_rate,
 250         .set_parent = _ipu_pixel_clk_set_parent,
 251         .enable = _ipu_pixel_clk_enable,
 252         .disable = _ipu_pixel_clk_disable,
 253         },
 254         {
 255         __INIT_CLK_DEBUG(pixel_clk_1)
 256         .id = 1,
 257         .get_rate = _ipu_pixel_clk_get_rate,
 258         .set_rate = _ipu_pixel_clk_set_rate,
 259         .round_rate = _ipu_pixel_clk_round_rate,
 260         .set_parent = _ipu_pixel_clk_set_parent,
 261         .enable = _ipu_pixel_clk_enable,
 262         .disable = _ipu_pixel_clk_disable,
 263         },
 264 };
 265
 266 #define _REGISTER_CLOCK(d, n, c) \
 267         { \
 268                 .dev_id = d, \
 269                 .con_id = n, \
 270                 .clk = &c, \
 271         }
 272
 273 static struct clk_lookup ipu_lookups[] = {
 274         _REGISTER_CLOCK(NULL, "pixel_clk_0", pixel_clk[0]),
 275         _REGISTER_CLOCK(NULL, "pixel_clk_1", pixel_clk[1]),
 276
 277 };
 278
 279 int __initdata primary_di = { 0 };
 280 static int __init di1_setup(char *__unused)
 281 {
 282         primary_di = MXC_PRI_DI1;
 283         return 1;
 284 }
 285 __setup("di1_primary", di1_setup);
 286
 287 static int __init di0_setup(char *__unused)
 288 {
 289         primary_di = MXC_PRI_DI0;
 290         return 1;
 291 }
 292 __setup("di0_primary", di0_setup);
 293
 294 struct platform_device *__init imx_add_ipuv3_fb(
 295                 const struct ipuv3_fb_platform_data *pdata, int id)
 296 {
 297         if (pdata) {
 298                 if (pdata->res_size > 0) {
 299                         struct resource res[] = {
 300                                 {
 301                                         .start = pdata->res_base,
 302                                         .end = pdata->res_base + pdata->res_size - 1,
 303                                         .flags = IORESOURCE_MEM,
 304                                 },
 305                         };
 306
 307                         return imx_add_platform_device_dmamask("mxc_sdc_fb",
 308                                         id, res, ARRAY_SIZE(res), pdata,
 309                                         sizeof(*pdata), DMA_BIT_MASK(32));
 310                 } else
 311                         return imx_add_platform_device_dmamask("mxc_sdc_fb", id,
 312                                         NULL, 0, pdata, sizeof(*pdata),
 313                                         DMA_BIT_MASK(32));
 314         } else
 315                 return imx_add_platform_device_dmamask("mxc_sdc_fb", id,
 316                                 NULL, 0, NULL, 0, DMA_BIT_MASK(32));
 317 }
 318
 319 static int __init register_fb_device(struct platform_device *pdev)
 320 {
 321         struct imx_ipuv3_platform_data *plat_data = pdev->dev.platform_data;
 322
 323         if (!primary_di)
 324                 primary_di = plat_data->primary_di;
 325
 326         if (primary_di == MXC_PRI_DI1) {
 327                 dev_info(g_ipu_dev, "DI1 is primary\n");
 328                 /* DI1 -> DP-BG channel: */
 329                 imx_add_ipuv3_fb(plat_data->fb_head1_platform_data, 1);
 330                 /* DI0 -> DC channel: */
 331                 plat_data->fb_head0_platform_data->res_base = 0;
 332                 plat_data->fb_head0_platform_data->res_size = 0;
 333                 imx_add_ipuv3_fb(plat_data->fb_head0_platform_data, 0);
 334         } else {
 335                 dev_info(g_ipu_dev, "DI0 is primary\n");
 336                 /* DI0 -> DP-BG channel: */
 337                 imx_add_ipuv3_fb(plat_data->fb_head0_platform_data, 0);
 338                 /* DI1 -> DC channel: */
 339                 plat_data->fb_head1_platform_data->res_base = 0;
 340                 plat_data->fb_head1_platform_data->res_size = 0;
 341                 imx_add_ipuv3_fb(plat_data->fb_head1_platform_data, 1);
 342         }
 343
 344         /*
 345          * DI0/1 DP-FG channel:
 346          */
 347         imx_add_ipuv3_fb(NULL, 2);
 348
 349         return 0;
 350 }
 351
 352 /*!
 353  * This function is called by the driver framework to initialize the IPU
 354  * hardware.
 355  *
 356  * @param       dev     The device structure for the IPU passed in by the
 357  *                      driver framework.
 358  *
 359  * @return      Returns 0 on success or negative error code on error
 360  */
 361 static int ipu_probe(struct platform_device *pdev)
 362 {
 363         struct resource *res;
 364         struct imx_ipuv3_platform_data *plat_data = pdev->dev.platform_data;
 365         unsigned long ipu_base;
 366
 367         spin_lock_init(&ipu_lock);
 368
 369         g_ipu_hw_rev = plat_data->rev;
 370
 371         g_ipu_dev = &pdev->dev;
 372
 373         /* Register IPU interrupts */
 374         g_ipu_irq[0] = platform_get_irq(pdev, 0);
 375         if (g_ipu_irq[0] < 0)
 376                 return -EINVAL;
 377
 378         if (request_irq(g_ipu_irq[0], ipu_irq_handler, 0, pdev->name, 0) != 0) {
 379                 dev_err(g_ipu_dev, "request SYNC interrupt failed\n");
 380                 return -EBUSY;
 381         }
 382         /* Some platforms have 2 IPU interrupts */
 383         g_ipu_irq[1] = platform_get_irq(pdev, 1);
 384         if (g_ipu_irq[1] >= 0) {
 385                 if (request_irq
 386                     (g_ipu_irq[1], ipu_irq_handler, 0, pdev->name, 0) != 0) {
 387                         dev_err(g_ipu_dev, "request ERR interrupt failed\n");
 388                         return -EBUSY;
 389                 }
 390         }
 391
 392         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 393         if (IS_ERR(res))
 394                 return -ENODEV;
 395
 396         ipu_base = res->start;
 397         if (g_ipu_hw_rev == 3)  /* IPUv3M */
 398                 ipu_base += IPUV3M_REG_BASE;
 399         else                    /* IPUv3D, v3E, v3EX */
 400                 ipu_base += IPU_REG_BASE;
 401
 402         ipu_cm_reg = ioremap(ipu_base + IPU_CM_REG_BASE, PAGE_SIZE);
 403         ipu_ic_reg = ioremap(ipu_base + IPU_IC_REG_BASE, PAGE_SIZE);
 404         ipu_idmac_reg = ioremap(ipu_base + IPU_IDMAC_REG_BASE, PAGE_SIZE);
 405         /* DP Registers are accessed thru the SRM */
 406         ipu_dp_reg = ioremap(ipu_base + IPU_SRM_REG_BASE, PAGE_SIZE);
 407         ipu_dc_reg = ioremap(ipu_base + IPU_DC_REG_BASE, PAGE_SIZE);
 408         ipu_dmfc_reg = ioremap(ipu_base + IPU_DMFC_REG_BASE, PAGE_SIZE);
 409         ipu_di_reg[0] = ioremap(ipu_base + IPU_DI0_REG_BASE, PAGE_SIZE);
 410         ipu_di_reg[1] = ioremap(ipu_base + IPU_DI1_REG_BASE, PAGE_SIZE);
 411         ipu_smfc_reg = ioremap(ipu_base + IPU_SMFC_REG_BASE, PAGE_SIZE);
 412         ipu_csi_reg[0] = ioremap(ipu_base + IPU_CSI0_REG_BASE, PAGE_SIZE);
 413         ipu_csi_reg[1] = ioremap(ipu_base + IPU_CSI1_REG_BASE, PAGE_SIZE);
 414         ipu_cpmem_base = ioremap(ipu_base + IPU_CPMEM_REG_BASE, SZ_128K);
 415         ipu_tpmem_base = ioremap(ipu_base + IPU_TPM_REG_BASE, SZ_64K);
 416         ipu_dc_tmpl_reg = ioremap(ipu_base + IPU_DC_TMPL_REG_BASE, SZ_128K);
 417         ipu_disp_base[1] = ioremap(ipu_base + IPU_DISP1_BASE, SZ_4K);
 418         ipu_vdi_reg = ioremap(ipu_base + IPU_VDI_REG_BASE, PAGE_SIZE);
 419
 420         dev_dbg(g_ipu_dev, "IPU VDI Regs = %p\n", ipu_vdi_reg);
 421         dev_dbg(g_ipu_dev, "IPU CM Regs = %p\n", ipu_cm_reg);
 422         dev_dbg(g_ipu_dev, "IPU IC Regs = %p\n", ipu_ic_reg);
 423         dev_dbg(g_ipu_dev, "IPU IDMAC Regs = %p\n", ipu_idmac_reg);
 424         dev_dbg(g_ipu_dev, "IPU DP Regs = %p\n", ipu_dp_reg);
 425         dev_dbg(g_ipu_dev, "IPU DC Regs = %p\n", ipu_dc_reg);
 426         dev_dbg(g_ipu_dev, "IPU DMFC Regs = %p\n", ipu_dmfc_reg);
 427         dev_dbg(g_ipu_dev, "IPU DI0 Regs = %p\n", ipu_di_reg[0]);
 428         dev_dbg(g_ipu_dev, "IPU DI1 Regs = %p\n", ipu_di_reg[1]);
 429         dev_dbg(g_ipu_dev, "IPU SMFC Regs = %p\n", ipu_smfc_reg);
 430         dev_dbg(g_ipu_dev, "IPU CSI0 Regs = %p\n", ipu_csi_reg[0]);
 431         dev_dbg(g_ipu_dev, "IPU CSI1 Regs = %p\n", ipu_csi_reg[1]);
 432         dev_dbg(g_ipu_dev, "IPU CPMem = %p\n", ipu_cpmem_base);
 433         dev_dbg(g_ipu_dev, "IPU TPMem = %p\n", ipu_tpmem_base);
 434         dev_dbg(g_ipu_dev, "IPU DC Template Mem = %p\n", ipu_dc_tmpl_reg);
 435         dev_dbg(g_ipu_dev, "IPU Display Region 1 Mem = %p\n", ipu_disp_base[1]);
 436
 437         clkdev_add(&ipu_lookups[0]);
 438         clkdev_add(&ipu_lookups[1]);
 439         clk_debug_register(&pixel_clk[0]);
 440         clk_debug_register(&pixel_clk[1]);
 441
 442         g_pixel_clk[0] = &pixel_clk[0];
 443         g_pixel_clk[1] = &pixel_clk[1];
 444
 445         /* Enable IPU and CSI clocks */
 446         /* Get IPU clock freq */
 447         g_ipu_clk = clk_get(&pdev->dev, "ipu_clk");
 448         dev_dbg(g_ipu_dev, "ipu_clk = %lu\n", clk_get_rate(g_ipu_clk));
 449
 450         if (plat_data->init)
 451                 plat_data->init();
 452
 453         clk_set_parent(g_pixel_clk[0], g_ipu_clk);
 454         clk_set_parent(g_pixel_clk[1], g_ipu_clk);
 455         clk_enable(g_ipu_clk);
 456
 457         g_di_clk[0] = clk_get(&pdev->dev, "ipu_di0_clk");
 458         g_di_clk[1] = clk_get(&pdev->dev, "ipu_di1_clk");
 459
 460         g_csi_clk[0] = plat_data->csi_clk[0];
 461         g_csi_clk[1] = plat_data->csi_clk[1];
 462
 463         __raw_writel(0x807FFFFF, IPU_MEM_RST);
 464         while (__raw_readl(IPU_MEM_RST) & 0x80000000)
 465                 ;
 466
 467         _ipu_init_dc_mappings();
 468
 469         /* Enable error interrupts by default */
 470         __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(5));
 471         __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(6));
 472         __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(9));
 473         __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(10));
 474
 475         /* DMFC Init */
 476         _ipu_dmfc_init(DMFC_NORMAL, 1);
 477
 478         /* Set sync refresh channels and CSI->mem channel as high priority */
 479         __raw_writel(0x18800001L, IDMAC_CHA_PRI(0));
 480
 481         /* Set MCU_T to divide MCU access window into 2 */
 482         __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN);
 483
 484         clk_disable(g_ipu_clk);
 485
 486         register_fb_device(pdev);
 487
 488         register_ipu_device();
 489
 490         return 0;
 491 }
 492
 493 int ipu_remove(struct platform_device *pdev)
 494 {
 495         if (g_ipu_irq[0])
 496                 free_irq(g_ipu_irq[0], 0);
 497         if (g_ipu_irq[1])
 498                 free_irq(g_ipu_irq[1], 0);
 499
 500         clk_put(g_ipu_clk);
 501
 502         iounmap(ipu_cm_reg);
 503         iounmap(ipu_ic_reg);
 504         iounmap(ipu_idmac_reg);
 505         iounmap(ipu_dc_reg);
 506         iounmap(ipu_dp_reg);
 507         iounmap(ipu_dmfc_reg);
 508         iounmap(ipu_di_reg[0]);
 509         iounmap(ipu_di_reg[1]);
 510         iounmap(ipu_smfc_reg);
 511         iounmap(ipu_csi_reg[0]);
 512         iounmap(ipu_csi_reg[1]);
 513         iounmap(ipu_cpmem_base);
 514         iounmap(ipu_tpmem_base);
 515         iounmap(ipu_dc_tmpl_reg);
 516         iounmap(ipu_disp_base[1]);
 517         iounmap(ipu_vdi_reg);
 518
 519         return 0;
 520 }
 521
 522 void ipu_dump_registers(void)
 523 {
 524         printk(KERN_DEBUG "IPU_CONF = \t0x%08X\n", __raw_readl(IPU_CONF));
 525         printk(KERN_DEBUG "IDMAC_CONF = \t0x%08X\n", __raw_readl(IDMAC_CONF));
 526         printk(KERN_DEBUG "IDMAC_CHA_EN1 = \t0x%08X\n",
 527                __raw_readl(IDMAC_CHA_EN(0)));
 528         printk(KERN_DEBUG "IDMAC_CHA_EN2 = \t0x%08X\n",
 529                __raw_readl(IDMAC_CHA_EN(32)));
 530         printk(KERN_DEBUG "IDMAC_CHA_PRI1 = \t0x%08X\n",
 531                __raw_readl(IDMAC_CHA_PRI(0)));
 532         printk(KERN_DEBUG "IDMAC_CHA_PRI2 = \t0x%08X\n",
 533                __raw_readl(IDMAC_CHA_PRI(32)));
 534         printk(KERN_DEBUG "IDMAC_BAND_EN1 = \t0x%08X\n",
 535                __raw_readl(IDMAC_BAND_EN(0)));
 536         printk(KERN_DEBUG "IDMAC_BAND_EN2 = \t0x%08X\n",
 537                __raw_readl(IDMAC_BAND_EN(32)));
 538         printk(KERN_DEBUG "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
 539                __raw_readl(IPU_CHA_DB_MODE_SEL(0)));
 540         printk(KERN_DEBUG "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
 541                __raw_readl(IPU_CHA_DB_MODE_SEL(32)));
 542         if (g_ipu_hw_rev >= 2) {
 543                 printk(KERN_DEBUG "IPU_CHA_TRB_MODE_SEL0 = \t0x%08X\n",
 544                        __raw_readl(IPU_CHA_TRB_MODE_SEL(0)));
 545                 printk(KERN_DEBUG "IPU_CHA_TRB_MODE_SEL1 = \t0x%08X\n",
 546                        __raw_readl(IPU_CHA_TRB_MODE_SEL(32)));
 547         }
 548         printk(KERN_DEBUG "DMFC_WR_CHAN = \t0x%08X\n",
 549                __raw_readl(DMFC_WR_CHAN));
 550         printk(KERN_DEBUG "DMFC_WR_CHAN_DEF = \t0x%08X\n",
 551                __raw_readl(DMFC_WR_CHAN_DEF));
 552         printk(KERN_DEBUG "DMFC_DP_CHAN = \t0x%08X\n",
 553                __raw_readl(DMFC_DP_CHAN));
 554         printk(KERN_DEBUG "DMFC_DP_CHAN_DEF = \t0x%08X\n",
 555                __raw_readl(DMFC_DP_CHAN_DEF));
 556         printk(KERN_DEBUG "DMFC_IC_CTRL = \t0x%08X\n",
 557                __raw_readl(DMFC_IC_CTRL));
 558         printk(KERN_DEBUG "IPU_FS_PROC_FLOW1 = \t0x%08X\n",
 559                __raw_readl(IPU_FS_PROC_FLOW1));
 560         printk(KERN_DEBUG "IPU_FS_PROC_FLOW2 = \t0x%08X\n",
 561                __raw_readl(IPU_FS_PROC_FLOW2));
 562         printk(KERN_DEBUG "IPU_FS_PROC_FLOW3 = \t0x%08X\n",
 563                __raw_readl(IPU_FS_PROC_FLOW3));
 564         printk(KERN_DEBUG "IPU_FS_DISP_FLOW1 = \t0x%08X\n",
 565                __raw_readl(IPU_FS_DISP_FLOW1));
 566 }
 567
 568 /*!
 569  * This function is called to initialize a logical IPU channel.
 570  *
 571  * @param       channel Input parameter for the logical channel ID to init.
 572  *
 573  * @param       params  Input parameter containing union of channel
 574  *                      initialization parameters.
 575  *
 576  * @return      Returns 0 on success or negative error code on fail
 577  */
 578 int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)
 579 {
 580         int ret = 0;
 581         uint32_t ipu_conf;
 582         uint32_t reg;
 583         unsigned long lock_flags;
 584
 585         dev_dbg(g_ipu_dev, "init channel = %d\n", IPU_CHAN_ID(channel));
 586
 587         /* re-enable error interrupts every time a channel is initialized */
 588         __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(5));
 589         __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(6));
 590         __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(9));
 591         __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(10));
 592
 593         if (g_ipu_clk_enabled == false) {
 594                 g_ipu_clk_enabled = true;
 595                 clk_enable(g_ipu_clk);
 596         }
 597
 598         spin_lock_irqsave(&ipu_lock, lock_flags);
 599
 600         if (g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) {
 601                 dev_err(g_ipu_dev, "Warning: channel already initialized %d\n",
 602                         IPU_CHAN_ID(channel));
 603         }
 604
 605         ipu_conf = __raw_readl(IPU_CONF);
 606
 607         switch (channel) {
 608         case CSI_MEM0:
 609         case CSI_MEM1:
 610         case CSI_MEM2:
 611         case CSI_MEM3:
 612                 if (params->csi_mem.csi > 1) {
 613                         ret = -EINVAL;
 614                         goto err;
 615                 }
 616
 617                 if (params->csi_mem.interlaced)
 618                         g_chan_is_interlaced[channel_2_dma(channel,
 619                                 IPU_OUTPUT_BUFFER)] = true;
 620                 else
 621                         g_chan_is_interlaced[channel_2_dma(channel,
 622                                 IPU_OUTPUT_BUFFER)] = false;
 623
 624                 ipu_smfc_use_count++;
 625                 g_ipu_csi_channel[params->csi_mem.csi] = channel;
 626
 627                 /*SMFC setting*/
 628                 if (params->csi_mem.mipi_en) {
 629                         ipu_conf |= (1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
 630                                 params->csi_mem.csi));
 631                         _ipu_smfc_init(channel, params->csi_mem.mipi_id,
 632                                 params->csi_mem.csi);
 633                 } else {
 634                         ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
 635                                 params->csi_mem.csi));
 636                         _ipu_smfc_init(channel, 0, params->csi_mem.csi);
 637                 }
 638
 639                 /*CSI data (include compander) dest*/
 640                 _ipu_csi_init(channel, params->csi_mem.csi);
 641                 break;
 642         case CSI_PRP_ENC_MEM:
 643                 if (params->csi_prp_enc_mem.csi > 1) {
 644                         ret = -EINVAL;
 645                         goto err;
 646                 }
 647                 if (using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM) {
 648                         ret = -EINVAL;
 649                         goto err;
 650                 }
 651                 using_ic_dirct_ch = CSI_PRP_ENC_MEM;
 652
 653                 ipu_ic_use_count++;
 654                 g_ipu_csi_channel[params->csi_prp_enc_mem.csi] = channel;
 655
 656                 /*Without SMFC, CSI only support parallel data source*/
 657                 ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
 658                         params->csi_prp_enc_mem.csi));
 659
 660                 /*CSI0/1 feed into IC*/
 661                 ipu_conf &= ~IPU_CONF_IC_INPUT;
 662                 if (params->csi_prp_enc_mem.csi)
 663                         ipu_conf |= IPU_CONF_CSI_SEL;
 664                 else
 665                         ipu_conf &= ~IPU_CONF_CSI_SEL;
 666
 667                 /*PRP skip buffer in memory, only valid when RWS_EN is true*/
 668                 reg = __raw_readl(IPU_FS_PROC_FLOW1);
 669                 __raw_writel(reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1);
 670
 671                 /*CSI data (include compander) dest*/
 672                 _ipu_csi_init(channel, params->csi_prp_enc_mem.csi);
 673                 _ipu_ic_init_prpenc(params, true);
 674                 break;
 675         case CSI_PRP_VF_MEM:
 676                 if (params->csi_prp_vf_mem.csi > 1) {
 677                         ret = -EINVAL;
 678                         goto err;
 679                 }
 680                 if (using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM) {
 681                         ret = -EINVAL;
 682                         goto err;
 683                 }
 684                 using_ic_dirct_ch = CSI_PRP_VF_MEM;
 685
 686                 ipu_ic_use_count++;
 687                 g_ipu_csi_channel[params->csi_prp_vf_mem.csi] = channel;
 688
 689                 /*Without SMFC, CSI only support parallel data source*/
 690                 ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
 691                         params->csi_prp_vf_mem.csi));
 692
 693                 /*CSI0/1 feed into IC*/
 694                 ipu_conf &= ~IPU_CONF_IC_INPUT;
 695                 if (params->csi_prp_vf_mem.csi)
 696                         ipu_conf |= IPU_CONF_CSI_SEL;
 697                 else
 698                         ipu_conf &= ~IPU_CONF_CSI_SEL;
 699
 700                 /*PRP skip buffer in memory, only valid when RWS_EN is true*/
 701                 reg = __raw_readl(IPU_FS_PROC_FLOW1);
 702                 __raw_writel(reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
 703
 704                 /*CSI data (include compander) dest*/
 705                 _ipu_csi_init(channel, params->csi_prp_vf_mem.csi);
 706                 _ipu_ic_init_prpvf(params, true);
 707                 break;
 708         case MEM_PRP_VF_MEM:
 709                 ipu_ic_use_count++;
 710                 reg = __raw_readl(IPU_FS_PROC_FLOW1);
 711                 __raw_writel(reg | FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
 712
 713                 if (params->mem_prp_vf_mem.graphics_combine_en)
 714                         g_sec_chan_en[IPU_CHAN_ID(channel)] = true;
 715                 if (params->mem_prp_vf_mem.alpha_chan_en)
 716                         g_thrd_chan_en[IPU_CHAN_ID(channel)] = true;
 717
 718                 _ipu_ic_init_prpvf(params, false);
 719                 break;
 720         case MEM_VDI_PRP_VF_MEM:
 721                 if ((using_ic_dirct_ch == CSI_PRP_VF_MEM) ||
 722                      (using_ic_dirct_ch == CSI_PRP_ENC_MEM)) {
 723                         ret = -EINVAL;
 724                         goto err;
 725                 }
 726                 using_ic_dirct_ch = MEM_VDI_PRP_VF_MEM;
 727                 ipu_ic_use_count++;
 728                 ipu_vdi_use_count++;
 729                 reg = __raw_readl(IPU_FS_PROC_FLOW1);
 730                 reg &= ~FS_VDI_SRC_SEL_MASK;
 731                 __raw_writel(reg , IPU_FS_PROC_FLOW1);
 732
 733                 if (params->mem_prp_vf_mem.graphics_combine_en)
 734                         g_sec_chan_en[IPU_CHAN_ID(channel)] = true;
 735                 _ipu_ic_init_prpvf(params, false);
 736                 _ipu_vdi_init(channel, params);
 737                 break;
 738         case MEM_VDI_PRP_VF_MEM_P:
 739                 _ipu_vdi_init(channel, params);
 740                 break;
 741         case MEM_VDI_PRP_VF_MEM_N:
 742                 _ipu_vdi_init(channel, params);
 743                 break;
 744         case MEM_ROT_VF_MEM:
 745                 ipu_ic_use_count++;
 746                 ipu_rot_use_count++;
 747                 _ipu_ic_init_rotate_vf(params);
 748                 break;
 749         case MEM_PRP_ENC_MEM:
 750                 ipu_ic_use_count++;
 751                 reg = __raw_readl(IPU_FS_PROC_FLOW1);
 752                 __raw_writel(reg | FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1);
 753                 _ipu_ic_init_prpenc(params, false);
 754                 break;
 755         case MEM_ROT_ENC_MEM:
 756                 ipu_ic_use_count++;
 757                 ipu_rot_use_count++;
 758                 _ipu_ic_init_rotate_enc(params);
 759                 break;
 760         case MEM_PP_MEM:
 761                 if (params->mem_pp_mem.graphics_combine_en)
 762                         g_sec_chan_en[IPU_CHAN_ID(channel)] = true;
 763                 if (params->mem_pp_mem.alpha_chan_en)
 764                         g_thrd_chan_en[IPU_CHAN_ID(channel)] = true;
 765                 _ipu_ic_init_pp(params);
 766                 ipu_ic_use_count++;
 767                 break;
 768         case MEM_ROT_PP_MEM:
 769                 _ipu_ic_init_rotate_pp(params);
 770                 ipu_ic_use_count++;
 771                 ipu_rot_use_count++;
 772                 break;
 773         case MEM_DC_SYNC:
 774                 if (params->mem_dc_sync.di > 1) {
 775                         ret = -EINVAL;
 776                         goto err;
 777                 }
 778
 779                 g_dc_di_assignment[1] = params->mem_dc_sync.di;
 780                 _ipu_dc_init(1, params->mem_dc_sync.di,
 781                              params->mem_dc_sync.interlaced,
 782                              params->mem_dc_sync.out_pixel_fmt);
 783                 ipu_di_use_count[params->mem_dc_sync.di]++;
 784                 ipu_dc_use_count++;
 785                 ipu_dmfc_use_count++;
 786                 break;
 787         case MEM_BG_SYNC:
 788                 if (params->mem_dp_bg_sync.di > 1) {
 789                         ret = -EINVAL;
 790                         goto err;
 791                 }
 792
 793                 if (params->mem_dp_bg_sync.alpha_chan_en)
 794                         g_thrd_chan_en[IPU_CHAN_ID(channel)] = true;
 795
 796                 g_dc_di_assignment[5] = params->mem_dp_bg_sync.di;
 797                 _ipu_dp_init(channel, params->mem_dp_bg_sync.in_pixel_fmt,
 798                              params->mem_dp_bg_sync.out_pixel_fmt);
 799                 _ipu_dc_init(5, params->mem_dp_bg_sync.di,
 800                              params->mem_dp_bg_sync.interlaced,
 801                              params->mem_dp_bg_sync.out_pixel_fmt);
 802                 ipu_di_use_count[params->mem_dp_bg_sync.di]++;
 803                 ipu_dc_use_count++;
 804                 ipu_dp_use_count++;
 805                 ipu_dmfc_use_count++;
 806                 break;
 807         case MEM_FG_SYNC:
 808                 _ipu_dp_init(channel, params->mem_dp_fg_sync.in_pixel_fmt,
 809                              params->mem_dp_fg_sync.out_pixel_fmt);
 810
 811                 if (params->mem_dp_fg_sync.alpha_chan_en)
 812                         g_thrd_chan_en[IPU_CHAN_ID(channel)] = true;
 813
 814                 ipu_dc_use_count++;
 815                 ipu_dp_use_count++;
 816                 ipu_dmfc_use_count++;
 817                 break;
 818         case DIRECT_ASYNC0:
 819                 if (params->direct_async.di > 1) {
 820                         ret = -EINVAL;
 821                         goto err;
 822                 }
 823
 824                 g_dc_di_assignment[8] = params->direct_async.di;
 825                 _ipu_dc_init(8, params->direct_async.di, false, IPU_PIX_FMT_GENERIC);
 826                 ipu_di_use_count[params->direct_async.di]++;
 827                 ipu_dc_use_count++;
 828                 break;
 829         case DIRECT_ASYNC1:
 830                 if (params->direct_async.di > 1) {
 831                         ret = -EINVAL;
 832                         goto err;
 833                 }
 834
 835                 g_dc_di_assignment[9] = params->direct_async.di;
 836                 _ipu_dc_init(9, params->direct_async.di, false, IPU_PIX_FMT_GENERIC);
 837                 ipu_di_use_count[params->direct_async.di]++;
 838                 ipu_dc_use_count++;
 839                 break;
 840         default:
 841                 dev_err(g_ipu_dev, "Missing channel initialization\n");
 842                 break;
 843         }
 844
 845         /* Enable IPU sub module */
 846         g_channel_init_mask |= 1L << IPU_CHAN_ID(channel);
 847
 848         __raw_writel(ipu_conf, IPU_CONF);
 849
 850 err:
 851         spin_unlock_irqrestore(&ipu_lock, lock_flags);
 852         return ret;
 853 }
 854 EXPORT_SYMBOL(ipu_init_channel);
 855
 856 /*!
 857  * This function is called to uninitialize a logical IPU channel.
 858  *
 859  * @param       channel Input parameter for the logical channel ID to uninit.
 860  */
 861 void ipu_uninit_channel(ipu_channel_t channel)
 862 {
 863         unsigned long lock_flags;
 864         uint32_t reg;
 865         uint32_t in_dma, out_dma = 0;
 866         uint32_t ipu_conf;
 867
 868         if ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
 869                 dev_err(g_ipu_dev, "Channel already uninitialized %d\n",
 870                         IPU_CHAN_ID(channel));
 871                 return;
 872         }
 873
 874         /* Make sure channel is disabled */
 875         /* Get input and output dma channels */
 876         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
 877         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
 878
 879         if (idma_is_set(IDMAC_CHA_EN, in_dma) ||
 880             idma_is_set(IDMAC_CHA_EN, out_dma)) {
 881                 dev_err(g_ipu_dev,
 882                         "Channel %d is not disabled, disable first\n",
 883                         IPU_CHAN_ID(channel));
 884                 return;
 885         }
 886
 887         spin_lock_irqsave(&ipu_lock, lock_flags);
 888
 889         ipu_conf = __raw_readl(IPU_CONF);
 890
 891         /* Reset the double buffer */
 892         reg = __raw_readl(IPU_CHA_DB_MODE_SEL(in_dma));
 893         __raw_writel(reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma));
 894         reg = __raw_readl(IPU_CHA_DB_MODE_SEL(out_dma));
 895         __raw_writel(reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma));
 896
 897         /* Reset the triple buffer */
 898         reg = __raw_readl(IPU_CHA_TRB_MODE_SEL(in_dma));
 899         __raw_writel(reg & ~idma_mask(in_dma), IPU_CHA_TRB_MODE_SEL(in_dma));
 900         reg = __raw_readl(IPU_CHA_TRB_MODE_SEL(out_dma));
 901         __raw_writel(reg & ~idma_mask(out_dma), IPU_CHA_TRB_MODE_SEL(out_dma));
 902
 903         if (_ipu_is_ic_chan(in_dma) || _ipu_is_dp_graphic_chan(in_dma)) {
 904                 g_sec_chan_en[IPU_CHAN_ID(channel)] = false;
 905                 g_thrd_chan_en[IPU_CHAN_ID(channel)] = false;
 906         }
 907
 908         switch (channel) {
 909         case CSI_MEM0:
 910         case CSI_MEM1:
 911         case CSI_MEM2:
 912         case CSI_MEM3:
 913                 ipu_smfc_use_count--;
 914                 if (g_ipu_csi_channel[0] == channel) {
 915                         g_ipu_csi_channel[0] = CHAN_NONE;
 916                 } else if (g_ipu_csi_channel[1] == channel) {
 917                         g_ipu_csi_channel[1] = CHAN_NONE;
 918                 }
 919                 break;
 920         case CSI_PRP_ENC_MEM:
 921                 ipu_ic_use_count--;
 922                 if (using_ic_dirct_ch == CSI_PRP_ENC_MEM)
 923                         using_ic_dirct_ch = 0;
 924                 _ipu_ic_uninit_prpenc();
 925                 if (g_ipu_csi_channel[0] == channel) {
 926                         g_ipu_csi_channel[0] = CHAN_NONE;
 927                 } else if (g_ipu_csi_channel[1] == channel) {
 928                         g_ipu_csi_channel[1] = CHAN_NONE;
 929                 }
 930                 break;
 931         case CSI_PRP_VF_MEM:
 932                 ipu_ic_use_count--;
 933                 if (using_ic_dirct_ch == CSI_PRP_VF_MEM)
 934                         using_ic_dirct_ch = 0;
 935                 _ipu_ic_uninit_prpvf();
 936                 if (g_ipu_csi_channel[0] == channel) {
 937                         g_ipu_csi_channel[0] = CHAN_NONE;
 938                 } else if (g_ipu_csi_channel[1] == channel) {
 939                         g_ipu_csi_channel[1] = CHAN_NONE;
 940                 }
 941                 break;
 942         case MEM_PRP_VF_MEM:
 943                 ipu_ic_use_count--;
 944                 _ipu_ic_uninit_prpvf();
 945                 reg = __raw_readl(IPU_FS_PROC_FLOW1);
 946                 __raw_writel(reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
 947                 break;
 948         case MEM_VDI_PRP_VF_MEM:
 949                 ipu_ic_use_count--;
 950                 ipu_vdi_use_count--;
 951                 if (using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM)
 952                         using_ic_dirct_ch = 0;
 953                 _ipu_ic_uninit_prpvf();
 954                 _ipu_vdi_uninit();
 955                 reg = __raw_readl(IPU_FS_PROC_FLOW1);
 956                 __raw_writel(reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
 957                 break;
 958         case MEM_VDI_PRP_VF_MEM_P:
 959         case MEM_VDI_PRP_VF_MEM_N:
 960                 break;
 961         case MEM_ROT_VF_MEM:
 962                 ipu_rot_use_count--;
 963                 ipu_ic_use_count--;
 964                 _ipu_ic_uninit_rotate_vf();
 965                 break;
 966         case MEM_PRP_ENC_MEM:
 967                 ipu_ic_use_count--;
 968                 _ipu_ic_uninit_prpenc();
 969                 reg = __raw_readl(IPU_FS_PROC_FLOW1);
 970                 __raw_writel(reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1);
 971                 break;
 972         case MEM_ROT_ENC_MEM:
 973                 ipu_rot_use_count--;
 974                 ipu_ic_use_count--;
 975                 _ipu_ic_uninit_rotate_enc();
 976                 break;
 977         case MEM_PP_MEM:
 978                 ipu_ic_use_count--;
 979                 _ipu_ic_uninit_pp();
 980                 break;
 981         case MEM_ROT_PP_MEM:
 982                 ipu_rot_use_count--;
 983                 ipu_ic_use_count--;
 984                 _ipu_ic_uninit_rotate_pp();
 985                 break;
 986         case MEM_DC_SYNC:
 987                 _ipu_dc_uninit(1);
 988                 ipu_di_use_count[g_dc_di_assignment[1]]--;
 989                 ipu_dc_use_count--;
 990                 ipu_dmfc_use_count--;
 991                 break;
 992         case MEM_BG_SYNC:
 993                 _ipu_dp_uninit(channel);
 994                 _ipu_dc_uninit(5);
 995                 ipu_di_use_count[g_dc_di_assignment[5]]--;
 996                 ipu_dc_use_count--;
 997                 ipu_dp_use_count--;
 998                 ipu_dmfc_use_count--;
 999                 break;
1000         case MEM_FG_SYNC:
1001                 _ipu_dp_uninit(channel);
1002                 ipu_dc_use_count--;
1003                 ipu_dp_use_count--;
1004                 ipu_dmfc_use_count--;
1005                 break;
1006         case DIRECT_ASYNC0:
1007                 _ipu_dc_uninit(8);
1008                 ipu_di_use_count[g_dc_di_assignment[8]]--;
1009                 ipu_dc_use_count--;
1010                 break;
1011         case DIRECT_ASYNC1:
1012                 _ipu_dc_uninit(9);
1013                 ipu_di_use_count[g_dc_di_assignment[9]]--;
1014                 ipu_dc_use_count--;
1015                 break;
1016         default:
1017                 break;
1018         }
1019
1020         g_channel_init_mask &= ~(1L << IPU_CHAN_ID(channel));
1021
1022         if (ipu_ic_use_count == 0)
1023                 ipu_conf &= ~IPU_CONF_IC_EN;
1024         if (ipu_vdi_use_count == 0) {
1025                 ipu_conf &= ~IPU_CONF_ISP_EN;
1026                 ipu_conf &= ~IPU_CONF_VDI_EN;
1027                 ipu_conf &= ~IPU_CONF_IC_INPUT;
1028         }
1029         if (ipu_rot_use_count == 0)
1030                 ipu_conf &= ~IPU_CONF_ROT_EN;
1031         if (ipu_dc_use_count == 0)
1032                 ipu_conf &= ~IPU_CONF_DC_EN;
1033         if (ipu_dp_use_count == 0)
1034                 ipu_conf &= ~IPU_CONF_DP_EN;
1035         if (ipu_dmfc_use_count == 0)
1036                 ipu_conf &= ~IPU_CONF_DMFC_EN;
1037         if (ipu_di_use_count[0] == 0) {
1038                 ipu_conf &= ~IPU_CONF_DI0_EN;
1039         }
1040         if (ipu_di_use_count[1] == 0) {
1041                 ipu_conf &= ~IPU_CONF_DI1_EN;
1042         }
1043         if (ipu_smfc_use_count == 0)
1044                 ipu_conf &= ~IPU_CONF_SMFC_EN;
1045
1046         __raw_writel(ipu_conf, IPU_CONF);
1047
1048         spin_unlock_irqrestore(&ipu_lock, lock_flags);
1049
1050         if (ipu_conf == 0) {
1051                 clk_disable(g_ipu_clk);
1052                 g_ipu_clk_enabled = false;
1053         }
1054
1055         WARN_ON(ipu_ic_use_count < 0);
1056         WARN_ON(ipu_vdi_use_count < 0);
1057         WARN_ON(ipu_rot_use_count < 0);
1058         WARN_ON(ipu_dc_use_count < 0);
1059         WARN_ON(ipu_dp_use_count < 0);
1060         WARN_ON(ipu_dmfc_use_count < 0);
1061         WARN_ON(ipu_smfc_use_count < 0);
1062 }
1063 EXPORT_SYMBOL(ipu_uninit_channel);
1064
1065 /*!
1066  * This function is called to initialize buffer(s) for logical IPU channel.
1067  *
1068  * @param       channel         Input parameter for the logical channel ID.
1069  *
1070  * @param       type            Input parameter which buffer to initialize.
1071  *
1072  * @param       pixel_fmt       Input parameter for pixel format of buffer.
1073  *                              Pixel format is a FOURCC ASCII code.
1074  *
1075  * @param       width           Input parameter for width of buffer in pixels.
1076  *
1077  * @param       height          Input parameter for height of buffer in pixels.
1078  *
1079  * @param       stride          Input parameter for stride length of buffer
1080  *                              in pixels.
1081  *
1082  * @param       rot_mode        Input parameter for rotation setting of buffer.
1083  *                              A rotation setting other than
1084  *                              IPU_ROTATE_VERT_FLIP
1085  *                              should only be used for input buffers of
1086  *                              rotation channels.
1087  *
1088  * @param       phyaddr_0       Input parameter buffer 0 physical address.
1089  *
1090  * @param       phyaddr_1       Input parameter buffer 1 physical address.
1091  *                              Setting this to a value other than NULL enables
1092  *                              double buffering mode.
1093  *
1094  * @param       phyaddr_2       Input parameter buffer 2 physical address.
1095  *                              Setting this to a value other than NULL enables
1096  *                              triple buffering mode, phyaddr_1 should not be
1097  *                              NULL then.
1098  *
1099  * @param       u               private u offset for additional cropping,
1100  *                              zero if not used.
1101  *
1102  * @param       v               private v offset for additional cropping,
1103  *                              zero if not used.
1104  *
1105  * @return      Returns 0 on success or negative error code on fail
1106  */
1107 int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
1108                                 uint32_t pixel_fmt,
1109                                 uint16_t width, uint16_t height,
1110                                 uint32_t stride,
1111                                 ipu_rotate_mode_t rot_mode,
1112                                 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
1113                                 dma_addr_t phyaddr_2,
1114                                 uint32_t u, uint32_t v)
1115 {
1116         unsigned long lock_flags;
1117         uint32_t reg;
1118         uint32_t dma_chan;
1119         uint32_t burst_size;
1120
1121         dma_chan = channel_2_dma(channel, type);
1122         if (!idma_is_valid(dma_chan))
1123                 return -EINVAL;
1124
1125         if (stride < width * bytes_per_pixel(pixel_fmt))
1126                 stride = width * bytes_per_pixel(pixel_fmt);
1127
1128         if (stride % 4) {
1129                 dev_err(g_ipu_dev,
1130                         "Stride not 32-bit aligned, stride = %d\n", stride);
1131                 return -EINVAL;
1132         }
1133         /* IC & IRT channels' width must be multiple of 8 pixels */
1134         if ((_ipu_is_ic_chan(dma_chan) || _ipu_is_irt_chan(dma_chan))
1135                 && (width % 8)) {
1136                 dev_err(g_ipu_dev, "Width must be 8 pixel multiple\n");
1137                 return -EINVAL;
1138         }
1139
1140         /* IPUv3EX and IPUv3M support triple buffer */
1141         if ((!_ipu_is_trb_chan(dma_chan)) && phyaddr_2) {
1142                 dev_err(g_ipu_dev, "Chan%d doesn't support triple buffer "
1143                                    "mode\n", dma_chan);
1144                 return -EINVAL;
1145         }
1146         if (!phyaddr_1 && phyaddr_2) {
1147                 dev_err(g_ipu_dev, "Chan%d's buf1 physical addr is NULL for "
1148                                    "triple buffer mode\n", dma_chan);
1149                 return -EINVAL;
1150         }
1151
1152         /* Build parameter memory data for DMA channel */
1153         _ipu_ch_param_init(dma_chan, pixel_fmt, width, height, stride, u, v, 0,
1154                            phyaddr_0, phyaddr_1, phyaddr_2);
1155
1156         /* Set correlative channel parameter of local alpha channel */
1157         if ((_ipu_is_ic_graphic_chan(dma_chan) ||
1158              _ipu_is_dp_graphic_chan(dma_chan)) &&
1159             (g_thrd_chan_en[IPU_CHAN_ID(channel)] == true)) {
1160                 _ipu_ch_param_set_alpha_use_separate_channel(dma_chan, true);
1161                 _ipu_ch_param_set_alpha_buffer_memory(dma_chan);
1162                 _ipu_ch_param_set_alpha_condition_read(dma_chan);
1163                 /* fix alpha width as 8 and burst size as 16*/
1164                 _ipu_ch_params_set_alpha_width(dma_chan, 8);
1165                 _ipu_ch_param_set_burst_size(dma_chan, 16);
1166         } else if (_ipu_is_ic_graphic_chan(dma_chan) &&
1167                    ipu_pixel_format_has_alpha(pixel_fmt))
1168                 _ipu_ch_param_set_alpha_use_separate_channel(dma_chan, false);
1169
1170         if (rot_mode)
1171                 _ipu_ch_param_set_rotation(dma_chan, rot_mode);
1172
1173         /* IC and ROT channels have restriction of 8 or 16 pix burst length */
1174         if (_ipu_is_ic_chan(dma_chan)) {
1175                 if ((width % 16) == 0)
1176                         _ipu_ch_param_set_burst_size(dma_chan, 16);
1177                 else
1178                         _ipu_ch_param_set_burst_size(dma_chan, 8);
1179         } else if (_ipu_is_irt_chan(dma_chan)) {
1180                 _ipu_ch_param_set_burst_size(dma_chan, 8);
1181                 _ipu_ch_param_set_block_mode(dma_chan);
1182         } else if (_ipu_is_dmfc_chan(dma_chan)) {
1183                 burst_size = _ipu_ch_param_get_burst_size(dma_chan);
1184                 spin_lock_irqsave(&ipu_lock, lock_flags);
1185                 _ipu_dmfc_set_wait4eot(dma_chan, width);
1186                 _ipu_dmfc_set_burst_size(dma_chan, burst_size);
1187                 spin_unlock_irqrestore(&ipu_lock, lock_flags);
1188         }
1189
1190         if (_ipu_disp_chan_is_interlaced(channel) ||
1191                 g_chan_is_interlaced[dma_chan])
1192                 _ipu_ch_param_set_interlaced_scan(dma_chan);
1193
1194         if (_ipu_is_ic_chan(dma_chan) || _ipu_is_irt_chan(dma_chan)) {
1195                 burst_size = _ipu_ch_param_get_burst_size(dma_chan);
1196                 _ipu_ic_idma_init(dma_chan, width, height, burst_size,
1197                         rot_mode);
1198         } else if (_ipu_is_smfc_chan(dma_chan)) {
1199                 burst_size = _ipu_ch_param_get_burst_size(dma_chan);
1200                 if ((pixel_fmt == IPU_PIX_FMT_GENERIC) &&
1201                         ((_ipu_ch_param_get_bpp(dma_chan) == 5) ||
1202                         (_ipu_ch_param_get_bpp(dma_chan) == 3)))
1203                         burst_size = burst_size >> 4;
1204                 else
1205                         burst_size = burst_size >> 2;
1206                 _ipu_smfc_set_burst_size(channel, burst_size-1);
1207         }
1208
1209         if (idma_is_set(IDMAC_CHA_PRI, dma_chan) && !cpu_is_mx53())
1210                 _ipu_ch_param_set_high_priority(dma_chan);
1211
1212         _ipu_ch_param_dump(dma_chan);
1213
1214         spin_lock_irqsave(&ipu_lock, lock_flags);
1215         if (phyaddr_2 && g_ipu_hw_rev >= 2) {
1216                 reg = __raw_readl(IPU_CHA_DB_MODE_SEL(dma_chan));
1217                 reg &= ~idma_mask(dma_chan);
1218                 __raw_writel(reg, IPU_CHA_DB_MODE_SEL(dma_chan));
1219
1220                 reg = __raw_readl(IPU_CHA_TRB_MODE_SEL(dma_chan));
1221                 reg |= idma_mask(dma_chan);
1222                 __raw_writel(reg, IPU_CHA_TRB_MODE_SEL(dma_chan));
1223
1224                 /* Set IDMAC third buffer's cpmem number */
1225                 /* See __ipu_ch_get_third_buf_cpmem_num() for mapping */
1226                 __raw_writel(0x00444047L, IDMAC_SUB_ADDR_4);
1227                 __raw_writel(0x46004241L, IDMAC_SUB_ADDR_3);
1228                 __raw_writel(0x00000045L, IDMAC_SUB_ADDR_1);
1229
1230                 /* Reset to buffer 0 */
1231                 __raw_writel(tri_cur_buf_mask(dma_chan),
1232                                 IPU_CHA_TRIPLE_CUR_BUF(dma_chan));
1233         } else {
1234                 reg = __raw_readl(IPU_CHA_TRB_MODE_SEL(dma_chan));
1235                 reg &= ~idma_mask(dma_chan);
1236                 __raw_writel(reg, IPU_CHA_TRB_MODE_SEL(dma_chan));
1237
1238                 reg = __raw_readl(IPU_CHA_DB_MODE_SEL(dma_chan));
1239                 if (phyaddr_1)
1240                         reg |= idma_mask(dma_chan);
1241                 else
1242                         reg &= ~idma_mask(dma_chan);
1243                 __raw_writel(reg, IPU_CHA_DB_MODE_SEL(dma_chan));
1244
1245                 /* Reset to buffer 0 */
1246                 __raw_writel(idma_mask(dma_chan),
1247                                 IPU_CHA_CUR_BUF(dma_chan));
1248
1249         }
1250         spin_unlock_irqrestore(&ipu_lock, lock_flags);
1251
1252         return 0;
1253 }
1254 EXPORT_SYMBOL(ipu_init_channel_buffer);
1255
1256 /*!
1257  * This function is called to update the physical address of a buffer for
1258  * a logical IPU channel.
1259  *
1260  * @param       channel         Input parameter for the logical channel ID.
1261  *
1262  * @param       type            Input parameter which buffer to initialize.
1263  *
1264  * @param       bufNum          Input parameter for buffer number to update.
1265  *                              0 or 1 are the only valid values.
1266  *
1267  * @param       phyaddr         Input parameter buffer physical address.
1268  *
1269  * @return      This function returns 0 on success or negative error code on
1270  *              fail. This function will fail if the buffer is set to ready.
1271  */
1272 int32_t ipu_update_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
1273                                   uint32_t bufNum, dma_addr_t phyaddr)
1274 {
1275         uint32_t reg;
1276         int ret = 0;
1277         unsigned long lock_flags;
1278         uint32_t dma_chan = channel_2_dma(channel, type);
1279         if (dma_chan == IDMA_CHAN_INVALID)
1280                 return -EINVAL;
1281
1282         spin_lock_irqsave(&ipu_lock, lock_flags);
1283
1284         if (bufNum == 0)
1285                 reg = __raw_readl(IPU_CHA_BUF0_RDY(dma_chan));
1286         else if (bufNum == 1)
1287                 reg = __raw_readl(IPU_CHA_BUF1_RDY(dma_chan));
1288         else
1289                 reg = __raw_readl(IPU_CHA_BUF2_RDY(dma_chan));
1290
1291         if ((reg & idma_mask(dma_chan)) == 0)
1292                 _ipu_ch_param_set_buffer(dma_chan, bufNum, phyaddr);
1293         else
1294                 ret = -EACCES;
1295
1296         spin_unlock_irqrestore(&ipu_lock, lock_flags);
1297         return ret;
1298 }
1299 EXPORT_SYMBOL(ipu_update_channel_buffer);
1300
1301
1302 /*!
1303  * This function is called to initialize a buffer for logical IPU channel.
1304  *
1305  * @param       channel         Input parameter for the logical channel ID.
1306  *
1307  * @param       type            Input parameter which buffer to initialize.
1308  *
1309  * @param       pixel_fmt       Input parameter for pixel format of buffer.
1310  *                              Pixel format is a FOURCC ASCII code.
1311  *
1312  * @param       width           Input parameter for width of buffer in pixels.
1313  *
1314  * @param       height          Input parameter for height of buffer in pixels.
1315  *
1316  * @param       stride          Input parameter for stride length of buffer
1317  *                              in pixels.
1318  *
1319  * @param       u               predefined private u offset for additional cropping,
1320  *                                                              zero if not used.
1321  *
1322  * @param       v               predefined private v offset for additional cropping,
1323  *                                                              zero if not used.
1324  *
1325  * @param                       vertical_offset vertical offset for Y coordinate
1326  *                                                              in the existed frame
1327  *
1328  *
1329  * @param                       horizontal_offset horizontal offset for X coordinate
1330  *                                                              in the existed frame
1331  *
1332  *
1333  * @return      Returns 0 on success or negative error code on fail
1334  *              This function will fail if any buffer is set to ready.
1335  */
1336
1337 int32_t ipu_update_channel_offset(ipu_channel_t channel, ipu_buffer_t type,
1338                                 uint32_t pixel_fmt,
1339                                 uint16_t width, uint16_t height,
1340                                 uint32_t stride,
1341                                 uint32_t u, uint32_t v,
1342                                 uint32_t vertical_offset, uint32_t horizontal_offset)
1343 {
1344         int ret = 0;
1345         unsigned long lock_flags;
1346         uint32_t dma_chan = channel_2_dma(channel, type);
1347
1348         if (dma_chan == IDMA_CHAN_INVALID)
1349                 return -EINVAL;
1350
1351         spin_lock_irqsave(&ipu_lock, lock_flags);
1352
1353         if ((__raw_readl(IPU_CHA_BUF0_RDY(dma_chan)) & idma_mask(dma_chan)) ||
1354             (__raw_readl(IPU_CHA_BUF1_RDY(dma_chan)) & idma_mask(dma_chan)) ||
1355             ((__raw_readl(IPU_CHA_BUF2_RDY(dma_chan)) & idma_mask(dma_chan)) &&
1356              (__raw_readl(IPU_CHA_TRB_MODE_SEL(dma_chan)) & idma_mask(dma_chan)) &&
1357              _ipu_is_trb_chan(dma_chan)))
1358                 ret = -EACCES;
1359         else
1360                 _ipu_ch_offset_update(dma_chan, pixel_fmt, width, height, stride,
1361                                       u, v, 0, vertical_offset, horizontal_offset);
1362
1363         spin_unlock_irqrestore(&ipu_lock, lock_flags);
1364         return ret;
1365 }
1366 EXPORT_SYMBOL(ipu_update_channel_offset);
1367
1368
1369 /*!
1370  * This function is called to set a channel's buffer as ready.
1371  *
1372  * @param       channel         Input parameter for the logical channel ID.
1373  *
1374  * @param       type            Input parameter which buffer to initialize.
1375  *
1376  * @param       bufNum          Input parameter for which buffer number set to
1377  *                              ready state.
1378  *
1379  * @return      Returns 0 on success or negative error code on fail
1380  */
1381 int32_t ipu_select_buffer(ipu_channel_t channel, ipu_buffer_t type,
1382                           uint32_t bufNum)
1383 {
1384         uint32_t dma_chan = channel_2_dma(channel, type);
1385         unsigned long lock_flags;
1386
1387         if (dma_chan == IDMA_CHAN_INVALID)
1388                 return -EINVAL;
1389
1390         /* Mark buffer to be ready. */
1391         spin_lock_irqsave(&ipu_lock, lock_flags);
1392         if (bufNum == 0)
1393                 __raw_writel(idma_mask(dma_chan),
1394                              IPU_CHA_BUF0_RDY(dma_chan));
1395         else if (bufNum == 1)
1396                 __raw_writel(idma_mask(dma_chan),
1397                              IPU_CHA_BUF1_RDY(dma_chan));
1398         else
1399                 __raw_writel(idma_mask(dma_chan),
1400                              IPU_CHA_BUF2_RDY(dma_chan));
1401         spin_unlock_irqrestore(&ipu_lock, lock_flags);
1402         return 0;
1403 }
1404 EXPORT_SYMBOL(ipu_select_buffer);
1405
1406 /*!
1407  * This function is called to set a channel's buffer as ready.
1408  *
1409  * @param       bufNum          Input parameter for which buffer number set to
1410  *                              ready state.
1411  *
1412  * @return      Returns 0 on success or negative error code on fail
1413  */
1414 int32_t ipu_select_multi_vdi_buffer(uint32_t bufNum)
1415 {
1416
1417         uint32_t dma_chan = channel_2_dma(MEM_VDI_PRP_VF_MEM, IPU_INPUT_BUFFER);
1418         uint32_t mask_bit =
1419                 idma_mask(channel_2_dma(MEM_VDI_PRP_VF_MEM_P, IPU_INPUT_BUFFER))|
1420                 idma_mask(dma_chan)|
1421                 idma_mask(channel_2_dma(MEM_VDI_PRP_VF_MEM_N, IPU_INPUT_BUFFER));
1422         unsigned long lock_flags;
1423
1424         /* Mark buffers to be ready. */
1425         spin_lock_irqsave(&ipu_lock, lock_flags);
1426         if (bufNum == 0)
1427                 __raw_writel(mask_bit, IPU_CHA_BUF0_RDY(dma_chan));
1428         else
1429                 __raw_writel(mask_bit, IPU_CHA_BUF1_RDY(dma_chan));
1430         spin_unlock_irqrestore(&ipu_lock, lock_flags);
1431         return 0;
1432 }
1433 EXPORT_SYMBOL(ipu_select_multi_vdi_buffer);
1434
1435 #define NA      -1
1436 static int proc_dest_sel[] = {
1437         0, 1, 1, 3, 5, 5, 4, 7, 8, 9, 10, 11, 12, 14, 15, 16,
1438         0, 1, 1, 5, 5, 5, 5, 5, 7, 8, 9, 10, 11, 12, 14, 31 };
1439 static int proc_src_sel[] = { 0, 6, 7, 6, 7, 8, 5, NA, NA, NA,
1440   NA, NA, NA, NA, NA,  1,  2,  3,  4,  7,  8, NA, 8, NA };
1441 static int disp_src_sel[] = { 0, 6, 7, 8, 3, 4, 5, NA, NA, NA,
1442   NA, NA, NA, NA, NA,  1, NA,  2, NA,  3,  4,  4,  4,  4 };
1443
1444
1445 /*!
1446  * This function links 2 channels together for automatic frame
1447  * synchronization. The output of the source channel is linked to the input of
1448  * the destination channel.
1449  *
1450  * @param       src_ch          Input parameter for the logical channel ID of
1451  *                              the source channel.
1452  *
1453  * @param       dest_ch         Input parameter for the logical channel ID of
1454  *                              the destination channel.
1455  *
1456  * @return      This function returns 0 on success or negative error code on
1457  *              fail.
1458  */
1459 int32_t ipu_link_channels(ipu_channel_t src_ch, ipu_channel_t dest_ch)
1460 {
1461         int retval = 0;
1462         unsigned long lock_flags;
1463         uint32_t fs_proc_flow1;
1464         uint32_t fs_proc_flow2;
1465         uint32_t fs_proc_flow3;
1466         uint32_t fs_disp_flow1;
1467
1468         spin_lock_irqsave(&ipu_lock, lock_flags);
1469
1470         fs_proc_flow1 = __raw_readl(IPU_FS_PROC_FLOW1);
1471         fs_proc_flow2 = __raw_readl(IPU_FS_PROC_FLOW2);
1472         fs_proc_flow3 = __raw_readl(IPU_FS_PROC_FLOW3);
1473         fs_disp_flow1 = __raw_readl(IPU_FS_DISP_FLOW1);
1474
1475         switch (src_ch) {
1476         case CSI_MEM0:
1477                 fs_proc_flow3 &= ~FS_SMFC0_DEST_SEL_MASK;
1478                 fs_proc_flow3 |=
1479                         proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1480                         FS_SMFC0_DEST_SEL_OFFSET;
1481                 break;
1482         case CSI_MEM1:
1483                 fs_proc_flow3 &= ~FS_SMFC1_DEST_SEL_MASK;
1484                 fs_proc_flow3 |=
1485                         proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1486                         FS_SMFC1_DEST_SEL_OFFSET;
1487                 break;
1488         case CSI_MEM2:
1489                 fs_proc_flow3 &= ~FS_SMFC2_DEST_SEL_MASK;
1490                 fs_proc_flow3 |=
1491                         proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1492                         FS_SMFC2_DEST_SEL_OFFSET;
1493                 break;
1494         case CSI_MEM3:
1495                 fs_proc_flow3 &= ~FS_SMFC3_DEST_SEL_MASK;
1496                 fs_proc_flow3 |=
1497                         proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1498                         FS_SMFC3_DEST_SEL_OFFSET;
1499                 break;
1500         case CSI_PRP_ENC_MEM:
1501                 fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
1502                 fs_proc_flow2 |=
1503                         proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1504                         FS_PRPENC_DEST_SEL_OFFSET;
1505                 break;
1506         case CSI_PRP_VF_MEM:
1507                 fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
1508                 fs_proc_flow2 |=
1509                         proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1510                         FS_PRPVF_DEST_SEL_OFFSET;
1511                 break;
1512         case MEM_PP_MEM:
1513                 fs_proc_flow2 &= ~FS_PP_DEST_SEL_MASK;
1514                 fs_proc_flow2 |=
1515                     proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1516                     FS_PP_DEST_SEL_OFFSET;
1517                 break;
1518         case MEM_ROT_PP_MEM:
1519                 fs_proc_flow2 &= ~FS_PP_ROT_DEST_SEL_MASK;
1520                 fs_proc_flow2 |=
1521                     proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1522                     FS_PP_ROT_DEST_SEL_OFFSET;
1523                 break;
1524         case MEM_PRP_ENC_MEM:
1525                 fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
1526                 fs_proc_flow2 |=
1527                     proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1528                     FS_PRPENC_DEST_SEL_OFFSET;
1529                 break;
1530         case MEM_ROT_ENC_MEM:
1531                 fs_proc_flow2 &= ~FS_PRPENC_ROT_DEST_SEL_MASK;
1532                 fs_proc_flow2 |=
1533                     proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1534                     FS_PRPENC_ROT_DEST_SEL_OFFSET;
1535                 break;
1536         case MEM_PRP_VF_MEM:
1537                 fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
1538                 fs_proc_flow2 |=
1539                     proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1540                     FS_PRPVF_DEST_SEL_OFFSET;
1541                 break;
1542         case MEM_VDI_PRP_VF_MEM:
1543                 fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
1544                 fs_proc_flow2 |=
1545                     proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1546                     FS_PRPVF_DEST_SEL_OFFSET;
1547                 break;
1548         case MEM_ROT_VF_MEM:
1549                 fs_proc_flow2 &= ~FS_PRPVF_ROT_DEST_SEL_MASK;
1550                 fs_proc_flow2 |=
1551                     proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1552                     FS_PRPVF_ROT_DEST_SEL_OFFSET;
1553                 break;
1554         default:
1555                 retval = -EINVAL;
1556                 goto err;
1557         }
1558
1559         switch (dest_ch) {
1560         case MEM_PP_MEM:
1561                 fs_proc_flow1 &= ~FS_PP_SRC_SEL_MASK;
1562                 fs_proc_flow1 |=
1563                     proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PP_SRC_SEL_OFFSET;
1564                 break;
1565         case MEM_ROT_PP_MEM:
1566                 fs_proc_flow1 &= ~FS_PP_ROT_SRC_SEL_MASK;
1567                 fs_proc_flow1 |=
1568                     proc_src_sel[IPU_CHAN_ID(src_ch)] <<
1569                     FS_PP_ROT_SRC_SEL_OFFSET;
1570                 break;
1571         case MEM_PRP_ENC_MEM:
1572                 fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
1573                 fs_proc_flow1 |=
1574                     proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET;
1575                 break;
1576         case MEM_ROT_ENC_MEM:
1577                 fs_proc_flow1 &= ~FS_PRPENC_ROT_SRC_SEL_MASK;
1578                 fs_proc_flow1 |=
1579                     proc_src_sel[IPU_CHAN_ID(src_ch)] <<
1580                     FS_PRPENC_ROT_SRC_SEL_OFFSET;
1581                 break;
1582         case MEM_PRP_VF_MEM:
1583                 fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
1584                 fs_proc_flow1 |=
1585                     proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET;
1586                 break;
1587         case MEM_VDI_PRP_VF_MEM:
1588                 fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
1589                 fs_proc_flow1 |=
1590                     proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET;
1591                 break;
1592         case MEM_ROT_VF_MEM:
1593                 fs_proc_flow1 &= ~FS_PRPVF_ROT_SRC_SEL_MASK;
1594                 fs_proc_flow1 |=
1595                     proc_src_sel[IPU_CHAN_ID(src_ch)] <<
1596                     FS_PRPVF_ROT_SRC_SEL_OFFSET;
1597                 break;
1598         case MEM_DC_SYNC:
1599                 fs_disp_flow1 &= ~FS_DC1_SRC_SEL_MASK;
1600                 fs_disp_flow1 |=
1601                     disp_src_sel[IPU_CHAN_ID(src_ch)] << FS_DC1_SRC_SEL_OFFSET;
1602                 break;
1603         case MEM_BG_SYNC:
1604                 fs_disp_flow1 &= ~FS_DP_SYNC0_SRC_SEL_MASK;
1605                 fs_disp_flow1 |=
1606                     disp_src_sel[IPU_CHAN_ID(src_ch)] <<
1607                     FS_DP_SYNC0_SRC_SEL_OFFSET;
1608                 break;
1609         case MEM_FG_SYNC:
1610                 fs_disp_flow1 &= ~FS_DP_SYNC1_SRC_SEL_MASK;
1611                 fs_disp_flow1 |=
1612                     disp_src_sel[IPU_CHAN_ID(src_ch)] <<
1613                     FS_DP_SYNC1_SRC_SEL_OFFSET;
1614                 break;
1615         case MEM_DC_ASYNC:
1616                 fs_disp_flow1 &= ~FS_DC2_SRC_SEL_MASK;
1617                 fs_disp_flow1 |=
1618                     disp_src_sel[IPU_CHAN_ID(src_ch)] << FS_DC2_SRC_SEL_OFFSET;
1619                 break;
1620         case MEM_BG_ASYNC0:
1621                 fs_disp_flow1 &= ~FS_DP_ASYNC0_SRC_SEL_MASK;
1622                 fs_disp_flow1 |=
1623                     disp_src_sel[IPU_CHAN_ID(src_ch)] <<
1624                     FS_DP_ASYNC0_SRC_SEL_OFFSET;
1625                 break;
1626         case MEM_FG_ASYNC0:
1627                 fs_disp_flow1 &= ~FS_DP_ASYNC1_SRC_SEL_MASK;
1628                 fs_disp_flow1 |=
1629                     disp_src_sel[IPU_CHAN_ID(src_ch)] <<
1630                     FS_DP_ASYNC1_SRC_SEL_OFFSET;
1631                 break;
1632         default:
1633                 retval = -EINVAL;
1634                 goto err;
1635         }
1636
1637         __raw_writel(fs_proc_flow1, IPU_FS_PROC_FLOW1);
1638         __raw_writel(fs_proc_flow2, IPU_FS_PROC_FLOW2);
1639         __raw_writel(fs_proc_flow3, IPU_FS_PROC_FLOW3);
1640         __raw_writel(fs_disp_flow1, IPU_FS_DISP_FLOW1);
1641
1642 err:
1643         spin_unlock_irqrestore(&ipu_lock, lock_flags);
1644         return retval;
1645 }
1646 EXPORT_SYMBOL(ipu_link_channels);
1647
1648 /*!
1649  * This function unlinks 2 channels and disables automatic frame
1650  * synchronization.
1651  *
1652  * @param       src_ch          Input parameter for the logical channel ID of
1653  *                              the source channel.
1654  *
1655  * @param       dest_ch         Input parameter for the logical channel ID of
1656  *                              the destination channel.
1657  *
1658  * @return      This function returns 0 on success or negative error code on
1659  *              fail.
1660  */
1661 int32_t ipu_unlink_channels(ipu_channel_t src_ch, ipu_channel_t dest_ch)
1662 {
1663         int retval = 0;
1664         unsigned long lock_flags;
1665         uint32_t fs_proc_flow1;
1666         uint32_t fs_proc_flow2;
1667         uint32_t fs_proc_flow3;
1668         uint32_t fs_disp_flow1;
1669
1670         spin_lock_irqsave(&ipu_lock, lock_flags);
1671
1672         fs_proc_flow1 = __raw_readl(IPU_FS_PROC_FLOW1);
1673         fs_proc_flow2 = __raw_readl(IPU_FS_PROC_FLOW2);
1674         fs_proc_flow3 = __raw_readl(IPU_FS_PROC_FLOW3);
1675         fs_disp_flow1 = __raw_readl(IPU_FS_DISP_FLOW1);
1676
1677         switch (src_ch) {
1678         case CSI_MEM0:
1679                 fs_proc_flow3 &= ~FS_SMFC0_DEST_SEL_MASK;
1680                 break;
1681         case CSI_MEM1:
1682                 fs_proc_flow3 &= ~FS_SMFC1_DEST_SEL_MASK;
1683                 break;
1684         case CSI_MEM2:
1685                 fs_proc_flow3 &= ~FS_SMFC2_DEST_SEL_MASK;
1686                 break;
1687         case CSI_MEM3:
1688                 fs_proc_flow3 &= ~FS_SMFC3_DEST_SEL_MASK;
1689                 break;
1690         case CSI_PRP_ENC_MEM:
1691                 fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
1692                 break;
1693         case CSI_PRP_VF_MEM:
1694                 fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
1695                 break;
1696         case MEM_PP_MEM:
1697                 fs_proc_flow2 &= ~FS_PP_DEST_SEL_MASK;
1698                 break;
1699         case MEM_ROT_PP_MEM:
1700                 fs_proc_flow2 &= ~FS_PP_ROT_DEST_SEL_MASK;
1701                 break;
1702         case MEM_PRP_ENC_MEM:
1703                 fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
1704                 break;
1705         case MEM_ROT_ENC_MEM:
1706                 fs_proc_flow2 &= ~FS_PRPENC_ROT_DEST_SEL_MASK;
1707                 break;
1708         case MEM_PRP_VF_MEM:
1709                 fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
1710                 break;
1711         case MEM_VDI_PRP_VF_MEM:
1712                 fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
1713                 break;
1714         case MEM_ROT_VF_MEM:
1715                 fs_proc_flow2 &= ~FS_PRPVF_ROT_DEST_SEL_MASK;
1716                 break;
1717         default:
1718                 retval = -EINVAL;
1719                 goto err;
1720         }
1721
1722         switch (dest_ch) {
1723         case MEM_PP_MEM:
1724                 fs_proc_flow1 &= ~FS_PP_SRC_SEL_MASK;
1725                 break;
1726         case MEM_ROT_PP_MEM:
1727                 fs_proc_flow1 &= ~FS_PP_ROT_SRC_SEL_MASK;
1728                 break;
1729         case MEM_PRP_ENC_MEM:
1730                 fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
1731                 break;
1732         case MEM_ROT_ENC_MEM:
1733                 fs_proc_flow1 &= ~FS_PRPENC_ROT_SRC_SEL_MASK;
1734                 break;
1735         case MEM_PRP_VF_MEM:
1736                 fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
1737                 break;
1738         case MEM_VDI_PRP_VF_MEM:
1739                 fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
1740                 break;
1741         case MEM_ROT_VF_MEM:
1742                 fs_proc_flow1 &= ~FS_PRPVF_ROT_SRC_SEL_MASK;
1743                 break;
1744         case MEM_DC_SYNC:
1745                 fs_disp_flow1 &= ~FS_DC1_SRC_SEL_MASK;
1746                 break;
1747         case MEM_BG_SYNC:
1748                 fs_disp_flow1 &= ~FS_DP_SYNC0_SRC_SEL_MASK;
1749                 break;
1750         case MEM_FG_SYNC:
1751                 fs_disp_flow1 &= ~FS_DP_SYNC1_SRC_SEL_MASK;
1752                 break;
1753         case MEM_DC_ASYNC:
1754                 fs_disp_flow1 &= ~FS_DC2_SRC_SEL_MASK;
1755                 break;
1756         case MEM_BG_ASYNC0:
1757                 fs_disp_flow1 &= ~FS_DP_ASYNC0_SRC_SEL_MASK;
1758                 break;
1759         case MEM_FG_ASYNC0:
1760                 fs_disp_flow1 &= ~FS_DP_ASYNC1_SRC_SEL_MASK;
1761                 break;
1762         default:
1763                 retval = -EINVAL;
1764                 goto err;
1765         }
1766
1767         __raw_writel(fs_proc_flow1, IPU_FS_PROC_FLOW1);
1768         __raw_writel(fs_proc_flow2, IPU_FS_PROC_FLOW2);
1769         __raw_writel(fs_proc_flow3, IPU_FS_PROC_FLOW3);
1770         __raw_writel(fs_disp_flow1, IPU_FS_DISP_FLOW1);
1771
1772 err:
1773         spin_unlock_irqrestore(&ipu_lock, lock_flags);
1774         return retval;
1775 }
1776 EXPORT_SYMBOL(ipu_unlink_channels);
1777
1778 /*!
1779  * This function check whether a logical channel was enabled.
1780  *
1781  * @param       channel         Input parameter for the logical channel ID.
1782  *
1783  * @return      This function returns 1 while request channel is enabled or
1784  *              0 for not enabled.
1785  */
1786 int32_t ipu_is_channel_busy(ipu_channel_t channel)
1787 {
1788         uint32_t reg;
1789         uint32_t in_dma;
1790         uint32_t out_dma;
1791
1792         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
1793         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1794
1795         reg = __raw_readl(IDMAC_CHA_EN(in_dma));
1796         if (reg & idma_mask(in_dma))
1797                 return 1;
1798         reg = __raw_readl(IDMAC_CHA_EN(out_dma));
1799         if (reg & idma_mask(out_dma))
1800                 return 1;
1801         return 0;
1802 }
1803 EXPORT_SYMBOL(ipu_is_channel_busy);
1804
1805 /*!
1806  * This function enables a logical channel.
1807  *
1808  * @param       channel         Input parameter for the logical channel ID.
1809  *
1810  * @return      This function returns 0 on success or negative error code on
1811  *              fail.
1812  */
1813 int32_t ipu_enable_channel(ipu_channel_t channel)
1814 {
1815         uint32_t reg;
1816         unsigned long lock_flags;
1817         uint32_t ipu_conf;
1818         uint32_t in_dma;
1819         uint32_t out_dma;
1820         uint32_t sec_dma;
1821         uint32_t thrd_dma;
1822
1823         spin_lock_irqsave(&ipu_lock, lock_flags);
1824
1825         if (g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) {
1826                 dev_err(g_ipu_dev, "Warning: channel already enabled %d\n",
1827                         IPU_CHAN_ID(channel));
1828                 spin_unlock_irqrestore(&ipu_lock, lock_flags);
1829                 return -EACCES;
1830         }
1831
1832         /* Get input and output dma channels */
1833         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
1834         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1835
1836         ipu_conf = __raw_readl(IPU_CONF);
1837         if (ipu_di_use_count[0] > 0) {
1838                 ipu_conf |= IPU_CONF_DI0_EN;
1839         }
1840         if (ipu_di_use_count[1] > 0) {
1841                 ipu_conf |= IPU_CONF_DI1_EN;
1842         }
1843         if (ipu_dp_use_count > 0)
1844                 ipu_conf |= IPU_CONF_DP_EN;
1845         if (ipu_dc_use_count > 0)
1846                 ipu_conf |= IPU_CONF_DC_EN;
1847         if (ipu_dmfc_use_count > 0)
1848                 ipu_conf |= IPU_CONF_DMFC_EN;
1849         if (ipu_ic_use_count > 0)
1850                 ipu_conf |= IPU_CONF_IC_EN;
1851         if (ipu_vdi_use_count > 0) {
1852                 ipu_conf |= IPU_CONF_ISP_EN;
1853                 ipu_conf |= IPU_CONF_VDI_EN;
1854                 ipu_conf |= IPU_CONF_IC_INPUT;
1855         }
1856         if (ipu_rot_use_count > 0)
1857                 ipu_conf |= IPU_CONF_ROT_EN;
1858         if (ipu_smfc_use_count > 0)
1859                 ipu_conf |= IPU_CONF_SMFC_EN;
1860         __raw_writel(ipu_conf, IPU_CONF);
1861
1862         if (idma_is_valid(in_dma)) {
1863                 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
1864                 __raw_writel(reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
1865         }
1866         if (idma_is_valid(out_dma)) {
1867                 reg = __raw_readl(IDMAC_CHA_EN(out_dma));
1868                 __raw_writel(reg | idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
1869         }
1870
1871         if ((g_sec_chan_en[IPU_CHAN_ID(channel)]) &&
1872                 ((channel == MEM_PP_MEM) || (channel == MEM_PRP_VF_MEM) ||
1873                  (channel == MEM_VDI_PRP_VF_MEM))) {
1874                 sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
1875                 reg = __raw_readl(IDMAC_CHA_EN(sec_dma));
1876                 __raw_writel(reg | idma_mask(sec_dma), IDMAC_CHA_EN(sec_dma));
1877         }
1878         if ((g_thrd_chan_en[IPU_CHAN_ID(channel)]) &&
1879                 ((channel == MEM_PP_MEM) || (channel == MEM_PRP_VF_MEM))) {
1880                 thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);
1881                 reg = __raw_readl(IDMAC_CHA_EN(thrd_dma));
1882                 __raw_writel(reg | idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma));
1883
1884                 sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
1885                 reg = __raw_readl(IDMAC_SEP_ALPHA);
1886                 __raw_writel(reg | idma_mask(sec_dma), IDMAC_SEP_ALPHA);
1887         } else if ((g_thrd_chan_en[IPU_CHAN_ID(channel)]) &&
1888                    ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC))) {
1889                 thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);
1890                 reg = __raw_readl(IDMAC_CHA_EN(thrd_dma));
1891                 __raw_writel(reg | idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma));
1892                 reg = __raw_readl(IDMAC_SEP_ALPHA);
1893                 __raw_writel(reg | idma_mask(in_dma), IDMAC_SEP_ALPHA);
1894         }
1895
1896         if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) ||
1897             (channel == MEM_FG_SYNC)) {
1898                 reg = __raw_readl(IDMAC_WM_EN(in_dma));
1899                 __raw_writel(reg | idma_mask(in_dma), IDMAC_WM_EN(in_dma));
1900
1901                 _ipu_dp_dc_enable(channel);
1902         }
1903
1904         if (_ipu_is_ic_chan(in_dma) || _ipu_is_ic_chan(out_dma) ||
1905                 _ipu_is_irt_chan(in_dma) || _ipu_is_irt_chan(out_dma))
1906                 _ipu_ic_enable_task(channel);
1907
1908         g_channel_enable_mask |= 1L << IPU_CHAN_ID(channel);
1909
1910         spin_unlock_irqrestore(&ipu_lock, lock_flags);
1911
1912         return 0;
1913 }
1914 EXPORT_SYMBOL(ipu_enable_channel);
1915
1916 /*!
1917  * This function check buffer ready for a logical channel.
1918  *
1919  * @param       channel         Input parameter for the logical channel ID.
1920  *
1921  * @param       type            Input parameter which buffer to clear.
1922  *
1923  * @param       bufNum          Input parameter for which buffer number clear
1924  *                              ready state.
1925  *
1926  */
1927 int32_t ipu_check_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
1928                 uint32_t bufNum)
1929 {
1930         uint32_t dma_chan = channel_2_dma(channel, type);
1931         uint32_t reg;
1932
1933         if (dma_chan == IDMA_CHAN_INVALID)
1934                 return -EINVAL;
1935
1936         if (bufNum == 0)
1937                 reg = __raw_readl(IPU_CHA_BUF0_RDY(dma_chan));
1938         else if (bufNum == 1)
1939                 reg = __raw_readl(IPU_CHA_BUF1_RDY(dma_chan));
1940         else
1941                 reg = __raw_readl(IPU_CHA_BUF2_RDY(dma_chan));
1942
1943         if (reg & idma_mask(dma_chan))
1944                 return 1;
1945         else
1946                 return 0;
1947 }
1948 EXPORT_SYMBOL(ipu_check_buffer_ready);
1949
1950 /*!
1951  * This function clear buffer ready for a logical channel.
1952  *
1953  * @param       channel         Input parameter for the logical channel ID.
1954  *
1955  * @param       type            Input parameter which buffer to clear.
1956  *
1957  * @param       bufNum          Input parameter for which buffer number clear
1958  *                              ready state.
1959  *
1960  */
1961 void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
1962                 uint32_t bufNum)
1963 {
1964         unsigned long lock_flags;
1965         uint32_t dma_ch = channel_2_dma(channel, type);
1966
1967         if (!idma_is_valid(dma_ch))
1968                 return;
1969
1970         spin_lock_irqsave(&ipu_lock, lock_flags);
1971         __raw_writel(0xF0300000, IPU_GPR); /* write one to clear */
1972         if (bufNum == 0) {
1973                 if (idma_is_set(IPU_CHA_BUF0_RDY, dma_ch)) {
1974                         __raw_writel(idma_mask(dma_ch),
1975                                         IPU_CHA_BUF0_RDY(dma_ch));
1976                 }
1977         } else if (bufNum == 1) {
1978                 if (idma_is_set(IPU_CHA_BUF1_RDY, dma_ch)) {
1979                         __raw_writel(idma_mask(dma_ch),
1980                                         IPU_CHA_BUF1_RDY(dma_ch));
1981                 }
1982         } else {
1983                 if (idma_is_set(IPU_CHA_BUF2_RDY, dma_ch)) {
1984                         __raw_writel(idma_mask(dma_ch),
1985                                         IPU_CHA_BUF2_RDY(dma_ch));
1986                 }
1987         }
1988         __raw_writel(0x0, IPU_GPR); /* write one to set */
1989         spin_unlock_irqrestore(&ipu_lock, lock_flags);
1990 }
1991 EXPORT_SYMBOL(ipu_clear_buffer_ready);
1992
1993 static irqreturn_t disable_chan_irq_handler(int irq, void *dev_id)
1994 {
1995         struct completion *comp = dev_id;
1996
1997         complete(comp);
1998         return IRQ_HANDLED;
1999 }
2000
2001 /*!
2002  * This function disables a logical channel.
2003  *
2004  * @param       channel         Input parameter for the logical channel ID.
2005  *
2006  * @param       wait_for_stop   Flag to set whether to wait for channel end
2007  *                              of frame or return immediately.
2008  *
2009  * @return      This function returns 0 on success or negative error code on
2010  *              fail.
2011  */
2012 int32_t ipu_disable_channel(ipu_channel_t channel, bool wait_for_stop)
2013 {
2014         uint32_t reg;
2015         unsigned long lock_flags;
2016         uint32_t in_dma;
2017         uint32_t out_dma;
2018         uint32_t sec_dma = NO_DMA;
2019         uint32_t thrd_dma = NO_DMA;
2020
2021         spin_lock_irqsave(&ipu_lock, lock_flags);
2022
2023         if ((g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
2024                 dev_err(g_ipu_dev, "Channel already disabled %d\n",
2025                         IPU_CHAN_ID(channel));
2026                 spin_unlock_irqrestore(&ipu_lock, lock_flags);
2027                 return -EACCES;
2028         }
2029
2030         spin_unlock_irqrestore(&ipu_lock, lock_flags);
2031
2032         /* Get input and output dma channels */
2033         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
2034         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
2035
2036         if ((idma_is_valid(in_dma) &&
2037                 !idma_is_set(IDMAC_CHA_EN, in_dma))
2038                 && (idma_is_valid(out_dma) &&
2039                 !idma_is_set(IDMAC_CHA_EN, out_dma)))
2040                 return -EINVAL;
2041
2042         if (g_sec_chan_en[IPU_CHAN_ID(channel)])
2043                 sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
2044         if (g_thrd_chan_en[IPU_CHAN_ID(channel)]) {
2045                 sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
2046                 thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);
2047         }
2048
2049         if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
2050             (channel == MEM_DC_SYNC)) {
2051                 if (channel == MEM_FG_SYNC)
2052                         ipu_disp_set_window_pos(channel, 0, 0);
2053
2054                 _ipu_dp_dc_disable(channel, false);
2055
2056                 /*
2057                  * wait for BG channel EOF then disable FG-IDMAC,
2058                  * it avoid FG NFB4EOF error.
2059                  */
2060                 if (channel == MEM_FG_SYNC) {
2061                         int timeout = 50;
2062
2063                         __raw_writel(IPUIRQ_2_MASK(IPU_IRQ_BG_SYNC_EOF),
2064                                         IPUIRQ_2_STATREG(IPU_IRQ_BG_SYNC_EOF));
2065                         while ((__raw_readl(IPUIRQ_2_STATREG(IPU_IRQ_BG_SYNC_EOF)) &
2066                                         IPUIRQ_2_MASK(IPU_IRQ_BG_SYNC_EOF)) == 0) {
2067                                 msleep(10);
2068                                 timeout -= 10;
2069                                 if (timeout <= 0) {
2070                                         dev_err(g_ipu_dev, "warning: wait for bg sync eof timeout\n");
2071                                         break;
2072                                 }
2073                         }
2074                 }
2075         } else if (wait_for_stop) {
2076                 while (idma_is_set(IDMAC_CHA_BUSY, in_dma) ||
2077                        idma_is_set(IDMAC_CHA_BUSY, out_dma) ||
2078                         (g_sec_chan_en[IPU_CHAN_ID(channel)] &&
2079                         idma_is_set(IDMAC_CHA_BUSY, sec_dma)) ||
2080                         (g_thrd_chan_en[IPU_CHAN_ID(channel)] &&
2081                         idma_is_set(IDMAC_CHA_BUSY, thrd_dma))) {
2082                         uint32_t ret, irq = 0xffffffff;
2083                         DECLARE_COMPLETION_ONSTACK(disable_comp);
2084
2085                         if (idma_is_set(IDMAC_CHA_BUSY, out_dma))
2086                                 irq = out_dma;
2087                         if (g_sec_chan_en[IPU_CHAN_ID(channel)] &&
2088                                 idma_is_set(IDMAC_CHA_BUSY, sec_dma))
2089                                 irq = sec_dma;
2090                         if (g_thrd_chan_en[IPU_CHAN_ID(channel)] &&
2091                                 idma_is_set(IDMAC_CHA_BUSY, thrd_dma))
2092                                 irq = thrd_dma;
2093                         if (idma_is_set(IDMAC_CHA_BUSY, in_dma))
2094                                 irq = in_dma;
2095
2096                         if (irq == 0xffffffff) {
2097                                 dev_err(g_ipu_dev, "warning: no channel busy, break\n");
2098                                 break;
2099                         }
2100                         ret = ipu_request_irq(irq, disable_chan_irq_handler, 0, NULL, &disable_comp);
2101                         if (ret < 0) {
2102                                 dev_err(g_ipu_dev, "irq %d in use\n", irq);
2103                                 break;
2104                         } else {
2105                                 ret = wait_for_completion_timeout(&disable_comp, msecs_to_jiffies(200));
2106                                 ipu_free_irq(irq, &disable_comp);
2107                                 if (ret == 0) {
2108                                         ipu_dump_registers();
2109                                         dev_err(g_ipu_dev, "warning: disable ipu dma channel %d during its busy state\n", irq);
2110                                         break;
2111                                 }
2112                         }
2113                 }
2114         }
2115
2116         spin_lock_irqsave(&ipu_lock, lock_flags);
2117
2118         if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
2119             (channel == MEM_DC_SYNC)) {
2120                 reg = __raw_readl(IDMAC_WM_EN(in_dma));
2121                 __raw_writel(reg & ~idma_mask(in_dma), IDMAC_WM_EN(in_dma));
2122         }
2123
2124         /* Disable IC task */
2125         if (_ipu_is_ic_chan(in_dma) || _ipu_is_ic_chan(out_dma) ||
2126                 _ipu_is_irt_chan(in_dma) || _ipu_is_irt_chan(out_dma))
2127                 _ipu_ic_disable_task(channel);
2128
2129         /* Disable DMA channel(s) */
2130         if (idma_is_valid(in_dma)) {
2131                 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
2132                 __raw_writel(reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
2133                 __raw_writel(idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma));
2134                 __raw_writel(tri_cur_buf_mask(in_dma),
2135                                         IPU_CHA_TRIPLE_CUR_BUF(in_dma));
2136         }
2137         if (idma_is_valid(out_dma)) {
2138                 reg = __raw_readl(IDMAC_CHA_EN(out_dma));
2139                 __raw_writel(reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
2140                 __raw_writel(idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma));
2141                 __raw_writel(tri_cur_buf_mask(out_dma),
2142                                         IPU_CHA_TRIPLE_CUR_BUF(out_dma));
2143         }
2144         if (g_sec_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(sec_dma)) {
2145                 reg = __raw_readl(IDMAC_CHA_EN(sec_dma));
2146                 __raw_writel(reg & ~idma_mask(sec_dma), IDMAC_CHA_EN(sec_dma));
2147                 __raw_writel(idma_mask(sec_dma), IPU_CHA_CUR_BUF(sec_dma));
2148         }
2149         if (g_thrd_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(thrd_dma)) {
2150                 reg = __raw_readl(IDMAC_CHA_EN(thrd_dma));
2151                 __raw_writel(reg & ~idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma));
2152                 if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) {
2153                         reg = __raw_readl(IDMAC_SEP_ALPHA);
2154                         __raw_writel(reg & ~idma_mask(in_dma), IDMAC_SEP_ALPHA);
2155                 } else {
2156                         reg = __raw_readl(IDMAC_SEP_ALPHA);
2157                         __raw_writel(reg & ~idma_mask(sec_dma), IDMAC_SEP_ALPHA);
2158                 }
2159                 __raw_writel(idma_mask(thrd_dma), IPU_CHA_CUR_BUF(thrd_dma));
2160         }
2161
2162         g_channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel));
2163
2164         spin_unlock_irqrestore(&ipu_lock, lock_flags);
2165
2166         /* Set channel buffers NOT to be ready */
2167         if (idma_is_valid(in_dma)) {
2168                 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 0);
2169                 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 1);
2170                 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 2);
2171         }
2172         if (idma_is_valid(out_dma)) {
2173                 ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 0);
2174                 ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 1);
2175         }
2176         if (g_sec_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(sec_dma)) {
2177                 ipu_clear_buffer_ready(channel, IPU_GRAPH_IN_BUFFER, 0);
2178                 ipu_clear_buffer_ready(channel, IPU_GRAPH_IN_BUFFER, 1);
2179         }
2180         if (g_thrd_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(thrd_dma)) {
2181                 ipu_clear_buffer_ready(channel, IPU_ALPHA_IN_BUFFER, 0);
2182                 ipu_clear_buffer_ready(channel, IPU_ALPHA_IN_BUFFER, 1);
2183         }
2184
2185         return 0;
2186 }
2187 EXPORT_SYMBOL(ipu_disable_channel);
2188
2189 /*!
2190  * This function enables CSI.
2191  *
2192  * @param       csi     csi num 0 or 1
2193  *
2194  * @return      This function returns 0 on success or negative error code on
2195  *              fail.
2196  */
2197 int32_t ipu_enable_csi(uint32_t csi)
2198 {
2199         uint32_t reg;
2200         unsigned long lock_flags;
2201
2202         if (csi > 1) {
2203                 dev_err(g_ipu_dev, "Wrong csi num_%d\n", csi);
2204                 return -EINVAL;
2205         }
2206
2207         spin_lock_irqsave(&ipu_lock, lock_flags);
2208         ipu_csi_use_count[csi]++;
2209
2210         if (ipu_csi_use_count[csi] == 1) {
2211                 reg = __raw_readl(IPU_CONF);
2212                 if (csi == 0)
2213                         __raw_writel(reg | IPU_CONF_CSI0_EN, IPU_CONF);
2214                 else
2215                         __raw_writel(reg | IPU_CONF_CSI1_EN, IPU_CONF);
2216         }
2217         spin_unlock_irqrestore(&ipu_lock, lock_flags);
2218         return 0;
2219 }
2220 EXPORT_SYMBOL(ipu_enable_csi);
2221
2222 /*!
2223  * This function disables CSI.
2224  *
2225  * @param       csi     csi num 0 or 1
2226  *
2227  * @return      This function returns 0 on success or negative error code on
2228  *              fail.
2229  */
2230 int32_t ipu_disable_csi(uint32_t csi)
2231 {
2232         uint32_t reg;
2233         unsigned long lock_flags;
2234
2235         if (csi > 1) {
2236                 dev_err(g_ipu_dev, "Wrong csi num_%d\n", csi);
2237                 return -EINVAL;
2238         }
2239
2240         spin_lock_irqsave(&ipu_lock, lock_flags);
2241         ipu_csi_use_count[csi]--;
2242
2243         if (ipu_csi_use_count[csi] == 0) {
2244                 reg = __raw_readl(IPU_CONF);
2245                 if (csi == 0)
2246                         __raw_writel(reg & ~IPU_CONF_CSI0_EN, IPU_CONF);
2247                 else
2248                         __raw_writel(reg & ~IPU_CONF_CSI1_EN, IPU_CONF);
2249         }
2250         spin_unlock_irqrestore(&ipu_lock, lock_flags);
2251         return 0;
2252 }
2253 EXPORT_SYMBOL(ipu_disable_csi);
2254
2255 static irqreturn_t ipu_irq_handler(int irq, void *desc)
2256 {
2257         int i;
2258         uint32_t line;
2259         irqreturn_t result = IRQ_NONE;
2260         uint32_t int_stat;
2261         const int err_reg[] = { 5, 6, 9, 10, 0 };
2262         const int int_reg[] = { 1, 2, 3, 4, 11, 12, 13, 14, 15, 0 };
2263
2264         for (i = 0;; i++) {
2265                 if (err_reg[i] == 0)
2266                         break;
2267                 int_stat = __raw_readl(IPU_INT_STAT(err_reg[i]));
2268                 int_stat &= __raw_readl(IPU_INT_CTRL(err_reg[i]));
2269                 if (int_stat) {
2270                         __raw_writel(int_stat, IPU_INT_STAT(err_reg[i]));
2271                         dev_err(g_ipu_dev,
2272                                 "IPU Error - IPU_INT_STAT_%d = 0x%08X\n",
2273                                 err_reg[i], int_stat);
2274                         /* Disable interrupts so we only get error once */
2275                         int_stat =
2276                             __raw_readl(IPU_INT_CTRL(err_reg[i])) & ~int_stat;
2277                         __raw_writel(int_stat, IPU_INT_CTRL(err_reg[i]));
2278                 }
2279         }
2280
2281         for (i = 0;; i++) {
2282                 if (int_reg[i] == 0)
2283                         break;
2284                 int_stat = __raw_readl(IPU_INT_STAT(int_reg[i]));
2285                 int_stat &= __raw_readl(IPU_INT_CTRL(int_reg[i]));
2286                 __raw_writel(int_stat, IPU_INT_STAT(int_reg[i]));
2287                 while ((line = ffs(int_stat)) != 0) {
2288                         line--;
2289                         int_stat &= ~(1UL << line);
2290                         line += (int_reg[i] - 1) * 32;
2291                         result |=
2292                             ipu_irq_list[line].handler(line,
2293                                                        ipu_irq_list[line].
2294                                                        dev_id);
2295                 }
2296         }
2297
2298         return result;
2299 }
2300
2301 /*!
2302  * This function enables the interrupt for the specified interrupt line.
2303  * The interrupt lines are defined in \b ipu_irq_line enum.
2304  *
2305  * @param       irq             Interrupt line to enable interrupt for.
2306  *
2307  */
2308 void ipu_enable_irq(uint32_t irq)
2309 {
2310         uint32_t reg;
2311         unsigned long lock_flags;
2312
2313         if (!g_ipu_clk_enabled)
2314                 clk_enable(g_ipu_clk);
2315
2316         spin_lock_irqsave(&ipu_lock, lock_flags);
2317
2318         reg = __raw_readl(IPUIRQ_2_CTRLREG(irq));
2319         reg |= IPUIRQ_2_MASK(irq);
2320         __raw_writel(reg, IPUIRQ_2_CTRLREG(irq));
2321
2322         spin_unlock_irqrestore(&ipu_lock, lock_flags);
2323         if (!g_ipu_clk_enabled)
2324                 clk_disable(g_ipu_clk);
2325 }
2326 EXPORT_SYMBOL(ipu_enable_irq);
2327
2328 /*!
2329  * This function disables the interrupt for the specified interrupt line.
2330  * The interrupt lines are defined in \b ipu_irq_line enum.
2331  *
2332  * @param       irq             Interrupt line to disable interrupt for.
2333  *
2334  */
2335 void ipu_disable_irq(uint32_t irq)
2336 {
2337         uint32_t reg;
2338         unsigned long lock_flags;
2339
2340         if (!g_ipu_clk_enabled)
2341                 clk_enable(g_ipu_clk);
2342         spin_lock_irqsave(&ipu_lock, lock_flags);
2343
2344         reg = __raw_readl(IPUIRQ_2_CTRLREG(irq));
2345         reg &= ~IPUIRQ_2_MASK(irq);
2346         __raw_writel(reg, IPUIRQ_2_CTRLREG(irq));
2347
2348         spin_unlock_irqrestore(&ipu_lock, lock_flags);
2349         if (!g_ipu_clk_enabled)
2350                 clk_disable(g_ipu_clk);
2351 }
2352 EXPORT_SYMBOL(ipu_disable_irq);
2353
2354 /*!
2355  * This function clears the interrupt for the specified interrupt line.
2356  * The interrupt lines are defined in \b ipu_irq_line enum.
2357  *
2358  * @param       irq             Interrupt line to clear interrupt for.
2359  *
2360  */
2361 void ipu_clear_irq(uint32_t irq)
2362 {
2363         if (!g_ipu_clk_enabled)
2364                 clk_enable(g_ipu_clk);
2365
2366         __raw_writel(IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq));
2367
2368         if (!g_ipu_clk_enabled)
2369                 clk_disable(g_ipu_clk);
2370 }
2371 EXPORT_SYMBOL(ipu_clear_irq);
2372
2373 /*!
2374  * This function returns the current interrupt status for the specified
2375  * interrupt line. The interrupt lines are defined in \b ipu_irq_line enum.
2376  *
2377  * @param       irq             Interrupt line to get status for.
2378  *
2379  * @return      Returns true if the interrupt is pending/asserted or false if
2380  *              the interrupt is not pending.
2381  */
2382 bool ipu_get_irq_status(uint32_t irq)
2383 {
2384         uint32_t reg;
2385
2386         if (!g_ipu_clk_enabled)
2387                 clk_enable(g_ipu_clk);
2388
2389         reg = __raw_readl(IPUIRQ_2_STATREG(irq));
2390
2391         if (!g_ipu_clk_enabled)
2392                 clk_disable(g_ipu_clk);
2393
2394         if (reg & IPUIRQ_2_MASK(irq))
2395                 return true;
2396         else
2397                 return false;
2398 }
2399 EXPORT_SYMBOL(ipu_get_irq_status);
2400
2401 /*!
2402  * This function registers an interrupt handler function for the specified
2403  * interrupt line. The interrupt lines are defined in \b ipu_irq_line enum.
2404  *
2405  * @param       irq             Interrupt line to get status for.
2406  *
2407  * @param       handler         Input parameter for address of the handler
2408  *                              function.
2409  *
2410  * @param       irq_flags       Flags for interrupt mode. Currently not used.
2411  *
2412  * @param       devname         Input parameter for string name of driver
2413  *                              registering the handler.
2414  *
2415  * @param       dev_id          Input parameter for pointer of data to be
2416  *                              passed to the handler.
2417  *
2418  * @return      This function returns 0 on success or negative error code on
2419  *              fail.
2420  */
2421 int ipu_request_irq(uint32_t irq,
2422                     irqreturn_t(*handler) (int, void *),
2423                     uint32_t irq_flags, const char *devname, void *dev_id)
2424 {
2425         unsigned long lock_flags;
2426
2427         BUG_ON(irq >= IPU_IRQ_COUNT);
2428
2429         spin_lock_irqsave(&ipu_lock, lock_flags);
2430
2431         if (ipu_irq_list[irq].handler != NULL) {
2432                 dev_err(g_ipu_dev,
2433                         "handler already installed on irq %d\n", irq);
2434                 spin_unlock_irqrestore(&ipu_lock, lock_flags);
2435                 return -EINVAL;
2436         }
2437
2438         ipu_irq_list[irq].handler = handler;
2439         ipu_irq_list[irq].flags = irq_flags;
2440         ipu_irq_list[irq].dev_id = dev_id;
2441         ipu_irq_list[irq].name = devname;
2442
2443         spin_unlock_irqrestore(&ipu_lock, lock_flags);
2444
2445         ipu_enable_irq(irq);    /* enable the interrupt */
2446
2447         return 0;
2448 }
2449 EXPORT_SYMBOL(ipu_request_irq);
2450
2451 /*!
2452  * This function unregisters an interrupt handler for the specified interrupt
2453  * line. The interrupt lines are defined in \b ipu_irq_line enum.
2454  *
2455  * @param       irq             Interrupt line to get status for.
2456  *
2457  * @param       dev_id          Input parameter for pointer of data to be passed
2458  *                              to the handler. This must match value passed to
2459  *                              ipu_request_irq().
2460  *
2461  */
2462 void ipu_free_irq(uint32_t irq, void *dev_id)
2463 {
2464         ipu_disable_irq(irq);   /* disable the interrupt */
2465
2466         if (ipu_irq_list[irq].dev_id == dev_id)
2467                 ipu_irq_list[irq].handler = NULL;
2468 }
2469 EXPORT_SYMBOL(ipu_free_irq);
2470
2471 uint32_t ipu_get_cur_buffer_idx(ipu_channel_t channel, ipu_buffer_t type)
2472 {
2473         uint32_t reg, dma_chan;
2474
2475         dma_chan = channel_2_dma(channel, type);
2476         if (!idma_is_valid(dma_chan))
2477                 return -EINVAL;
2478
2479         reg = __raw_readl(IPU_CHA_TRB_MODE_SEL(dma_chan));
2480         if ((reg & idma_mask(dma_chan)) && _ipu_is_trb_chan(dma_chan)) {
2481                 reg = __raw_readl(IPU_CHA_TRIPLE_CUR_BUF(dma_chan));
2482                 return (reg & tri_cur_buf_mask(dma_chan)) >>
2483                                 tri_cur_buf_shift(dma_chan);
2484         } else {
2485                 reg = __raw_readl(IPU_CHA_CUR_BUF(dma_chan));
2486                 if (reg & idma_mask(dma_chan))
2487                         return 1;
2488                 else
2489                         return 0;
2490         }
2491 }
2492 EXPORT_SYMBOL(ipu_get_cur_buffer_idx);
2493
2494 uint32_t _ipu_channel_status(ipu_channel_t channel)
2495 {
2496         uint32_t stat = 0;
2497         uint32_t task_stat_reg = __raw_readl(IPU_PROC_TASK_STAT);
2498
2499         switch (channel) {
2500         case MEM_PRP_VF_MEM:
2501                 stat = (task_stat_reg & TSTAT_VF_MASK) >> TSTAT_VF_OFFSET;
2502                 break;
2503         case MEM_VDI_PRP_VF_MEM:
2504                 stat = (task_stat_reg & TSTAT_VF_MASK) >> TSTAT_VF_OFFSET;
2505                 break;
2506         case MEM_ROT_VF_MEM:
2507                 stat =
2508                     (task_stat_reg & TSTAT_VF_ROT_MASK) >> TSTAT_VF_ROT_OFFSET;
2509                 break;
2510         case MEM_PRP_ENC_MEM:
2511                 stat = (task_stat_reg & TSTAT_ENC_MASK) >> TSTAT_ENC_OFFSET;
2512                 break;
2513         case MEM_ROT_ENC_MEM:
2514                 stat =
2515                     (task_stat_reg & TSTAT_ENC_ROT_MASK) >>
2516                     TSTAT_ENC_ROT_OFFSET;
2517                 break;
2518         case MEM_PP_MEM:
2519                 stat = (task_stat_reg & TSTAT_PP_MASK) >> TSTAT_PP_OFFSET;
2520                 break;
2521         case MEM_ROT_PP_MEM:
2522                 stat =
2523                     (task_stat_reg & TSTAT_PP_ROT_MASK) >> TSTAT_PP_ROT_OFFSET;
2524                 break;
2525
2526         default:
2527                 stat = TASK_STAT_IDLE;
2528                 break;
2529         }
2530         return stat;
2531 }
2532
2533 int32_t ipu_swap_channel(ipu_channel_t from_ch, ipu_channel_t to_ch)
2534 {
2535         uint32_t reg;
2536         unsigned long lock_flags;
2537
2538         int from_dma = channel_2_dma(from_ch, IPU_INPUT_BUFFER);
2539         int to_dma = channel_2_dma(to_ch, IPU_INPUT_BUFFER);
2540
2541         /* enable target channel */
2542         spin_lock_irqsave(&ipu_lock, lock_flags);
2543
2544         reg = __raw_readl(IDMAC_CHA_EN(to_dma));
2545         __raw_writel(reg | idma_mask(to_dma), IDMAC_CHA_EN(to_dma));
2546
2547         g_channel_enable_mask |= 1L << IPU_CHAN_ID(to_ch);
2548
2549         spin_unlock_irqrestore(&ipu_lock, lock_flags);
2550
2551         /* switch dp dc */
2552         _ipu_dp_dc_disable(from_ch, true);
2553
2554         /* disable source channel */
2555         spin_lock_irqsave(&ipu_lock, lock_flags);
2556
2557         reg = __raw_readl(IDMAC_CHA_EN(from_dma));
2558         __raw_writel(reg & ~idma_mask(from_dma), IDMAC_CHA_EN(from_dma));
2559         __raw_writel(idma_mask(from_dma), IPU_CHA_CUR_BUF(from_dma));
2560         __raw_writel(tri_cur_buf_mask(from_dma),
2561                                 IPU_CHA_TRIPLE_CUR_BUF(from_dma));
2562
2563         g_channel_enable_mask &= ~(1L << IPU_CHAN_ID(from_ch));
2564
2565         spin_unlock_irqrestore(&ipu_lock, lock_flags);
2566
2567         ipu_clear_buffer_ready(from_ch, IPU_VIDEO_IN_BUFFER, 0);
2568         ipu_clear_buffer_ready(from_ch, IPU_VIDEO_IN_BUFFER, 1);
2569         ipu_clear_buffer_ready(from_ch, IPU_VIDEO_IN_BUFFER, 2);
2570
2571         return 0;
2572 }
2573 EXPORT_SYMBOL(ipu_swap_channel);
2574
2575 uint32_t bytes_per_pixel(uint32_t fmt)
2576 {
2577         switch (fmt) {
2578         case IPU_PIX_FMT_GENERIC:       /*generic data */
2579         case IPU_PIX_FMT_RGB332:
2580         case IPU_PIX_FMT_YUV420P:
2581         case IPU_PIX_FMT_YVU420P:
2582         case IPU_PIX_FMT_YUV422P:
2583                 return 1;
2584                 break;
2585         case IPU_PIX_FMT_RGB565:
2586         case IPU_PIX_FMT_YUYV:
2587         case IPU_PIX_FMT_UYVY:
2588                 return 2;
2589                 break;
2590         case IPU_PIX_FMT_BGR24:
2591         case IPU_PIX_FMT_RGB24:
2592                 return 3;
2593                 break;
2594         case IPU_PIX_FMT_GENERIC_32:    /*generic data */
2595         case IPU_PIX_FMT_BGR32:
2596         case IPU_PIX_FMT_BGRA32:
2597         case IPU_PIX_FMT_RGB32:
2598         case IPU_PIX_FMT_RGBA32:
2599         case IPU_PIX_FMT_ABGR32:
2600                 return 4;
2601                 break;
2602         default:
2603                 return 1;
2604                 break;
2605         }
2606         return 0;
2607 }
2608 EXPORT_SYMBOL(bytes_per_pixel);
2609
2610 ipu_color_space_t format_to_colorspace(uint32_t fmt)
2611 {
2612         switch (fmt) {
2613         case IPU_PIX_FMT_RGB666:
2614         case IPU_PIX_FMT_RGB565:
2615         case IPU_PIX_FMT_BGR24:
2616         case IPU_PIX_FMT_RGB24:
2617         case IPU_PIX_FMT_GBR24:
2618         case IPU_PIX_FMT_BGR32:
2619         case IPU_PIX_FMT_BGRA32:
2620         case IPU_PIX_FMT_RGB32:
2621         case IPU_PIX_FMT_RGBA32:
2622         case IPU_PIX_FMT_ABGR32:
2623         case IPU_PIX_FMT_LVDS666:
2624         case IPU_PIX_FMT_LVDS888:
2625                 return RGB;
2626                 break;
2627
2628         default:
2629                 return YCbCr;
2630                 break;
2631         }
2632         return RGB;
2633 }
2634
2635 bool ipu_pixel_format_has_alpha(uint32_t fmt)
2636 {
2637         switch (fmt) {
2638         case IPU_PIX_FMT_RGBA32:
2639         case IPU_PIX_FMT_BGRA32:
2640         case IPU_PIX_FMT_ABGR32:
2641                 return true;
2642                 break;
2643         default:
2644                 return false;
2645                 break;
2646         }
2647         return false;
2648 }
2649
2650 void ipu_set_csc_coefficients(ipu_channel_t channel, int32_t param[][3])
2651 {
2652         _ipu_dp_set_csc_coefficients(channel, param);
2653 }
2654 EXPORT_SYMBOL(ipu_set_csc_coefficients);
2655
2656 static int ipu_suspend(struct platform_device *pdev, pm_message_t state)
2657 {
2658         struct imx_ipuv3_platform_data *plat_data = pdev->dev.platform_data;
2659
2660         if (g_ipu_clk_enabled) {
2661                 /* save and disable enabled channels*/
2662                 idma_enable_reg[0] = __raw_readl(IDMAC_CHA_EN(0));
2663                 idma_enable_reg[1] = __raw_readl(IDMAC_CHA_EN(32));
2664                 while ((__raw_readl(IDMAC_CHA_BUSY(0)) & idma_enable_reg[0])
2665                         || (__raw_readl(IDMAC_CHA_BUSY(32)) &
2666                                 idma_enable_reg[1])) {
2667                         /* disable channel not busy already */
2668                         uint32_t chan_should_disable, timeout = 1000, time = 0;
2669
2670                         chan_should_disable =
2671                                 __raw_readl(IDMAC_CHA_BUSY(0))
2672                                         ^ idma_enable_reg[0];
2673                         __raw_writel((~chan_should_disable) &
2674                                         idma_enable_reg[0], IDMAC_CHA_EN(0));
2675                         chan_should_disable =
2676                                 __raw_readl(IDMAC_CHA_BUSY(1))
2677                                         ^ idma_enable_reg[1];
2678                         __raw_writel((~chan_should_disable) &
2679                                         idma_enable_reg[1], IDMAC_CHA_EN(32));
2680                         msleep(2);
2681                         time += 2;
2682                         if (time >= timeout)
2683                                 return -1;
2684                 }
2685                 __raw_writel(0, IDMAC_CHA_EN(0));
2686                 __raw_writel(0, IDMAC_CHA_EN(32));
2687
2688                 /* save double buffer select regs */
2689                 ipu_cha_db_mode_reg[0] = __raw_readl(IPU_CHA_DB_MODE_SEL(0));
2690                 ipu_cha_db_mode_reg[1] = __raw_readl(IPU_CHA_DB_MODE_SEL(32));
2691                 ipu_cha_db_mode_reg[2] =
2692                         __raw_readl(IPU_ALT_CHA_DB_MODE_SEL(0));
2693                 ipu_cha_db_mode_reg[3] =
2694                         __raw_readl(IPU_ALT_CHA_DB_MODE_SEL(32));
2695
2696                 /* save triple buffer select regs */
2697                 ipu_cha_trb_mode_reg[0] = __raw_readl(IPU_CHA_TRB_MODE_SEL(0));
2698                 ipu_cha_trb_mode_reg[1] = __raw_readl(IPU_CHA_TRB_MODE_SEL(32));
2699
2700                 /* save current buffer regs */
2701                 ipu_cha_cur_buf_reg[0] = __raw_readl(IPU_CHA_CUR_BUF(0));
2702                 ipu_cha_cur_buf_reg[1] = __raw_readl(IPU_CHA_CUR_BUF(32));
2703                 ipu_cha_cur_buf_reg[2] = __raw_readl(IPU_ALT_CUR_BUF0);
2704                 ipu_cha_cur_buf_reg[3] = __raw_readl(IPU_ALT_CUR_BUF1);
2705
2706                 /* save current triple buffer regs */
2707                 ipu_cha_triple_cur_buf_reg[0] =
2708                                         __raw_readl(IPU_CHA_TRIPLE_CUR_BUF(0));
2709                 ipu_cha_triple_cur_buf_reg[1] =
2710                                         __raw_readl(IPU_CHA_TRIPLE_CUR_BUF(32));
2711                 ipu_cha_triple_cur_buf_reg[2] =
2712                                         __raw_readl(IPU_CHA_TRIPLE_CUR_BUF(64));
2713                 ipu_cha_triple_cur_buf_reg[3] =
2714                                         __raw_readl(IPU_CHA_TRIPLE_CUR_BUF(96));
2715
2716                 /* save idamc sub addr regs */
2717                 idma_sub_addr_reg[0] = __raw_readl(IDMAC_SUB_ADDR_0);
2718                 idma_sub_addr_reg[1] = __raw_readl(IDMAC_SUB_ADDR_1);
2719                 idma_sub_addr_reg[2] = __raw_readl(IDMAC_SUB_ADDR_2);
2720                 idma_sub_addr_reg[3] = __raw_readl(IDMAC_SUB_ADDR_3);
2721                 idma_sub_addr_reg[4] = __raw_readl(IDMAC_SUB_ADDR_4);
2722
2723                 /* save sub-modules status and disable all */
2724                 ic_conf_reg = __raw_readl(IC_CONF);
2725                 __raw_writel(0, IC_CONF);
2726                 ipu_conf_reg = __raw_readl(IPU_CONF);
2727                 __raw_writel(0, IPU_CONF);
2728
2729                 /* save buf ready regs */
2730                 buf_ready_reg[0] = __raw_readl(IPU_CHA_BUF0_RDY(0));
2731                 buf_ready_reg[1] = __raw_readl(IPU_CHA_BUF0_RDY(32));
2732                 buf_ready_reg[2] = __raw_readl(IPU_CHA_BUF1_RDY(0));
2733                 buf_ready_reg[3] = __raw_readl(IPU_CHA_BUF1_RDY(32));
2734                 buf_ready_reg[4] = __raw_readl(IPU_ALT_CHA_BUF0_RDY(0));
2735                 buf_ready_reg[5] = __raw_readl(IPU_ALT_CHA_BUF0_RDY(32));
2736                 buf_ready_reg[6] = __raw_readl(IPU_ALT_CHA_BUF1_RDY(0));
2737                 buf_ready_reg[7] = __raw_readl(IPU_ALT_CHA_BUF1_RDY(32));
2738                 buf_ready_reg[8] = __raw_readl(IPU_CHA_BUF2_RDY(0));
2739                 buf_ready_reg[9] = __raw_readl(IPU_CHA_BUF2_RDY(32));
2740         }
2741
2742         if (plat_data->pg)
2743                 plat_data->pg(1);
2744
2745         return 0;
2746 }
2747
2748 static int ipu_resume(struct platform_device *pdev)
2749 {
2750         struct imx_ipuv3_platform_data *plat_data = pdev->dev.platform_data;
2751
2752         if (plat_data->pg)
2753                 plat_data->pg(0);
2754
2755         if (g_ipu_clk_enabled) {
2756
2757                 /* restore buf ready regs */
2758                 __raw_writel(buf_ready_reg[0], IPU_CHA_BUF0_RDY(0));
2759                 __raw_writel(buf_ready_reg[1], IPU_CHA_BUF0_RDY(32));
2760                 __raw_writel(buf_ready_reg[2], IPU_CHA_BUF1_RDY(0));
2761                 __raw_writel(buf_ready_reg[3], IPU_CHA_BUF1_RDY(32));
2762                 __raw_writel(buf_ready_reg[4], IPU_ALT_CHA_BUF0_RDY(0));
2763                 __raw_writel(buf_ready_reg[5], IPU_ALT_CHA_BUF0_RDY(32));
2764                 __raw_writel(buf_ready_reg[6], IPU_ALT_CHA_BUF1_RDY(0));
2765                 __raw_writel(buf_ready_reg[7], IPU_ALT_CHA_BUF1_RDY(32));
2766                 __raw_writel(buf_ready_reg[8], IPU_CHA_BUF2_RDY(0));
2767                 __raw_writel(buf_ready_reg[9], IPU_CHA_BUF2_RDY(32));
2768
2769                 /* re-enable sub-modules*/
2770                 __raw_writel(ipu_conf_reg, IPU_CONF);
2771                 __raw_writel(ic_conf_reg, IC_CONF);
2772
2773                 /* restore double buffer select regs */
2774                 __raw_writel(ipu_cha_db_mode_reg[0], IPU_CHA_DB_MODE_SEL(0));
2775                 __raw_writel(ipu_cha_db_mode_reg[1], IPU_CHA_DB_MODE_SEL(32));
2776                 __raw_writel(ipu_cha_db_mode_reg[2],
2777                                 IPU_ALT_CHA_DB_MODE_SEL(0));
2778                 __raw_writel(ipu_cha_db_mode_reg[3],
2779                                 IPU_ALT_CHA_DB_MODE_SEL(32));
2780
2781                 /* restore triple buffer select regs */
2782                 __raw_writel(ipu_cha_trb_mode_reg[0], IPU_CHA_TRB_MODE_SEL(0));
2783                 __raw_writel(ipu_cha_trb_mode_reg[1], IPU_CHA_TRB_MODE_SEL(32));
2784
2785                 /* restore current buffer select regs */
2786                 __raw_writel(~(ipu_cha_cur_buf_reg[0]), IPU_CHA_CUR_BUF(0));
2787                 __raw_writel(~(ipu_cha_cur_buf_reg[1]), IPU_CHA_CUR_BUF(32));
2788                 __raw_writel(~(ipu_cha_cur_buf_reg[2]), IPU_ALT_CUR_BUF0);
2789                 __raw_writel(~(ipu_cha_cur_buf_reg[3]), IPU_ALT_CUR_BUF1);
2790
2791                 /* restore triple current buffer select regs */
2792                 __raw_writel(~(ipu_cha_triple_cur_buf_reg[0]),
2793                                                 IPU_CHA_TRIPLE_CUR_BUF(0));
2794                 __raw_writel(~(ipu_cha_triple_cur_buf_reg[1]),
2795                                                 IPU_CHA_TRIPLE_CUR_BUF(32));
2796                 __raw_writel(~(ipu_cha_triple_cur_buf_reg[2]),
2797                                                 IPU_CHA_TRIPLE_CUR_BUF(64));
2798                 __raw_writel(~(ipu_cha_triple_cur_buf_reg[3]),
2799                                                 IPU_CHA_TRIPLE_CUR_BUF(96));
2800
2801                 /* restore idamc sub addr regs */
2802                 __raw_writel(idma_sub_addr_reg[0], IDMAC_SUB_ADDR_0);
2803                 __raw_writel(idma_sub_addr_reg[1], IDMAC_SUB_ADDR_1);
2804                 __raw_writel(idma_sub_addr_reg[2], IDMAC_SUB_ADDR_2);
2805                 __raw_writel(idma_sub_addr_reg[3], IDMAC_SUB_ADDR_3);
2806                 __raw_writel(idma_sub_addr_reg[4], IDMAC_SUB_ADDR_4);
2807
2808                 /* restart idma channel*/
2809                 __raw_writel(idma_enable_reg[0], IDMAC_CHA_EN(0));
2810                 __raw_writel(idma_enable_reg[1], IDMAC_CHA_EN(32));
2811         } else {
2812                 clk_enable(g_ipu_clk);
2813                 _ipu_dmfc_init(dmfc_type_setup, 1);
2814                 _ipu_init_dc_mappings();
2815
2816                 /* Set sync refresh channels as high priority */
2817                 __raw_writel(0x18800001L, IDMAC_CHA_PRI(0));
2818                 clk_disable(g_ipu_clk);
2819         }
2820
2821         return 0;
2822 }
2823
2824 /*!
2825  * This structure contains pointers to the power management callback functions.
2826  */
2827 static struct platform_driver mxcipu_driver = {
2828         .driver = {
2829                    .name = "imx-ipuv3",
2830                    },
2831         .probe = ipu_probe,
2832         .remove = ipu_remove,
2833         .suspend = ipu_suspend,
2834         .resume = ipu_resume,
2835 };
2836
2837 int32_t __init ipu_gen_init(void)
2838 {
2839         int32_t ret;
2840
2841         ret = platform_driver_register(&mxcipu_driver);
2842         return 0;
2843 }
2844
2845 subsys_initcall(ipu_gen_init);
2846
2847 static void __exit ipu_gen_uninit(void)
2848 {
2849         platform_driver_unregister(&mxcipu_driver);
2850 }
2851
2852 module_exit(ipu_gen_uninit);