drivers/mxc/ipu3/ipu_ic.c

   1 /*
   2  * Copyright 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved.
   3  */
   4
   5 /*
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /*
  15  * @file ipu_ic.c
  16  *
  17  * @brief IPU IC functions
  18  *
  19  * @ingroup IPU
  20  */
  21 #include <linux/types.h>
  22 #include <linux/init.h>
  23 #include <linux/errno.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/videodev2.h>
  26 #include <linux/io.h>
  27 #include <mach/ipu-v3.h>
  28
  29 #include "ipu_prv.h"
  30 #include "ipu_regs.h"
  31 #include "ipu_param_mem.h"
  32
  33 enum {
  34         IC_TASK_VIEWFINDER,
  35         IC_TASK_ENCODER,
  36         IC_TASK_POST_PROCESSOR
  37 };
  38
  39 static void _init_csc(struct ipu_soc *ipu, uint8_t ic_task, ipu_color_space_t in_format,
  40                       ipu_color_space_t out_format, int csc_index);
  41 static bool _calc_resize_coeffs(struct ipu_soc *ipu,
  42                                 uint32_t inSize, uint32_t outSize,
  43                                 uint32_t *resizeCoeff,
  44                                 uint32_t *downsizeCoeff);
  45
  46 void _ipu_vdi_set_top_field_man(struct ipu_soc *ipu, bool top_field_0)
  47 {
  48         uint32_t reg;
  49
  50         reg = ipu_vdi_read(ipu, VDI_C);
  51         if (top_field_0)
  52                 reg &= ~VDI_C_TOP_FIELD_MAN_1;
  53         else
  54                 reg |= VDI_C_TOP_FIELD_MAN_1;
  55         ipu_vdi_write(ipu, reg, VDI_C);
  56 }
  57
  58 void _ipu_vdi_set_motion(struct ipu_soc *ipu, ipu_motion_sel motion_sel)
  59 {
  60         uint32_t reg;
  61
  62         reg = ipu_vdi_read(ipu, VDI_C);
  63         reg &= ~(VDI_C_MOT_SEL_FULL | VDI_C_MOT_SEL_MED | VDI_C_MOT_SEL_LOW);
  64         if (motion_sel == HIGH_MOTION)
  65                 reg |= VDI_C_MOT_SEL_FULL;
  66         else if (motion_sel == MED_MOTION)
  67                 reg |= VDI_C_MOT_SEL_MED;
  68         else
  69                 reg |= VDI_C_MOT_SEL_LOW;
  70
  71         ipu_vdi_write(ipu, reg, VDI_C);
  72 }
  73
  74 void ic_dump_register(struct ipu_soc *ipu)
  75 {
  76         printk(KERN_DEBUG "IC_CONF = \t0x%08X\n", ipu_ic_read(ipu, IC_CONF));
  77         printk(KERN_DEBUG "IC_PRP_ENC_RSC = \t0x%08X\n",
  78                ipu_ic_read(ipu, IC_PRP_ENC_RSC));
  79         printk(KERN_DEBUG "IC_PRP_VF_RSC = \t0x%08X\n",
  80                ipu_ic_read(ipu, IC_PRP_VF_RSC));
  81         printk(KERN_DEBUG "IC_PP_RSC = \t0x%08X\n", ipu_ic_read(ipu, IC_PP_RSC));
  82         printk(KERN_DEBUG "IC_IDMAC_1 = \t0x%08X\n", ipu_ic_read(ipu, IC_IDMAC_1));
  83         printk(KERN_DEBUG "IC_IDMAC_2 = \t0x%08X\n", ipu_ic_read(ipu, IC_IDMAC_2));
  84         printk(KERN_DEBUG "IC_IDMAC_3 = \t0x%08X\n", ipu_ic_read(ipu, IC_IDMAC_3));
  85 }
  86
  87 void _ipu_ic_enable_task(struct ipu_soc *ipu, ipu_channel_t channel)
  88 {
  89         uint32_t ic_conf;
  90
  91         ic_conf = ipu_ic_read(ipu, IC_CONF);
  92         switch (channel) {
  93         case CSI_PRP_VF_MEM:
  94         case MEM_PRP_VF_MEM:
  95                 ic_conf |= IC_CONF_PRPVF_EN;
  96                 break;
  97         case MEM_VDI_PRP_VF_MEM:
  98                 ic_conf |= IC_CONF_PRPVF_EN;
  99                 break;
 100         case MEM_VDI_MEM:
 101                 ic_conf |= IC_CONF_PRPVF_EN | IC_CONF_RWS_EN ;
 102                 break;
 103         case MEM_ROT_VF_MEM:
 104                 ic_conf |= IC_CONF_PRPVF_ROT_EN;
 105                 break;
 106         case CSI_PRP_ENC_MEM:
 107         case MEM_PRP_ENC_MEM:
 108                 ic_conf |= IC_CONF_PRPENC_EN;
 109                 break;
 110         case MEM_ROT_ENC_MEM:
 111                 ic_conf |= IC_CONF_PRPENC_ROT_EN;
 112                 break;
 113         case MEM_PP_MEM:
 114                 ic_conf |= IC_CONF_PP_EN;
 115                 break;
 116         case MEM_ROT_PP_MEM:
 117                 ic_conf |= IC_CONF_PP_ROT_EN;
 118                 break;
 119         default:
 120                 break;
 121         }
 122         ipu_ic_write(ipu, ic_conf, IC_CONF);
 123 }
 124
 125 void _ipu_ic_disable_task(struct ipu_soc *ipu, ipu_channel_t channel)
 126 {
 127         uint32_t ic_conf;
 128
 129         ic_conf = ipu_ic_read(ipu, IC_CONF);
 130         switch (channel) {
 131         case CSI_PRP_VF_MEM:
 132         case MEM_PRP_VF_MEM:
 133                 ic_conf &= ~IC_CONF_PRPVF_EN;
 134                 break;
 135         case MEM_VDI_PRP_VF_MEM:
 136                 ic_conf &= ~IC_CONF_PRPVF_EN;
 137                 break;
 138         case MEM_VDI_MEM:
 139                 ic_conf &= ~(IC_CONF_PRPVF_EN | IC_CONF_RWS_EN);
 140                 break;
 141         case MEM_ROT_VF_MEM:
 142                 ic_conf &= ~IC_CONF_PRPVF_ROT_EN;
 143                 break;
 144         case CSI_PRP_ENC_MEM:
 145         case MEM_PRP_ENC_MEM:
 146                 ic_conf &= ~IC_CONF_PRPENC_EN;
 147                 break;
 148         case MEM_ROT_ENC_MEM:
 149                 ic_conf &= ~IC_CONF_PRPENC_ROT_EN;
 150                 break;
 151         case MEM_PP_MEM:
 152                 ic_conf &= ~IC_CONF_PP_EN;
 153                 break;
 154         case MEM_ROT_PP_MEM:
 155                 ic_conf &= ~IC_CONF_PP_ROT_EN;
 156                 break;
 157         default:
 158                 break;
 159         }
 160         ipu_ic_write(ipu, ic_conf, IC_CONF);
 161 }
 162
 163 void _ipu_vdi_init(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params)
 164 {
 165         uint32_t reg;
 166         uint32_t pixel_fmt;
 167         uint32_t pix_per_burst;
 168
 169         reg = ((params->mem_prp_vf_mem.in_height-1) << 16) |
 170           (params->mem_prp_vf_mem.in_width-1);
 171         ipu_vdi_write(ipu, reg, VDI_FSIZE);
 172
 173         /* Full motion, only vertical filter is used
 174            Burst size is 4 accesses */
 175         if (params->mem_prp_vf_mem.in_pixel_fmt ==
 176              IPU_PIX_FMT_UYVY ||
 177              params->mem_prp_vf_mem.in_pixel_fmt ==
 178              IPU_PIX_FMT_YUYV) {
 179                 pixel_fmt = VDI_C_CH_422;
 180                 pix_per_burst = 32;
 181          } else {
 182                 pixel_fmt = VDI_C_CH_420;
 183                 pix_per_burst = 64;
 184         }
 185
 186         reg = ipu_vdi_read(ipu, VDI_C);
 187         reg |= pixel_fmt;
 188         switch (channel) {
 189         case MEM_VDI_PRP_VF_MEM:
 190                 reg |= VDI_C_BURST_SIZE2_4;
 191                 break;
 192         case MEM_VDI_PRP_VF_MEM_P:
 193                 reg |= VDI_C_BURST_SIZE1_4 | VDI_C_VWM1_SET_1 | VDI_C_VWM1_CLR_2;
 194                 break;
 195         case MEM_VDI_PRP_VF_MEM_N:
 196                 reg |= VDI_C_BURST_SIZE3_4 | VDI_C_VWM3_SET_1 | VDI_C_VWM3_CLR_2;
 197                 break;
 198
 199         case MEM_VDI_MEM:
 200                 reg |= (((pix_per_burst >> 2) - 1) & VDI_C_BURST_SIZE_MASK)
 201                                 << VDI_C_BURST_SIZE2_OFFSET;
 202                 break;
 203         case MEM_VDI_MEM_P:
 204                 reg |= (((pix_per_burst >> 2) - 1) & VDI_C_BURST_SIZE_MASK)
 205                                 << VDI_C_BURST_SIZE1_OFFSET;
 206                 reg |= VDI_C_VWM1_SET_2 | VDI_C_VWM1_CLR_2;
 207                 break;
 208         case MEM_VDI_MEM_N:
 209                 reg |= (((pix_per_burst >> 2) - 1) & VDI_C_BURST_SIZE_MASK)
 210                                 << VDI_C_BURST_SIZE3_OFFSET;
 211                 reg |= VDI_C_VWM3_SET_2 | VDI_C_VWM3_CLR_2;
 212                 break;
 213         default:
 214                 break;
 215         }
 216         ipu_vdi_write(ipu, reg, VDI_C);
 217
 218         if (params->mem_prp_vf_mem.field_fmt == V4L2_FIELD_INTERLACED_TB)
 219                 _ipu_vdi_set_top_field_man(ipu, false);
 220         else if (params->mem_prp_vf_mem.field_fmt == V4L2_FIELD_INTERLACED_BT)
 221                 _ipu_vdi_set_top_field_man(ipu, true);
 222
 223         _ipu_vdi_set_motion(ipu, params->mem_prp_vf_mem.motion_sel);
 224
 225         reg = ipu_ic_read(ipu, IC_CONF);
 226         reg &= ~IC_CONF_RWS_EN;
 227         ipu_ic_write(ipu, reg, IC_CONF);
 228 }
 229
 230 void _ipu_vdi_uninit(struct ipu_soc *ipu)
 231 {
 232         ipu_vdi_write(ipu, 0, VDI_FSIZE);
 233         ipu_vdi_write(ipu, 0, VDI_C);
 234 }
 235
 236 void _ipu_ic_init_prpvf(struct ipu_soc *ipu, ipu_channel_params_t *params, bool src_is_csi)
 237 {
 238         uint32_t reg, ic_conf;
 239         uint32_t downsizeCoeff, resizeCoeff;
 240         ipu_color_space_t in_fmt, out_fmt;
 241
 242         /* Setup vertical resizing */
 243         if (!(params->mem_prp_vf_mem.outv_resize_ratio)) {
 244                 _calc_resize_coeffs(ipu, params->mem_prp_vf_mem.in_height,
 245                                 params->mem_prp_vf_mem.out_height,
 246                                 &resizeCoeff, &downsizeCoeff);
 247                 reg = (downsizeCoeff << 30) | (resizeCoeff << 16);
 248         } else
 249                 reg = (params->mem_prp_vf_mem.outv_resize_ratio) << 16;
 250
 251         /* Setup horizontal resizing */
 252         /* Upadeted for IC split case */
 253         if (!(params->mem_prp_vf_mem.outh_resize_ratio)) {
 254                 _calc_resize_coeffs(ipu, params->mem_prp_vf_mem.in_width,
 255                                 params->mem_prp_vf_mem.out_width,
 256                                 &resizeCoeff, &downsizeCoeff);
 257                 reg |= (downsizeCoeff << 14) | resizeCoeff;
 258         } else
 259                 reg |= params->mem_prp_vf_mem.outh_resize_ratio;
 260
 261         ipu_ic_write(ipu, reg, IC_PRP_VF_RSC);
 262
 263         ic_conf = ipu_ic_read(ipu, IC_CONF);
 264
 265         /* Setup color space conversion */
 266         in_fmt = format_to_colorspace(params->mem_prp_vf_mem.in_pixel_fmt);
 267         out_fmt = format_to_colorspace(params->mem_prp_vf_mem.out_pixel_fmt);
 268         if (in_fmt == RGB) {
 269                 if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
 270                         /* Enable RGB->YCBCR CSC1 */
 271                         _init_csc(ipu, IC_TASK_VIEWFINDER, RGB, out_fmt, 1);
 272                         ic_conf |= IC_CONF_PRPVF_CSC1;
 273                 }
 274         }
 275         if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
 276                 if (out_fmt == RGB) {
 277                         /* Enable YCBCR->RGB CSC1 */
 278                         _init_csc(ipu, IC_TASK_VIEWFINDER, YCbCr, RGB, 1);
 279                         ic_conf |= IC_CONF_PRPVF_CSC1;
 280                 } else {
 281                         /* TODO: Support YUV<->YCbCr conversion? */
 282                 }
 283         }
 284
 285         if (params->mem_prp_vf_mem.graphics_combine_en) {
 286                 ic_conf |= IC_CONF_PRPVF_CMB;
 287
 288                 if (!(ic_conf & IC_CONF_PRPVF_CSC1)) {
 289                         /* need transparent CSC1 conversion */
 290                         _init_csc(ipu, IC_TASK_VIEWFINDER, RGB, RGB, 1);
 291                         ic_conf |= IC_CONF_PRPVF_CSC1;  /* Enable RGB->RGB CSC */
 292                 }
 293                 in_fmt = format_to_colorspace(params->mem_prp_vf_mem.in_g_pixel_fmt);
 294                 out_fmt = format_to_colorspace(params->mem_prp_vf_mem.out_pixel_fmt);
 295                 if (in_fmt == RGB) {
 296                         if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
 297                                 /* Enable RGB->YCBCR CSC2 */
 298                                 _init_csc(ipu, IC_TASK_VIEWFINDER, RGB, out_fmt, 2);
 299                                 ic_conf |= IC_CONF_PRPVF_CSC2;
 300                         }
 301                 }
 302                 if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
 303                         if (out_fmt == RGB) {
 304                                 /* Enable YCBCR->RGB CSC2 */
 305                                 _init_csc(ipu, IC_TASK_VIEWFINDER, YCbCr, RGB, 2);
 306                                 ic_conf |= IC_CONF_PRPVF_CSC2;
 307                         } else {
 308                                 /* TODO: Support YUV<->YCbCr conversion? */
 309                         }
 310                 }
 311
 312                 if (params->mem_prp_vf_mem.global_alpha_en) {
 313                         ic_conf |= IC_CONF_IC_GLB_LOC_A;
 314                         reg = ipu_ic_read(ipu, IC_CMBP_1);
 315                         reg &= ~(0xff);
 316                         reg |= params->mem_prp_vf_mem.alpha;
 317                         ipu_ic_write(ipu, reg, IC_CMBP_1);
 318                 } else
 319                         ic_conf &= ~IC_CONF_IC_GLB_LOC_A;
 320
 321                 if (params->mem_prp_vf_mem.key_color_en) {
 322                         ic_conf |= IC_CONF_KEY_COLOR_EN;
 323                         ipu_ic_write(ipu, params->mem_prp_vf_mem.key_color,
 324                                         IC_CMBP_2);
 325                 } else
 326                         ic_conf &= ~IC_CONF_KEY_COLOR_EN;
 327         } else {
 328                 ic_conf &= ~IC_CONF_PRPVF_CMB;
 329         }
 330
 331         if (src_is_csi)
 332                 ic_conf &= ~IC_CONF_RWS_EN;
 333         else
 334                 ic_conf |= IC_CONF_RWS_EN;
 335
 336         ipu_ic_write(ipu, ic_conf, IC_CONF);
 337 }
 338
 339 void _ipu_ic_uninit_prpvf(struct ipu_soc *ipu)
 340 {
 341         uint32_t reg;
 342
 343         reg = ipu_ic_read(ipu, IC_CONF);
 344         reg &= ~(IC_CONF_PRPVF_EN | IC_CONF_PRPVF_CMB |
 345                  IC_CONF_PRPVF_CSC2 | IC_CONF_PRPVF_CSC1);
 346         ipu_ic_write(ipu, reg, IC_CONF);
 347 }
 348
 349 void _ipu_ic_init_rotate_vf(struct ipu_soc *ipu, ipu_channel_params_t *params)
 350 {
 351 }
 352
 353 void _ipu_ic_uninit_rotate_vf(struct ipu_soc *ipu)
 354 {
 355         uint32_t reg;
 356         reg = ipu_ic_read(ipu, IC_CONF);
 357         reg &= ~IC_CONF_PRPVF_ROT_EN;
 358         ipu_ic_write(ipu, reg, IC_CONF);
 359 }
 360
 361 void _ipu_ic_init_prpenc(struct ipu_soc *ipu, ipu_channel_params_t *params, bool src_is_csi)
 362 {
 363         uint32_t reg, ic_conf;
 364         uint32_t downsizeCoeff, resizeCoeff;
 365         ipu_color_space_t in_fmt, out_fmt;
 366
 367         /* Setup vertical resizing */
 368         if (!(params->mem_prp_enc_mem.outv_resize_ratio)) {
 369                 _calc_resize_coeffs(ipu, params->mem_prp_enc_mem.in_height,
 370                                 params->mem_prp_enc_mem.out_height,
 371                                 &resizeCoeff, &downsizeCoeff);
 372                 reg = (downsizeCoeff << 30) | (resizeCoeff << 16);
 373         } else
 374                 reg = (params->mem_prp_enc_mem.outv_resize_ratio) << 16;
 375
 376         /* Setup horizontal resizing */
 377         /* Upadeted for IC split case */
 378         if (!(params->mem_prp_enc_mem.outh_resize_ratio)) {
 379                 _calc_resize_coeffs(ipu, params->mem_prp_enc_mem.in_width,
 380                                 params->mem_prp_enc_mem.out_width,
 381                                 &resizeCoeff, &downsizeCoeff);
 382                 reg |= (downsizeCoeff << 14) | resizeCoeff;
 383         } else
 384                 reg |= params->mem_prp_enc_mem.outh_resize_ratio;
 385
 386         ipu_ic_write(ipu, reg, IC_PRP_ENC_RSC);
 387
 388         ic_conf = ipu_ic_read(ipu, IC_CONF);
 389
 390         /* Setup color space conversion */
 391         in_fmt = format_to_colorspace(params->mem_prp_enc_mem.in_pixel_fmt);
 392         out_fmt = format_to_colorspace(params->mem_prp_enc_mem.out_pixel_fmt);
 393         if (in_fmt == RGB) {
 394                 if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
 395                         /* Enable RGB->YCBCR CSC1 */
 396                         _init_csc(ipu, IC_TASK_ENCODER, RGB, out_fmt, 1);
 397                         ic_conf |= IC_CONF_PRPENC_CSC1;
 398                 }
 399         }
 400         if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
 401                 if (out_fmt == RGB) {
 402                         /* Enable YCBCR->RGB CSC1 */
 403                         _init_csc(ipu, IC_TASK_ENCODER, YCbCr, RGB, 1);
 404                         ic_conf |= IC_CONF_PRPENC_CSC1;
 405                 } else {
 406                         /* TODO: Support YUV<->YCbCr conversion? */
 407                 }
 408         }
 409
 410         if (src_is_csi)
 411                 ic_conf &= ~IC_CONF_RWS_EN;
 412         else
 413                 ic_conf |= IC_CONF_RWS_EN;
 414
 415         ipu_ic_write(ipu, ic_conf, IC_CONF);
 416 }
 417
 418 void _ipu_ic_uninit_prpenc(struct ipu_soc *ipu)
 419 {
 420         uint32_t reg;
 421
 422         reg = ipu_ic_read(ipu, IC_CONF);
 423         reg &= ~(IC_CONF_PRPENC_EN | IC_CONF_PRPENC_CSC1);
 424         ipu_ic_write(ipu, reg, IC_CONF);
 425 }
 426
 427 void _ipu_ic_init_rotate_enc(struct ipu_soc *ipu, ipu_channel_params_t *params)
 428 {
 429 }
 430
 431 void _ipu_ic_uninit_rotate_enc(struct ipu_soc *ipu)
 432 {
 433         uint32_t reg;
 434
 435         reg = ipu_ic_read(ipu, IC_CONF);
 436         reg &= ~(IC_CONF_PRPENC_ROT_EN);
 437         ipu_ic_write(ipu, reg, IC_CONF);
 438 }
 439
 440 void _ipu_ic_init_pp(struct ipu_soc *ipu, ipu_channel_params_t *params)
 441 {
 442         uint32_t reg, ic_conf;
 443         uint32_t downsizeCoeff, resizeCoeff;
 444         ipu_color_space_t in_fmt, out_fmt;
 445
 446         /* Setup vertical resizing */
 447         if (!(params->mem_pp_mem.outv_resize_ratio)) {
 448                 _calc_resize_coeffs(ipu, params->mem_pp_mem.in_height,
 449                             params->mem_pp_mem.out_height,
 450                             &resizeCoeff, &downsizeCoeff);
 451                 reg = (downsizeCoeff << 30) | (resizeCoeff << 16);
 452         } else {
 453                 reg = (params->mem_pp_mem.outv_resize_ratio) << 16;
 454         }
 455
 456         /* Setup horizontal resizing */
 457         /* Upadeted for IC split case */
 458         if (!(params->mem_pp_mem.outh_resize_ratio)) {
 459                 _calc_resize_coeffs(ipu, params->mem_pp_mem.in_width,
 460                                                         params->mem_pp_mem.out_width,
 461                                                         &resizeCoeff, &downsizeCoeff);
 462                 reg |= (downsizeCoeff << 14) | resizeCoeff;
 463         } else {
 464                 reg |= params->mem_pp_mem.outh_resize_ratio;
 465         }
 466
 467         ipu_ic_write(ipu, reg, IC_PP_RSC);
 468
 469         ic_conf = ipu_ic_read(ipu, IC_CONF);
 470
 471         /* Setup color space conversion */
 472         in_fmt = format_to_colorspace(params->mem_pp_mem.in_pixel_fmt);
 473         out_fmt = format_to_colorspace(params->mem_pp_mem.out_pixel_fmt);
 474         if (in_fmt == RGB) {
 475                 if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
 476                         /* Enable RGB->YCBCR CSC1 */
 477                         _init_csc(ipu, IC_TASK_POST_PROCESSOR, RGB, out_fmt, 1);
 478                         ic_conf |= IC_CONF_PP_CSC1;
 479                 }
 480         }
 481         if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
 482                 if (out_fmt == RGB) {
 483                         /* Enable YCBCR->RGB CSC1 */
 484                         _init_csc(ipu, IC_TASK_POST_PROCESSOR, YCbCr, RGB, 1);
 485                         ic_conf |= IC_CONF_PP_CSC1;
 486                 } else {
 487                         /* TODO: Support YUV<->YCbCr conversion? */
 488                 }
 489         }
 490
 491         if (params->mem_pp_mem.graphics_combine_en) {
 492                 ic_conf |= IC_CONF_PP_CMB;
 493
 494                 if (!(ic_conf & IC_CONF_PP_CSC1)) {
 495                         /* need transparent CSC1 conversion */
 496                         _init_csc(ipu, IC_TASK_POST_PROCESSOR, RGB, RGB, 1);
 497                         ic_conf |= IC_CONF_PP_CSC1;  /* Enable RGB->RGB CSC */
 498                 }
 499
 500                 in_fmt = format_to_colorspace(params->mem_pp_mem.in_g_pixel_fmt);
 501                 out_fmt = format_to_colorspace(params->mem_pp_mem.out_pixel_fmt);
 502                 if (in_fmt == RGB) {
 503                         if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
 504                                 /* Enable RGB->YCBCR CSC2 */
 505                                 _init_csc(ipu, IC_TASK_POST_PROCESSOR, RGB, out_fmt, 2);
 506                                 ic_conf |= IC_CONF_PP_CSC2;
 507                         }
 508                 }
 509                 if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
 510                         if (out_fmt == RGB) {
 511                                 /* Enable YCBCR->RGB CSC2 */
 512                                 _init_csc(ipu, IC_TASK_POST_PROCESSOR, YCbCr, RGB, 2);
 513                                 ic_conf |= IC_CONF_PP_CSC2;
 514                         } else {
 515                                 /* TODO: Support YUV<->YCbCr conversion? */
 516                         }
 517                 }
 518
 519                 if (params->mem_pp_mem.global_alpha_en) {
 520                         ic_conf |= IC_CONF_IC_GLB_LOC_A;
 521                         reg = ipu_ic_read(ipu, IC_CMBP_1);
 522                         reg &= ~(0xff00);
 523                         reg |= (params->mem_pp_mem.alpha << 8);
 524                         ipu_ic_write(ipu, reg, IC_CMBP_1);
 525                 } else
 526                         ic_conf &= ~IC_CONF_IC_GLB_LOC_A;
 527
 528                 if (params->mem_pp_mem.key_color_en) {
 529                         ic_conf |= IC_CONF_KEY_COLOR_EN;
 530                         ipu_ic_write(ipu, params->mem_pp_mem.key_color,
 531                                         IC_CMBP_2);
 532                 } else
 533                         ic_conf &= ~IC_CONF_KEY_COLOR_EN;
 534         } else {
 535                 ic_conf &= ~IC_CONF_PP_CMB;
 536         }
 537
 538         ipu_ic_write(ipu, ic_conf, IC_CONF);
 539 }
 540
 541 void _ipu_ic_uninit_pp(struct ipu_soc *ipu)
 542 {
 543         uint32_t reg;
 544
 545         reg = ipu_ic_read(ipu, IC_CONF);
 546         reg &= ~(IC_CONF_PP_EN | IC_CONF_PP_CSC1 | IC_CONF_PP_CSC2 |
 547                  IC_CONF_PP_CMB);
 548         ipu_ic_write(ipu, reg, IC_CONF);
 549 }
 550
 551 void _ipu_ic_init_rotate_pp(struct ipu_soc *ipu, ipu_channel_params_t *params)
 552 {
 553 }
 554
 555 void _ipu_ic_uninit_rotate_pp(struct ipu_soc *ipu)
 556 {
 557         uint32_t reg;
 558         reg = ipu_ic_read(ipu, IC_CONF);
 559         reg &= ~IC_CONF_PP_ROT_EN;
 560         ipu_ic_write(ipu, reg, IC_CONF);
 561 }
 562
 563 int _ipu_ic_idma_init(struct ipu_soc *ipu, int dma_chan,
 564                 uint16_t width, uint16_t height,
 565                 int burst_size, ipu_rotate_mode_t rot)
 566 {
 567         u32 ic_idmac_1, ic_idmac_2, ic_idmac_3;
 568         u32 temp_rot = bitrev8(rot) >> 5;
 569         bool need_hor_flip = false;
 570
 571         if ((burst_size != 8) && (burst_size != 16)) {
 572                 dev_dbg(ipu->dev, "Illegal burst length for IC\n");
 573                 return -EINVAL;
 574         }
 575
 576         width--;
 577         height--;
 578
 579         if (temp_rot & 0x2)     /* Need horizontal flip */
 580                 need_hor_flip = true;
 581
 582         ic_idmac_1 = ipu_ic_read(ipu, IC_IDMAC_1);
 583         ic_idmac_2 = ipu_ic_read(ipu, IC_IDMAC_2);
 584         ic_idmac_3 = ipu_ic_read(ipu, IC_IDMAC_3);
 585         if (dma_chan == 22) {   /* PP output - CB2 */
 586                 if (burst_size == 16)
 587                         ic_idmac_1 |= IC_IDMAC_1_CB2_BURST_16;
 588                 else
 589                         ic_idmac_1 &= ~IC_IDMAC_1_CB2_BURST_16;
 590
 591                 if (need_hor_flip)
 592                         ic_idmac_1 |= IC_IDMAC_1_PP_FLIP_RS;
 593                 else
 594                         ic_idmac_1 &= ~IC_IDMAC_1_PP_FLIP_RS;
 595
 596                 ic_idmac_2 &= ~IC_IDMAC_2_PP_HEIGHT_MASK;
 597                 ic_idmac_2 |= height << IC_IDMAC_2_PP_HEIGHT_OFFSET;
 598
 599                 ic_idmac_3 &= ~IC_IDMAC_3_PP_WIDTH_MASK;
 600                 ic_idmac_3 |= width << IC_IDMAC_3_PP_WIDTH_OFFSET;
 601         } else if (dma_chan == 11) {    /* PP Input - CB5 */
 602                 if (burst_size == 16)
 603                         ic_idmac_1 |= IC_IDMAC_1_CB5_BURST_16;
 604                 else
 605                         ic_idmac_1 &= ~IC_IDMAC_1_CB5_BURST_16;
 606         } else if (dma_chan == 47) {    /* PP Rot input */
 607                 ic_idmac_1 &= ~IC_IDMAC_1_PP_ROT_MASK;
 608                 ic_idmac_1 |= temp_rot << IC_IDMAC_1_PP_ROT_OFFSET;
 609         }
 610
 611         if (dma_chan == 12) {   /* PRP Input - CB6 */
 612                 if (burst_size == 16)
 613                         ic_idmac_1 |= IC_IDMAC_1_CB6_BURST_16;
 614                 else
 615                         ic_idmac_1 &= ~IC_IDMAC_1_CB6_BURST_16;
 616         }
 617
 618         if (dma_chan == 20) {   /* PRP ENC output - CB0 */
 619                 if (burst_size == 16)
 620                         ic_idmac_1 |= IC_IDMAC_1_CB0_BURST_16;
 621                 else
 622                         ic_idmac_1 &= ~IC_IDMAC_1_CB0_BURST_16;
 623
 624                 if (need_hor_flip)
 625                         ic_idmac_1 |= IC_IDMAC_1_PRPENC_FLIP_RS;
 626                 else
 627                         ic_idmac_1 &= ~IC_IDMAC_1_PRPENC_FLIP_RS;
 628
 629                 ic_idmac_2 &= ~IC_IDMAC_2_PRPENC_HEIGHT_MASK;
 630                 ic_idmac_2 |= height << IC_IDMAC_2_PRPENC_HEIGHT_OFFSET;
 631
 632                 ic_idmac_3 &= ~IC_IDMAC_3_PRPENC_WIDTH_MASK;
 633                 ic_idmac_3 |= width << IC_IDMAC_3_PRPENC_WIDTH_OFFSET;
 634
 635         } else if (dma_chan == 45) {    /* PRP ENC Rot input */
 636                 ic_idmac_1 &= ~IC_IDMAC_1_PRPENC_ROT_MASK;
 637                 ic_idmac_1 |= temp_rot << IC_IDMAC_1_PRPENC_ROT_OFFSET;
 638         }
 639
 640         if (dma_chan == 21) {   /* PRP VF output - CB1 */
 641                 if (burst_size == 16)
 642                         ic_idmac_1 |= IC_IDMAC_1_CB1_BURST_16;
 643                 else
 644                         ic_idmac_1 &= ~IC_IDMAC_1_CB1_BURST_16;
 645
 646                 if (need_hor_flip)
 647                         ic_idmac_1 |= IC_IDMAC_1_PRPVF_FLIP_RS;
 648                 else
 649                         ic_idmac_1 &= ~IC_IDMAC_1_PRPVF_FLIP_RS;
 650
 651                 ic_idmac_2 &= ~IC_IDMAC_2_PRPVF_HEIGHT_MASK;
 652                 ic_idmac_2 |= height << IC_IDMAC_2_PRPVF_HEIGHT_OFFSET;
 653
 654                 ic_idmac_3 &= ~IC_IDMAC_3_PRPVF_WIDTH_MASK;
 655                 ic_idmac_3 |= width << IC_IDMAC_3_PRPVF_WIDTH_OFFSET;
 656
 657         } else if (dma_chan == 46) {    /* PRP VF Rot input */
 658                 ic_idmac_1 &= ~IC_IDMAC_1_PRPVF_ROT_MASK;
 659                 ic_idmac_1 |= temp_rot << IC_IDMAC_1_PRPVF_ROT_OFFSET;
 660         }
 661
 662         if (dma_chan == 14) {   /* PRP VF graphics combining input - CB3 */
 663                 if (burst_size == 16)
 664                         ic_idmac_1 |= IC_IDMAC_1_CB3_BURST_16;
 665                 else
 666                         ic_idmac_1 &= ~IC_IDMAC_1_CB3_BURST_16;
 667         } else if (dma_chan == 15) {    /* PP graphics combining input - CB4 */
 668                 if (burst_size == 16)
 669                         ic_idmac_1 |= IC_IDMAC_1_CB4_BURST_16;
 670                 else
 671                         ic_idmac_1 &= ~IC_IDMAC_1_CB4_BURST_16;
 672         } else if (dma_chan == 5) {     /* VDIC OUTPUT - CB7 */
 673                 if (burst_size == 16)
 674                         ic_idmac_1 |= IC_IDMAC_1_CB7_BURST_16;
 675                 else
 676                         ic_idmac_1 &= ~IC_IDMAC_1_CB7_BURST_16;
 677         }
 678
 679         ipu_ic_write(ipu, ic_idmac_1, IC_IDMAC_1);
 680         ipu_ic_write(ipu, ic_idmac_2, IC_IDMAC_2);
 681         ipu_ic_write(ipu, ic_idmac_3, IC_IDMAC_3);
 682         return 0;
 683 }
 684
 685 static void _init_csc(struct ipu_soc *ipu, uint8_t ic_task, ipu_color_space_t in_format,
 686                       ipu_color_space_t out_format, int csc_index)
 687 {
 688
 689 /*     Y = R *  .299 + G *  .587 + B *  .114;
 690        U = R * -.169 + G * -.332 + B *  .500 + 128.;
 691        V = R *  .500 + G * -.419 + B * -.0813 + 128.;*/
 692         static const uint32_t rgb2ycbcr_coeff[4][3] = {
 693                 {0x004D, 0x0096, 0x001D},
 694                 {0x01D5, 0x01AB, 0x0080},
 695                 {0x0080, 0x0195, 0x01EB},
 696                 {0x0000, 0x0200, 0x0200},       /* A0, A1, A2 */
 697         };
 698
 699         /* transparent RGB->RGB matrix for combining
 700          */
 701         static const uint32_t rgb2rgb_coeff[4][3] = {
 702                 {0x0080, 0x0000, 0x0000},
 703                 {0x0000, 0x0080, 0x0000},
 704                 {0x0000, 0x0000, 0x0080},
 705                 {0x0000, 0x0000, 0x0000},       /* A0, A1, A2 */
 706         };
 707
 708 /*     R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
 709        G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
 710        B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); */
 711         static const uint32_t ycbcr2rgb_coeff[4][3] = {
 712                 {149, 0, 204},
 713                 {149, 462, 408},
 714                 {149, 255, 0},
 715                 {8192 - 446, 266, 8192 - 554},  /* A0, A1, A2 */
 716         };
 717
 718         uint32_t param;
 719         uint32_t *base = NULL;
 720
 721         if (ic_task == IC_TASK_ENCODER) {
 722                 base = ipu->tpmem_base + 0x2008 / 4;
 723         } else if (ic_task == IC_TASK_VIEWFINDER) {
 724                 if (csc_index == 1)
 725                         base = ipu->tpmem_base + 0x4028 / 4;
 726                 else
 727                         base = ipu->tpmem_base + 0x4040 / 4;
 728         } else if (ic_task == IC_TASK_POST_PROCESSOR) {
 729                 if (csc_index == 1)
 730                         base = ipu->tpmem_base + 0x6060 / 4;
 731                 else
 732                         base = ipu->tpmem_base + 0x6078 / 4;
 733         } else {
 734                 BUG();
 735         }
 736
 737         if ((in_format == YCbCr) && (out_format == RGB)) {
 738                 /* Init CSC (YCbCr->RGB) */
 739                 param = (ycbcr2rgb_coeff[3][0] << 27) |
 740                         (ycbcr2rgb_coeff[0][0] << 18) |
 741                         (ycbcr2rgb_coeff[1][1] << 9) | ycbcr2rgb_coeff[2][2];
 742                 writel(param, base++);
 743                 /* scale = 2, sat = 0 */
 744                 param = (ycbcr2rgb_coeff[3][0] >> 5) | (2L << (40 - 32));
 745                 writel(param, base++);
 746
 747                 param = (ycbcr2rgb_coeff[3][1] << 27) |
 748                         (ycbcr2rgb_coeff[0][1] << 18) |
 749                         (ycbcr2rgb_coeff[1][0] << 9) | ycbcr2rgb_coeff[2][0];
 750                 writel(param, base++);
 751                 param = (ycbcr2rgb_coeff[3][1] >> 5);
 752                 writel(param, base++);
 753
 754                 param = (ycbcr2rgb_coeff[3][2] << 27) |
 755                         (ycbcr2rgb_coeff[0][2] << 18) |
 756                         (ycbcr2rgb_coeff[1][2] << 9) | ycbcr2rgb_coeff[2][1];
 757                 writel(param, base++);
 758                 param = (ycbcr2rgb_coeff[3][2] >> 5);
 759                 writel(param, base++);
 760         } else if ((in_format == RGB) && (out_format == YCbCr)) {
 761                 /* Init CSC (RGB->YCbCr) */
 762                 param = (rgb2ycbcr_coeff[3][0] << 27) |
 763                         (rgb2ycbcr_coeff[0][0] << 18) |
 764                         (rgb2ycbcr_coeff[1][1] << 9) | rgb2ycbcr_coeff[2][2];
 765                 writel(param, base++);
 766                 /* scale = 1, sat = 0 */
 767                 param = (rgb2ycbcr_coeff[3][0] >> 5) | (1UL << 8);
 768                 writel(param, base++);
 769
 770                 param = (rgb2ycbcr_coeff[3][1] << 27) |
 771                         (rgb2ycbcr_coeff[0][1] << 18) |
 772                         (rgb2ycbcr_coeff[1][0] << 9) | rgb2ycbcr_coeff[2][0];
 773                 writel(param, base++);
 774                 param = (rgb2ycbcr_coeff[3][1] >> 5);
 775                 writel(param, base++);
 776
 777                 param = (rgb2ycbcr_coeff[3][2] << 27) |
 778                         (rgb2ycbcr_coeff[0][2] << 18) |
 779                         (rgb2ycbcr_coeff[1][2] << 9) | rgb2ycbcr_coeff[2][1];
 780                 writel(param, base++);
 781                 param = (rgb2ycbcr_coeff[3][2] >> 5);
 782                 writel(param, base++);
 783         } else if ((in_format == RGB) && (out_format == RGB)) {
 784                 /* Init CSC */
 785                 param =
 786                     (rgb2rgb_coeff[3][0] << 27) | (rgb2rgb_coeff[0][0] << 18) |
 787                     (rgb2rgb_coeff[1][1] << 9) | rgb2rgb_coeff[2][2];
 788                 writel(param, base++);
 789                 /* scale = 2, sat = 0 */
 790                 param = (rgb2rgb_coeff[3][0] >> 5) | (2UL << 8);
 791                 writel(param, base++);
 792
 793                 param =
 794                     (rgb2rgb_coeff[3][1] << 27) | (rgb2rgb_coeff[0][1] << 18) |
 795                     (rgb2rgb_coeff[1][0] << 9) | rgb2rgb_coeff[2][0];
 796                 writel(param, base++);
 797                 param = (rgb2rgb_coeff[3][1] >> 5);
 798                 writel(param, base++);
 799
 800                 param =
 801                     (rgb2rgb_coeff[3][2] << 27) | (rgb2rgb_coeff[0][2] << 18) |
 802                     (rgb2rgb_coeff[1][2] << 9) | rgb2rgb_coeff[2][1];
 803                 writel(param, base++);
 804                 param = (rgb2rgb_coeff[3][2] >> 5);
 805                 writel(param, base++);
 806         } else {
 807                 dev_err(ipu->dev, "Unsupported color space conversion\n");
 808         }
 809 }
 810
 811 static bool _calc_resize_coeffs(struct ipu_soc *ipu,
 812                                 uint32_t inSize, uint32_t outSize,
 813                                 uint32_t *resizeCoeff,
 814                                 uint32_t *downsizeCoeff)
 815 {
 816         uint32_t tempSize;
 817         uint32_t tempDownsize;
 818
 819         /* Input size cannot be more than 4096 */
 820         /* Output size cannot be more than 1024 */
 821         if ((inSize > 4096) || (outSize > 1024))
 822                 return false;
 823
 824         /* Cannot downsize more than 8:1 */
 825         if ((outSize << 3) < inSize)
 826                 return false;
 827
 828         /* Compute downsizing coefficient */
 829         /* Output of downsizing unit cannot be more than 1024 */
 830         tempDownsize = 0;
 831         tempSize = inSize;
 832         while (((tempSize > 1024) || (tempSize >= outSize * 2)) &&
 833                (tempDownsize < 2)) {
 834                 tempSize >>= 1;
 835                 tempDownsize++;
 836         }
 837         *downsizeCoeff = tempDownsize;
 838
 839         /* compute resizing coefficient using the following equation:
 840            resizeCoeff = M*(SI -1)/(SO - 1)
 841            where M = 2^13, SI - input size, SO - output size    */
 842         *resizeCoeff = (8192L * (tempSize - 1)) / (outSize - 1);
 843         if (*resizeCoeff >= 16384L) {
 844                 dev_dbg(ipu->dev, "Warning! Overflow on resize coeff.\n");
 845                 *resizeCoeff = 0x3FFF;
 846         }
 847
 848         dev_dbg(ipu->dev, "resizing from %u -> %u pixels, "
 849                 "downsize=%u, resize=%u.%lu (reg=%u)\n", inSize, outSize,
 850                 *downsizeCoeff, (*resizeCoeff >= 8192L) ? 1 : 0,
 851                 ((*resizeCoeff & 0x1FFF) * 10000L) / 8192L, *resizeCoeff);
 852
 853         return true;
 854 }
 855
 856 void _ipu_vdi_toggle_top_field_man(struct ipu_soc *ipu)
 857 {
 858         uint32_t reg;
 859         uint32_t mask_reg;
 860
 861         reg = ipu_vdi_read(ipu, VDI_C);
 862         mask_reg = reg & VDI_C_TOP_FIELD_MAN_1;
 863         if (mask_reg == VDI_C_TOP_FIELD_MAN_1)
 864                 reg &= ~VDI_C_TOP_FIELD_MAN_1;
 865         else
 866                 reg |= VDI_C_TOP_FIELD_MAN_1;
 867
 868         ipu_vdi_write(ipu, reg, VDI_C);
 869 }
 870