1 /* bnx2x.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2012 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
16 #include <linux/netdevice.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/types.h>
20 /* compilation time flags */
22 /* define this to make the driver freeze on error to allow getting debug info
23 * (you will need to reboot afterwards) */
24 /* #define BNX2X_STOP_ON_ERROR */
26 #define DRV_MODULE_VERSION "1.78.00-0"
27 #define DRV_MODULE_RELDATE "2012/09/27"
28 #define BNX2X_BC_VER 0x040200
30 #if defined(CONFIG_DCB)
35 #include "bnx2x_hsi.h"
37 #include "../cnic_if.h"
40 #define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt)
42 #include <linux/mdio.h>
44 #include "bnx2x_reg.h"
45 #include "bnx2x_fw_defs.h"
46 #include "bnx2x_mfw_req.h"
47 #include "bnx2x_link.h"
49 #include "bnx2x_dcb.h"
50 #include "bnx2x_stats.h"
51 #include "bnx2x_vfpf.h"
59 /* error/debug prints */
61 #define DRV_MODULE_NAME "bnx2x"
63 /* for messages that are currently off */
64 #define BNX2X_MSG_OFF 0x0
65 #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */
66 #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */
67 #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */
68 #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */
69 #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */
70 #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */
71 #define BNX2X_MSG_IOV 0x0800000
72 #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/
73 #define BNX2X_MSG_ETHTOOL 0x4000000
74 #define BNX2X_MSG_DCB 0x8000000
76 /* regular debug print */
77 #define DP(__mask, fmt, ...) \
79 if (unlikely(bp->msg_enable & (__mask))) \
80 pr_notice("[%s:%d(%s)]" fmt, \
82 bp->dev ? (bp->dev->name) : "?", \
86 #define DP_CONT(__mask, fmt, ...) \
88 if (unlikely(bp->msg_enable & (__mask))) \
89 pr_cont(fmt, ##__VA_ARGS__); \
92 /* errors debug print */
93 #define BNX2X_DBG_ERR(fmt, ...) \
95 if (unlikely(netif_msg_probe(bp))) \
96 pr_err("[%s:%d(%s)]" fmt, \
98 bp->dev ? (bp->dev->name) : "?", \
102 /* for errors (never masked) */
103 #define BNX2X_ERR(fmt, ...) \
105 pr_err("[%s:%d(%s)]" fmt, \
106 __func__, __LINE__, \
107 bp->dev ? (bp->dev->name) : "?", \
111 #define BNX2X_ERROR(fmt, ...) \
112 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__)
115 /* before we have a dev->name use dev_info() */
116 #define BNX2X_DEV_INFO(fmt, ...) \
118 if (unlikely(netif_msg_probe(bp))) \
119 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \
122 #ifdef BNX2X_STOP_ON_ERROR
123 void bnx2x_int_disable(struct bnx2x *bp);
124 #define bnx2x_panic() \
127 BNX2X_ERR("driver assert\n"); \
128 bnx2x_int_disable(bp); \
129 bnx2x_panic_dump(bp); \
132 #define bnx2x_panic() \
135 BNX2X_ERR("driver assert\n"); \
136 bnx2x_panic_dump(bp); \
140 #define bnx2x_mc_addr(ha) ((ha)->addr)
141 #define bnx2x_uc_addr(ha) ((ha)->addr)
143 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
144 #define U64_HI(x) (u32)(((u64)(x)) >> 32)
145 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
148 #define REG_ADDR(bp, offset) ((bp->regview) + (offset))
150 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
151 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
152 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
154 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
155 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
156 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
158 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
159 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
161 #define REG_RD_DMAE(bp, offset, valp, len32) \
163 bnx2x_read_dmae(bp, offset, len32);\
164 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
167 #define REG_WR_DMAE(bp, offset, valp, len32) \
169 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
170 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
174 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
175 REG_WR_DMAE(bp, offset, valp, len32)
177 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
179 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
180 bnx2x_write_big_buf_wb(bp, addr, len32); \
183 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
184 offsetof(struct shmem_region, field))
185 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
186 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
188 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
189 offsetof(struct shmem2_region, field))
190 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
191 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
192 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
193 offsetof(struct mf_cfg, field))
194 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
195 offsetof(struct mf2_cfg, field))
197 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
198 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
199 MF_CFG_ADDR(bp, field), (val))
200 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
202 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
203 (SHMEM2_RD((bp), size) > \
204 offsetof(struct shmem2_region, field)))
206 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
207 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
211 /* General SP events - stats query, cfc delete, etc */
212 #define HC_SP_INDEX_ETH_DEF_CONS 3
215 #define HC_SP_INDEX_EQ_CONS 7
217 /* FCoE L2 connection completions */
218 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
219 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
221 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
222 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
224 /* Special clients parameters */
228 #define BNX2X_FCOE_L2_RX_INDEX \
229 (&bp->def_status_blk->sp_sb.\
230 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
232 #define BNX2X_FCOE_L2_TX_INDEX \
233 (&bp->def_status_blk->sp_sb.\
234 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
238 * CLIDs below is a CLID for func 0, then the CLID for other
239 * functions will be calculated by the formula:
241 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
245 BNX2X_ISCSI_ETH_CL_ID_IDX,
246 BNX2X_FCOE_ETH_CL_ID_IDX,
247 BNX2X_MAX_CNIC_ETH_CL_ID_IDX,
250 #define BNX2X_CNIC_START_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) *\
253 #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp))
255 #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1)
257 #define CNIC_SUPPORT(bp) ((bp)->cnic_support)
258 #define CNIC_ENABLED(bp) ((bp)->cnic_enabled)
259 #define CNIC_LOADED(bp) ((bp)->cnic_loaded)
260 #define FCOE_INIT(bp) ((bp)->fcoe_init)
262 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
263 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
268 /* defines for multiple tx priority indices */
269 #define FIRST_TX_ONLY_COS_INDEX 1
270 #define FIRST_TX_COS_INDEX 0
272 /* rules for calculating the cids of tx-only connections */
273 #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp))
274 #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \
275 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
277 /* fp index inside class of service range */
278 #define FP_COS_TO_TXQ(fp, cos, bp) \
279 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
281 /* Indexes for transmission queues array:
282 * txdata for RSS i CoS j is at location i + (j * num of RSS)
283 * txdata for FCoE (if exist) is at location max cos * num of RSS
284 * txdata for FWD (if exist) is one location after FCoE
285 * txdata for OOO (if exist) is one location after FWD
292 #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos)
293 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET)
297 * This driver uses new build_skb() API :
298 * RX ring buffer contains pointer to kmalloc() data only,
299 * skb are built only after Hardware filled the frame.
303 DEFINE_DMA_UNMAP_ADDR(mapping);
310 /* Set on the first BD descriptor when there is a split BD */
311 #define BNX2X_TSO_SPLIT_BD (1<<0)
316 DEFINE_DMA_UNMAP_ADDR(mapping);
320 struct doorbell_set_prod data;
324 /* dropless fc FW/HW related params */
325 #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512)
326 #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \
327 ETH_MAX_AGGREGATION_QUEUES_E1 :\
328 ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
329 #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp))
330 #define FW_PREFETCH_CNT 16
331 #define DROPLESS_FC_HEADROOM 100
334 #define BCM_PAGE_SHIFT 12
335 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
336 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
337 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
339 #define PAGES_PER_SGE_SHIFT 0
340 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
341 #define SGE_PAGE_SIZE PAGE_SIZE
342 #define SGE_PAGE_SHIFT PAGE_SHIFT
343 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
344 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE)
345 #define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \
348 /* SGE ring related macros */
349 #define NUM_RX_SGE_PAGES 2
350 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
351 #define NEXT_PAGE_SGE_DESC_CNT 2
352 #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
353 /* RX_SGE_CNT is promised to be a power of 2 */
354 #define RX_SGE_MASK (RX_SGE_CNT - 1)
355 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
356 #define MAX_RX_SGE (NUM_RX_SGE - 1)
357 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
358 (MAX_RX_SGE_CNT - 1)) ? \
359 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \
361 #define RX_SGE(x) ((x) & MAX_RX_SGE)
364 * Number of required SGEs is the sum of two:
365 * 1. Number of possible opened aggregations (next packet for
366 * these aggregations will probably consume SGE immidiatelly)
367 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
368 * after placement on BD for new TPA aggregation)
370 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page
372 #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \
373 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)
374 #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \
376 #define SGE_TH_LO(bp) (NUM_SGE_REQ + \
377 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT)
378 #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM)
380 /* Manipulate a bit vector defined as an array of u64 */
382 /* Number of bits in one sge_mask array element */
383 #define BIT_VEC64_ELEM_SZ 64
384 #define BIT_VEC64_ELEM_SHIFT 6
385 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1)
388 #define __BIT_VEC64_SET_BIT(el, bit) \
390 el = ((el) | ((u64)0x1 << (bit))); \
393 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
395 el = ((el) & (~((u64)0x1 << (bit)))); \
399 #define BIT_VEC64_SET_BIT(vec64, idx) \
400 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
401 (idx) & BIT_VEC64_ELEM_MASK)
403 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
404 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
405 (idx) & BIT_VEC64_ELEM_MASK)
407 #define BIT_VEC64_TEST_BIT(vec64, idx) \
408 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
409 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
411 /* Creates a bitmask of all ones in less significant bits.
412 idx - index of the most significant bit in the created mask */
413 #define BIT_VEC64_ONES_MASK(idx) \
414 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
415 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0))
417 /*******************************************************/
421 /* Number of u64 elements in SGE mask array */
422 #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ)
423 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
424 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
426 union host_hc_status_block {
427 /* pointer to fp status block e1x */
428 struct host_hc_status_block_e1x *e1x_sb;
429 /* pointer to fp status block e2 */
430 struct host_hc_status_block_e2 *e2_sb;
433 struct bnx2x_agg_info {
435 * First aggregation buffer is a data buffer, the following - are pages.
436 * We will preallocate the data buffer for each aggregation when
437 * we open the interface and will replace the BD at the consumer
438 * with this one when we receive the TPA_START CQE in order to
439 * keep the Rx BD ring consistent.
441 struct sw_rx_bd first_buf;
443 #define BNX2X_TPA_START 1
444 #define BNX2X_TPA_STOP 2
445 #define BNX2X_TPA_ERROR 3
456 #define Q_STATS_OFFSET32(stat_name) \
457 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
459 struct bnx2x_fp_txdata {
461 struct sw_tx_bd *tx_buf_ring;
463 union eth_tx_bd_types *tx_desc_ring;
464 dma_addr_t tx_desc_mapping;
475 unsigned long tx_pkt;
480 struct bnx2x_fastpath *parent_fp;
484 enum bnx2x_tpa_mode_t {
489 struct bnx2x_fastpath {
490 struct bnx2x *bp; /* parent */
492 #define BNX2X_NAPI_WEIGHT 128
493 struct napi_struct napi;
494 union host_hc_status_block status_blk;
495 /* chip independed shortcuts into sb structure */
496 __le16 *sb_index_values;
497 __le16 *sb_running_index;
498 /* chip independed shortcut into rx_prods_offset memory */
499 u32 ustorm_rx_prods_offset;
502 u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */
503 dma_addr_t status_blk_mapping;
505 enum bnx2x_tpa_mode_t mode;
507 u8 max_cos; /* actual number of active tx coses */
508 struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS];
510 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
511 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
513 struct eth_rx_bd *rx_desc_ring;
514 dma_addr_t rx_desc_mapping;
516 union eth_rx_cqe *rx_comp_ring;
517 dma_addr_t rx_comp_mapping;
520 struct eth_rx_sge *rx_sge_ring;
521 dma_addr_t rx_sge_mapping;
523 u64 sge_mask[RX_SGE_MASK_LEN];
529 u8 index; /* number in fp array */
530 u8 rx_queue; /* index for skb_record */
531 u8 cl_id; /* eth client id */
533 u8 fw_sb_id; /* status block number in FW */
534 u8 igu_sb_id; /* status block number in HW */
541 /* The last maximal completed SGE */
544 unsigned long rx_pkt,
548 struct bnx2x_agg_info *tpa_info;
550 #ifdef BNX2X_STOP_ON_ERROR
553 /* The size is calculated using the following:
554 sizeof name field from netdev structure +
556 4 (for the digits and to make it DWORD aligned) */
557 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
558 char name[FP_NAME_SIZE];
561 #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var)
562 #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index])
563 #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index]))
564 #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats))
566 /* Use 2500 as a mini-jumbo MTU for FCoE */
567 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500
569 #define FCOE_IDX_OFFSET 0
571 #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \
573 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)])
574 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
575 #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)])
576 #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var)
577 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \
578 txdata_ptr[FIRST_TX_COS_INDEX] \
582 #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp))
583 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp))
584 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp))
588 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
589 #define RX_COPY_THRESH 92
591 #define NUM_TX_RINGS 16
592 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
593 #define NEXT_PAGE_TX_DESC_CNT 1
594 #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT)
595 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
596 #define MAX_TX_BD (NUM_TX_BD - 1)
597 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
598 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
599 (MAX_TX_DESC_CNT - 1)) ? \
600 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \
602 #define TX_BD(x) ((x) & MAX_TX_BD)
603 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
605 /* number of NEXT_PAGE descriptors may be required during placement */
606 #define NEXT_CNT_PER_TX_PKT(bds) \
607 (((bds) + MAX_TX_DESC_CNT - 1) / \
608 MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT)
609 /* max BDs per tx packet w/o next_pages:
610 * START_BD - describes packed
611 * START_BD(splitted) - includes unpaged data segment for GSO
612 * PARSING_BD - for TSO and CSUM data
613 * Frag BDs - decribes pages for frags
615 #define BDS_PER_TX_PKT 3
616 #define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT)
617 /* max BDs per tx packet including next pages */
618 #define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \
619 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT))
621 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
622 #define NUM_RX_RINGS 8
623 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
624 #define NEXT_PAGE_RX_DESC_CNT 2
625 #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT)
626 #define RX_DESC_MASK (RX_DESC_CNT - 1)
627 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
628 #define MAX_RX_BD (NUM_RX_BD - 1)
629 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
631 /* dropless fc calculations for BDs
633 * Number of BDs should as number of buffers in BRB:
634 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT
635 * "next" elements on each page
637 #define NUM_BD_REQ BRB_SIZE(bp)
638 #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \
640 #define BD_TH_LO(bp) (NUM_BD_REQ + \
641 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \
643 #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM)
645 #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)
647 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \
648 ETH_MIN_RX_CQES_WITH_TPA_E1 : \
649 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
650 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
651 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
652 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
655 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
656 (MAX_RX_DESC_CNT - 1)) ? \
657 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \
659 #define RX_BD(x) ((x) & MAX_RX_BD)
662 * As long as CQE is X times bigger than BD entry we have to allocate X times
663 * more pages for CQ ring in order to keep it balanced with BD ring
665 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
666 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL)
667 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
668 #define NEXT_PAGE_RCQ_DESC_CNT 1
669 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT)
670 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
671 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
672 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
673 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
674 (MAX_RCQ_DESC_CNT - 1)) ? \
675 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \
677 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
679 /* dropless fc calculations for RCQs
681 * Number of RCQs should be as number of buffers in BRB:
682 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT
683 * "next" elements on each page
685 #define NUM_RCQ_REQ BRB_SIZE(bp)
686 #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \
688 #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \
689 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \
691 #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM)
694 /* This is needed for determining of last_max */
695 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
696 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b))
699 #define BNX2X_SWCID_SHIFT 17
700 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
702 /* used on a CID received from the HW */
703 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK)
704 #define CQE_CMD(x) (le32_to_cpu(x) >> \
705 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
707 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
708 le32_to_cpu((bd)->addr_lo))
709 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
711 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
712 #define BNX2X_DB_SHIFT 7 /* 128 bytes*/
713 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
714 #error "Min DB doorbell stride is 8"
716 #define DPM_TRIGER_TYPE 0x40
717 #define DOORBELL(bp, cid, val) \
719 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \
724 /* TX CSUM helpers */
725 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
727 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
730 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
733 #define XMIT_CSUM_V4 0x1
734 #define XMIT_CSUM_V6 0x2
735 #define XMIT_CSUM_TCP 0x4
736 #define XMIT_GSO_V4 0x8
737 #define XMIT_GSO_V6 0x10
739 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
740 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
743 /* stuff added to make the code fit 80Col */
744 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
745 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
746 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
747 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
748 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
750 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
752 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
753 (((le16_to_cpu(flags) & \
754 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
755 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
756 == PRS_FLAG_OVERETH_IPV4)
757 #define BNX2X_RX_SUM_FIX(cqe) \
758 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
761 #define FP_USB_FUNC_OFF \
762 offsetof(struct cstorm_status_block_u, func)
763 #define FP_CSB_FUNC_OFF \
764 offsetof(struct cstorm_status_block_c, func)
766 #define HC_INDEX_ETH_RX_CQ_CONS 1
768 #define HC_INDEX_OOO_TX_CQ_CONS 4
770 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
772 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
774 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
776 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
778 #define BNX2X_RX_SB_INDEX \
779 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
781 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0
783 #define BNX2X_TX_SB_INDEX_COS0 \
784 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0])
786 /* end of fast path */
790 struct bnx2x_common {
793 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
794 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
796 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
797 #define CHIP_NUM_57710 0x164e
798 #define CHIP_NUM_57711 0x164f
799 #define CHIP_NUM_57711E 0x1650
800 #define CHIP_NUM_57712 0x1662
801 #define CHIP_NUM_57712_MF 0x1663
802 #define CHIP_NUM_57713 0x1651
803 #define CHIP_NUM_57713E 0x1652
804 #define CHIP_NUM_57800 0x168a
805 #define CHIP_NUM_57800_MF 0x16a5
806 #define CHIP_NUM_57810 0x168e
807 #define CHIP_NUM_57810_MF 0x16ae
808 #define CHIP_NUM_57811 0x163d
809 #define CHIP_NUM_57811_MF 0x163e
810 #define CHIP_NUM_57840_OBSOLETE 0x168d
811 #define CHIP_NUM_57840_MF_OBSOLETE 0x16ab
812 #define CHIP_NUM_57840_4_10 0x16a1
813 #define CHIP_NUM_57840_2_20 0x16a2
814 #define CHIP_NUM_57840_MF 0x16a4
815 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
816 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
817 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
818 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
819 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
820 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800)
821 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
822 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810)
823 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
824 #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811)
825 #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF)
826 #define CHIP_IS_57840(bp) \
827 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \
828 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \
829 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE))
830 #define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \
831 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE))
832 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
834 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
835 CHIP_IS_57712_MF(bp))
836 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \
837 CHIP_IS_57800_MF(bp) || \
838 CHIP_IS_57810(bp) || \
839 CHIP_IS_57810_MF(bp) || \
840 CHIP_IS_57811(bp) || \
841 CHIP_IS_57811_MF(bp) || \
842 CHIP_IS_57840(bp) || \
843 CHIP_IS_57840_MF(bp))
844 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
845 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp))
846 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp))
848 #define CHIP_REV_SHIFT 12
849 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
850 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK)
851 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
852 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
853 /* assume maximum 5 revisions */
854 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000)
855 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
856 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
857 !(CHIP_REV_VAL(bp) & 0x00001000))
858 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
859 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
860 (CHIP_REV_VAL(bp) & 0x00001000))
862 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
863 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
865 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
866 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
867 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
868 (CHIP_REV_SHIFT + 1)) \
870 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \
873 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \
874 (CHIP_REV(bp) == CHIP_REV_Bx))
875 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \
876 (CHIP_REV(bp) == CHIP_REV_Ax))
877 /* This define is used in two main places:
878 * 1. In the early stages of nic_load, to know if to configrue Parser / Searcher
879 * to nic-only mode or to offload mode. Offload mode is configured if either the
880 * chip is E1x (where MIC_MODE register is not applicable), or if cnic already
881 * registered for this port (which means that the user wants storage services).
882 * 2. During cnic-related load, to know if offload mode is already configured in
883 * the HW or needs to be configrued.
884 * Since the transition from nic-mode to offload-mode in HW causes traffic
885 * coruption, nic-mode is configured only in ports on which storage services
886 * where never requested.
888 #define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp))
891 #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
892 #define BNX2X_NVRAM_TIMEOUT_COUNT 30000
893 #define BNX2X_NVRAM_PAGE_SIZE 256
905 #define INT_BLOCK_HC 0
906 #define INT_BLOCK_IGU 1
907 #define INT_BLOCK_MODE_NORMAL 0
908 #define INT_BLOCK_MODE_BW_COMP 2
909 #define CHIP_INT_MODE_IS_NBC(bp) \
910 (!CHIP_IS_E1x(bp) && \
911 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
912 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
915 #define CHIP_4_PORT_MODE 0x0
916 #define CHIP_2_PORT_MODE 0x1
917 #define CHIP_PORT_MODE_NONE 0x2
918 #define CHIP_MODE(bp) (bp->common.chip_port_mode)
919 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
924 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
925 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
926 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
928 #define MAX_IGU_ATTN_ACK_TO 100
936 u32 link_config[LINK_CONFIG_SIZE];
938 u32 supported[LINK_CONFIG_SIZE];
939 /* link settings - missing defines */
940 #define SUPPORTED_2500baseX_Full (1 << 15)
942 u32 advertising[LINK_CONFIG_SIZE];
943 /* link settings - missing defines */
944 #define ADVERTISED_2500baseX_Full (1 << 15)
948 /* used to synchronize phy accesses */
949 struct mutex phy_mutex;
953 struct nig_stats old_nig_stats;
958 #define STATS_OFFSET32(stat_name) \
959 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
963 /* slow path work-queue */
964 extern struct workqueue_struct *bnx2x_wq;
966 #define BNX2X_MAX_NUM_OF_VFS 64
967 #define BNX2X_VF_CID_WND 0
968 #define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND)
969 #define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF)
970 #define BNX2X_VF_ID_INVALID 0xFF
973 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
974 * control by the number of fast-path status blocks supported by the
975 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
976 * status block represents an independent interrupts context that can
977 * serve a regular L2 networking queue. However special L2 queues such
978 * as the FCoE queue do not require a FP-SB and other components like
979 * the CNIC may consume FP-SB reducing the number of possible L2 queues
981 * If the maximum number of FP-SB available is X then:
982 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
983 * regular L2 queues is Y=X-1
984 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
985 * c. If the FCoE L2 queue is supported the actual number of L2 queues
987 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
988 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
989 * FP interrupt context for the CNIC).
990 * e. The number of HW context (CID count) is always X or X+1 if FCoE
991 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
994 /* fast-path interrupt contexts E1x */
995 #define FP_SB_MAX_E1x 16
996 /* fast-path interrupt contexts E2 */
997 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
1000 struct eth_context eth;
1004 /* CDU host DB constants */
1005 #define CDU_ILT_PAGE_SZ_HW 2
1006 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
1007 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
1009 #define CNIC_ISCSI_CID_MAX 256
1010 #define CNIC_FCOE_CID_MAX 2048
1011 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
1012 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
1014 #define QM_ILT_PAGE_SZ_HW 0
1015 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
1016 #define QM_CID_ROUND 1024
1018 /* TM (timers) host DB constants */
1019 #define TM_ILT_PAGE_SZ_HW 0
1020 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
1021 /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
1022 #define TM_CONN_NUM 1024
1023 #define TM_ILT_SZ (8 * TM_CONN_NUM)
1024 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
1026 /* SRC (Searcher) host DB constants */
1027 #define SRC_ILT_PAGE_SZ_HW 0
1028 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
1029 #define SRC_HASH_BITS 10
1030 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
1031 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
1032 #define SRC_T2_SZ SRC_ILT_SZ
1033 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
1035 #define MAX_DMAE_C 8
1037 /* DMA memory not used in fastpath */
1038 struct bnx2x_slowpath {
1040 struct mac_configuration_cmd e1x;
1041 struct eth_classify_rules_ramrod_data e2;
1046 struct tstorm_eth_mac_filter_config e1x;
1047 struct eth_filter_rules_ramrod_data e2;
1051 struct mac_configuration_cmd e1;
1052 struct eth_multicast_rules_ramrod_data e2;
1055 struct eth_rss_update_ramrod_data rss_rdata;
1057 /* Queue State related ramrods are always sent under rtnl_lock */
1059 struct client_init_ramrod_data init_data;
1060 struct client_update_ramrod_data update_data;
1064 struct function_start_data func_start;
1065 /* pfc configuration for DCBX ramrod */
1066 struct flow_control_configuration pfc_config;
1069 /* afex ramrod can not be a part of func_rdata union because these
1070 * events might arrive in parallel to other events from func_rdata.
1071 * Therefore, if they would have been defined in the same union,
1072 * data can get corrupted.
1074 struct afex_vif_list_ramrod_data func_afex_rdata;
1076 /* used by dmae command executer */
1077 struct dmae_command dmae[MAX_DMAE_C];
1080 union mac_stats mac_stats;
1081 struct nig_stats nig_stats;
1082 struct host_port_stats port_stats;
1083 struct host_func_stats func_stats;
1088 union drv_info_to_mcp drv_info_to_mcp;
1091 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
1092 #define bnx2x_sp_mapping(bp, var) \
1093 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
1096 /* attn group wiring */
1097 #define MAX_DYNAMIC_ATTN_GRPS 8
1112 union cdu_context *vcxt;
1113 dma_addr_t cxt_mapping;
1121 enum bnx2x_recovery_state {
1122 BNX2X_RECOVERY_DONE,
1123 BNX2X_RECOVERY_INIT,
1124 BNX2X_RECOVERY_WAIT,
1125 BNX2X_RECOVERY_FAILED,
1126 BNX2X_RECOVERY_NIC_LOADING
1130 * Event queue (EQ or event ring) MC hsi
1131 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
1133 #define NUM_EQ_PAGES 1
1134 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1135 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1136 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1137 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1138 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1140 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1141 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
1142 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1144 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1145 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1147 #define BNX2X_EQ_INDEX \
1148 (&bp->def_status_blk->sp_sb.\
1149 index_values[HC_SP_INDEX_EQ_CONS])
1151 /* This is a data that will be used to create a link report message.
1152 * We will keep the data used for the last link report in order
1153 * to prevent reporting the same link parameters twice.
1155 struct bnx2x_link_report_data {
1156 u16 line_speed; /* Effective line speed */
1157 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
1161 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */
1162 BNX2X_LINK_REPORT_LINK_DOWN,
1163 BNX2X_LINK_REPORT_RX_FC_ON,
1164 BNX2X_LINK_REPORT_TX_FC_ON,
1168 BNX2X_PORT_QUERY_IDX,
1170 BNX2X_FCOE_QUERY_IDX,
1171 BNX2X_FIRST_QUEUE_QUERY_IDX,
1174 struct bnx2x_fw_stats_req {
1175 struct stats_query_header hdr;
1176 struct stats_query_entry query[FP_SB_MAX_E1x+
1177 BNX2X_FIRST_QUEUE_QUERY_IDX];
1180 struct bnx2x_fw_stats_data {
1181 struct stats_counter storm_counters;
1182 struct per_port_stats port;
1183 struct per_pf_stats pf;
1184 struct fcoe_statistics_params fcoe;
1185 struct per_queue_stats queue_stats[1];
1188 /* Public slow path states */
1190 BNX2X_SP_RTNL_SETUP_TC,
1191 BNX2X_SP_RTNL_TX_TIMEOUT,
1192 BNX2X_SP_RTNL_AFEX_F_UPDATE,
1193 BNX2X_SP_RTNL_FAN_FAILURE,
1197 struct bnx2x_prev_path_list {
1201 struct list_head list;
1205 struct bnx2x_sp_objs {
1207 struct bnx2x_vlan_mac_obj mac_obj;
1209 /* Queue State object */
1210 struct bnx2x_queue_sp_obj q_obj;
1213 struct bnx2x_fp_stats {
1214 struct tstorm_per_queue_stats old_tclient;
1215 struct ustorm_per_queue_stats old_uclient;
1216 struct xstorm_per_queue_stats old_xclient;
1217 struct bnx2x_eth_q_stats eth_q_stats;
1218 struct bnx2x_eth_q_stats_old eth_q_stats_old;
1222 /* Fields used in the tx and intr/napi performance paths
1223 * are grouped together in the beginning of the structure
1225 struct bnx2x_fastpath *fp;
1226 struct bnx2x_sp_objs *sp_objs;
1227 struct bnx2x_fp_stats *fp_stats;
1228 struct bnx2x_fp_txdata *bnx2x_txq;
1229 void __iomem *regview;
1230 void __iomem *doorbells;
1233 u8 pf_num; /* absolute PF number */
1234 u8 pfid; /* per-path PF number */
1235 int base_fw_ndsb; /**/
1236 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1237 #define BP_PORT(bp) (bp->pfid & 1)
1238 #define BP_FUNC(bp) (bp->pfid)
1239 #define BP_ABS_FUNC(bp) (bp->pf_num)
1240 #define BP_VN(bp) ((bp)->pfid >> 1)
1241 #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)
1242 #define BP_L_ID(bp) (BP_VN(bp) << 2)
1243 #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\
1244 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1))
1245 #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp))
1247 /* vf pf channel mailbox contains request and response buffers */
1248 struct bnx2x_vf_mbx_msg *vf2pf_mbox;
1249 dma_addr_t vf2pf_mbox_mapping;
1251 /* we set aside a copy of the acquire response */
1252 struct pfvf_acquire_resp_tlv acquire_resp;
1254 struct net_device *dev;
1255 struct pci_dev *pdev;
1257 const struct iro *iro_arr;
1258 #define IRO (bp->iro_arr)
1260 enum bnx2x_recovery_state recovery_state;
1262 struct msix_entry *msix_table;
1266 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1267 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
1268 #define ETH_MIN_PACKET_SIZE 60
1269 #define ETH_MAX_PACKET_SIZE 1500
1270 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
1271 /* TCP with Timestamp Option (32) + IPv6 (40) */
1272 #define ETH_MAX_TPA_HEADER_SIZE 72
1274 /* Max supported alignment is 256 (8 shift) */
1275 #define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT)
1277 /* FW uses 2 Cache lines Alignment for start packet and size
1279 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes
1280 * at the end of skb->data, to avoid wasting a full cache line.
1281 * This reduces memory use (skb->truesize).
1283 #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT)
1285 #define BNX2X_FW_RX_ALIGN_END \
1286 max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \
1287 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
1289 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
1291 struct host_sp_status_block *def_status_blk;
1292 #define DEF_SB_IGU_ID 16
1293 #define DEF_SB_ID HC_SP_SB_ID
1297 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1299 /* slow path ring */
1300 struct eth_spe *spq;
1301 dma_addr_t spq_mapping;
1303 struct eth_spe *spq_prod_bd;
1304 struct eth_spe *spq_last_bd;
1305 __le16 *dsb_sp_prod;
1306 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */
1307 /* used to synchronize spq accesses */
1308 spinlock_t spq_lock;
1311 union event_ring_elem *eq_ring;
1312 dma_addr_t eq_mapping;
1316 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */
1320 /* Counter for marking that there is a STAT_QUERY ramrod pending */
1322 /* Counter for completed statistics ramrods */
1325 /* End of fields used in the performance code paths */
1331 #define PCIX_FLAG (1 << 0)
1332 #define PCI_32BIT_FLAG (1 << 1)
1333 #define ONE_PORT_FLAG (1 << 2)
1334 #define NO_WOL_FLAG (1 << 3)
1335 #define USING_DAC_FLAG (1 << 4)
1336 #define USING_MSIX_FLAG (1 << 5)
1337 #define USING_MSI_FLAG (1 << 6)
1338 #define DISABLE_MSI_FLAG (1 << 7)
1339 #define TPA_ENABLE_FLAG (1 << 8)
1340 #define NO_MCP_FLAG (1 << 9)
1341 #define GRO_ENABLE_FLAG (1 << 10)
1342 #define MF_FUNC_DIS (1 << 11)
1343 #define OWN_CNIC_IRQ (1 << 12)
1344 #define NO_ISCSI_OOO_FLAG (1 << 13)
1345 #define NO_ISCSI_FLAG (1 << 14)
1346 #define NO_FCOE_FLAG (1 << 15)
1347 #define BC_SUPPORTS_PFC_STATS (1 << 17)
1348 #define BC_SUPPORTS_FCOE_FEATURES (1 << 19)
1349 #define USING_SINGLE_MSIX_FLAG (1 << 20)
1350 #define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21)
1351 #define IS_VF_FLAG (1 << 22)
1353 #define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG)
1354 #define IS_VF(bp) ((bp)->flags & IS_VF_FLAG)
1355 #define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG))
1357 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
1358 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
1359 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
1364 struct cnic_eth_dev *(*cnic_probe)(struct net_device *);
1366 /* Flag that indicates that we can start looking for FCoE L2 queue
1367 * completions in the default status block.
1374 struct delayed_work sp_task;
1375 struct delayed_work sp_rtnl_task;
1377 struct delayed_work period_task;
1378 struct timer_list timer;
1379 int current_interval;
1382 u16 fw_drv_pulse_wr_seq;
1385 struct link_params link_params;
1386 struct link_vars link_vars;
1388 struct bnx2x_link_report_data last_reported_link;
1390 struct mdio_if_info mdio;
1392 struct bnx2x_common common;
1393 struct bnx2x_port port;
1395 struct cmng_init cmng;
1397 u32 mf_config[E1HVN_MAX];
1399 u32 path_has_ovlan; /* E3 */
1402 #define IS_MF(bp) (bp->mf_mode != 0)
1403 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI)
1404 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD)
1405 #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX)
1411 u16 tx_quick_cons_trip_int;
1412 u16 tx_quick_cons_trip;
1416 u16 rx_quick_cons_trip_int;
1417 u16 rx_quick_cons_trip;
1420 /* Maximal coalescing timeout in us */
1421 #define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
1426 #define BNX2X_STATE_CLOSED 0
1427 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
1428 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
1429 #define BNX2X_STATE_OPEN 0x3000
1430 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
1431 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1433 #define BNX2X_STATE_DIAG 0xe000
1434 #define BNX2X_STATE_ERROR 0xf000
1436 #define BNX2X_MAX_PRIORITY 8
1437 #define BNX2X_MAX_ENTRIES_PER_PRI 16
1438 #define BNX2X_MAX_COS 3
1439 #define BNX2X_MAX_TX_COS 2
1441 uint num_ethernet_queues;
1442 uint num_cnic_queues;
1443 int num_napi_queues;
1447 #define BNX2X_RX_MODE_NONE 0
1448 #define BNX2X_RX_MODE_NORMAL 1
1449 #define BNX2X_RX_MODE_ALLMULTI 2
1450 #define BNX2X_RX_MODE_PROMISC 3
1451 #define BNX2X_MAX_MULTICAST 64
1456 u8 min_msix_vec_cnt;
1459 dma_addr_t def_status_blk_mapping;
1461 struct bnx2x_slowpath *slowpath;
1462 dma_addr_t slowpath_mapping;
1464 /* Total number of FW statistics requests */
1468 * This is a memory buffer that will contain both statistics
1469 * ramrod request and data.
1472 dma_addr_t fw_stats_mapping;
1475 * FW statistics request shortcut (points at the
1476 * beginning of fw_stats buffer).
1478 struct bnx2x_fw_stats_req *fw_stats_req;
1479 dma_addr_t fw_stats_req_mapping;
1480 int fw_stats_req_sz;
1483 * FW statistics data shortcut (points at the beginning of
1484 * fw_stats buffer + fw_stats_req_sz).
1486 struct bnx2x_fw_stats_data *fw_stats_data;
1487 dma_addr_t fw_stats_data_mapping;
1488 int fw_stats_data_sz;
1490 /* For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB
1491 * context size we need 8 ILT entries.
1493 #define ILT_MAX_L2_LINES 8
1494 struct hw_context context[ILT_MAX_L2_LINES];
1496 struct bnx2x_ilt *ilt;
1497 #define BP_ILT(bp) ((bp)->ilt)
1498 #define ILT_MAX_LINES 256
1500 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes
1503 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp))
1506 * Maximum CID count that might be required by the bnx2x:
1507 * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI
1509 #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \
1510 + 2 * CNIC_SUPPORT(bp))
1511 #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \
1512 + 2 * CNIC_SUPPORT(bp))
1513 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1521 dma_addr_t t2_mapping;
1522 struct cnic_ops __rcu *cnic_ops;
1525 struct cnic_eth_dev cnic_eth_dev;
1526 union host_hc_status_block cnic_sb;
1527 dma_addr_t cnic_sb_mapping;
1528 struct eth_spe *cnic_kwq;
1529 struct eth_spe *cnic_kwq_prod;
1530 struct eth_spe *cnic_kwq_cons;
1531 struct eth_spe *cnic_kwq_last;
1532 u16 cnic_kwq_pending;
1533 u16 cnic_spq_pending;
1534 u8 fip_mac[ETH_ALEN];
1535 struct mutex cnic_mutex;
1536 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
1538 /* Start index of the "special" (CNIC related) L2 cleints */
1542 /* used to synchronize dmae accesses */
1543 spinlock_t dmae_lock;
1545 /* used to protect the FW mail box */
1546 struct mutex fw_mb_mutex;
1548 /* used to synchronize stats collecting */
1551 /* used for synchronization of concurrent threads statistics handling */
1552 spinlock_t stats_lock;
1554 /* used by dmae command loader */
1555 struct dmae_command stats_dmae;
1559 struct bnx2x_eth_stats eth_stats;
1560 struct host_func_stats func_stats;
1561 struct bnx2x_eth_stats_old eth_stats_old;
1562 struct bnx2x_net_stats_old net_stats_old;
1563 struct bnx2x_fw_port_stats_old fw_stats_old;
1566 struct z_stream_s *strm;
1568 dma_addr_t gunzip_mapping;
1570 #define FW_BUF_SIZE 0x8000
1571 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1572 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1573 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1575 struct raw_op *init_ops;
1576 /* Init blocks offsets inside init_ops */
1577 u16 *init_ops_offsets;
1578 /* Data blob - has 32 bit granularity */
1580 u32 init_mode_flags;
1581 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags)
1582 /* Zipped PRAM blobs - raw data */
1583 const u8 *tsem_int_table_data;
1584 const u8 *tsem_pram_data;
1585 const u8 *usem_int_table_data;
1586 const u8 *usem_pram_data;
1587 const u8 *xsem_int_table_data;
1588 const u8 *xsem_pram_data;
1589 const u8 *csem_int_table_data;
1590 const u8 *csem_pram_data;
1591 #define INIT_OPS(bp) (bp->init_ops)
1592 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1593 #define INIT_DATA(bp) (bp->init_data)
1594 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1595 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1596 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1597 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1598 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1599 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1600 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1601 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1603 #define PHY_FW_VER_LEN 20
1605 const struct firmware *firmware;
1607 /* DCB support on/off */
1609 #define BNX2X_DCB_STATE_OFF 0
1610 #define BNX2X_DCB_STATE_ON 1
1612 /* DCBX engine mode */
1614 #define BNX2X_DCBX_ENABLED_OFF 0
1615 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1616 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1617 #define BNX2X_DCBX_ENABLED_INVALID (-1)
1619 bool dcbx_mode_uset;
1621 struct bnx2x_config_dcbx_params dcbx_config_params;
1622 struct bnx2x_dcbx_port_params dcbx_port_params;
1625 /* CAM credit pools */
1626 struct bnx2x_credit_pool_obj macs_pool;
1628 /* RX_MODE object */
1629 struct bnx2x_rx_mode_obj rx_mode_obj;
1632 struct bnx2x_mcast_obj mcast_obj;
1634 /* RSS configuration object */
1635 struct bnx2x_rss_config_obj rss_conf_obj;
1637 /* Function State controlling object */
1638 struct bnx2x_func_sp_obj func_obj;
1640 unsigned long sp_state;
1642 /* operation indication for the sp_rtnl task */
1643 unsigned long sp_rtnl_state;
1645 /* DCBX Negotation results */
1646 struct dcbx_features dcbx_local_feat;
1650 struct dcbx_features dcbx_remote_feat;
1651 u32 dcbx_remote_flags;
1653 /* AFEX: store default vlan used */
1654 int afex_def_vlan_tag;
1655 enum mf_cfg_afex_vlan_mode afex_vlan_mode;
1658 /* multiple tx classes of service */
1661 /* priority to cos mapping */
1665 /* Tx queues may be less or equal to Rx queues */
1666 extern int num_queues;
1667 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1668 #define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues)
1669 #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \
1670 (bp)->num_cnic_queues)
1671 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp)
1673 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1675 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp)
1676 /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */
1678 #define RSS_IPV4_CAP_MASK \
1679 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1681 #define RSS_IPV4_TCP_CAP_MASK \
1682 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1684 #define RSS_IPV6_CAP_MASK \
1685 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1687 #define RSS_IPV6_TCP_CAP_MASK \
1688 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1690 /* func init flags */
1691 #define FUNC_FLG_RSS 0x0001
1692 #define FUNC_FLG_STATS 0x0002
1693 /* removed FUNC_FLG_UNMATCHED 0x0004 */
1694 #define FUNC_FLG_TPA 0x0008
1695 #define FUNC_FLG_SPQ 0x0010
1696 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1699 struct bnx2x_func_init_params {
1701 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */
1702 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */
1705 u16 func_id; /* abs fid */
1707 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */
1710 #define for_each_cnic_queue(bp, var) \
1711 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1713 if (skip_queue(bp, var)) \
1717 #define for_each_eth_queue(bp, var) \
1718 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1720 #define for_each_nondefault_eth_queue(bp, var) \
1721 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1723 #define for_each_queue(bp, var) \
1724 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1725 if (skip_queue(bp, var)) \
1729 /* Skip forwarding FP */
1730 #define for_each_valid_rx_queue(bp, var) \
1732 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
1733 BNX2X_NUM_ETH_QUEUES(bp)); \
1735 if (skip_rx_queue(bp, var)) \
1739 #define for_each_rx_queue_cnic(bp, var) \
1740 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1742 if (skip_rx_queue(bp, var)) \
1746 #define for_each_rx_queue(bp, var) \
1747 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1748 if (skip_rx_queue(bp, var)) \
1753 #define for_each_valid_tx_queue(bp, var) \
1755 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
1756 BNX2X_NUM_ETH_QUEUES(bp)); \
1758 if (skip_tx_queue(bp, var)) \
1762 #define for_each_tx_queue_cnic(bp, var) \
1763 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1765 if (skip_tx_queue(bp, var)) \
1769 #define for_each_tx_queue(bp, var) \
1770 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1771 if (skip_tx_queue(bp, var)) \
1775 #define for_each_nondefault_queue(bp, var) \
1776 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1777 if (skip_queue(bp, var)) \
1781 #define for_each_cos_in_tx_queue(fp, var) \
1782 for ((var) = 0; (var) < (fp)->max_cos; (var)++)
1785 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1787 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1790 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1792 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1794 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1800 * bnx2x_set_mac_one - configure a single MAC address
1802 * @bp: driver handle
1803 * @mac: MAC to configure
1804 * @obj: MAC object handle
1805 * @set: if 'true' add a new MAC, otherwise - delete
1806 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list)
1807 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT)
1809 * Configures one MAC according to provided parameters or continues the
1810 * execution of previously scheduled commands if RAMROD_CONT is set in
1813 * Returns zero if operation has successfully completed, a positive value if the
1814 * operation has been successfully scheduled and a negative - if a requested
1815 * operations has failed.
1817 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
1818 struct bnx2x_vlan_mac_obj *obj, bool set,
1819 int mac_type, unsigned long *ramrod_flags);
1821 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
1823 * @bp: driver handle
1824 * @mac_obj: MAC object handle
1825 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC)
1826 * @wait_for_comp: if 'true' block until completion
1828 * Deletes all MACs of the specific type (e.g. ETH, UC list).
1830 * Returns zero if operation has successfully completed, a positive value if the
1831 * operation has been successfully scheduled and a negative - if a requested
1832 * operations has failed.
1834 int bnx2x_del_all_macs(struct bnx2x *bp,
1835 struct bnx2x_vlan_mac_obj *mac_obj,
1836 int mac_type, bool wait_for_comp);
1838 /* Init Function API */
1839 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
1840 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1841 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1842 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
1843 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1844 void bnx2x_read_mf_cfg(struct bnx2x *bp);
1848 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1849 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1851 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
1852 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
1853 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
1854 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
1855 bool with_comp, u8 comp_type);
1858 void bnx2x_calc_fc_adv(struct bnx2x *bp);
1859 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
1860 u32 data_hi, u32 data_lo, int cmd_type);
1861 void bnx2x_update_coalesce(struct bnx2x *bp);
1862 int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
1864 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1870 val = REG_RD(bp, reg);
1871 if (val == expected)
1881 #define BNX2X_ILT_ZALLOC(x, y, size) \
1883 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
1885 memset(x, 0, size); \
1888 #define BNX2X_ILT_FREE(x, y, size) \
1891 dma_free_coherent(&bp->pdev->dev, size, x, y); \
1897 #define ILOG2(x) (ilog2((x)))
1899 #define ILT_NUM_PAGE_ENTRIES (3072)
1900 /* In 57710/11 we use whole table since we have 8 func
1901 * In 57712 we have only 4 func, but use same size per func, then only half of
1904 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
1906 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
1908 * the phys address is shifted right 12 bits and has an added
1909 * 1=valid bit added to the 53rd bit
1910 * then since this is a wide register(TM)
1911 * we split it into two 32 bit writes
1913 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
1914 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
1916 /* load/unload mode */
1917 #define LOAD_NORMAL 0
1920 #define LOAD_LOOPBACK_EXT 3
1921 #define UNLOAD_NORMAL 0
1922 #define UNLOAD_CLOSE 1
1923 #define UNLOAD_RECOVERY 2
1926 /* DMAE command defines */
1927 #define DMAE_TIMEOUT -1
1928 #define DMAE_PCI_ERROR -2 /* E2 and onward */
1929 #define DMAE_NOT_RDY -3
1930 #define DMAE_PCI_ERR_FLAG 0x80000000
1932 #define DMAE_SRC_PCI 0
1933 #define DMAE_SRC_GRC 1
1935 #define DMAE_DST_NONE 0
1936 #define DMAE_DST_PCI 1
1937 #define DMAE_DST_GRC 2
1939 #define DMAE_COMP_PCI 0
1940 #define DMAE_COMP_GRC 1
1942 /* E2 and onward - PCI error handling in the completion */
1944 #define DMAE_COMP_REGULAR 0
1945 #define DMAE_COM_SET_ERR 1
1947 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
1948 DMAE_COMMAND_SRC_SHIFT)
1949 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
1950 DMAE_COMMAND_SRC_SHIFT)
1952 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
1953 DMAE_COMMAND_DST_SHIFT)
1954 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
1955 DMAE_COMMAND_DST_SHIFT)
1957 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
1958 DMAE_COMMAND_C_DST_SHIFT)
1959 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
1960 DMAE_COMMAND_C_DST_SHIFT)
1962 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1964 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1965 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1966 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1967 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1969 #define DMAE_CMD_PORT_0 0
1970 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1972 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1973 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1974 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1976 #define DMAE_SRC_PF 0
1977 #define DMAE_SRC_VF 1
1979 #define DMAE_DST_PF 0
1980 #define DMAE_DST_VF 1
1982 #define DMAE_C_SRC 0
1983 #define DMAE_C_DST 1
1985 #define DMAE_LEN32_RD_MAX 0x80
1986 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
1988 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
1991 #define MAX_DMAE_C_PER_PORT 8
1992 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1994 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1997 /* PCIE link and speed */
1998 #define PCICFG_LINK_WIDTH 0x1f00000
1999 #define PCICFG_LINK_WIDTH_SHIFT 20
2000 #define PCICFG_LINK_SPEED 0xf0000
2001 #define PCICFG_LINK_SPEED_SHIFT 16
2003 #define BNX2X_NUM_TESTS_SF 7
2004 #define BNX2X_NUM_TESTS_MF 3
2005 #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \
2008 #define BNX2X_PHY_LOOPBACK 0
2009 #define BNX2X_MAC_LOOPBACK 1
2010 #define BNX2X_EXT_LOOPBACK 2
2011 #define BNX2X_PHY_LOOPBACK_FAILED 1
2012 #define BNX2X_MAC_LOOPBACK_FAILED 2
2013 #define BNX2X_EXT_LOOPBACK_FAILED 3
2014 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
2015 BNX2X_PHY_LOOPBACK_FAILED)
2018 #define STROM_ASSERT_ARRAY_SIZE 50
2021 /* must be used on a CID before placing it on a HW ring */
2022 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
2023 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
2026 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
2027 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
2031 #define MAX_SPQ_PENDING 8
2033 /* CMNG constants, as derived from system spec calculations */
2034 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
2035 #define DEF_MIN_RATE 100
2036 /* resolution of the rate shaping timer - 400 usec */
2037 #define RS_PERIODIC_TIMEOUT_USEC 400
2038 /* number of bytes in single QM arbitration cycle -
2039 * coefficient for calculating the fairness timer */
2040 #define QM_ARB_BYTES 160000
2041 /* resolution of Min algorithm 1:100 */
2043 /* how many bytes above threshold for the minimal credit of Min algorithm*/
2044 #define MIN_ABOVE_THRESH 32768
2045 /* Fairness algorithm integration time coefficient -
2046 * for calculating the actual Tfair */
2047 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
2048 /* Memory of fairness algorithm . 2 cycles */
2052 #define ATTN_NIG_FOR_FUNC (1L << 8)
2053 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
2054 #define GPIO_2_FUNC (1L << 10)
2055 #define GPIO_3_FUNC (1L << 11)
2056 #define GPIO_4_FUNC (1L << 12)
2057 #define ATTN_GENERAL_ATTN_1 (1L << 13)
2058 #define ATTN_GENERAL_ATTN_2 (1L << 14)
2059 #define ATTN_GENERAL_ATTN_3 (1L << 15)
2060 #define ATTN_GENERAL_ATTN_4 (1L << 13)
2061 #define ATTN_GENERAL_ATTN_5 (1L << 14)
2062 #define ATTN_GENERAL_ATTN_6 (1L << 15)
2064 #define ATTN_HARD_WIRED_MASK 0xff00
2065 #define ATTENTION_ID 4
2068 /* stuff added to make the code fit 80Col */
2070 #define BNX2X_PMF_LINK_ASSERT \
2071 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
2073 #define BNX2X_MC_ASSERT_BITS \
2074 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2075 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2076 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2077 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
2079 #define BNX2X_MCP_ASSERT \
2080 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
2082 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
2083 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
2084 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
2085 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
2086 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
2087 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
2088 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
2090 #define HW_INTERRUT_ASSERT_SET_0 \
2091 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
2092 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
2093 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
2094 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
2095 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
2096 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
2097 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
2098 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
2099 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
2100 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
2101 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
2102 #define HW_INTERRUT_ASSERT_SET_1 \
2103 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
2104 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
2105 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
2106 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
2107 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
2108 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
2109 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
2110 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
2111 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
2112 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
2113 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
2114 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
2115 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
2116 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
2117 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
2118 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
2119 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
2120 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
2121 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
2122 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
2123 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
2124 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
2125 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
2126 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
2127 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
2128 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
2129 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
2130 #define HW_INTERRUT_ASSERT_SET_2 \
2131 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
2132 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
2133 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
2134 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
2135 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
2136 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
2137 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
2138 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
2139 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
2140 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
2141 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
2142 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
2143 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
2145 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
2146 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
2147 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
2148 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
2150 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
2151 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
2153 #define MULTI_MASK 0x7f
2156 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func)
2157 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func)
2158 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func)
2159 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func)
2161 #define DEF_USB_IGU_INDEX_OFF \
2162 offsetof(struct cstorm_def_status_block_u, igu_index)
2163 #define DEF_CSB_IGU_INDEX_OFF \
2164 offsetof(struct cstorm_def_status_block_c, igu_index)
2165 #define DEF_XSB_IGU_INDEX_OFF \
2166 offsetof(struct xstorm_def_status_block, igu_index)
2167 #define DEF_TSB_IGU_INDEX_OFF \
2168 offsetof(struct tstorm_def_status_block, igu_index)
2170 #define DEF_USB_SEGMENT_OFF \
2171 offsetof(struct cstorm_def_status_block_u, segment)
2172 #define DEF_CSB_SEGMENT_OFF \
2173 offsetof(struct cstorm_def_status_block_c, segment)
2174 #define DEF_XSB_SEGMENT_OFF \
2175 offsetof(struct xstorm_def_status_block, segment)
2176 #define DEF_TSB_SEGMENT_OFF \
2177 offsetof(struct tstorm_def_status_block, segment)
2179 #define BNX2X_SP_DSB_INDEX \
2180 (&bp->def_status_blk->sp_sb.\
2181 index_values[HC_SP_INDEX_ETH_DEF_CONS])
2183 #define SET_FLAG(value, mask, flag) \
2185 (value) &= ~(mask);\
2186 (value) |= ((flag) << (mask##_SHIFT));\
2189 #define GET_FLAG(value, mask) \
2190 (((value) & (mask)) >> (mask##_SHIFT))
2192 #define GET_FIELD(value, fname) \
2193 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
2195 #define CAM_IS_INVALID(x) \
2196 (GET_FLAG(x.flags, \
2197 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
2198 (T_ETH_MAC_COMMAND_INVALIDATE))
2200 /* Number of u32 elements in MC hash array */
2201 #define MC_HASH_SIZE 8
2202 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
2203 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
2206 #ifndef PXP2_REG_PXP2_INT_STS
2207 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
2210 #ifndef ETH_MAX_RX_CLIENTS_E2
2211 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
2214 #define BNX2X_VPD_LEN 128
2215 #define VENDOR_ID_LEN 4
2217 #define VF_ACQUIRE_THRESH 3
2218 #define VF_ACQUIRE_MAC_FILTERS 1
2219 #define VF_ACQUIRE_MC_FILTERS 10
2221 #define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \
2222 (!((me_reg) & ME_REG_VF_ERR)))
2223 int bnx2x_get_vf_id(struct bnx2x *bp, u32 *vf_id);
2224 int bnx2x_send_msg2pf(struct bnx2x *bp, u8 *done, dma_addr_t msg_mapping);
2225 int bnx2x_vfpf_acquire(struct bnx2x *bp, u8 tx_count, u8 rx_count);
2226 int bnx2x_vfpf_release(struct bnx2x *bp);
2227 int bnx2x_vfpf_init(struct bnx2x *bp);
2228 void bnx2x_vfpf_close_vf(struct bnx2x *bp);
2229 int bnx2x_vfpf_setup_q(struct bnx2x *bp, int fp_idx);
2230 int bnx2x_vfpf_teardown_queue(struct bnx2x *bp, int qidx);
2231 int bnx2x_vfpf_set_mac(struct bnx2x *bp);
2232 int bnx2x_nic_load_analyze_req(struct bnx2x *bp, u32 load_code);
2233 /* Congestion management fairness mode */
2234 #define CMNG_FNS_NONE 0
2235 #define CMNG_FNS_MINMAX 1
2237 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
2238 #define HC_SEG_ACCESS_ATTN 4
2239 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
2241 static const u32 dmae_reg_go_c[] = {
2242 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
2243 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
2244 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
2245 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
2248 void bnx2x_set_ethtool_ops(struct net_device *netdev);
2249 void bnx2x_notify_link_changed(struct bnx2x *bp);
2252 #define BNX2X_MF_SD_PROTOCOL(bp) \
2253 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK)
2255 #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \
2256 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI)
2258 #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \
2259 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE)
2261 #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp))
2262 #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))
2264 #define BNX2X_MF_EXT_PROTOCOL_FCOE(bp) ((bp)->mf_ext_config & \
2265 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2267 #define IS_MF_FCOE_AFEX(bp) (IS_MF_AFEX(bp) && BNX2X_MF_EXT_PROTOCOL_FCOE(bp))
2268 #define IS_MF_STORAGE_SD(bp) (IS_MF_SD(bp) && \
2269 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \
2270 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
2279 #endif /* bnx2x.h */