drivers/net/ethernet/broadcom/bnxt/bnxt.c

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2015 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  */
   9
  10 #include <linux/module.h>
  11
  12 #include <linux/stringify.h>
  13 #include <linux/kernel.h>
  14 #include <linux/timer.h>
  15 #include <linux/errno.h>
  16 #include <linux/ioport.h>
  17 #include <linux/slab.h>
  18 #include <linux/vmalloc.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/pci.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/etherdevice.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/bitops.h>
  26 #include <linux/io.h>
  27 #include <linux/irq.h>
  28 #include <linux/delay.h>
  29 #include <asm/byteorder.h>
  30 #include <asm/page.h>
  31 #include <linux/time.h>
  32 #include <linux/mii.h>
  33 #include <linux/if.h>
  34 #include <linux/if_vlan.h>
  35 #include <net/ip.h>
  36 #include <net/tcp.h>
  37 #include <net/udp.h>
  38 #include <net/checksum.h>
  39 #include <net/ip6_checksum.h>
  40 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
  41 #include <net/vxlan.h>
  42 #endif
  43 #ifdef CONFIG_NET_RX_BUSY_POLL
  44 #include <net/busy_poll.h>
  45 #endif
  46 #include <linux/workqueue.h>
  47 #include <linux/prefetch.h>
  48 #include <linux/cache.h>
  49 #include <linux/log2.h>
  50 #include <linux/aer.h>
  51 #include <linux/bitmap.h>
  52 #include <linux/cpu_rmap.h>
  53
  54 #include "bnxt_hsi.h"
  55 #include "bnxt.h"
  56 #include "bnxt_sriov.h"
  57 #include "bnxt_ethtool.h"
  58
  59 #define BNXT_TX_TIMEOUT         (5 * HZ)
  60
  61 static const char version[] =
  62         "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
  63
  64 MODULE_LICENSE("GPL");
  65 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
  66 MODULE_VERSION(DRV_MODULE_VERSION);
  67
  68 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
  69 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
  70 #define BNXT_RX_COPY_THRESH 256
  71
  72 #define BNXT_TX_PUSH_THRESH 164
  73
  74 enum board_idx {
  75         BCM57301,
  76         BCM57302,
  77         BCM57304,
  78         BCM57402,
  79         BCM57404,
  80         BCM57406,
  81         BCM57304_VF,
  82         BCM57404_VF,
  83 };
  84
  85 /* indexed by enum above */
  86 static const struct {
  87         char *name;
  88 } board_info[] = {
  89         { "Broadcom BCM57301 NetXtreme-C Single-port 10Gb Ethernet" },
  90         { "Broadcom BCM57302 NetXtreme-C Dual-port 10Gb/25Gb Ethernet" },
  91         { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
  92         { "Broadcom BCM57402 NetXtreme-E Dual-port 10Gb Ethernet" },
  93         { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
  94         { "Broadcom BCM57406 NetXtreme-E Dual-port 10GBase-T Ethernet" },
  95         { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" },
  96         { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" },
  97 };
  98
  99 static const struct pci_device_id bnxt_pci_tbl[] = {
 100         { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
 101         { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
 102         { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
 103         { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
 104         { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
 105         { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
 106 #ifdef CONFIG_BNXT_SRIOV
 107         { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = BCM57304_VF },
 108         { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = BCM57404_VF },
 109 #endif
 110         { 0 }
 111 };
 112
 113 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
 114
 115 static const u16 bnxt_vf_req_snif[] = {
 116         HWRM_FUNC_CFG,
 117         HWRM_PORT_PHY_QCFG,
 118         HWRM_CFA_L2_FILTER_ALLOC,
 119 };
 120
 121 static bool bnxt_vf_pciid(enum board_idx idx)
 122 {
 123         return (idx == BCM57304_VF || idx == BCM57404_VF);
 124 }
 125
 126 #define DB_CP_REARM_FLAGS       (DB_KEY_CP | DB_IDX_VALID)
 127 #define DB_CP_FLAGS             (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
 128 #define DB_CP_IRQ_DIS_FLAGS     (DB_KEY_CP | DB_IRQ_DIS)
 129
 130 #define BNXT_CP_DB_REARM(db, raw_cons)                                  \
 131                 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
 132
 133 #define BNXT_CP_DB(db, raw_cons)                                        \
 134                 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
 135
 136 #define BNXT_CP_DB_IRQ_DIS(db)                                          \
 137                 writel(DB_CP_IRQ_DIS_FLAGS, db)
 138
 139 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
 140 {
 141         /* Tell compiler to fetch tx indices from memory. */
 142         barrier();
 143
 144         return bp->tx_ring_size -
 145                 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
 146 }
 147
 148 static const u16 bnxt_lhint_arr[] = {
 149         TX_BD_FLAGS_LHINT_512_AND_SMALLER,
 150         TX_BD_FLAGS_LHINT_512_TO_1023,
 151         TX_BD_FLAGS_LHINT_1024_TO_2047,
 152         TX_BD_FLAGS_LHINT_1024_TO_2047,
 153         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 154         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 155         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 156         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 157         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 158         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 159         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 160         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 161         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 162         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 163         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 164         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 165         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 166         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 167         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 168 };
 169
 170 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
 171 {
 172         struct bnxt *bp = netdev_priv(dev);
 173         struct tx_bd *txbd;
 174         struct tx_bd_ext *txbd1;
 175         struct netdev_queue *txq;
 176         int i;
 177         dma_addr_t mapping;
 178         unsigned int length, pad = 0;
 179         u32 len, free_size, vlan_tag_flags, cfa_action, flags;
 180         u16 prod, last_frag;
 181         struct pci_dev *pdev = bp->pdev;
 182         struct bnxt_tx_ring_info *txr;
 183         struct bnxt_sw_tx_bd *tx_buf;
 184
 185         i = skb_get_queue_mapping(skb);
 186         if (unlikely(i >= bp->tx_nr_rings)) {
 187                 dev_kfree_skb_any(skb);
 188                 return NETDEV_TX_OK;
 189         }
 190
 191         txr = &bp->tx_ring[i];
 192         txq = netdev_get_tx_queue(dev, i);
 193         prod = txr->tx_prod;
 194
 195         free_size = bnxt_tx_avail(bp, txr);
 196         if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
 197                 netif_tx_stop_queue(txq);
 198                 return NETDEV_TX_BUSY;
 199         }
 200
 201         length = skb->len;
 202         len = skb_headlen(skb);
 203         last_frag = skb_shinfo(skb)->nr_frags;
 204
 205         txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 206
 207         txbd->tx_bd_opaque = prod;
 208
 209         tx_buf = &txr->tx_buf_ring[prod];
 210         tx_buf->skb = skb;
 211         tx_buf->nr_frags = last_frag;
 212
 213         vlan_tag_flags = 0;
 214         cfa_action = 0;
 215         if (skb_vlan_tag_present(skb)) {
 216                 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
 217                                  skb_vlan_tag_get(skb);
 218                 /* Currently supports 8021Q, 8021AD vlan offloads
 219                  * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
 220                  */
 221                 if (skb->vlan_proto == htons(ETH_P_8021Q))
 222                         vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
 223         }
 224
 225         if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
 226                 struct tx_push_buffer *tx_push_buf = txr->tx_push;
 227                 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
 228                 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
 229                 void *pdata = tx_push_buf->data;
 230                 u64 *end;
 231                 int j, push_len;
 232
 233                 /* Set COAL_NOW to be ready quickly for the next push */
 234                 tx_push->tx_bd_len_flags_type =
 235                         cpu_to_le32((length << TX_BD_LEN_SHIFT) |
 236                                         TX_BD_TYPE_LONG_TX_BD |
 237                                         TX_BD_FLAGS_LHINT_512_AND_SMALLER |
 238                                         TX_BD_FLAGS_COAL_NOW |
 239                                         TX_BD_FLAGS_PACKET_END |
 240                                         (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
 241
 242                 if (skb->ip_summed == CHECKSUM_PARTIAL)
 243                         tx_push1->tx_bd_hsize_lflags =
 244                                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 245                 else
 246                         tx_push1->tx_bd_hsize_lflags = 0;
 247
 248                 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 249                 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
 250
 251                 end = PTR_ALIGN(pdata + length + 1, 8) - 1;
 252                 *end = 0;
 253
 254                 skb_copy_from_linear_data(skb, pdata, len);
 255                 pdata += len;
 256                 for (j = 0; j < last_frag; j++) {
 257                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
 258                         void *fptr;
 259
 260                         fptr = skb_frag_address_safe(frag);
 261                         if (!fptr)
 262                                 goto normal_tx;
 263
 264                         memcpy(pdata, fptr, skb_frag_size(frag));
 265                         pdata += skb_frag_size(frag);
 266                 }
 267
 268                 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
 269                 txbd->tx_bd_haddr = txr->data_mapping;
 270                 prod = NEXT_TX(prod);
 271                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 272                 memcpy(txbd, tx_push1, sizeof(*txbd));
 273                 prod = NEXT_TX(prod);
 274                 tx_push->doorbell =
 275                         cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
 276                 txr->tx_prod = prod;
 277
 278                 netdev_tx_sent_queue(txq, skb->len);
 279
 280                 push_len = (length + sizeof(*tx_push) + 7) / 8;
 281                 if (push_len > 16) {
 282                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
 283                         __iowrite64_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
 284                                          push_len - 16);
 285                 } else {
 286                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
 287                                          push_len);
 288                 }
 289
 290                 tx_buf->is_push = 1;
 291                 goto tx_done;
 292         }
 293
 294 normal_tx:
 295         if (length < BNXT_MIN_PKT_SIZE) {
 296                 pad = BNXT_MIN_PKT_SIZE - length;
 297                 if (skb_pad(skb, pad)) {
 298                         /* SKB already freed. */
 299                         tx_buf->skb = NULL;
 300                         return NETDEV_TX_OK;
 301                 }
 302                 length = BNXT_MIN_PKT_SIZE;
 303         }
 304
 305         mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
 306
 307         if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
 308                 dev_kfree_skb_any(skb);
 309                 tx_buf->skb = NULL;
 310                 return NETDEV_TX_OK;
 311         }
 312
 313         dma_unmap_addr_set(tx_buf, mapping, mapping);
 314         flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
 315                 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
 316
 317         txbd->tx_bd_haddr = cpu_to_le64(mapping);
 318
 319         prod = NEXT_TX(prod);
 320         txbd1 = (struct tx_bd_ext *)
 321                 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 322
 323         txbd1->tx_bd_hsize_lflags = 0;
 324         if (skb_is_gso(skb)) {
 325                 u32 hdr_len;
 326
 327                 if (skb->encapsulation)
 328                         hdr_len = skb_inner_network_offset(skb) +
 329                                 skb_inner_network_header_len(skb) +
 330                                 inner_tcp_hdrlen(skb);
 331                 else
 332                         hdr_len = skb_transport_offset(skb) +
 333                                 tcp_hdrlen(skb);
 334
 335                 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
 336                                         TX_BD_FLAGS_T_IPID |
 337                                         (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
 338                 length = skb_shinfo(skb)->gso_size;
 339                 txbd1->tx_bd_mss = cpu_to_le32(length);
 340                 length += hdr_len;
 341         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 342                 txbd1->tx_bd_hsize_lflags =
 343                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 344                 txbd1->tx_bd_mss = 0;
 345         }
 346
 347         length >>= 9;
 348         flags |= bnxt_lhint_arr[length];
 349         txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 350
 351         txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 352         txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
 353         for (i = 0; i < last_frag; i++) {
 354                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 355
 356                 prod = NEXT_TX(prod);
 357                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 358
 359                 len = skb_frag_size(frag);
 360                 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
 361                                            DMA_TO_DEVICE);
 362
 363                 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 364                         goto tx_dma_error;
 365
 366                 tx_buf = &txr->tx_buf_ring[prod];
 367                 dma_unmap_addr_set(tx_buf, mapping, mapping);
 368
 369                 txbd->tx_bd_haddr = cpu_to_le64(mapping);
 370
 371                 flags = len << TX_BD_LEN_SHIFT;
 372                 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 373         }
 374
 375         flags &= ~TX_BD_LEN;
 376         txbd->tx_bd_len_flags_type =
 377                 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
 378                             TX_BD_FLAGS_PACKET_END);
 379
 380         netdev_tx_sent_queue(txq, skb->len);
 381
 382         /* Sync BD data before updating doorbell */
 383         wmb();
 384
 385         prod = NEXT_TX(prod);
 386         txr->tx_prod = prod;
 387
 388         writel(DB_KEY_TX | prod, txr->tx_doorbell);
 389         writel(DB_KEY_TX | prod, txr->tx_doorbell);
 390
 391 tx_done:
 392
 393         mmiowb();
 394
 395         if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
 396                 netif_tx_stop_queue(txq);
 397
 398                 /* netif_tx_stop_queue() must be done before checking
 399                  * tx index in bnxt_tx_avail() below, because in
 400                  * bnxt_tx_int(), we update tx index before checking for
 401                  * netif_tx_queue_stopped().
 402                  */
 403                 smp_mb();
 404                 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
 405                         netif_tx_wake_queue(txq);
 406         }
 407         return NETDEV_TX_OK;
 408
 409 tx_dma_error:
 410         last_frag = i;
 411
 412         /* start back at beginning and unmap skb */
 413         prod = txr->tx_prod;
 414         tx_buf = &txr->tx_buf_ring[prod];
 415         tx_buf->skb = NULL;
 416         dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 417                          skb_headlen(skb), PCI_DMA_TODEVICE);
 418         prod = NEXT_TX(prod);
 419
 420         /* unmap remaining mapped pages */
 421         for (i = 0; i < last_frag; i++) {
 422                 prod = NEXT_TX(prod);
 423                 tx_buf = &txr->tx_buf_ring[prod];
 424                 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 425                                skb_frag_size(&skb_shinfo(skb)->frags[i]),
 426                                PCI_DMA_TODEVICE);
 427         }
 428
 429         dev_kfree_skb_any(skb);
 430         return NETDEV_TX_OK;
 431 }
 432
 433 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
 434 {
 435         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
 436         int index = txr - &bp->tx_ring[0];
 437         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, index);
 438         u16 cons = txr->tx_cons;
 439         struct pci_dev *pdev = bp->pdev;
 440         int i;
 441         unsigned int tx_bytes = 0;
 442
 443         for (i = 0; i < nr_pkts; i++) {
 444                 struct bnxt_sw_tx_bd *tx_buf;
 445                 struct sk_buff *skb;
 446                 int j, last;
 447
 448                 tx_buf = &txr->tx_buf_ring[cons];
 449                 cons = NEXT_TX(cons);
 450                 skb = tx_buf->skb;
 451                 tx_buf->skb = NULL;
 452
 453                 if (tx_buf->is_push) {
 454                         tx_buf->is_push = 0;
 455                         goto next_tx_int;
 456                 }
 457
 458                 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 459                                  skb_headlen(skb), PCI_DMA_TODEVICE);
 460                 last = tx_buf->nr_frags;
 461
 462                 for (j = 0; j < last; j++) {
 463                         cons = NEXT_TX(cons);
 464                         tx_buf = &txr->tx_buf_ring[cons];
 465                         dma_unmap_page(
 466                                 &pdev->dev,
 467                                 dma_unmap_addr(tx_buf, mapping),
 468                                 skb_frag_size(&skb_shinfo(skb)->frags[j]),
 469                                 PCI_DMA_TODEVICE);
 470                 }
 471
 472 next_tx_int:
 473                 cons = NEXT_TX(cons);
 474
 475                 tx_bytes += skb->len;
 476                 dev_kfree_skb_any(skb);
 477         }
 478
 479         netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
 480         txr->tx_cons = cons;
 481
 482         /* Need to make the tx_cons update visible to bnxt_start_xmit()
 483          * before checking for netif_tx_queue_stopped().  Without the
 484          * memory barrier, there is a small possibility that bnxt_start_xmit()
 485          * will miss it and cause the queue to be stopped forever.
 486          */
 487         smp_mb();
 488
 489         if (unlikely(netif_tx_queue_stopped(txq)) &&
 490             (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
 491                 __netif_tx_lock(txq, smp_processor_id());
 492                 if (netif_tx_queue_stopped(txq) &&
 493                     bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
 494                     txr->dev_state != BNXT_DEV_STATE_CLOSING)
 495                         netif_tx_wake_queue(txq);
 496                 __netif_tx_unlock(txq);
 497         }
 498 }
 499
 500 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
 501                                        gfp_t gfp)
 502 {
 503         u8 *data;
 504         struct pci_dev *pdev = bp->pdev;
 505
 506         data = kmalloc(bp->rx_buf_size, gfp);
 507         if (!data)
 508                 return NULL;
 509
 510         *mapping = dma_map_single(&pdev->dev, data + BNXT_RX_DMA_OFFSET,
 511                                   bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
 512
 513         if (dma_mapping_error(&pdev->dev, *mapping)) {
 514                 kfree(data);
 515                 data = NULL;
 516         }
 517         return data;
 518 }
 519
 520 static inline int bnxt_alloc_rx_data(struct bnxt *bp,
 521                                      struct bnxt_rx_ring_info *rxr,
 522                                      u16 prod, gfp_t gfp)
 523 {
 524         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 525         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
 526         u8 *data;
 527         dma_addr_t mapping;
 528
 529         data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
 530         if (!data)
 531                 return -ENOMEM;
 532
 533         rx_buf->data = data;
 534         dma_unmap_addr_set(rx_buf, mapping, mapping);
 535
 536         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 537
 538         return 0;
 539 }
 540
 541 static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons,
 542                                u8 *data)
 543 {
 544         u16 prod = rxr->rx_prod;
 545         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 546         struct rx_bd *cons_bd, *prod_bd;
 547
 548         prod_rx_buf = &rxr->rx_buf_ring[prod];
 549         cons_rx_buf = &rxr->rx_buf_ring[cons];
 550
 551         prod_rx_buf->data = data;
 552
 553         dma_unmap_addr_set(prod_rx_buf, mapping,
 554                            dma_unmap_addr(cons_rx_buf, mapping));
 555
 556         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 557         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
 558
 559         prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
 560 }
 561
 562 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
 563 {
 564         u16 next, max = rxr->rx_agg_bmap_size;
 565
 566         next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
 567         if (next >= max)
 568                 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
 569         return next;
 570 }
 571
 572 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
 573                                      struct bnxt_rx_ring_info *rxr,
 574                                      u16 prod, gfp_t gfp)
 575 {
 576         struct rx_bd *rxbd =
 577                 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 578         struct bnxt_sw_rx_agg_bd *rx_agg_buf;
 579         struct pci_dev *pdev = bp->pdev;
 580         struct page *page;
 581         dma_addr_t mapping;
 582         u16 sw_prod = rxr->rx_sw_agg_prod;
 583
 584         page = alloc_page(gfp);
 585         if (!page)
 586                 return -ENOMEM;
 587
 588         mapping = dma_map_page(&pdev->dev, page, 0, PAGE_SIZE,
 589                                PCI_DMA_FROMDEVICE);
 590         if (dma_mapping_error(&pdev->dev, mapping)) {
 591                 __free_page(page);
 592                 return -EIO;
 593         }
 594
 595         if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 596                 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 597
 598         __set_bit(sw_prod, rxr->rx_agg_bmap);
 599         rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
 600         rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
 601
 602         rx_agg_buf->page = page;
 603         rx_agg_buf->mapping = mapping;
 604         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 605         rxbd->rx_bd_opaque = sw_prod;
 606         return 0;
 607 }
 608
 609 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
 610                                    u32 agg_bufs)
 611 {
 612         struct bnxt *bp = bnapi->bp;
 613         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 614         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 615         u16 prod = rxr->rx_agg_prod;
 616         u16 sw_prod = rxr->rx_sw_agg_prod;
 617         u32 i;
 618
 619         for (i = 0; i < agg_bufs; i++) {
 620                 u16 cons;
 621                 struct rx_agg_cmp *agg;
 622                 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
 623                 struct rx_bd *prod_bd;
 624                 struct page *page;
 625
 626                 agg = (struct rx_agg_cmp *)
 627                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 628                 cons = agg->rx_agg_cmp_opaque;
 629                 __clear_bit(cons, rxr->rx_agg_bmap);
 630
 631                 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 632                         sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 633
 634                 __set_bit(sw_prod, rxr->rx_agg_bmap);
 635                 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
 636                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 637
 638                 /* It is possible for sw_prod to be equal to cons, so
 639                  * set cons_rx_buf->page to NULL first.
 640                  */
 641                 page = cons_rx_buf->page;
 642                 cons_rx_buf->page = NULL;
 643                 prod_rx_buf->page = page;
 644
 645                 prod_rx_buf->mapping = cons_rx_buf->mapping;
 646
 647                 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 648
 649                 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
 650                 prod_bd->rx_bd_opaque = sw_prod;
 651
 652                 prod = NEXT_RX_AGG(prod);
 653                 sw_prod = NEXT_RX_AGG(sw_prod);
 654                 cp_cons = NEXT_CMP(cp_cons);
 655         }
 656         rxr->rx_agg_prod = prod;
 657         rxr->rx_sw_agg_prod = sw_prod;
 658 }
 659
 660 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
 661                                    struct bnxt_rx_ring_info *rxr, u16 cons,
 662                                    u16 prod, u8 *data, dma_addr_t dma_addr,
 663                                    unsigned int len)
 664 {
 665         int err;
 666         struct sk_buff *skb;
 667
 668         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 669         if (unlikely(err)) {
 670                 bnxt_reuse_rx_data(rxr, cons, data);
 671                 return NULL;
 672         }
 673
 674         skb = build_skb(data, 0);
 675         dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
 676                          PCI_DMA_FROMDEVICE);
 677         if (!skb) {
 678                 kfree(data);
 679                 return NULL;
 680         }
 681
 682         skb_reserve(skb, BNXT_RX_OFFSET);
 683         skb_put(skb, len);
 684         return skb;
 685 }
 686
 687 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
 688                                      struct sk_buff *skb, u16 cp_cons,
 689                                      u32 agg_bufs)
 690 {
 691         struct pci_dev *pdev = bp->pdev;
 692         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 693         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 694         u16 prod = rxr->rx_agg_prod;
 695         u32 i;
 696
 697         for (i = 0; i < agg_bufs; i++) {
 698                 u16 cons, frag_len;
 699                 struct rx_agg_cmp *agg;
 700                 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
 701                 struct page *page;
 702                 dma_addr_t mapping;
 703
 704                 agg = (struct rx_agg_cmp *)
 705                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 706                 cons = agg->rx_agg_cmp_opaque;
 707                 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
 708                             RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
 709
 710                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 711                 skb_fill_page_desc(skb, i, cons_rx_buf->page, 0, frag_len);
 712                 __clear_bit(cons, rxr->rx_agg_bmap);
 713
 714                 /* It is possible for bnxt_alloc_rx_page() to allocate
 715                  * a sw_prod index that equals the cons index, so we
 716                  * need to clear the cons entry now.
 717                  */
 718                 mapping = dma_unmap_addr(cons_rx_buf, mapping);
 719                 page = cons_rx_buf->page;
 720                 cons_rx_buf->page = NULL;
 721
 722                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
 723                         struct skb_shared_info *shinfo;
 724                         unsigned int nr_frags;
 725
 726                         shinfo = skb_shinfo(skb);
 727                         nr_frags = --shinfo->nr_frags;
 728                         __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
 729
 730                         dev_kfree_skb(skb);
 731
 732                         cons_rx_buf->page = page;
 733
 734                         /* Update prod since possibly some pages have been
 735                          * allocated already.
 736                          */
 737                         rxr->rx_agg_prod = prod;
 738                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
 739                         return NULL;
 740                 }
 741
 742                 dma_unmap_page(&pdev->dev, mapping, PAGE_SIZE,
 743                                PCI_DMA_FROMDEVICE);
 744
 745                 skb->data_len += frag_len;
 746                 skb->len += frag_len;
 747                 skb->truesize += PAGE_SIZE;
 748
 749                 prod = NEXT_RX_AGG(prod);
 750                 cp_cons = NEXT_CMP(cp_cons);
 751         }
 752         rxr->rx_agg_prod = prod;
 753         return skb;
 754 }
 755
 756 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 757                                u8 agg_bufs, u32 *raw_cons)
 758 {
 759         u16 last;
 760         struct rx_agg_cmp *agg;
 761
 762         *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
 763         last = RING_CMP(*raw_cons);
 764         agg = (struct rx_agg_cmp *)
 765                 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
 766         return RX_AGG_CMP_VALID(agg, *raw_cons);
 767 }
 768
 769 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
 770                                             unsigned int len,
 771                                             dma_addr_t mapping)
 772 {
 773         struct bnxt *bp = bnapi->bp;
 774         struct pci_dev *pdev = bp->pdev;
 775         struct sk_buff *skb;
 776
 777         skb = napi_alloc_skb(&bnapi->napi, len);
 778         if (!skb)
 779                 return NULL;
 780
 781         dma_sync_single_for_cpu(&pdev->dev, mapping,
 782                                 bp->rx_copy_thresh, PCI_DMA_FROMDEVICE);
 783
 784         memcpy(skb->data - BNXT_RX_OFFSET, data, len + BNXT_RX_OFFSET);
 785
 786         dma_sync_single_for_device(&pdev->dev, mapping,
 787                                    bp->rx_copy_thresh,
 788                                    PCI_DMA_FROMDEVICE);
 789
 790         skb_put(skb, len);
 791         return skb;
 792 }
 793
 794 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
 795                            struct rx_tpa_start_cmp *tpa_start,
 796                            struct rx_tpa_start_cmp_ext *tpa_start1)
 797 {
 798         u8 agg_id = TPA_START_AGG_ID(tpa_start);
 799         u16 cons, prod;
 800         struct bnxt_tpa_info *tpa_info;
 801         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 802         struct rx_bd *prod_bd;
 803         dma_addr_t mapping;
 804
 805         cons = tpa_start->rx_tpa_start_cmp_opaque;
 806         prod = rxr->rx_prod;
 807         cons_rx_buf = &rxr->rx_buf_ring[cons];
 808         prod_rx_buf = &rxr->rx_buf_ring[prod];
 809         tpa_info = &rxr->rx_tpa[agg_id];
 810
 811         prod_rx_buf->data = tpa_info->data;
 812
 813         mapping = tpa_info->mapping;
 814         dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
 815
 816         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 817
 818         prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
 819
 820         tpa_info->data = cons_rx_buf->data;
 821         cons_rx_buf->data = NULL;
 822         tpa_info->mapping = dma_unmap_addr(cons_rx_buf, mapping);
 823
 824         tpa_info->len =
 825                 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
 826                                 RX_TPA_START_CMP_LEN_SHIFT;
 827         if (likely(TPA_START_HASH_VALID(tpa_start))) {
 828                 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
 829
 830                 tpa_info->hash_type = PKT_HASH_TYPE_L4;
 831                 tpa_info->gso_type = SKB_GSO_TCPV4;
 832                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
 833                 if (hash_type == 3)
 834                         tpa_info->gso_type = SKB_GSO_TCPV6;
 835                 tpa_info->rss_hash =
 836                         le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
 837         } else {
 838                 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
 839                 tpa_info->gso_type = 0;
 840                 if (netif_msg_rx_err(bp))
 841                         netdev_warn(bp->dev, "TPA packet without valid hash\n");
 842         }
 843         tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
 844         tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
 845
 846         rxr->rx_prod = NEXT_RX(prod);
 847         cons = NEXT_RX(cons);
 848         cons_rx_buf = &rxr->rx_buf_ring[cons];
 849
 850         bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
 851         rxr->rx_prod = NEXT_RX(rxr->rx_prod);
 852         cons_rx_buf->data = NULL;
 853 }
 854
 855 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
 856                            u16 cp_cons, u32 agg_bufs)
 857 {
 858         if (agg_bufs)
 859                 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
 860 }
 861
 862 #define BNXT_IPV4_HDR_SIZE      (sizeof(struct iphdr) + sizeof(struct tcphdr))
 863 #define BNXT_IPV6_HDR_SIZE      (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
 864
 865 static inline struct sk_buff *bnxt_gro_skb(struct bnxt_tpa_info *tpa_info,
 866                                            struct rx_tpa_end_cmp *tpa_end,
 867                                            struct rx_tpa_end_cmp_ext *tpa_end1,
 868                                            struct sk_buff *skb)
 869 {
 870 #ifdef CONFIG_INET
 871         struct tcphdr *th;
 872         int payload_off, tcp_opt_len = 0;
 873         int len, nw_off;
 874         u16 segs;
 875
 876         segs = TPA_END_TPA_SEGS(tpa_end);
 877         if (segs == 1)
 878                 return skb;
 879
 880         NAPI_GRO_CB(skb)->count = segs;
 881         skb_shinfo(skb)->gso_size =
 882                 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
 883         skb_shinfo(skb)->gso_type = tpa_info->gso_type;
 884         payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
 885                        RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
 886                       RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
 887         if (TPA_END_GRO_TS(tpa_end))
 888                 tcp_opt_len = 12;
 889
 890         if (tpa_info->gso_type == SKB_GSO_TCPV4) {
 891                 struct iphdr *iph;
 892
 893                 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
 894                          ETH_HLEN;
 895                 skb_set_network_header(skb, nw_off);
 896                 iph = ip_hdr(skb);
 897                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
 898                 len = skb->len - skb_transport_offset(skb);
 899                 th = tcp_hdr(skb);
 900                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
 901         } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
 902                 struct ipv6hdr *iph;
 903
 904                 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
 905                          ETH_HLEN;
 906                 skb_set_network_header(skb, nw_off);
 907                 iph = ipv6_hdr(skb);
 908                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
 909                 len = skb->len - skb_transport_offset(skb);
 910                 th = tcp_hdr(skb);
 911                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
 912         } else {
 913                 dev_kfree_skb_any(skb);
 914                 return NULL;
 915         }
 916         tcp_gro_complete(skb);
 917
 918         if (nw_off) { /* tunnel */
 919                 struct udphdr *uh = NULL;
 920
 921                 if (skb->protocol == htons(ETH_P_IP)) {
 922                         struct iphdr *iph = (struct iphdr *)skb->data;
 923
 924                         if (iph->protocol == IPPROTO_UDP)
 925                                 uh = (struct udphdr *)(iph + 1);
 926                 } else {
 927                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
 928
 929                         if (iph->nexthdr == IPPROTO_UDP)
 930                                 uh = (struct udphdr *)(iph + 1);
 931                 }
 932                 if (uh) {
 933                         if (uh->check)
 934                                 skb_shinfo(skb)->gso_type |=
 935                                         SKB_GSO_UDP_TUNNEL_CSUM;
 936                         else
 937                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
 938                 }
 939         }
 940 #endif
 941         return skb;
 942 }
 943
 944 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
 945                                            struct bnxt_napi *bnapi,
 946                                            u32 *raw_cons,
 947                                            struct rx_tpa_end_cmp *tpa_end,
 948                                            struct rx_tpa_end_cmp_ext *tpa_end1,
 949                                            bool *agg_event)
 950 {
 951         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 952         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 953         u8 agg_id = TPA_END_AGG_ID(tpa_end);
 954         u8 *data, agg_bufs;
 955         u16 cp_cons = RING_CMP(*raw_cons);
 956         unsigned int len;
 957         struct bnxt_tpa_info *tpa_info;
 958         dma_addr_t mapping;
 959         struct sk_buff *skb;
 960
 961         tpa_info = &rxr->rx_tpa[agg_id];
 962         data = tpa_info->data;
 963         prefetch(data);
 964         len = tpa_info->len;
 965         mapping = tpa_info->mapping;
 966
 967         agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
 968                     RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
 969
 970         if (agg_bufs) {
 971                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
 972                         return ERR_PTR(-EBUSY);
 973
 974                 *agg_event = true;
 975                 cp_cons = NEXT_CMP(cp_cons);
 976         }
 977
 978         if (unlikely(agg_bufs > MAX_SKB_FRAGS)) {
 979                 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
 980                 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
 981                             agg_bufs, (int)MAX_SKB_FRAGS);
 982                 return NULL;
 983         }
 984
 985         if (len <= bp->rx_copy_thresh) {
 986                 skb = bnxt_copy_skb(bnapi, data, len, mapping);
 987                 if (!skb) {
 988                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
 989                         return NULL;
 990                 }
 991         } else {
 992                 u8 *new_data;
 993                 dma_addr_t new_mapping;
 994
 995                 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
 996                 if (!new_data) {
 997                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
 998                         return NULL;
 999                 }
1000
1001                 tpa_info->data = new_data;
1002                 tpa_info->mapping = new_mapping;
1003
1004                 skb = build_skb(data, 0);
1005                 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size,
1006                                  PCI_DMA_FROMDEVICE);
1007
1008                 if (!skb) {
1009                         kfree(data);
1010                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1011                         return NULL;
1012                 }
1013                 skb_reserve(skb, BNXT_RX_OFFSET);
1014                 skb_put(skb, len);
1015         }
1016
1017         if (agg_bufs) {
1018                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1019                 if (!skb) {
1020                         /* Page reuse already handled by bnxt_rx_pages(). */
1021                         return NULL;
1022                 }
1023         }
1024         skb->protocol = eth_type_trans(skb, bp->dev);
1025
1026         if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1027                 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1028
1029         if (tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) {
1030                 netdev_features_t features = skb->dev->features;
1031                 u16 vlan_proto = tpa_info->metadata >>
1032                         RX_CMP_FLAGS2_METADATA_TPID_SFT;
1033
1034                 if (((features & NETIF_F_HW_VLAN_CTAG_RX) &&
1035                      vlan_proto == ETH_P_8021Q) ||
1036                     ((features & NETIF_F_HW_VLAN_STAG_RX) &&
1037                      vlan_proto == ETH_P_8021AD)) {
1038                         __vlan_hwaccel_put_tag(skb, htons(vlan_proto),
1039                                                tpa_info->metadata &
1040                                                RX_CMP_FLAGS2_METADATA_VID_MASK);
1041                 }
1042         }
1043
1044         skb_checksum_none_assert(skb);
1045         if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1046                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1047                 skb->csum_level =
1048                         (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1049         }
1050
1051         if (TPA_END_GRO(tpa_end))
1052                 skb = bnxt_gro_skb(tpa_info, tpa_end, tpa_end1, skb);
1053
1054         return skb;
1055 }
1056
1057 /* returns the following:
1058  * 1       - 1 packet successfully received
1059  * 0       - successful TPA_START, packet not completed yet
1060  * -EBUSY  - completion ring does not have all the agg buffers yet
1061  * -ENOMEM - packet aborted due to out of memory
1062  * -EIO    - packet aborted due to hw error indicated in BD
1063  */
1064 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1065                        bool *agg_event)
1066 {
1067         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1068         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1069         struct net_device *dev = bp->dev;
1070         struct rx_cmp *rxcmp;
1071         struct rx_cmp_ext *rxcmp1;
1072         u32 tmp_raw_cons = *raw_cons;
1073         u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1074         struct bnxt_sw_rx_bd *rx_buf;
1075         unsigned int len;
1076         u8 *data, agg_bufs, cmp_type;
1077         dma_addr_t dma_addr;
1078         struct sk_buff *skb;
1079         int rc = 0;
1080
1081         rxcmp = (struct rx_cmp *)
1082                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1083
1084         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1085         cp_cons = RING_CMP(tmp_raw_cons);
1086         rxcmp1 = (struct rx_cmp_ext *)
1087                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1088
1089         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1090                 return -EBUSY;
1091
1092         cmp_type = RX_CMP_TYPE(rxcmp);
1093
1094         prod = rxr->rx_prod;
1095
1096         if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1097                 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1098                                (struct rx_tpa_start_cmp_ext *)rxcmp1);
1099
1100                 goto next_rx_no_prod;
1101
1102         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1103                 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1104                                    (struct rx_tpa_end_cmp *)rxcmp,
1105                                    (struct rx_tpa_end_cmp_ext *)rxcmp1,
1106                                    agg_event);
1107
1108                 if (unlikely(IS_ERR(skb)))
1109                         return -EBUSY;
1110
1111                 rc = -ENOMEM;
1112                 if (likely(skb)) {
1113                         skb_record_rx_queue(skb, bnapi->index);
1114                         skb_mark_napi_id(skb, &bnapi->napi);
1115                         if (bnxt_busy_polling(bnapi))
1116                                 netif_receive_skb(skb);
1117                         else
1118                                 napi_gro_receive(&bnapi->napi, skb);
1119                         rc = 1;
1120                 }
1121                 goto next_rx_no_prod;
1122         }
1123
1124         cons = rxcmp->rx_cmp_opaque;
1125         rx_buf = &rxr->rx_buf_ring[cons];
1126         data = rx_buf->data;
1127         prefetch(data);
1128
1129         agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & RX_CMP_AGG_BUFS) >>
1130                                 RX_CMP_AGG_BUFS_SHIFT;
1131
1132         if (agg_bufs) {
1133                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1134                         return -EBUSY;
1135
1136                 cp_cons = NEXT_CMP(cp_cons);
1137                 *agg_event = true;
1138         }
1139
1140         rx_buf->data = NULL;
1141         if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1142                 bnxt_reuse_rx_data(rxr, cons, data);
1143                 if (agg_bufs)
1144                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1145
1146                 rc = -EIO;
1147                 goto next_rx;
1148         }
1149
1150         len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1151         dma_addr = dma_unmap_addr(rx_buf, mapping);
1152
1153         if (len <= bp->rx_copy_thresh) {
1154                 skb = bnxt_copy_skb(bnapi, data, len, dma_addr);
1155                 bnxt_reuse_rx_data(rxr, cons, data);
1156                 if (!skb) {
1157                         rc = -ENOMEM;
1158                         goto next_rx;
1159                 }
1160         } else {
1161                 skb = bnxt_rx_skb(bp, rxr, cons, prod, data, dma_addr, len);
1162                 if (!skb) {
1163                         rc = -ENOMEM;
1164                         goto next_rx;
1165                 }
1166         }
1167
1168         if (agg_bufs) {
1169                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1170                 if (!skb) {
1171                         rc = -ENOMEM;
1172                         goto next_rx;
1173                 }
1174         }
1175
1176         if (RX_CMP_HASH_VALID(rxcmp)) {
1177                 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1178                 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1179
1180                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1181                 if (hash_type != 1 && hash_type != 3)
1182                         type = PKT_HASH_TYPE_L3;
1183                 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1184         }
1185
1186         skb->protocol = eth_type_trans(skb, dev);
1187
1188         if (rxcmp1->rx_cmp_flags2 &
1189             cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) {
1190                 netdev_features_t features = skb->dev->features;
1191                 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1192                 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1193
1194                 if (((features & NETIF_F_HW_VLAN_CTAG_RX) &&
1195                      vlan_proto == ETH_P_8021Q) ||
1196                     ((features & NETIF_F_HW_VLAN_STAG_RX) &&
1197                      vlan_proto == ETH_P_8021AD))
1198                         __vlan_hwaccel_put_tag(skb, htons(vlan_proto),
1199                                                meta_data &
1200                                                RX_CMP_FLAGS2_METADATA_VID_MASK);
1201         }
1202
1203         skb_checksum_none_assert(skb);
1204         if (RX_CMP_L4_CS_OK(rxcmp1)) {
1205                 if (dev->features & NETIF_F_RXCSUM) {
1206                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1207                         skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1208                 }
1209         } else {
1210                 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1211                         if (dev->features & NETIF_F_RXCSUM)
1212                                 cpr->rx_l4_csum_errors++;
1213                 }
1214         }
1215
1216         skb_record_rx_queue(skb, bnapi->index);
1217         skb_mark_napi_id(skb, &bnapi->napi);
1218         if (bnxt_busy_polling(bnapi))
1219                 netif_receive_skb(skb);
1220         else
1221                 napi_gro_receive(&bnapi->napi, skb);
1222         rc = 1;
1223
1224 next_rx:
1225         rxr->rx_prod = NEXT_RX(prod);
1226
1227 next_rx_no_prod:
1228         *raw_cons = tmp_raw_cons;
1229
1230         return rc;
1231 }
1232
1233 static int bnxt_async_event_process(struct bnxt *bp,
1234                                     struct hwrm_async_event_cmpl *cmpl)
1235 {
1236         u16 event_id = le16_to_cpu(cmpl->event_id);
1237
1238         /* TODO CHIMP_FW: Define event id's for link change, error etc */
1239         switch (event_id) {
1240         case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1241                 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1242                 schedule_work(&bp->sp_task);
1243                 break;
1244         default:
1245                 netdev_err(bp->dev, "unhandled ASYNC event (id 0x%x)\n",
1246                            event_id);
1247                 break;
1248         }
1249         return 0;
1250 }
1251
1252 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1253 {
1254         u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1255         struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1256         struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1257                                 (struct hwrm_fwd_req_cmpl *)txcmp;
1258
1259         switch (cmpl_type) {
1260         case CMPL_BASE_TYPE_HWRM_DONE:
1261                 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1262                 if (seq_id == bp->hwrm_intr_seq_id)
1263                         bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1264                 else
1265                         netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1266                 break;
1267
1268         case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1269                 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1270
1271                 if ((vf_id < bp->pf.first_vf_id) ||
1272                     (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1273                         netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1274                                    vf_id);
1275                         return -EINVAL;
1276                 }
1277
1278                 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1279                 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1280                 schedule_work(&bp->sp_task);
1281                 break;
1282
1283         case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1284                 bnxt_async_event_process(bp,
1285                                          (struct hwrm_async_event_cmpl *)txcmp);
1286
1287         default:
1288                 break;
1289         }
1290
1291         return 0;
1292 }
1293
1294 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1295 {
1296         struct bnxt_napi *bnapi = dev_instance;
1297         struct bnxt *bp = bnapi->bp;
1298         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1299         u32 cons = RING_CMP(cpr->cp_raw_cons);
1300
1301         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1302         napi_schedule(&bnapi->napi);
1303         return IRQ_HANDLED;
1304 }
1305
1306 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1307 {
1308         u32 raw_cons = cpr->cp_raw_cons;
1309         u16 cons = RING_CMP(raw_cons);
1310         struct tx_cmp *txcmp;
1311
1312         txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1313
1314         return TX_CMP_VALID(txcmp, raw_cons);
1315 }
1316
1317 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1318 {
1319         struct bnxt_napi *bnapi = dev_instance;
1320         struct bnxt *bp = bnapi->bp;
1321         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1322         u32 cons = RING_CMP(cpr->cp_raw_cons);
1323         u32 int_status;
1324
1325         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1326
1327         if (!bnxt_has_work(bp, cpr)) {
1328                 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1329                 /* return if erroneous interrupt */
1330                 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1331                         return IRQ_NONE;
1332         }
1333
1334         /* disable ring IRQ */
1335         BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1336
1337         /* Return here if interrupt is shared and is disabled. */
1338         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1339                 return IRQ_HANDLED;
1340
1341         napi_schedule(&bnapi->napi);
1342         return IRQ_HANDLED;
1343 }
1344
1345 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1346 {
1347         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1348         u32 raw_cons = cpr->cp_raw_cons;
1349         u32 cons;
1350         int tx_pkts = 0;
1351         int rx_pkts = 0;
1352         bool rx_event = false;
1353         bool agg_event = false;
1354         struct tx_cmp *txcmp;
1355
1356         while (1) {
1357                 int rc;
1358
1359                 cons = RING_CMP(raw_cons);
1360                 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1361
1362                 if (!TX_CMP_VALID(txcmp, raw_cons))
1363                         break;
1364
1365                 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1366                         tx_pkts++;
1367                         /* return full budget so NAPI will complete. */
1368                         if (unlikely(tx_pkts > bp->tx_wake_thresh))
1369                                 rx_pkts = budget;
1370                 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1371                         rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event);
1372                         if (likely(rc >= 0))
1373                                 rx_pkts += rc;
1374                         else if (rc == -EBUSY)  /* partial completion */
1375                                 break;
1376                         rx_event = true;
1377                 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1378                                      CMPL_BASE_TYPE_HWRM_DONE) ||
1379                                     (TX_CMP_TYPE(txcmp) ==
1380                                      CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1381                                     (TX_CMP_TYPE(txcmp) ==
1382                                      CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1383                         bnxt_hwrm_handler(bp, txcmp);
1384                 }
1385                 raw_cons = NEXT_RAW_CMP(raw_cons);
1386
1387                 if (rx_pkts == budget)
1388                         break;
1389         }
1390
1391         cpr->cp_raw_cons = raw_cons;
1392         /* ACK completion ring before freeing tx ring and producing new
1393          * buffers in rx/agg rings to prevent overflowing the completion
1394          * ring.
1395          */
1396         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1397
1398         if (tx_pkts)
1399                 bnxt_tx_int(bp, bnapi, tx_pkts);
1400
1401         if (rx_event) {
1402                 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1403
1404                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1405                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1406                 if (agg_event) {
1407                         writel(DB_KEY_RX | rxr->rx_agg_prod,
1408                                rxr->rx_agg_doorbell);
1409                         writel(DB_KEY_RX | rxr->rx_agg_prod,
1410                                rxr->rx_agg_doorbell);
1411                 }
1412         }
1413         return rx_pkts;
1414 }
1415
1416 static int bnxt_poll(struct napi_struct *napi, int budget)
1417 {
1418         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1419         struct bnxt *bp = bnapi->bp;
1420         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1421         int work_done = 0;
1422
1423         if (!bnxt_lock_napi(bnapi))
1424                 return budget;
1425
1426         while (1) {
1427                 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1428
1429                 if (work_done >= budget)
1430                         break;
1431
1432                 if (!bnxt_has_work(bp, cpr)) {
1433                         napi_complete(napi);
1434                         BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1435                         break;
1436                 }
1437         }
1438         mmiowb();
1439         bnxt_unlock_napi(bnapi);
1440         return work_done;
1441 }
1442
1443 #ifdef CONFIG_NET_RX_BUSY_POLL
1444 static int bnxt_busy_poll(struct napi_struct *napi)
1445 {
1446         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1447         struct bnxt *bp = bnapi->bp;
1448         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1449         int rx_work, budget = 4;
1450
1451         if (atomic_read(&bp->intr_sem) != 0)
1452                 return LL_FLUSH_FAILED;
1453
1454         if (!bnxt_lock_poll(bnapi))
1455                 return LL_FLUSH_BUSY;
1456
1457         rx_work = bnxt_poll_work(bp, bnapi, budget);
1458
1459         BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1460
1461         bnxt_unlock_poll(bnapi);
1462         return rx_work;
1463 }
1464 #endif
1465
1466 static void bnxt_free_tx_skbs(struct bnxt *bp)
1467 {
1468         int i, max_idx;
1469         struct pci_dev *pdev = bp->pdev;
1470
1471         if (!bp->tx_ring)
1472                 return;
1473
1474         max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1475         for (i = 0; i < bp->tx_nr_rings; i++) {
1476                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1477                 int j;
1478
1479                 for (j = 0; j < max_idx;) {
1480                         struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
1481                         struct sk_buff *skb = tx_buf->skb;
1482                         int k, last;
1483
1484                         if (!skb) {
1485                                 j++;
1486                                 continue;
1487                         }
1488
1489                         tx_buf->skb = NULL;
1490
1491                         if (tx_buf->is_push) {
1492                                 dev_kfree_skb(skb);
1493                                 j += 2;
1494                                 continue;
1495                         }
1496
1497                         dma_unmap_single(&pdev->dev,
1498                                          dma_unmap_addr(tx_buf, mapping),
1499                                          skb_headlen(skb),
1500                                          PCI_DMA_TODEVICE);
1501
1502                         last = tx_buf->nr_frags;
1503                         j += 2;
1504                         for (k = 0; k < last; k++, j++) {
1505                                 int ring_idx = j & bp->tx_ring_mask;
1506                                 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
1507
1508                                 tx_buf = &txr->tx_buf_ring[ring_idx];
1509                                 dma_unmap_page(
1510                                         &pdev->dev,
1511                                         dma_unmap_addr(tx_buf, mapping),
1512                                         skb_frag_size(frag), PCI_DMA_TODEVICE);
1513                         }
1514                         dev_kfree_skb(skb);
1515                 }
1516                 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
1517         }
1518 }
1519
1520 static void bnxt_free_rx_skbs(struct bnxt *bp)
1521 {
1522         int i, max_idx, max_agg_idx;
1523         struct pci_dev *pdev = bp->pdev;
1524
1525         if (!bp->rx_ring)
1526                 return;
1527
1528         max_idx = bp->rx_nr_pages * RX_DESC_CNT;
1529         max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
1530         for (i = 0; i < bp->rx_nr_rings; i++) {
1531                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1532                 int j;
1533
1534                 if (rxr->rx_tpa) {
1535                         for (j = 0; j < MAX_TPA; j++) {
1536                                 struct bnxt_tpa_info *tpa_info =
1537                                                         &rxr->rx_tpa[j];
1538                                 u8 *data = tpa_info->data;
1539
1540                                 if (!data)
1541                                         continue;
1542
1543                                 dma_unmap_single(
1544                                         &pdev->dev,
1545                                         dma_unmap_addr(tpa_info, mapping),
1546                                         bp->rx_buf_use_size,
1547                                         PCI_DMA_FROMDEVICE);
1548
1549                                 tpa_info->data = NULL;
1550
1551                                 kfree(data);
1552                         }
1553                 }
1554
1555                 for (j = 0; j < max_idx; j++) {
1556                         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
1557                         u8 *data = rx_buf->data;
1558
1559                         if (!data)
1560                                 continue;
1561
1562                         dma_unmap_single(&pdev->dev,
1563                                          dma_unmap_addr(rx_buf, mapping),
1564                                          bp->rx_buf_use_size,
1565                                          PCI_DMA_FROMDEVICE);
1566
1567                         rx_buf->data = NULL;
1568
1569                         kfree(data);
1570                 }
1571
1572                 for (j = 0; j < max_agg_idx; j++) {
1573                         struct bnxt_sw_rx_agg_bd *rx_agg_buf =
1574                                 &rxr->rx_agg_ring[j];
1575                         struct page *page = rx_agg_buf->page;
1576
1577                         if (!page)
1578                                 continue;
1579
1580                         dma_unmap_page(&pdev->dev,
1581                                        dma_unmap_addr(rx_agg_buf, mapping),
1582                                        PAGE_SIZE, PCI_DMA_FROMDEVICE);
1583
1584                         rx_agg_buf->page = NULL;
1585                         __clear_bit(j, rxr->rx_agg_bmap);
1586
1587                         __free_page(page);
1588                 }
1589         }
1590 }
1591
1592 static void bnxt_free_skbs(struct bnxt *bp)
1593 {
1594         bnxt_free_tx_skbs(bp);
1595         bnxt_free_rx_skbs(bp);
1596 }
1597
1598 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1599 {
1600         struct pci_dev *pdev = bp->pdev;
1601         int i;
1602
1603         for (i = 0; i < ring->nr_pages; i++) {
1604                 if (!ring->pg_arr[i])
1605                         continue;
1606
1607                 dma_free_coherent(&pdev->dev, ring->page_size,
1608                                   ring->pg_arr[i], ring->dma_arr[i]);
1609
1610                 ring->pg_arr[i] = NULL;
1611         }
1612         if (ring->pg_tbl) {
1613                 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
1614                                   ring->pg_tbl, ring->pg_tbl_map);
1615                 ring->pg_tbl = NULL;
1616         }
1617         if (ring->vmem_size && *ring->vmem) {
1618                 vfree(*ring->vmem);
1619                 *ring->vmem = NULL;
1620         }
1621 }
1622
1623 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1624 {
1625         int i;
1626         struct pci_dev *pdev = bp->pdev;
1627
1628         if (ring->nr_pages > 1) {
1629                 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
1630                                                   ring->nr_pages * 8,
1631                                                   &ring->pg_tbl_map,
1632                                                   GFP_KERNEL);
1633                 if (!ring->pg_tbl)
1634                         return -ENOMEM;
1635         }
1636
1637         for (i = 0; i < ring->nr_pages; i++) {
1638                 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
1639                                                      ring->page_size,
1640                                                      &ring->dma_arr[i],
1641                                                      GFP_KERNEL);
1642                 if (!ring->pg_arr[i])
1643                         return -ENOMEM;
1644
1645                 if (ring->nr_pages > 1)
1646                         ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
1647         }
1648
1649         if (ring->vmem_size) {
1650                 *ring->vmem = vzalloc(ring->vmem_size);
1651                 if (!(*ring->vmem))
1652                         return -ENOMEM;
1653         }
1654         return 0;
1655 }
1656
1657 static void bnxt_free_rx_rings(struct bnxt *bp)
1658 {
1659         int i;
1660
1661         if (!bp->rx_ring)
1662                 return;
1663
1664         for (i = 0; i < bp->rx_nr_rings; i++) {
1665                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1666                 struct bnxt_ring_struct *ring;
1667
1668                 kfree(rxr->rx_tpa);
1669                 rxr->rx_tpa = NULL;
1670
1671                 kfree(rxr->rx_agg_bmap);
1672                 rxr->rx_agg_bmap = NULL;
1673
1674                 ring = &rxr->rx_ring_struct;
1675                 bnxt_free_ring(bp, ring);
1676
1677                 ring = &rxr->rx_agg_ring_struct;
1678                 bnxt_free_ring(bp, ring);
1679         }
1680 }
1681
1682 static int bnxt_alloc_rx_rings(struct bnxt *bp)
1683 {
1684         int i, rc, agg_rings = 0, tpa_rings = 0;
1685
1686         if (!bp->rx_ring)
1687                 return -ENOMEM;
1688
1689         if (bp->flags & BNXT_FLAG_AGG_RINGS)
1690                 agg_rings = 1;
1691
1692         if (bp->flags & BNXT_FLAG_TPA)
1693                 tpa_rings = 1;
1694
1695         for (i = 0; i < bp->rx_nr_rings; i++) {
1696                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1697                 struct bnxt_ring_struct *ring;
1698
1699                 ring = &rxr->rx_ring_struct;
1700
1701                 rc = bnxt_alloc_ring(bp, ring);
1702                 if (rc)
1703                         return rc;
1704
1705                 if (agg_rings) {
1706                         u16 mem_size;
1707
1708                         ring = &rxr->rx_agg_ring_struct;
1709                         rc = bnxt_alloc_ring(bp, ring);
1710                         if (rc)
1711                                 return rc;
1712
1713                         rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
1714                         mem_size = rxr->rx_agg_bmap_size / 8;
1715                         rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
1716                         if (!rxr->rx_agg_bmap)
1717                                 return -ENOMEM;
1718
1719                         if (tpa_rings) {
1720                                 rxr->rx_tpa = kcalloc(MAX_TPA,
1721                                                 sizeof(struct bnxt_tpa_info),
1722                                                 GFP_KERNEL);
1723                                 if (!rxr->rx_tpa)
1724                                         return -ENOMEM;
1725                         }
1726                 }
1727         }
1728         return 0;
1729 }
1730
1731 static void bnxt_free_tx_rings(struct bnxt *bp)
1732 {
1733         int i;
1734         struct pci_dev *pdev = bp->pdev;
1735
1736         if (!bp->tx_ring)
1737                 return;
1738
1739         for (i = 0; i < bp->tx_nr_rings; i++) {
1740                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1741                 struct bnxt_ring_struct *ring;
1742
1743                 if (txr->tx_push) {
1744                         dma_free_coherent(&pdev->dev, bp->tx_push_size,
1745                                           txr->tx_push, txr->tx_push_mapping);
1746                         txr->tx_push = NULL;
1747                 }
1748
1749                 ring = &txr->tx_ring_struct;
1750
1751                 bnxt_free_ring(bp, ring);
1752         }
1753 }
1754
1755 static int bnxt_alloc_tx_rings(struct bnxt *bp)
1756 {
1757         int i, j, rc;
1758         struct pci_dev *pdev = bp->pdev;
1759
1760         bp->tx_push_size = 0;
1761         if (bp->tx_push_thresh) {
1762                 int push_size;
1763
1764                 push_size  = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
1765                                         bp->tx_push_thresh);
1766
1767                 if (push_size > 256) {
1768                         push_size = 0;
1769                         bp->tx_push_thresh = 0;
1770                 }
1771
1772                 bp->tx_push_size = push_size;
1773         }
1774
1775         for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
1776                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1777                 struct bnxt_ring_struct *ring;
1778
1779                 ring = &txr->tx_ring_struct;
1780
1781                 rc = bnxt_alloc_ring(bp, ring);
1782                 if (rc)
1783                         return rc;
1784
1785                 if (bp->tx_push_size) {
1786                         dma_addr_t mapping;
1787
1788                         /* One pre-allocated DMA buffer to backup
1789                          * TX push operation
1790                          */
1791                         txr->tx_push = dma_alloc_coherent(&pdev->dev,
1792                                                 bp->tx_push_size,
1793                                                 &txr->tx_push_mapping,
1794                                                 GFP_KERNEL);
1795
1796                         if (!txr->tx_push)
1797                                 return -ENOMEM;
1798
1799                         mapping = txr->tx_push_mapping +
1800                                 sizeof(struct tx_push_bd);
1801                         txr->data_mapping = cpu_to_le64(mapping);
1802
1803                         memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
1804                 }
1805                 ring->queue_id = bp->q_info[j].queue_id;
1806                 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
1807                         j++;
1808         }
1809         return 0;
1810 }
1811
1812 static void bnxt_free_cp_rings(struct bnxt *bp)
1813 {
1814         int i;
1815
1816         if (!bp->bnapi)
1817                 return;
1818
1819         for (i = 0; i < bp->cp_nr_rings; i++) {
1820                 struct bnxt_napi *bnapi = bp->bnapi[i];
1821                 struct bnxt_cp_ring_info *cpr;
1822                 struct bnxt_ring_struct *ring;
1823
1824                 if (!bnapi)
1825                         continue;
1826
1827                 cpr = &bnapi->cp_ring;
1828                 ring = &cpr->cp_ring_struct;
1829
1830                 bnxt_free_ring(bp, ring);
1831         }
1832 }
1833
1834 static int bnxt_alloc_cp_rings(struct bnxt *bp)
1835 {
1836         int i, rc;
1837
1838         for (i = 0; i < bp->cp_nr_rings; i++) {
1839                 struct bnxt_napi *bnapi = bp->bnapi[i];
1840                 struct bnxt_cp_ring_info *cpr;
1841                 struct bnxt_ring_struct *ring;
1842
1843                 if (!bnapi)
1844                         continue;
1845
1846                 cpr = &bnapi->cp_ring;
1847                 ring = &cpr->cp_ring_struct;
1848
1849                 rc = bnxt_alloc_ring(bp, ring);
1850                 if (rc)
1851                         return rc;
1852         }
1853         return 0;
1854 }
1855
1856 static void bnxt_init_ring_struct(struct bnxt *bp)
1857 {
1858         int i;
1859
1860         for (i = 0; i < bp->cp_nr_rings; i++) {
1861                 struct bnxt_napi *bnapi = bp->bnapi[i];
1862                 struct bnxt_cp_ring_info *cpr;
1863                 struct bnxt_rx_ring_info *rxr;
1864                 struct bnxt_tx_ring_info *txr;
1865                 struct bnxt_ring_struct *ring;
1866
1867                 if (!bnapi)
1868                         continue;
1869
1870                 cpr = &bnapi->cp_ring;
1871                 ring = &cpr->cp_ring_struct;
1872                 ring->nr_pages = bp->cp_nr_pages;
1873                 ring->page_size = HW_CMPD_RING_SIZE;
1874                 ring->pg_arr = (void **)cpr->cp_desc_ring;
1875                 ring->dma_arr = cpr->cp_desc_mapping;
1876                 ring->vmem_size = 0;
1877
1878                 rxr = bnapi->rx_ring;
1879                 if (!rxr)
1880                         goto skip_rx;
1881
1882                 ring = &rxr->rx_ring_struct;
1883                 ring->nr_pages = bp->rx_nr_pages;
1884                 ring->page_size = HW_RXBD_RING_SIZE;
1885                 ring->pg_arr = (void **)rxr->rx_desc_ring;
1886                 ring->dma_arr = rxr->rx_desc_mapping;
1887                 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
1888                 ring->vmem = (void **)&rxr->rx_buf_ring;
1889
1890                 ring = &rxr->rx_agg_ring_struct;
1891                 ring->nr_pages = bp->rx_agg_nr_pages;
1892                 ring->page_size = HW_RXBD_RING_SIZE;
1893                 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
1894                 ring->dma_arr = rxr->rx_agg_desc_mapping;
1895                 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
1896                 ring->vmem = (void **)&rxr->rx_agg_ring;
1897
1898 skip_rx:
1899                 txr = bnapi->tx_ring;
1900                 if (!txr)
1901                         continue;
1902
1903                 ring = &txr->tx_ring_struct;
1904                 ring->nr_pages = bp->tx_nr_pages;
1905                 ring->page_size = HW_RXBD_RING_SIZE;
1906                 ring->pg_arr = (void **)txr->tx_desc_ring;
1907                 ring->dma_arr = txr->tx_desc_mapping;
1908                 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
1909                 ring->vmem = (void **)&txr->tx_buf_ring;
1910         }
1911 }
1912
1913 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
1914 {
1915         int i;
1916         u32 prod;
1917         struct rx_bd **rx_buf_ring;
1918
1919         rx_buf_ring = (struct rx_bd **)ring->pg_arr;
1920         for (i = 0, prod = 0; i < ring->nr_pages; i++) {
1921                 int j;
1922                 struct rx_bd *rxbd;
1923
1924                 rxbd = rx_buf_ring[i];
1925                 if (!rxbd)
1926                         continue;
1927
1928                 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
1929                         rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
1930                         rxbd->rx_bd_opaque = prod;
1931                 }
1932         }
1933 }
1934
1935 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
1936 {
1937         struct net_device *dev = bp->dev;
1938         struct bnxt_rx_ring_info *rxr;
1939         struct bnxt_ring_struct *ring;
1940         u32 prod, type;
1941         int i;
1942
1943         type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
1944                 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
1945
1946         if (NET_IP_ALIGN == 2)
1947                 type |= RX_BD_FLAGS_SOP;
1948
1949         rxr = &bp->rx_ring[ring_nr];
1950         ring = &rxr->rx_ring_struct;
1951         bnxt_init_rxbd_pages(ring, type);
1952
1953         prod = rxr->rx_prod;
1954         for (i = 0; i < bp->rx_ring_size; i++) {
1955                 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
1956                         netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
1957                                     ring_nr, i, bp->rx_ring_size);
1958                         break;
1959                 }
1960                 prod = NEXT_RX(prod);
1961         }
1962         rxr->rx_prod = prod;
1963         ring->fw_ring_id = INVALID_HW_RING_ID;
1964
1965         ring = &rxr->rx_agg_ring_struct;
1966         ring->fw_ring_id = INVALID_HW_RING_ID;
1967
1968         if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
1969                 return 0;
1970
1971         type = ((u32)PAGE_SIZE << RX_BD_LEN_SHIFT) |
1972                 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
1973
1974         bnxt_init_rxbd_pages(ring, type);
1975
1976         prod = rxr->rx_agg_prod;
1977         for (i = 0; i < bp->rx_agg_ring_size; i++) {
1978                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
1979                         netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
1980                                     ring_nr, i, bp->rx_ring_size);
1981                         break;
1982                 }
1983                 prod = NEXT_RX_AGG(prod);
1984         }
1985         rxr->rx_agg_prod = prod;
1986
1987         if (bp->flags & BNXT_FLAG_TPA) {
1988                 if (rxr->rx_tpa) {
1989                         u8 *data;
1990                         dma_addr_t mapping;
1991
1992                         for (i = 0; i < MAX_TPA; i++) {
1993                                 data = __bnxt_alloc_rx_data(bp, &mapping,
1994                                                             GFP_KERNEL);
1995                                 if (!data)
1996                                         return -ENOMEM;
1997
1998                                 rxr->rx_tpa[i].data = data;
1999                                 rxr->rx_tpa[i].mapping = mapping;
2000                         }
2001                 } else {
2002                         netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2003                         return -ENOMEM;
2004                 }
2005         }
2006
2007         return 0;
2008 }
2009
2010 static int bnxt_init_rx_rings(struct bnxt *bp)
2011 {
2012         int i, rc = 0;
2013
2014         for (i = 0; i < bp->rx_nr_rings; i++) {
2015                 rc = bnxt_init_one_rx_ring(bp, i);
2016                 if (rc)
2017                         break;
2018         }
2019
2020         return rc;
2021 }
2022
2023 static int bnxt_init_tx_rings(struct bnxt *bp)
2024 {
2025         u16 i;
2026
2027         bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2028                                    MAX_SKB_FRAGS + 1);
2029
2030         for (i = 0; i < bp->tx_nr_rings; i++) {
2031                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2032                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2033
2034                 ring->fw_ring_id = INVALID_HW_RING_ID;
2035         }
2036
2037         return 0;
2038 }
2039
2040 static void bnxt_free_ring_grps(struct bnxt *bp)
2041 {
2042         kfree(bp->grp_info);
2043         bp->grp_info = NULL;
2044 }
2045
2046 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2047 {
2048         int i;
2049
2050         if (irq_re_init) {
2051                 bp->grp_info = kcalloc(bp->cp_nr_rings,
2052                                        sizeof(struct bnxt_ring_grp_info),
2053                                        GFP_KERNEL);
2054                 if (!bp->grp_info)
2055                         return -ENOMEM;
2056         }
2057         for (i = 0; i < bp->cp_nr_rings; i++) {
2058                 if (irq_re_init)
2059                         bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2060                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2061                 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2062                 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2063                 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2064         }
2065         return 0;
2066 }
2067
2068 static void bnxt_free_vnics(struct bnxt *bp)
2069 {
2070         kfree(bp->vnic_info);
2071         bp->vnic_info = NULL;
2072         bp->nr_vnics = 0;
2073 }
2074
2075 static int bnxt_alloc_vnics(struct bnxt *bp)
2076 {
2077         int num_vnics = 1;
2078
2079 #ifdef CONFIG_RFS_ACCEL
2080         if (bp->flags & BNXT_FLAG_RFS)
2081                 num_vnics += bp->rx_nr_rings;
2082 #endif
2083
2084         bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2085                                 GFP_KERNEL);
2086         if (!bp->vnic_info)
2087                 return -ENOMEM;
2088
2089         bp->nr_vnics = num_vnics;
2090         return 0;
2091 }
2092
2093 static void bnxt_init_vnics(struct bnxt *bp)
2094 {
2095         int i;
2096
2097         for (i = 0; i < bp->nr_vnics; i++) {
2098                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2099
2100                 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2101                 vnic->fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
2102                 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2103
2104                 if (bp->vnic_info[i].rss_hash_key) {
2105                         if (i == 0)
2106                                 prandom_bytes(vnic->rss_hash_key,
2107                                               HW_HASH_KEY_SIZE);
2108                         else
2109                                 memcpy(vnic->rss_hash_key,
2110                                        bp->vnic_info[0].rss_hash_key,
2111                                        HW_HASH_KEY_SIZE);
2112                 }
2113         }
2114 }
2115
2116 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2117 {
2118         int pages;
2119
2120         pages = ring_size / desc_per_pg;
2121
2122         if (!pages)
2123                 return 1;
2124
2125         pages++;
2126
2127         while (pages & (pages - 1))
2128                 pages++;
2129
2130         return pages;
2131 }
2132
2133 static void bnxt_set_tpa_flags(struct bnxt *bp)
2134 {
2135         bp->flags &= ~BNXT_FLAG_TPA;
2136         if (bp->dev->features & NETIF_F_LRO)
2137                 bp->flags |= BNXT_FLAG_LRO;
2138         if ((bp->dev->features & NETIF_F_GRO) && (bp->pdev->revision > 0))
2139                 bp->flags |= BNXT_FLAG_GRO;
2140 }
2141
2142 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2143  * be set on entry.
2144  */
2145 void bnxt_set_ring_params(struct bnxt *bp)
2146 {
2147         u32 ring_size, rx_size, rx_space;
2148         u32 agg_factor = 0, agg_ring_size = 0;
2149
2150         /* 8 for CRC and VLAN */
2151         rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2152
2153         rx_space = rx_size + NET_SKB_PAD +
2154                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2155
2156         bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2157         ring_size = bp->rx_ring_size;
2158         bp->rx_agg_ring_size = 0;
2159         bp->rx_agg_nr_pages = 0;
2160
2161         if (bp->flags & BNXT_FLAG_TPA)
2162                 agg_factor = 4;
2163
2164         bp->flags &= ~BNXT_FLAG_JUMBO;
2165         if (rx_space > PAGE_SIZE) {
2166                 u32 jumbo_factor;
2167
2168                 bp->flags |= BNXT_FLAG_JUMBO;
2169                 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2170                 if (jumbo_factor > agg_factor)
2171                         agg_factor = jumbo_factor;
2172         }
2173         agg_ring_size = ring_size * agg_factor;
2174
2175         if (agg_ring_size) {
2176                 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2177                                                         RX_DESC_CNT);
2178                 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2179                         u32 tmp = agg_ring_size;
2180
2181                         bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2182                         agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2183                         netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2184                                     tmp, agg_ring_size);
2185                 }
2186                 bp->rx_agg_ring_size = agg_ring_size;
2187                 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2188                 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2189                 rx_space = rx_size + NET_SKB_PAD +
2190                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2191         }
2192
2193         bp->rx_buf_use_size = rx_size;
2194         bp->rx_buf_size = rx_space;
2195
2196         bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2197         bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2198
2199         ring_size = bp->tx_ring_size;
2200         bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2201         bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2202
2203         ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2204         bp->cp_ring_size = ring_size;
2205
2206         bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2207         if (bp->cp_nr_pages > MAX_CP_PAGES) {
2208                 bp->cp_nr_pages = MAX_CP_PAGES;
2209                 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2210                 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2211                             ring_size, bp->cp_ring_size);
2212         }
2213         bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2214         bp->cp_ring_mask = bp->cp_bit - 1;
2215 }
2216
2217 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2218 {
2219         int i;
2220         struct bnxt_vnic_info *vnic;
2221         struct pci_dev *pdev = bp->pdev;
2222
2223         if (!bp->vnic_info)
2224                 return;
2225
2226         for (i = 0; i < bp->nr_vnics; i++) {
2227                 vnic = &bp->vnic_info[i];
2228
2229                 kfree(vnic->fw_grp_ids);
2230                 vnic->fw_grp_ids = NULL;
2231
2232                 kfree(vnic->uc_list);
2233                 vnic->uc_list = NULL;
2234
2235                 if (vnic->mc_list) {
2236                         dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2237                                           vnic->mc_list, vnic->mc_list_mapping);
2238                         vnic->mc_list = NULL;
2239                 }
2240
2241                 if (vnic->rss_table) {
2242                         dma_free_coherent(&pdev->dev, PAGE_SIZE,
2243                                           vnic->rss_table,
2244                                           vnic->rss_table_dma_addr);
2245                         vnic->rss_table = NULL;
2246                 }
2247
2248                 vnic->rss_hash_key = NULL;
2249                 vnic->flags = 0;
2250         }
2251 }
2252
2253 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2254 {
2255         int i, rc = 0, size;
2256         struct bnxt_vnic_info *vnic;
2257         struct pci_dev *pdev = bp->pdev;
2258         int max_rings;
2259
2260         for (i = 0; i < bp->nr_vnics; i++) {
2261                 vnic = &bp->vnic_info[i];
2262
2263                 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2264                         int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2265
2266                         if (mem_size > 0) {
2267                                 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2268                                 if (!vnic->uc_list) {
2269                                         rc = -ENOMEM;
2270                                         goto out;
2271                                 }
2272                         }
2273                 }
2274
2275                 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2276                         vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2277                         vnic->mc_list =
2278                                 dma_alloc_coherent(&pdev->dev,
2279                                                    vnic->mc_list_size,
2280                                                    &vnic->mc_list_mapping,
2281                                                    GFP_KERNEL);
2282                         if (!vnic->mc_list) {
2283                                 rc = -ENOMEM;
2284                                 goto out;
2285                         }
2286                 }
2287
2288                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2289                         max_rings = bp->rx_nr_rings;
2290                 else
2291                         max_rings = 1;
2292
2293                 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2294                 if (!vnic->fw_grp_ids) {
2295                         rc = -ENOMEM;
2296                         goto out;
2297                 }
2298
2299                 /* Allocate rss table and hash key */
2300                 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2301                                                      &vnic->rss_table_dma_addr,
2302                                                      GFP_KERNEL);
2303                 if (!vnic->rss_table) {
2304                         rc = -ENOMEM;
2305                         goto out;
2306                 }
2307
2308                 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2309
2310                 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2311                 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2312         }
2313         return 0;
2314
2315 out:
2316         return rc;
2317 }
2318
2319 static void bnxt_free_hwrm_resources(struct bnxt *bp)
2320 {
2321         struct pci_dev *pdev = bp->pdev;
2322
2323         dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2324                           bp->hwrm_cmd_resp_dma_addr);
2325
2326         bp->hwrm_cmd_resp_addr = NULL;
2327         if (bp->hwrm_dbg_resp_addr) {
2328                 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2329                                   bp->hwrm_dbg_resp_addr,
2330                                   bp->hwrm_dbg_resp_dma_addr);
2331
2332                 bp->hwrm_dbg_resp_addr = NULL;
2333         }
2334 }
2335
2336 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2337 {
2338         struct pci_dev *pdev = bp->pdev;
2339
2340         bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2341                                                    &bp->hwrm_cmd_resp_dma_addr,
2342                                                    GFP_KERNEL);
2343         if (!bp->hwrm_cmd_resp_addr)
2344                 return -ENOMEM;
2345         bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2346                                                     HWRM_DBG_REG_BUF_SIZE,
2347                                                     &bp->hwrm_dbg_resp_dma_addr,
2348                                                     GFP_KERNEL);
2349         if (!bp->hwrm_dbg_resp_addr)
2350                 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2351
2352         return 0;
2353 }
2354
2355 static void bnxt_free_stats(struct bnxt *bp)
2356 {
2357         u32 size, i;
2358         struct pci_dev *pdev = bp->pdev;
2359
2360         if (!bp->bnapi)
2361                 return;
2362
2363         size = sizeof(struct ctx_hw_stats);
2364
2365         for (i = 0; i < bp->cp_nr_rings; i++) {
2366                 struct bnxt_napi *bnapi = bp->bnapi[i];
2367                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2368
2369                 if (cpr->hw_stats) {
2370                         dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
2371                                           cpr->hw_stats_map);
2372                         cpr->hw_stats = NULL;
2373                 }
2374         }
2375 }
2376
2377 static int bnxt_alloc_stats(struct bnxt *bp)
2378 {
2379         u32 size, i;
2380         struct pci_dev *pdev = bp->pdev;
2381
2382         size = sizeof(struct ctx_hw_stats);
2383
2384         for (i = 0; i < bp->cp_nr_rings; i++) {
2385                 struct bnxt_napi *bnapi = bp->bnapi[i];
2386                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2387
2388                 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
2389                                                    &cpr->hw_stats_map,
2390                                                    GFP_KERNEL);
2391                 if (!cpr->hw_stats)
2392                         return -ENOMEM;
2393
2394                 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
2395         }
2396         return 0;
2397 }
2398
2399 static void bnxt_clear_ring_indices(struct bnxt *bp)
2400 {
2401         int i;
2402
2403         if (!bp->bnapi)
2404                 return;
2405
2406         for (i = 0; i < bp->cp_nr_rings; i++) {
2407                 struct bnxt_napi *bnapi = bp->bnapi[i];
2408                 struct bnxt_cp_ring_info *cpr;
2409                 struct bnxt_rx_ring_info *rxr;
2410                 struct bnxt_tx_ring_info *txr;
2411
2412                 if (!bnapi)
2413                         continue;
2414
2415                 cpr = &bnapi->cp_ring;
2416                 cpr->cp_raw_cons = 0;
2417
2418                 txr = bnapi->tx_ring;
2419                 if (txr) {
2420                         txr->tx_prod = 0;
2421                         txr->tx_cons = 0;
2422                 }
2423
2424                 rxr = bnapi->rx_ring;
2425                 if (rxr) {
2426                         rxr->rx_prod = 0;
2427                         rxr->rx_agg_prod = 0;
2428                         rxr->rx_sw_agg_prod = 0;
2429                 }
2430         }
2431 }
2432
2433 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
2434 {
2435 #ifdef CONFIG_RFS_ACCEL
2436         int i;
2437
2438         /* Under rtnl_lock and all our NAPIs have been disabled.  It's
2439          * safe to delete the hash table.
2440          */
2441         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
2442                 struct hlist_head *head;
2443                 struct hlist_node *tmp;
2444                 struct bnxt_ntuple_filter *fltr;
2445
2446                 head = &bp->ntp_fltr_hash_tbl[i];
2447                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
2448                         hlist_del(&fltr->hash);
2449                         kfree(fltr);
2450                 }
2451         }
2452         if (irq_reinit) {
2453                 kfree(bp->ntp_fltr_bmap);
2454                 bp->ntp_fltr_bmap = NULL;
2455         }
2456         bp->ntp_fltr_count = 0;
2457 #endif
2458 }
2459
2460 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
2461 {
2462 #ifdef CONFIG_RFS_ACCEL
2463         int i, rc = 0;
2464
2465         if (!(bp->flags & BNXT_FLAG_RFS))
2466                 return 0;
2467
2468         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
2469                 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
2470
2471         bp->ntp_fltr_count = 0;
2472         bp->ntp_fltr_bmap = kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
2473                                     GFP_KERNEL);
2474
2475         if (!bp->ntp_fltr_bmap)
2476                 rc = -ENOMEM;
2477
2478         return rc;
2479 #else
2480         return 0;
2481 #endif
2482 }
2483
2484 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
2485 {
2486         bnxt_free_vnic_attributes(bp);
2487         bnxt_free_tx_rings(bp);
2488         bnxt_free_rx_rings(bp);
2489         bnxt_free_cp_rings(bp);
2490         bnxt_free_ntp_fltrs(bp, irq_re_init);
2491         if (irq_re_init) {
2492                 bnxt_free_stats(bp);
2493                 bnxt_free_ring_grps(bp);
2494                 bnxt_free_vnics(bp);
2495                 kfree(bp->tx_ring);
2496                 bp->tx_ring = NULL;
2497                 kfree(bp->rx_ring);
2498                 bp->rx_ring = NULL;
2499                 kfree(bp->bnapi);
2500                 bp->bnapi = NULL;
2501         } else {
2502                 bnxt_clear_ring_indices(bp);
2503         }
2504 }
2505
2506 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
2507 {
2508         int i, j, rc, size, arr_size;
2509         void *bnapi;
2510
2511         if (irq_re_init) {
2512                 /* Allocate bnapi mem pointer array and mem block for
2513                  * all queues
2514                  */
2515                 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
2516                                 bp->cp_nr_rings);
2517                 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
2518                 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
2519                 if (!bnapi)
2520                         return -ENOMEM;
2521
2522                 bp->bnapi = bnapi;
2523                 bnapi += arr_size;
2524                 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
2525                         bp->bnapi[i] = bnapi;
2526                         bp->bnapi[i]->index = i;
2527                         bp->bnapi[i]->bp = bp;
2528                 }
2529
2530                 bp->rx_ring = kcalloc(bp->rx_nr_rings,
2531                                       sizeof(struct bnxt_rx_ring_info),
2532                                       GFP_KERNEL);
2533                 if (!bp->rx_ring)
2534                         return -ENOMEM;
2535
2536                 for (i = 0; i < bp->rx_nr_rings; i++) {
2537                         bp->rx_ring[i].bnapi = bp->bnapi[i];
2538                         bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
2539                 }
2540
2541                 bp->tx_ring = kcalloc(bp->tx_nr_rings,
2542                                       sizeof(struct bnxt_tx_ring_info),
2543                                       GFP_KERNEL);
2544                 if (!bp->tx_ring)
2545                         return -ENOMEM;
2546
2547                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
2548                         j = 0;
2549                 else
2550                         j = bp->rx_nr_rings;
2551
2552                 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
2553                         bp->tx_ring[i].bnapi = bp->bnapi[j];
2554                         bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
2555                 }
2556
2557                 rc = bnxt_alloc_stats(bp);
2558                 if (rc)
2559                         goto alloc_mem_err;
2560
2561                 rc = bnxt_alloc_ntp_fltrs(bp);
2562                 if (rc)
2563                         goto alloc_mem_err;
2564
2565                 rc = bnxt_alloc_vnics(bp);
2566                 if (rc)
2567                         goto alloc_mem_err;
2568         }
2569
2570         bnxt_init_ring_struct(bp);
2571
2572         rc = bnxt_alloc_rx_rings(bp);
2573         if (rc)
2574                 goto alloc_mem_err;
2575
2576         rc = bnxt_alloc_tx_rings(bp);
2577         if (rc)
2578                 goto alloc_mem_err;
2579
2580         rc = bnxt_alloc_cp_rings(bp);
2581         if (rc)
2582                 goto alloc_mem_err;
2583
2584         bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
2585                                   BNXT_VNIC_UCAST_FLAG;
2586         rc = bnxt_alloc_vnic_attributes(bp);
2587         if (rc)
2588                 goto alloc_mem_err;
2589         return 0;
2590
2591 alloc_mem_err:
2592         bnxt_free_mem(bp, true);
2593         return rc;
2594 }
2595
2596 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
2597                             u16 cmpl_ring, u16 target_id)
2598 {
2599         struct hwrm_cmd_req_hdr *req = request;
2600
2601         req->cmpl_ring_req_type =
2602                 cpu_to_le32(req_type | (cmpl_ring << HWRM_CMPL_RING_SFT));
2603         req->target_id_seq_id = cpu_to_le32(target_id << HWRM_TARGET_FID_SFT);
2604         req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
2605 }
2606
2607 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2608 {
2609         int i, intr_process, rc;
2610         struct hwrm_cmd_req_hdr *req = msg;
2611         u32 *data = msg;
2612         __le32 *resp_len, *valid;
2613         u16 cp_ring_id, len = 0;
2614         struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
2615
2616         req->target_id_seq_id |= cpu_to_le32(bp->hwrm_cmd_seq++);
2617         memset(resp, 0, PAGE_SIZE);
2618         cp_ring_id = (le32_to_cpu(req->cmpl_ring_req_type) &
2619                       HWRM_CMPL_RING_MASK) >>
2620                      HWRM_CMPL_RING_SFT;
2621         intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
2622
2623         /* Write request msg to hwrm channel */
2624         __iowrite32_copy(bp->bar0, data, msg_len / 4);
2625
2626         for (i = msg_len; i < HWRM_MAX_REQ_LEN; i += 4)
2627                 writel(0, bp->bar0 + i);
2628
2629         /* currently supports only one outstanding message */
2630         if (intr_process)
2631                 bp->hwrm_intr_seq_id = le32_to_cpu(req->target_id_seq_id) &
2632                                        HWRM_SEQ_ID_MASK;
2633
2634         /* Ring channel doorbell */
2635         writel(1, bp->bar0 + 0x100);
2636
2637         i = 0;
2638         if (intr_process) {
2639                 /* Wait until hwrm response cmpl interrupt is processed */
2640                 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
2641                        i++ < timeout) {
2642                         usleep_range(600, 800);
2643                 }
2644
2645                 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
2646                         netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
2647                                    req->cmpl_ring_req_type);
2648                         return -1;
2649                 }
2650         } else {
2651                 /* Check if response len is updated */
2652                 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
2653                 for (i = 0; i < timeout; i++) {
2654                         len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
2655                               HWRM_RESP_LEN_SFT;
2656                         if (len)
2657                                 break;
2658                         usleep_range(600, 800);
2659                 }
2660
2661                 if (i >= timeout) {
2662                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
2663                                    timeout, req->cmpl_ring_req_type,
2664                                    req->target_id_seq_id, *resp_len);
2665                         return -1;
2666                 }
2667
2668                 /* Last word of resp contains valid bit */
2669                 valid = bp->hwrm_cmd_resp_addr + len - 4;
2670                 for (i = 0; i < timeout; i++) {
2671                         if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
2672                                 break;
2673                         usleep_range(600, 800);
2674                 }
2675
2676                 if (i >= timeout) {
2677                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
2678                                    timeout, req->cmpl_ring_req_type,
2679                                    req->target_id_seq_id, len, *valid);
2680                         return -1;
2681                 }
2682         }
2683
2684         rc = le16_to_cpu(resp->error_code);
2685         if (rc) {
2686                 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
2687                            le16_to_cpu(resp->req_type),
2688                            le16_to_cpu(resp->seq_id), rc);
2689                 return rc;
2690         }
2691         return 0;
2692 }
2693
2694 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2695 {
2696         int rc;
2697
2698         mutex_lock(&bp->hwrm_cmd_lock);
2699         rc = _hwrm_send_message(bp, msg, msg_len, timeout);
2700         mutex_unlock(&bp->hwrm_cmd_lock);
2701         return rc;
2702 }
2703
2704 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
2705 {
2706         struct hwrm_func_drv_rgtr_input req = {0};
2707         int i;
2708
2709         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
2710
2711         req.enables =
2712                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
2713                             FUNC_DRV_RGTR_REQ_ENABLES_VER |
2714                             FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
2715
2716         /* TODO: current async event fwd bits are not defined and the firmware
2717          * only checks if it is non-zero to enable async event forwarding
2718          */
2719         req.async_event_fwd[0] |= cpu_to_le32(1);
2720         req.os_type = cpu_to_le16(1);
2721         req.ver_maj = DRV_VER_MAJ;
2722         req.ver_min = DRV_VER_MIN;
2723         req.ver_upd = DRV_VER_UPD;
2724
2725         if (BNXT_PF(bp)) {
2726                 DECLARE_BITMAP(vf_req_snif_bmap, 256);
2727                 u32 *data = (u32 *)vf_req_snif_bmap;
2728
2729                 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap));
2730                 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++)
2731                         __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap);
2732
2733                 for (i = 0; i < 8; i++)
2734                         req.vf_req_fwd[i] = cpu_to_le32(data[i]);
2735
2736                 req.enables |=
2737                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
2738         }
2739
2740         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2741 }
2742
2743 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
2744 {
2745         struct hwrm_func_drv_unrgtr_input req = {0};
2746
2747         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
2748         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2749 }
2750
2751 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
2752 {
2753         u32 rc = 0;
2754         struct hwrm_tunnel_dst_port_free_input req = {0};
2755
2756         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
2757         req.tunnel_type = tunnel_type;
2758
2759         switch (tunnel_type) {
2760         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
2761                 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
2762                 break;
2763         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
2764                 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
2765                 break;
2766         default:
2767                 break;
2768         }
2769
2770         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2771         if (rc)
2772                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
2773                            rc);
2774         return rc;
2775 }
2776
2777 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
2778                                            u8 tunnel_type)
2779 {
2780         u32 rc = 0;
2781         struct hwrm_tunnel_dst_port_alloc_input req = {0};
2782         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2783
2784         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
2785
2786         req.tunnel_type = tunnel_type;
2787         req.tunnel_dst_port_val = port;
2788
2789         mutex_lock(&bp->hwrm_cmd_lock);
2790         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2791         if (rc) {
2792                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
2793                            rc);
2794                 goto err_out;
2795         }
2796
2797         if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN)
2798                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2799
2800         else if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE)
2801                 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
2802 err_out:
2803         mutex_unlock(&bp->hwrm_cmd_lock);
2804         return rc;
2805 }
2806
2807 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
2808 {
2809         struct hwrm_cfa_l2_set_rx_mask_input req = {0};
2810         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2811
2812         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
2813         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
2814
2815         req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
2816         req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
2817         req.mask = cpu_to_le32(vnic->rx_mask);
2818         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2819 }
2820
2821 #ifdef CONFIG_RFS_ACCEL
2822 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
2823                                             struct bnxt_ntuple_filter *fltr)
2824 {
2825         struct hwrm_cfa_ntuple_filter_free_input req = {0};
2826
2827         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
2828         req.ntuple_filter_id = fltr->filter_id;
2829         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2830 }
2831
2832 #define BNXT_NTP_FLTR_FLAGS                                     \
2833         (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID |     \
2834          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE |        \
2835          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR |      \
2836          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE |      \
2837          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR |       \
2838          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK |  \
2839          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR |       \
2840          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK |  \
2841          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL |      \
2842          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT |         \
2843          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK |    \
2844          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT |         \
2845          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK |    \
2846          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
2847
2848 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
2849                                              struct bnxt_ntuple_filter *fltr)
2850 {
2851         int rc = 0;
2852         struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
2853         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
2854                 bp->hwrm_cmd_resp_addr;
2855         struct flow_keys *keys = &fltr->fkeys;
2856         struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
2857
2858         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
2859         req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[0];
2860
2861         req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
2862
2863         req.ethertype = htons(ETH_P_IP);
2864         memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
2865         req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
2866         req.ip_protocol = keys->basic.ip_proto;
2867
2868         req.src_ipaddr[0] = keys->addrs.v4addrs.src;
2869         req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
2870         req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
2871         req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
2872
2873         req.src_port = keys->ports.src;
2874         req.src_port_mask = cpu_to_be16(0xffff);
2875         req.dst_port = keys->ports.dst;
2876         req.dst_port_mask = cpu_to_be16(0xffff);
2877
2878         req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
2879         mutex_lock(&bp->hwrm_cmd_lock);
2880         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2881         if (!rc)
2882                 fltr->filter_id = resp->ntuple_filter_id;
2883         mutex_unlock(&bp->hwrm_cmd_lock);
2884         return rc;
2885 }
2886 #endif
2887
2888 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
2889                                      u8 *mac_addr)
2890 {
2891         u32 rc = 0;
2892         struct hwrm_cfa_l2_filter_alloc_input req = {0};
2893         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2894
2895         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
2896         req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX |
2897                                 CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
2898         req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
2899         req.enables =
2900                 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
2901                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
2902                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
2903         memcpy(req.l2_addr, mac_addr, ETH_ALEN);
2904         req.l2_addr_mask[0] = 0xff;
2905         req.l2_addr_mask[1] = 0xff;
2906         req.l2_addr_mask[2] = 0xff;
2907         req.l2_addr_mask[3] = 0xff;
2908         req.l2_addr_mask[4] = 0xff;
2909         req.l2_addr_mask[5] = 0xff;
2910
2911         mutex_lock(&bp->hwrm_cmd_lock);
2912         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2913         if (!rc)
2914                 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
2915                                                         resp->l2_filter_id;
2916         mutex_unlock(&bp->hwrm_cmd_lock);
2917         return rc;
2918 }
2919
2920 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
2921 {
2922         u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
2923         int rc = 0;
2924
2925         /* Any associated ntuple filters will also be cleared by firmware. */
2926         mutex_lock(&bp->hwrm_cmd_lock);
2927         for (i = 0; i < num_of_vnics; i++) {
2928                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2929
2930                 for (j = 0; j < vnic->uc_filter_count; j++) {
2931                         struct hwrm_cfa_l2_filter_free_input req = {0};
2932
2933                         bnxt_hwrm_cmd_hdr_init(bp, &req,
2934                                                HWRM_CFA_L2_FILTER_FREE, -1, -1);
2935
2936                         req.l2_filter_id = vnic->fw_l2_filter_id[j];
2937
2938                         rc = _hwrm_send_message(bp, &req, sizeof(req),
2939                                                 HWRM_CMD_TIMEOUT);
2940                 }
2941                 vnic->uc_filter_count = 0;
2942         }
2943         mutex_unlock(&bp->hwrm_cmd_lock);
2944
2945         return rc;
2946 }
2947
2948 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
2949 {
2950         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2951         struct hwrm_vnic_tpa_cfg_input req = {0};
2952
2953         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
2954
2955         if (tpa_flags) {
2956                 u16 mss = bp->dev->mtu - 40;
2957                 u32 nsegs, n, segs = 0, flags;
2958
2959                 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
2960                         VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
2961                         VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
2962                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
2963                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
2964                 if (tpa_flags & BNXT_FLAG_GRO)
2965                         flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
2966
2967                 req.flags = cpu_to_le32(flags);
2968
2969                 req.enables =
2970                         cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
2971                                     VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
2972                                     VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
2973
2974                 /* Number of segs are log2 units, and first packet is not
2975                  * included as part of this units.
2976                  */
2977                 if (mss <= PAGE_SIZE) {
2978                         n = PAGE_SIZE / mss;
2979                         nsegs = (MAX_SKB_FRAGS - 1) * n;
2980                 } else {
2981                         n = mss / PAGE_SIZE;
2982                         if (mss & (PAGE_SIZE - 1))
2983                                 n++;
2984                         nsegs = (MAX_SKB_FRAGS - n) / n;
2985                 }
2986
2987                 segs = ilog2(nsegs);
2988                 req.max_agg_segs = cpu_to_le16(segs);
2989                 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
2990
2991                 req.min_agg_len = cpu_to_le32(512);
2992         }
2993         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
2994
2995         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2996 }
2997
2998 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
2999 {
3000         u32 i, j, max_rings;
3001         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3002         struct hwrm_vnic_rss_cfg_input req = {0};
3003
3004         if (vnic->fw_rss_cos_lb_ctx == INVALID_HW_RING_ID)
3005                 return 0;
3006
3007         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3008         if (set_rss) {
3009                 vnic->hash_type = BNXT_RSS_HASH_TYPE_FLAG_IPV4 |
3010                                  BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4 |
3011                                  BNXT_RSS_HASH_TYPE_FLAG_IPV6 |
3012                                  BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6;
3013
3014                 req.hash_type = cpu_to_le32(vnic->hash_type);
3015
3016                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3017                         max_rings = bp->rx_nr_rings;
3018                 else
3019                         max_rings = 1;
3020
3021                 /* Fill the RSS indirection table with ring group ids */
3022                 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3023                         if (j == max_rings)
3024                                 j = 0;
3025                         vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3026                 }
3027
3028                 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3029                 req.hash_key_tbl_addr =
3030                         cpu_to_le64(vnic->rss_hash_key_dma_addr);
3031         }
3032         req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3033         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3034 }
3035
3036 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3037 {
3038         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3039         struct hwrm_vnic_plcmodes_cfg_input req = {0};
3040
3041         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3042         req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3043                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3044                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3045         req.enables =
3046                 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3047                             VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3048         /* thresholds not implemented in firmware yet */
3049         req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3050         req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3051         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3052         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3053 }
3054
3055 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id)
3056 {
3057         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3058
3059         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3060         req.rss_cos_lb_ctx_id =
3061                 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx);
3062
3063         hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3064         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3065 }
3066
3067 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3068 {
3069         int i;
3070
3071         for (i = 0; i < bp->nr_vnics; i++) {
3072                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3073
3074                 if (vnic->fw_rss_cos_lb_ctx != INVALID_HW_RING_ID)
3075                         bnxt_hwrm_vnic_ctx_free_one(bp, i);
3076         }
3077         bp->rsscos_nr_ctxs = 0;
3078 }
3079
3080 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id)
3081 {
3082         int rc;
3083         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3084         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3085                                                 bp->hwrm_cmd_resp_addr;
3086
3087         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3088                                -1);
3089
3090         mutex_lock(&bp->hwrm_cmd_lock);
3091         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3092         if (!rc)
3093                 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx =
3094                         le16_to_cpu(resp->rss_cos_lb_ctx_id);
3095         mutex_unlock(&bp->hwrm_cmd_lock);
3096
3097         return rc;
3098 }
3099
3100 static int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3101 {
3102         unsigned int ring = 0, grp_idx;
3103         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3104         struct hwrm_vnic_cfg_input req = {0};
3105
3106         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
3107         /* Only RSS support for now TBD: COS & LB */
3108         req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP |
3109                                   VNIC_CFG_REQ_ENABLES_RSS_RULE);
3110         req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3111         req.cos_rule = cpu_to_le16(0xffff);
3112         if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3113                 ring = 0;
3114         else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
3115                 ring = vnic_id - 1;
3116
3117         grp_idx = bp->rx_ring[ring].bnapi->index;
3118         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3119         req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3120
3121         req.lb_rule = cpu_to_le16(0xffff);
3122         req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3123                               VLAN_HLEN);
3124
3125         if (bp->flags & BNXT_FLAG_STRIP_VLAN)
3126                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
3127
3128         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3129 }
3130
3131 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3132 {
3133         u32 rc = 0;
3134
3135         if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3136                 struct hwrm_vnic_free_input req = {0};
3137
3138                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3139                 req.vnic_id =
3140                         cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3141
3142                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3143                 if (rc)
3144                         return rc;
3145                 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3146         }
3147         return rc;
3148 }
3149
3150 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3151 {
3152         u16 i;
3153
3154         for (i = 0; i < bp->nr_vnics; i++)
3155                 bnxt_hwrm_vnic_free_one(bp, i);
3156 }
3157
3158 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
3159                                 unsigned int start_rx_ring_idx,
3160                                 unsigned int nr_rings)
3161 {
3162         int rc = 0;
3163         unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
3164         struct hwrm_vnic_alloc_input req = {0};
3165         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3166
3167         /* map ring groups to this vnic */
3168         for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
3169                 grp_idx = bp->rx_ring[i].bnapi->index;
3170                 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
3171                         netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
3172                                    j, nr_rings);
3173                         break;
3174                 }
3175                 bp->vnic_info[vnic_id].fw_grp_ids[j] =
3176                                         bp->grp_info[grp_idx].fw_grp_id;
3177         }
3178
3179         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3180         if (vnic_id == 0)
3181                 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
3182
3183         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
3184
3185         mutex_lock(&bp->hwrm_cmd_lock);
3186         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3187         if (!rc)
3188                 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
3189         mutex_unlock(&bp->hwrm_cmd_lock);
3190         return rc;
3191 }
3192
3193 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
3194 {
3195         u16 i;
3196         u32 rc = 0;
3197
3198         mutex_lock(&bp->hwrm_cmd_lock);
3199         for (i = 0; i < bp->rx_nr_rings; i++) {
3200                 struct hwrm_ring_grp_alloc_input req = {0};
3201                 struct hwrm_ring_grp_alloc_output *resp =
3202                                         bp->hwrm_cmd_resp_addr;
3203                 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
3204
3205                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
3206
3207                 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
3208                 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
3209                 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
3210                 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
3211
3212                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3213                                         HWRM_CMD_TIMEOUT);
3214                 if (rc)
3215                         break;
3216
3217                 bp->grp_info[grp_idx].fw_grp_id =
3218                         le32_to_cpu(resp->ring_group_id);
3219         }
3220         mutex_unlock(&bp->hwrm_cmd_lock);
3221         return rc;
3222 }
3223
3224 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
3225 {
3226         u16 i;
3227         u32 rc = 0;
3228         struct hwrm_ring_grp_free_input req = {0};
3229
3230         if (!bp->grp_info)
3231                 return 0;
3232
3233         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
3234
3235         mutex_lock(&bp->hwrm_cmd_lock);
3236         for (i = 0; i < bp->cp_nr_rings; i++) {
3237                 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
3238                         continue;
3239                 req.ring_group_id =
3240                         cpu_to_le32(bp->grp_info[i].fw_grp_id);
3241
3242                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3243                                         HWRM_CMD_TIMEOUT);
3244                 if (rc)
3245                         break;
3246                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3247         }
3248         mutex_unlock(&bp->hwrm_cmd_lock);
3249         return rc;
3250 }
3251
3252 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
3253                                     struct bnxt_ring_struct *ring,
3254                                     u32 ring_type, u32 map_index,
3255                                     u32 stats_ctx_id)
3256 {
3257         int rc = 0, err = 0;
3258         struct hwrm_ring_alloc_input req = {0};
3259         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3260         u16 ring_id;
3261
3262         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
3263
3264         req.enables = 0;
3265         if (ring->nr_pages > 1) {
3266                 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
3267                 /* Page size is in log2 units */
3268                 req.page_size = BNXT_PAGE_SHIFT;
3269                 req.page_tbl_depth = 1;
3270         } else {
3271                 req.page_tbl_addr =  cpu_to_le64(ring->dma_arr[0]);
3272         }
3273         req.fbo = 0;
3274         /* Association of ring index with doorbell index and MSIX number */
3275         req.logical_id = cpu_to_le16(map_index);
3276
3277         switch (ring_type) {
3278         case HWRM_RING_ALLOC_TX:
3279                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
3280                 /* Association of transmit ring with completion ring */
3281                 req.cmpl_ring_id =
3282                         cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
3283                 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
3284                 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
3285                 req.queue_id = cpu_to_le16(ring->queue_id);
3286                 break;
3287         case HWRM_RING_ALLOC_RX:
3288                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3289                 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
3290                 break;
3291         case HWRM_RING_ALLOC_AGG:
3292                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3293                 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
3294                 break;
3295         case HWRM_RING_ALLOC_CMPL:
3296                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_CMPL;
3297                 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
3298                 if (bp->flags & BNXT_FLAG_USING_MSIX)
3299                         req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
3300                 break;
3301         default:
3302                 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
3303                            ring_type);
3304                 return -1;
3305         }
3306
3307         mutex_lock(&bp->hwrm_cmd_lock);
3308         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3309         err = le16_to_cpu(resp->error_code);
3310         ring_id = le16_to_cpu(resp->ring_id);
3311         mutex_unlock(&bp->hwrm_cmd_lock);
3312
3313         if (rc || err) {
3314                 switch (ring_type) {
3315                 case RING_FREE_REQ_RING_TYPE_CMPL:
3316                         netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3317                                    rc, err);
3318                         return -1;
3319
3320                 case RING_FREE_REQ_RING_TYPE_RX:
3321                         netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3322                                    rc, err);
3323                         return -1;
3324
3325                 case RING_FREE_REQ_RING_TYPE_TX:
3326                         netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3327                                    rc, err);
3328                         return -1;
3329
3330                 default:
3331                         netdev_err(bp->dev, "Invalid ring\n");
3332                         return -1;
3333                 }
3334         }
3335         ring->fw_ring_id = ring_id;
3336         return rc;
3337 }
3338
3339 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
3340 {
3341         int i, rc = 0;
3342
3343         for (i = 0; i < bp->cp_nr_rings; i++) {
3344                 struct bnxt_napi *bnapi = bp->bnapi[i];
3345                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3346                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3347
3348                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
3349                                               INVALID_STATS_CTX_ID);
3350                 if (rc)
3351                         goto err_out;
3352                 cpr->cp_doorbell = bp->bar1 + i * 0x80;
3353                 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3354                 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
3355         }
3356
3357         for (i = 0; i < bp->tx_nr_rings; i++) {
3358                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3359                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3360                 u32 map_idx = txr->bnapi->index;
3361                 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
3362
3363                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
3364                                               map_idx, fw_stats_ctx);
3365                 if (rc)
3366                         goto err_out;
3367                 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
3368         }
3369
3370         for (i = 0; i < bp->rx_nr_rings; i++) {
3371                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3372                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3373                 u32 map_idx = rxr->bnapi->index;
3374
3375                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
3376                                               map_idx, INVALID_STATS_CTX_ID);
3377                 if (rc)
3378                         goto err_out;
3379                 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
3380                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
3381                 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
3382         }
3383
3384         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3385                 for (i = 0; i < bp->rx_nr_rings; i++) {
3386                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3387                         struct bnxt_ring_struct *ring =
3388                                                 &rxr->rx_agg_ring_struct;
3389                         u32 grp_idx = rxr->bnapi->index;
3390                         u32 map_idx = grp_idx + bp->rx_nr_rings;
3391
3392                         rc = hwrm_ring_alloc_send_msg(bp, ring,
3393                                                       HWRM_RING_ALLOC_AGG,
3394                                                       map_idx,
3395                                                       INVALID_STATS_CTX_ID);
3396                         if (rc)
3397                                 goto err_out;
3398
3399                         rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
3400                         writel(DB_KEY_RX | rxr->rx_agg_prod,
3401                                rxr->rx_agg_doorbell);
3402                         bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
3403                 }
3404         }
3405 err_out:
3406         return rc;
3407 }
3408
3409 static int hwrm_ring_free_send_msg(struct bnxt *bp,
3410                                    struct bnxt_ring_struct *ring,
3411                                    u32 ring_type, int cmpl_ring_id)
3412 {
3413         int rc;
3414         struct hwrm_ring_free_input req = {0};
3415         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
3416         u16 error_code;
3417
3418         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
3419         req.ring_type = ring_type;
3420         req.ring_id = cpu_to_le16(ring->fw_ring_id);
3421
3422         mutex_lock(&bp->hwrm_cmd_lock);
3423         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3424         error_code = le16_to_cpu(resp->error_code);
3425         mutex_unlock(&bp->hwrm_cmd_lock);
3426
3427         if (rc || error_code) {
3428                 switch (ring_type) {
3429                 case RING_FREE_REQ_RING_TYPE_CMPL:
3430                         netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
3431                                    rc);
3432                         return rc;
3433                 case RING_FREE_REQ_RING_TYPE_RX:
3434                         netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
3435                                    rc);
3436                         return rc;
3437                 case RING_FREE_REQ_RING_TYPE_TX:
3438                         netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
3439                                    rc);
3440                         return rc;
3441                 default:
3442                         netdev_err(bp->dev, "Invalid ring\n");
3443                         return -1;
3444                 }
3445         }
3446         return 0;
3447 }
3448
3449 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
3450 {
3451         int i;
3452
3453         if (!bp->bnapi)
3454                 return;
3455
3456         for (i = 0; i < bp->tx_nr_rings; i++) {
3457                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3458                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3459                 u32 grp_idx = txr->bnapi->index;
3460                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3461
3462                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3463                         hwrm_ring_free_send_msg(bp, ring,
3464                                                 RING_FREE_REQ_RING_TYPE_TX,
3465                                                 close_path ? cmpl_ring_id :
3466                                                 INVALID_HW_RING_ID);
3467                         ring->fw_ring_id = INVALID_HW_RING_ID;
3468                 }
3469         }
3470
3471         for (i = 0; i < bp->rx_nr_rings; i++) {
3472                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3473                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3474                 u32 grp_idx = rxr->bnapi->index;
3475                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3476
3477                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3478                         hwrm_ring_free_send_msg(bp, ring,
3479                                                 RING_FREE_REQ_RING_TYPE_RX,
3480                                                 close_path ? cmpl_ring_id :
3481                                                 INVALID_HW_RING_ID);
3482                         ring->fw_ring_id = INVALID_HW_RING_ID;
3483                         bp->grp_info[grp_idx].rx_fw_ring_id =
3484                                 INVALID_HW_RING_ID;
3485                 }
3486         }
3487
3488         for (i = 0; i < bp->rx_nr_rings; i++) {
3489                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3490                 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
3491                 u32 grp_idx = rxr->bnapi->index;
3492                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3493
3494                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3495                         hwrm_ring_free_send_msg(bp, ring,
3496                                                 RING_FREE_REQ_RING_TYPE_RX,
3497                                                 close_path ? cmpl_ring_id :
3498                                                 INVALID_HW_RING_ID);
3499                         ring->fw_ring_id = INVALID_HW_RING_ID;
3500                         bp->grp_info[grp_idx].agg_fw_ring_id =
3501                                 INVALID_HW_RING_ID;
3502                 }
3503         }
3504
3505         for (i = 0; i < bp->cp_nr_rings; i++) {
3506                 struct bnxt_napi *bnapi = bp->bnapi[i];
3507                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3508                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3509
3510                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3511                         hwrm_ring_free_send_msg(bp, ring,
3512                                                 RING_FREE_REQ_RING_TYPE_CMPL,
3513                                                 INVALID_HW_RING_ID);
3514                         ring->fw_ring_id = INVALID_HW_RING_ID;
3515                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
3516                 }
3517         }
3518 }
3519
3520 int bnxt_hwrm_set_coal(struct bnxt *bp)
3521 {
3522         int i, rc = 0;
3523         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
3524         u16 max_buf, max_buf_irq;
3525         u16 buf_tmr, buf_tmr_irq;
3526         u32 flags;
3527
3528         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
3529                                -1, -1);
3530
3531         /* Each rx completion (2 records) should be DMAed immediately */
3532         max_buf = min_t(u16, bp->coal_bufs / 4, 2);
3533         /* max_buf must not be zero */
3534         max_buf = clamp_t(u16, max_buf, 1, 63);
3535         max_buf_irq = clamp_t(u16, bp->coal_bufs_irq, 1, 63);
3536         buf_tmr = max_t(u16, bp->coal_ticks / 4, 1);
3537         buf_tmr_irq = max_t(u16, bp->coal_ticks_irq, 1);
3538
3539         flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
3540
3541         /* RING_IDLE generates more IRQs for lower latency.  Enable it only
3542          * if coal_ticks is less than 25 us.
3543          */
3544         if (BNXT_COAL_TIMER_TO_USEC(bp->coal_ticks) < 25)
3545                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
3546
3547         req.flags = cpu_to_le16(flags);
3548         req.num_cmpl_dma_aggr = cpu_to_le16(max_buf);
3549         req.num_cmpl_dma_aggr_during_int = cpu_to_le16(max_buf_irq);
3550         req.cmpl_aggr_dma_tmr = cpu_to_le16(buf_tmr);
3551         req.cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmr_irq);
3552         req.int_lat_tmr_min = cpu_to_le16(buf_tmr);
3553         req.int_lat_tmr_max = cpu_to_le16(bp->coal_ticks);
3554         req.num_cmpl_aggr_int = cpu_to_le16(bp->coal_bufs);
3555
3556         mutex_lock(&bp->hwrm_cmd_lock);
3557         for (i = 0; i < bp->cp_nr_rings; i++) {
3558                 req.ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
3559
3560                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3561                                         HWRM_CMD_TIMEOUT);
3562                 if (rc)
3563                         break;
3564         }
3565         mutex_unlock(&bp->hwrm_cmd_lock);
3566         return rc;
3567 }
3568
3569 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
3570 {
3571         int rc = 0, i;
3572         struct hwrm_stat_ctx_free_input req = {0};
3573
3574         if (!bp->bnapi)
3575                 return 0;
3576
3577         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
3578
3579         mutex_lock(&bp->hwrm_cmd_lock);
3580         for (i = 0; i < bp->cp_nr_rings; i++) {
3581                 struct bnxt_napi *bnapi = bp->bnapi[i];
3582                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3583
3584                 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
3585                         req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
3586
3587                         rc = _hwrm_send_message(bp, &req, sizeof(req),
3588                                                 HWRM_CMD_TIMEOUT);
3589                         if (rc)
3590                                 break;
3591
3592                         cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3593                 }
3594         }
3595         mutex_unlock(&bp->hwrm_cmd_lock);
3596         return rc;
3597 }
3598
3599 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
3600 {
3601         int rc = 0, i;
3602         struct hwrm_stat_ctx_alloc_input req = {0};
3603         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3604
3605         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
3606
3607         req.update_period_ms = cpu_to_le32(1000);
3608
3609         mutex_lock(&bp->hwrm_cmd_lock);
3610         for (i = 0; i < bp->cp_nr_rings; i++) {
3611                 struct bnxt_napi *bnapi = bp->bnapi[i];
3612                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3613
3614                 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
3615
3616                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3617                                         HWRM_CMD_TIMEOUT);
3618                 if (rc)
3619                         break;
3620
3621                 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
3622
3623                 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
3624         }
3625         mutex_unlock(&bp->hwrm_cmd_lock);
3626         return 0;
3627 }
3628
3629 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
3630 {
3631         int rc = 0;
3632         struct hwrm_func_qcaps_input req = {0};
3633         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3634
3635         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
3636         req.fid = cpu_to_le16(0xffff);
3637
3638         mutex_lock(&bp->hwrm_cmd_lock);
3639         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3640         if (rc)
3641                 goto hwrm_func_qcaps_exit;
3642
3643         if (BNXT_PF(bp)) {
3644                 struct bnxt_pf_info *pf = &bp->pf;
3645
3646                 pf->fw_fid = le16_to_cpu(resp->fid);
3647                 pf->port_id = le16_to_cpu(resp->port_id);
3648                 memcpy(pf->mac_addr, resp->perm_mac_address, ETH_ALEN);
3649                 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN);
3650                 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
3651                 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
3652                 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
3653                 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
3654                 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
3655                 if (!pf->max_hw_ring_grps)
3656                         pf->max_hw_ring_grps = pf->max_tx_rings;
3657                 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
3658                 pf->max_vnics = le16_to_cpu(resp->max_vnics);
3659                 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
3660                 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
3661                 pf->max_vfs = le16_to_cpu(resp->max_vfs);
3662                 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
3663                 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
3664                 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
3665                 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
3666                 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
3667                 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
3668         } else {
3669 #ifdef CONFIG_BNXT_SRIOV
3670                 struct bnxt_vf_info *vf = &bp->vf;
3671
3672                 vf->fw_fid = le16_to_cpu(resp->fid);
3673                 memcpy(vf->mac_addr, resp->perm_mac_address, ETH_ALEN);
3674                 if (is_valid_ether_addr(vf->mac_addr))
3675                         /* overwrite netdev dev_adr with admin VF MAC */
3676                         memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
3677                 else
3678                         random_ether_addr(bp->dev->dev_addr);
3679
3680                 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
3681                 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
3682                 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
3683                 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
3684                 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
3685                 if (!vf->max_hw_ring_grps)
3686                         vf->max_hw_ring_grps = vf->max_tx_rings;
3687                 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
3688                 vf->max_vnics = le16_to_cpu(resp->max_vnics);
3689                 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
3690 #endif
3691         }
3692
3693         bp->tx_push_thresh = 0;
3694         if (resp->flags &
3695             cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
3696                 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
3697
3698 hwrm_func_qcaps_exit:
3699         mutex_unlock(&bp->hwrm_cmd_lock);
3700         return rc;
3701 }
3702
3703 static int bnxt_hwrm_func_reset(struct bnxt *bp)
3704 {
3705         struct hwrm_func_reset_input req = {0};
3706
3707         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
3708         req.enables = 0;
3709
3710         return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
3711 }
3712
3713 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
3714 {
3715         int rc = 0;
3716         struct hwrm_queue_qportcfg_input req = {0};
3717         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
3718         u8 i, *qptr;
3719
3720         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
3721
3722         mutex_lock(&bp->hwrm_cmd_lock);
3723         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3724         if (rc)
3725                 goto qportcfg_exit;
3726
3727         if (!resp->max_configurable_queues) {
3728                 rc = -EINVAL;
3729                 goto qportcfg_exit;
3730         }
3731         bp->max_tc = resp->max_configurable_queues;
3732         if (bp->max_tc > BNXT_MAX_QUEUE)
3733                 bp->max_tc = BNXT_MAX_QUEUE;
3734
3735         qptr = &resp->queue_id0;
3736         for (i = 0; i < bp->max_tc; i++) {
3737                 bp->q_info[i].queue_id = *qptr++;
3738                 bp->q_info[i].queue_profile = *qptr++;
3739         }
3740
3741 qportcfg_exit:
3742         mutex_unlock(&bp->hwrm_cmd_lock);
3743         return rc;
3744 }
3745
3746 static int bnxt_hwrm_ver_get(struct bnxt *bp)
3747 {
3748         int rc;
3749         struct hwrm_ver_get_input req = {0};
3750         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
3751
3752         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
3753         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
3754         req.hwrm_intf_min = HWRM_VERSION_MINOR;
3755         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
3756         mutex_lock(&bp->hwrm_cmd_lock);
3757         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3758         if (rc)
3759                 goto hwrm_ver_get_exit;
3760
3761         memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
3762
3763         if (resp->hwrm_intf_maj < 1) {
3764                 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
3765                             resp->hwrm_intf_maj, resp->hwrm_intf_min,
3766                             resp->hwrm_intf_upd);
3767                 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
3768         }
3769         snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "bc %d.%d.%d rm %d.%d.%d",
3770                  resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
3771                  resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
3772
3773 hwrm_ver_get_exit:
3774         mutex_unlock(&bp->hwrm_cmd_lock);
3775         return rc;
3776 }
3777
3778 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
3779 {
3780         if (bp->vxlan_port_cnt) {
3781                 bnxt_hwrm_tunnel_dst_port_free(
3782                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
3783         }
3784         bp->vxlan_port_cnt = 0;
3785         if (bp->nge_port_cnt) {
3786                 bnxt_hwrm_tunnel_dst_port_free(
3787                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
3788         }
3789         bp->nge_port_cnt = 0;
3790 }
3791
3792 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
3793 {
3794         int rc, i;
3795         u32 tpa_flags = 0;
3796
3797         if (set_tpa)
3798                 tpa_flags = bp->flags & BNXT_FLAG_TPA;
3799         for (i = 0; i < bp->nr_vnics; i++) {
3800                 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
3801                 if (rc) {
3802                         netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
3803                                    rc, i);
3804                         return rc;
3805                 }
3806         }
3807         return 0;
3808 }
3809
3810 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
3811 {
3812         int i;
3813
3814         for (i = 0; i < bp->nr_vnics; i++)
3815                 bnxt_hwrm_vnic_set_rss(bp, i, false);
3816 }
3817
3818 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
3819                                     bool irq_re_init)
3820 {
3821         if (bp->vnic_info) {
3822                 bnxt_hwrm_clear_vnic_filter(bp);
3823                 /* clear all RSS setting before free vnic ctx */
3824                 bnxt_hwrm_clear_vnic_rss(bp);
3825                 bnxt_hwrm_vnic_ctx_free(bp);
3826                 /* before free the vnic, undo the vnic tpa settings */
3827                 if (bp->flags & BNXT_FLAG_TPA)
3828                         bnxt_set_tpa(bp, false);
3829                 bnxt_hwrm_vnic_free(bp);
3830         }
3831         bnxt_hwrm_ring_free(bp, close_path);
3832         bnxt_hwrm_ring_grp_free(bp);
3833         if (irq_re_init) {
3834                 bnxt_hwrm_stat_ctx_free(bp);
3835                 bnxt_hwrm_free_tunnel_ports(bp);
3836         }
3837 }
3838
3839 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
3840 {
3841         int rc;
3842
3843         /* allocate context for vnic */
3844         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id);
3845         if (rc) {
3846                 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
3847                            vnic_id, rc);
3848                 goto vnic_setup_err;
3849         }
3850         bp->rsscos_nr_ctxs++;
3851
3852         /* configure default vnic, ring grp */
3853         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
3854         if (rc) {
3855                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
3856                            vnic_id, rc);
3857                 goto vnic_setup_err;
3858         }
3859
3860         /* Enable RSS hashing on vnic */
3861         rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
3862         if (rc) {
3863                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
3864                            vnic_id, rc);
3865                 goto vnic_setup_err;
3866         }
3867
3868         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3869                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
3870                 if (rc) {
3871                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
3872                                    vnic_id, rc);
3873                 }
3874         }
3875
3876 vnic_setup_err:
3877         return rc;
3878 }
3879
3880 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
3881 {
3882 #ifdef CONFIG_RFS_ACCEL
3883         int i, rc = 0;
3884
3885         for (i = 0; i < bp->rx_nr_rings; i++) {
3886                 u16 vnic_id = i + 1;
3887                 u16 ring_id = i;
3888
3889                 if (vnic_id >= bp->nr_vnics)
3890                         break;
3891
3892                 bp->vnic_info[vnic_id].flags |= BNXT_VNIC_RFS_FLAG;
3893                 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
3894                 if (rc) {
3895                         netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
3896                                    vnic_id, rc);
3897                         break;
3898                 }
3899                 rc = bnxt_setup_vnic(bp, vnic_id);
3900                 if (rc)
3901                         break;
3902         }
3903         return rc;
3904 #else
3905         return 0;
3906 #endif
3907 }
3908
3909 static int bnxt_cfg_rx_mode(struct bnxt *);
3910
3911 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
3912 {
3913         int rc = 0;
3914
3915         if (irq_re_init) {
3916                 rc = bnxt_hwrm_stat_ctx_alloc(bp);
3917                 if (rc) {
3918                         netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
3919                                    rc);
3920                         goto err_out;
3921                 }
3922         }
3923
3924         rc = bnxt_hwrm_ring_alloc(bp);
3925         if (rc) {
3926                 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
3927                 goto err_out;
3928         }
3929
3930         rc = bnxt_hwrm_ring_grp_alloc(bp);
3931         if (rc) {
3932                 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
3933                 goto err_out;
3934         }
3935
3936         /* default vnic 0 */
3937         rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, bp->rx_nr_rings);
3938         if (rc) {
3939                 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
3940                 goto err_out;
3941         }
3942
3943         rc = bnxt_setup_vnic(bp, 0);
3944         if (rc)
3945                 goto err_out;
3946
3947         if (bp->flags & BNXT_FLAG_RFS) {
3948                 rc = bnxt_alloc_rfs_vnics(bp);
3949                 if (rc)
3950                         goto err_out;
3951         }
3952
3953         if (bp->flags & BNXT_FLAG_TPA) {
3954                 rc = bnxt_set_tpa(bp, true);
3955                 if (rc)
3956                         goto err_out;
3957         }
3958
3959         if (BNXT_VF(bp))
3960                 bnxt_update_vf_mac(bp);
3961
3962         /* Filter for default vnic 0 */
3963         rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
3964         if (rc) {
3965                 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
3966                 goto err_out;
3967         }
3968         bp->vnic_info[0].uc_filter_count = 1;
3969
3970         bp->vnic_info[0].rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
3971
3972         if ((bp->dev->flags & IFF_PROMISC) && BNXT_PF(bp))
3973                 bp->vnic_info[0].rx_mask |=
3974                                 CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
3975
3976         rc = bnxt_cfg_rx_mode(bp);
3977         if (rc)
3978                 goto err_out;
3979
3980         rc = bnxt_hwrm_set_coal(bp);
3981         if (rc)
3982                 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
3983                             rc);
3984
3985         return 0;
3986
3987 err_out:
3988         bnxt_hwrm_resource_free(bp, 0, true);
3989
3990         return rc;
3991 }
3992
3993 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
3994 {
3995         bnxt_hwrm_resource_free(bp, 1, irq_re_init);
3996         return 0;
3997 }
3998
3999 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
4000 {
4001         bnxt_init_rx_rings(bp);
4002         bnxt_init_tx_rings(bp);
4003         bnxt_init_ring_grps(bp, irq_re_init);
4004         bnxt_init_vnics(bp);
4005
4006         return bnxt_init_chip(bp, irq_re_init);
4007 }
4008
4009 static void bnxt_disable_int(struct bnxt *bp)
4010 {
4011         int i;
4012
4013         if (!bp->bnapi)
4014                 return;
4015
4016         for (i = 0; i < bp->cp_nr_rings; i++) {
4017                 struct bnxt_napi *bnapi = bp->bnapi[i];
4018                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4019
4020                 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4021         }
4022 }
4023
4024 static void bnxt_enable_int(struct bnxt *bp)
4025 {
4026         int i;
4027
4028         atomic_set(&bp->intr_sem, 0);
4029         for (i = 0; i < bp->cp_nr_rings; i++) {
4030                 struct bnxt_napi *bnapi = bp->bnapi[i];
4031                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4032
4033                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
4034         }
4035 }
4036
4037 static int bnxt_set_real_num_queues(struct bnxt *bp)
4038 {
4039         int rc;
4040         struct net_device *dev = bp->dev;
4041
4042         rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings);
4043         if (rc)
4044                 return rc;
4045
4046         rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
4047         if (rc)
4048                 return rc;
4049
4050 #ifdef CONFIG_RFS_ACCEL
4051         if (bp->flags & BNXT_FLAG_RFS)
4052                 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
4053 #endif
4054
4055         return rc;
4056 }
4057
4058 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
4059                            bool shared)
4060 {
4061         int _rx = *rx, _tx = *tx;
4062
4063         if (shared) {
4064                 *rx = min_t(int, _rx, max);
4065                 *tx = min_t(int, _tx, max);
4066         } else {
4067                 if (max < 2)
4068                         return -ENOMEM;
4069
4070                 while (_rx + _tx > max) {
4071                         if (_rx > _tx && _rx > 1)
4072                                 _rx--;
4073                         else if (_tx > 1)
4074                                 _tx--;
4075                 }
4076                 *rx = _rx;
4077                 *tx = _tx;
4078         }
4079         return 0;
4080 }
4081
4082 static int bnxt_setup_msix(struct bnxt *bp)
4083 {
4084         struct msix_entry *msix_ent;
4085         struct net_device *dev = bp->dev;
4086         int i, total_vecs, rc = 0, min = 1;
4087         const int len = sizeof(bp->irq_tbl[0].name);
4088
4089         bp->flags &= ~BNXT_FLAG_USING_MSIX;
4090         total_vecs = bp->cp_nr_rings;
4091
4092         msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
4093         if (!msix_ent)
4094                 return -ENOMEM;
4095
4096         for (i = 0; i < total_vecs; i++) {
4097                 msix_ent[i].entry = i;
4098                 msix_ent[i].vector = 0;
4099         }
4100
4101         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
4102                 min = 2;
4103
4104         total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
4105         if (total_vecs < 0) {
4106                 rc = -ENODEV;
4107                 goto msix_setup_exit;
4108         }
4109
4110         bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
4111         if (bp->irq_tbl) {
4112                 int tcs;
4113
4114                 /* Trim rings based upon num of vectors allocated */
4115                 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
4116                                      total_vecs, min == 1);
4117                 if (rc)
4118                         goto msix_setup_exit;
4119
4120                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4121                 tcs = netdev_get_num_tc(dev);
4122                 if (tcs > 1) {
4123                         bp->tx_nr_rings_per_tc = bp->tx_nr_rings / tcs;
4124                         if (bp->tx_nr_rings_per_tc == 0) {
4125                                 netdev_reset_tc(dev);
4126                                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4127                         } else {
4128                                 int i, off, count;
4129
4130                                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs;
4131                                 for (i = 0; i < tcs; i++) {
4132                                         count = bp->tx_nr_rings_per_tc;
4133                                         off = i * count;
4134                                         netdev_set_tc_queue(dev, i, count, off);
4135                                 }
4136                         }
4137                 }
4138                 bp->cp_nr_rings = total_vecs;
4139
4140                 for (i = 0; i < bp->cp_nr_rings; i++) {
4141                         char *attr;
4142
4143                         bp->irq_tbl[i].vector = msix_ent[i].vector;
4144                         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4145                                 attr = "TxRx";
4146                         else if (i < bp->rx_nr_rings)
4147                                 attr = "rx";
4148                         else
4149                                 attr = "tx";
4150
4151                         snprintf(bp->irq_tbl[i].name, len,
4152                                  "%s-%s-%d", dev->name, attr, i);
4153                         bp->irq_tbl[i].handler = bnxt_msix;
4154                 }
4155                 rc = bnxt_set_real_num_queues(bp);
4156                 if (rc)
4157                         goto msix_setup_exit;
4158         } else {
4159                 rc = -ENOMEM;
4160                 goto msix_setup_exit;
4161         }
4162         bp->flags |= BNXT_FLAG_USING_MSIX;
4163         kfree(msix_ent);
4164         return 0;
4165
4166 msix_setup_exit:
4167         netdev_err(bp->dev, "bnxt_setup_msix err: %x\n", rc);
4168         pci_disable_msix(bp->pdev);
4169         kfree(msix_ent);
4170         return rc;
4171 }
4172
4173 static int bnxt_setup_inta(struct bnxt *bp)
4174 {
4175         int rc;
4176         const int len = sizeof(bp->irq_tbl[0].name);
4177
4178         if (netdev_get_num_tc(bp->dev))
4179                 netdev_reset_tc(bp->dev);
4180
4181         bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
4182         if (!bp->irq_tbl) {
4183                 rc = -ENOMEM;
4184                 return rc;
4185         }
4186         bp->rx_nr_rings = 1;
4187         bp->tx_nr_rings = 1;
4188         bp->cp_nr_rings = 1;
4189         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4190         bp->flags |= BNXT_FLAG_SHARED_RINGS;
4191         bp->irq_tbl[0].vector = bp->pdev->irq;
4192         snprintf(bp->irq_tbl[0].name, len,
4193                  "%s-%s-%d", bp->dev->name, "TxRx", 0);
4194         bp->irq_tbl[0].handler = bnxt_inta;
4195         rc = bnxt_set_real_num_queues(bp);
4196         return rc;
4197 }
4198
4199 static int bnxt_setup_int_mode(struct bnxt *bp)
4200 {
4201         int rc = 0;
4202
4203         if (bp->flags & BNXT_FLAG_MSIX_CAP)
4204                 rc = bnxt_setup_msix(bp);
4205
4206         if (!(bp->flags & BNXT_FLAG_USING_MSIX)) {
4207                 /* fallback to INTA */
4208                 rc = bnxt_setup_inta(bp);
4209         }
4210         return rc;
4211 }
4212
4213 static void bnxt_free_irq(struct bnxt *bp)
4214 {
4215         struct bnxt_irq *irq;
4216         int i;
4217
4218 #ifdef CONFIG_RFS_ACCEL
4219         free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
4220         bp->dev->rx_cpu_rmap = NULL;
4221 #endif
4222         if (!bp->irq_tbl)
4223                 return;
4224
4225         for (i = 0; i < bp->cp_nr_rings; i++) {
4226                 irq = &bp->irq_tbl[i];
4227                 if (irq->requested)
4228                         free_irq(irq->vector, bp->bnapi[i]);
4229                 irq->requested = 0;
4230         }
4231         if (bp->flags & BNXT_FLAG_USING_MSIX)
4232                 pci_disable_msix(bp->pdev);
4233         kfree(bp->irq_tbl);
4234         bp->irq_tbl = NULL;
4235 }
4236
4237 static int bnxt_request_irq(struct bnxt *bp)
4238 {
4239         int i, j, rc = 0;
4240         unsigned long flags = 0;
4241 #ifdef CONFIG_RFS_ACCEL
4242         struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
4243 #endif
4244
4245         if (!(bp->flags & BNXT_FLAG_USING_MSIX))
4246                 flags = IRQF_SHARED;
4247
4248         for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
4249                 struct bnxt_irq *irq = &bp->irq_tbl[i];
4250 #ifdef CONFIG_RFS_ACCEL
4251                 if (rmap && bp->bnapi[i]->rx_ring) {
4252                         rc = irq_cpu_rmap_add(rmap, irq->vector);
4253                         if (rc)
4254                                 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
4255                                             j);
4256                         j++;
4257                 }
4258 #endif
4259                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
4260                                  bp->bnapi[i]);
4261                 if (rc)
4262                         break;
4263
4264                 irq->requested = 1;
4265         }
4266         return rc;
4267 }
4268
4269 static void bnxt_del_napi(struct bnxt *bp)
4270 {
4271         int i;
4272
4273         if (!bp->bnapi)
4274                 return;
4275
4276         for (i = 0; i < bp->cp_nr_rings; i++) {
4277                 struct bnxt_napi *bnapi = bp->bnapi[i];
4278
4279                 napi_hash_del(&bnapi->napi);
4280                 netif_napi_del(&bnapi->napi);
4281         }
4282 }
4283
4284 static void bnxt_init_napi(struct bnxt *bp)
4285 {
4286         int i;
4287         struct bnxt_napi *bnapi;
4288
4289         if (bp->flags & BNXT_FLAG_USING_MSIX) {
4290                 for (i = 0; i < bp->cp_nr_rings; i++) {
4291                         bnapi = bp->bnapi[i];
4292                         netif_napi_add(bp->dev, &bnapi->napi,
4293                                        bnxt_poll, 64);
4294                 }
4295         } else {
4296                 bnapi = bp->bnapi[0];
4297                 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
4298         }
4299 }
4300
4301 static void bnxt_disable_napi(struct bnxt *bp)
4302 {
4303         int i;
4304
4305         if (!bp->bnapi)
4306                 return;
4307
4308         for (i = 0; i < bp->cp_nr_rings; i++) {
4309                 napi_disable(&bp->bnapi[i]->napi);
4310                 bnxt_disable_poll(bp->bnapi[i]);
4311         }
4312 }
4313
4314 static void bnxt_enable_napi(struct bnxt *bp)
4315 {
4316         int i;
4317
4318         for (i = 0; i < bp->cp_nr_rings; i++) {
4319                 bnxt_enable_poll(bp->bnapi[i]);
4320                 napi_enable(&bp->bnapi[i]->napi);
4321         }
4322 }
4323
4324 static void bnxt_tx_disable(struct bnxt *bp)
4325 {
4326         int i;
4327         struct bnxt_tx_ring_info *txr;
4328         struct netdev_queue *txq;
4329
4330         if (bp->tx_ring) {
4331                 for (i = 0; i < bp->tx_nr_rings; i++) {
4332                         txr = &bp->tx_ring[i];
4333                         txq = netdev_get_tx_queue(bp->dev, i);
4334                         __netif_tx_lock(txq, smp_processor_id());
4335                         txr->dev_state = BNXT_DEV_STATE_CLOSING;
4336                         __netif_tx_unlock(txq);
4337                 }
4338         }
4339         /* Stop all TX queues */
4340         netif_tx_disable(bp->dev);
4341         netif_carrier_off(bp->dev);
4342 }
4343
4344 static void bnxt_tx_enable(struct bnxt *bp)
4345 {
4346         int i;
4347         struct bnxt_tx_ring_info *txr;
4348         struct netdev_queue *txq;
4349
4350         for (i = 0; i < bp->tx_nr_rings; i++) {
4351                 txr = &bp->tx_ring[i];
4352                 txq = netdev_get_tx_queue(bp->dev, i);
4353                 txr->dev_state = 0;
4354         }
4355         netif_tx_wake_all_queues(bp->dev);
4356         if (bp->link_info.link_up)
4357                 netif_carrier_on(bp->dev);
4358 }
4359
4360 static void bnxt_report_link(struct bnxt *bp)
4361 {
4362         if (bp->link_info.link_up) {
4363                 const char *duplex;
4364                 const char *flow_ctrl;
4365                 u16 speed;
4366
4367                 netif_carrier_on(bp->dev);
4368                 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
4369                         duplex = "full";
4370                 else
4371                         duplex = "half";
4372                 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
4373                         flow_ctrl = "ON - receive & transmit";
4374                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
4375                         flow_ctrl = "ON - transmit";
4376                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
4377                         flow_ctrl = "ON - receive";
4378                 else
4379                         flow_ctrl = "none";
4380                 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
4381                 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
4382                             speed, duplex, flow_ctrl);
4383         } else {
4384                 netif_carrier_off(bp->dev);
4385                 netdev_err(bp->dev, "NIC Link is Down\n");
4386         }
4387 }
4388
4389 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
4390 {
4391         int rc = 0;
4392         struct bnxt_link_info *link_info = &bp->link_info;
4393         struct hwrm_port_phy_qcfg_input req = {0};
4394         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4395         u8 link_up = link_info->link_up;
4396
4397         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
4398
4399         mutex_lock(&bp->hwrm_cmd_lock);
4400         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4401         if (rc) {
4402                 mutex_unlock(&bp->hwrm_cmd_lock);
4403                 return rc;
4404         }
4405
4406         memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
4407         link_info->phy_link_status = resp->link;
4408         link_info->duplex =  resp->duplex;
4409         link_info->pause = resp->pause;
4410         link_info->auto_mode = resp->auto_mode;
4411         link_info->auto_pause_setting = resp->auto_pause;
4412         link_info->force_pause_setting = resp->force_pause;
4413         link_info->duplex_setting = resp->duplex;
4414         if (link_info->phy_link_status == BNXT_LINK_LINK)
4415                 link_info->link_speed = le16_to_cpu(resp->link_speed);
4416         else
4417                 link_info->link_speed = 0;
4418         link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
4419         link_info->auto_link_speed = le16_to_cpu(resp->auto_link_speed);
4420         link_info->support_speeds = le16_to_cpu(resp->support_speeds);
4421         link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
4422         link_info->preemphasis = le32_to_cpu(resp->preemphasis);
4423         link_info->phy_ver[0] = resp->phy_maj;
4424         link_info->phy_ver[1] = resp->phy_min;
4425         link_info->phy_ver[2] = resp->phy_bld;
4426         link_info->media_type = resp->media_type;
4427         link_info->transceiver = resp->transceiver_type;
4428         link_info->phy_addr = resp->phy_addr;
4429
4430         /* TODO: need to add more logic to report VF link */
4431         if (chng_link_state) {
4432                 if (link_info->phy_link_status == BNXT_LINK_LINK)
4433                         link_info->link_up = 1;
4434                 else
4435                         link_info->link_up = 0;
4436                 if (link_up != link_info->link_up)
4437                         bnxt_report_link(bp);
4438         } else {
4439                 /* alwasy link down if not require to update link state */
4440                 link_info->link_up = 0;
4441         }
4442         mutex_unlock(&bp->hwrm_cmd_lock);
4443         return 0;
4444 }
4445
4446 static void
4447 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
4448 {
4449         if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
4450                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4451                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
4452                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4453                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
4454                 req->enables |=
4455                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
4456         } else {
4457                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4458                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
4459                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4460                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
4461                 req->enables |=
4462                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
4463         }
4464 }
4465
4466 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
4467                                       struct hwrm_port_phy_cfg_input *req)
4468 {
4469         u8 autoneg = bp->link_info.autoneg;
4470         u16 fw_link_speed = bp->link_info.req_link_speed;
4471         u32 advertising = bp->link_info.advertising;
4472
4473         if (autoneg & BNXT_AUTONEG_SPEED) {
4474                 req->auto_mode |=
4475                         PORT_PHY_CFG_REQ_AUTO_MODE_MASK;
4476
4477                 req->enables |= cpu_to_le32(
4478                         PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
4479                 req->auto_link_speed_mask = cpu_to_le16(advertising);
4480
4481                 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
4482                 req->flags |=
4483                         cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
4484         } else {
4485                 req->force_link_speed = cpu_to_le16(fw_link_speed);
4486                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
4487         }
4488
4489         /* currently don't support half duplex */
4490         req->auto_duplex = PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL;
4491         req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX);
4492         /* tell chimp that the setting takes effect immediately */
4493         req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
4494 }
4495
4496 int bnxt_hwrm_set_pause(struct bnxt *bp)
4497 {
4498         struct hwrm_port_phy_cfg_input req = {0};
4499         int rc;
4500
4501         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4502         bnxt_hwrm_set_pause_common(bp, &req);
4503
4504         if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
4505             bp->link_info.force_link_chng)
4506                 bnxt_hwrm_set_link_common(bp, &req);
4507
4508         mutex_lock(&bp->hwrm_cmd_lock);
4509         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4510         if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
4511                 /* since changing of pause setting doesn't trigger any link
4512                  * change event, the driver needs to update the current pause
4513                  * result upon successfully return of the phy_cfg command
4514                  */
4515                 bp->link_info.pause =
4516                 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
4517                 bp->link_info.auto_pause_setting = 0;
4518                 if (!bp->link_info.force_link_chng)
4519                         bnxt_report_link(bp);
4520         }
4521         bp->link_info.force_link_chng = false;
4522         mutex_unlock(&bp->hwrm_cmd_lock);
4523         return rc;
4524 }
4525
4526 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause)
4527 {
4528         struct hwrm_port_phy_cfg_input req = {0};
4529
4530         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4531         if (set_pause)
4532                 bnxt_hwrm_set_pause_common(bp, &req);
4533
4534         bnxt_hwrm_set_link_common(bp, &req);
4535         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4536 }
4537
4538 static int bnxt_update_phy_setting(struct bnxt *bp)
4539 {
4540         int rc;
4541         bool update_link = false;
4542         bool update_pause = false;
4543         struct bnxt_link_info *link_info = &bp->link_info;
4544
4545         rc = bnxt_update_link(bp, true);
4546         if (rc) {
4547                 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
4548                            rc);
4549                 return rc;
4550         }
4551         if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
4552             link_info->auto_pause_setting != link_info->req_flow_ctrl)
4553                 update_pause = true;
4554         if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
4555             link_info->force_pause_setting != link_info->req_flow_ctrl)
4556                 update_pause = true;
4557         if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
4558                 if (BNXT_AUTO_MODE(link_info->auto_mode))
4559                         update_link = true;
4560                 if (link_info->req_link_speed != link_info->force_link_speed)
4561                         update_link = true;
4562                 if (link_info->req_duplex != link_info->duplex_setting)
4563                         update_link = true;
4564         } else {
4565                 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
4566                         update_link = true;
4567                 if (link_info->advertising != link_info->auto_link_speeds)
4568                         update_link = true;
4569         }
4570
4571         if (update_link)
4572                 rc = bnxt_hwrm_set_link_setting(bp, update_pause);
4573         else if (update_pause)
4574                 rc = bnxt_hwrm_set_pause(bp);
4575         if (rc) {
4576                 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
4577                            rc);
4578                 return rc;
4579         }
4580
4581         return rc;
4582 }
4583
4584 /* Common routine to pre-map certain register block to different GRC window.
4585  * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
4586  * in PF and 3 windows in VF that can be customized to map in different
4587  * register blocks.
4588  */
4589 static void bnxt_preset_reg_win(struct bnxt *bp)
4590 {
4591         if (BNXT_PF(bp)) {
4592                 /* CAG registers map to GRC window #4 */
4593                 writel(BNXT_CAG_REG_BASE,
4594                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
4595         }
4596 }
4597
4598 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4599 {
4600         int rc = 0;
4601
4602         bnxt_preset_reg_win(bp);
4603         netif_carrier_off(bp->dev);
4604         if (irq_re_init) {
4605                 rc = bnxt_setup_int_mode(bp);
4606                 if (rc) {
4607                         netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
4608                                    rc);
4609                         return rc;
4610                 }
4611         }
4612         if ((bp->flags & BNXT_FLAG_RFS) &&
4613             !(bp->flags & BNXT_FLAG_USING_MSIX)) {
4614                 /* disable RFS if falling back to INTA */
4615                 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
4616                 bp->flags &= ~BNXT_FLAG_RFS;
4617         }
4618
4619         rc = bnxt_alloc_mem(bp, irq_re_init);
4620         if (rc) {
4621                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
4622                 goto open_err_free_mem;
4623         }
4624
4625         if (irq_re_init) {
4626                 bnxt_init_napi(bp);
4627                 rc = bnxt_request_irq(bp);
4628                 if (rc) {
4629                         netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
4630                         goto open_err;
4631                 }
4632         }
4633
4634         bnxt_enable_napi(bp);
4635
4636         rc = bnxt_init_nic(bp, irq_re_init);
4637         if (rc) {
4638                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
4639                 goto open_err;
4640         }
4641
4642         if (link_re_init) {
4643                 rc = bnxt_update_phy_setting(bp);
4644                 if (rc)
4645                         netdev_warn(bp->dev, "failed to update phy settings\n");
4646         }
4647
4648         if (irq_re_init) {
4649 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
4650                 vxlan_get_rx_port(bp->dev);
4651 #endif
4652                 if (!bnxt_hwrm_tunnel_dst_port_alloc(
4653                                 bp, htons(0x17c1),
4654                                 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE))
4655                         bp->nge_port_cnt = 1;
4656         }
4657
4658         set_bit(BNXT_STATE_OPEN, &bp->state);
4659         bnxt_enable_int(bp);
4660         /* Enable TX queues */
4661         bnxt_tx_enable(bp);
4662         mod_timer(&bp->timer, jiffies + bp->current_interval);
4663         bnxt_update_link(bp, true);
4664
4665         return 0;
4666
4667 open_err:
4668         bnxt_disable_napi(bp);
4669         bnxt_del_napi(bp);
4670
4671 open_err_free_mem:
4672         bnxt_free_skbs(bp);
4673         bnxt_free_irq(bp);
4674         bnxt_free_mem(bp, true);
4675         return rc;
4676 }
4677
4678 /* rtnl_lock held */
4679 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4680 {
4681         int rc = 0;
4682
4683         rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
4684         if (rc) {
4685                 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
4686                 dev_close(bp->dev);
4687         }
4688         return rc;
4689 }
4690
4691 static int bnxt_open(struct net_device *dev)
4692 {
4693         struct bnxt *bp = netdev_priv(dev);
4694         int rc = 0;
4695
4696         rc = bnxt_hwrm_func_reset(bp);
4697         if (rc) {
4698                 netdev_err(bp->dev, "hwrm chip reset failure rc: %x\n",
4699                            rc);
4700                 rc = -1;
4701                 return rc;
4702         }
4703         return __bnxt_open_nic(bp, true, true);
4704 }
4705
4706 static void bnxt_disable_int_sync(struct bnxt *bp)
4707 {
4708         int i;
4709
4710         atomic_inc(&bp->intr_sem);
4711         if (!netif_running(bp->dev))
4712                 return;
4713
4714         bnxt_disable_int(bp);
4715         for (i = 0; i < bp->cp_nr_rings; i++)
4716                 synchronize_irq(bp->irq_tbl[i].vector);
4717 }
4718
4719 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4720 {
4721         int rc = 0;
4722
4723 #ifdef CONFIG_BNXT_SRIOV
4724         if (bp->sriov_cfg) {
4725                 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
4726                                                       !bp->sriov_cfg,
4727                                                       BNXT_SRIOV_CFG_WAIT_TMO);
4728                 if (rc)
4729                         netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
4730         }
4731 #endif
4732         /* Change device state to avoid TX queue wake up's */
4733         bnxt_tx_disable(bp);
4734
4735         clear_bit(BNXT_STATE_OPEN, &bp->state);
4736         smp_mb__after_atomic();
4737         while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state))
4738                 msleep(20);
4739
4740         /* Flush rings before disabling interrupts */
4741         bnxt_shutdown_nic(bp, irq_re_init);
4742
4743         /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
4744
4745         bnxt_disable_napi(bp);
4746         bnxt_disable_int_sync(bp);
4747         del_timer_sync(&bp->timer);
4748         bnxt_free_skbs(bp);
4749
4750         if (irq_re_init) {
4751                 bnxt_free_irq(bp);
4752                 bnxt_del_napi(bp);
4753         }
4754         bnxt_free_mem(bp, irq_re_init);
4755         return rc;
4756 }
4757
4758 static int bnxt_close(struct net_device *dev)
4759 {
4760         struct bnxt *bp = netdev_priv(dev);
4761
4762         bnxt_close_nic(bp, true, true);
4763         return 0;
4764 }
4765
4766 /* rtnl_lock held */
4767 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4768 {
4769         switch (cmd) {
4770         case SIOCGMIIPHY:
4771                 /* fallthru */
4772         case SIOCGMIIREG: {
4773                 if (!netif_running(dev))
4774                         return -EAGAIN;
4775
4776                 return 0;
4777         }
4778
4779         case SIOCSMIIREG:
4780                 if (!netif_running(dev))
4781                         return -EAGAIN;
4782
4783                 return 0;
4784
4785         default:
4786                 /* do nothing */
4787                 break;
4788         }
4789         return -EOPNOTSUPP;
4790 }
4791
4792 static struct rtnl_link_stats64 *
4793 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4794 {
4795         u32 i;
4796         struct bnxt *bp = netdev_priv(dev);
4797
4798         memset(stats, 0, sizeof(struct rtnl_link_stats64));
4799
4800         if (!bp->bnapi)
4801                 return stats;
4802
4803         /* TODO check if we need to synchronize with bnxt_close path */
4804         for (i = 0; i < bp->cp_nr_rings; i++) {
4805                 struct bnxt_napi *bnapi = bp->bnapi[i];
4806                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4807                 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
4808
4809                 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
4810                 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
4811                 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
4812
4813                 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
4814                 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
4815                 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
4816
4817                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
4818                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
4819                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
4820
4821                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
4822                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
4823                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
4824
4825                 stats->rx_missed_errors +=
4826                         le64_to_cpu(hw_stats->rx_discard_pkts);
4827
4828                 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
4829
4830                 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
4831         }
4832
4833         return stats;
4834 }
4835
4836 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
4837 {
4838         struct net_device *dev = bp->dev;
4839         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4840         struct netdev_hw_addr *ha;
4841         u8 *haddr;
4842         int mc_count = 0;
4843         bool update = false;
4844         int off = 0;
4845
4846         netdev_for_each_mc_addr(ha, dev) {
4847                 if (mc_count >= BNXT_MAX_MC_ADDRS) {
4848                         *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4849                         vnic->mc_list_count = 0;
4850                         return false;
4851                 }
4852                 haddr = ha->addr;
4853                 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
4854                         memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
4855                         update = true;
4856                 }
4857                 off += ETH_ALEN;
4858                 mc_count++;
4859         }
4860         if (mc_count)
4861                 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
4862
4863         if (mc_count != vnic->mc_list_count) {
4864                 vnic->mc_list_count = mc_count;
4865                 update = true;
4866         }
4867         return update;
4868 }
4869
4870 static bool bnxt_uc_list_updated(struct bnxt *bp)
4871 {
4872         struct net_device *dev = bp->dev;
4873         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4874         struct netdev_hw_addr *ha;
4875         int off = 0;
4876
4877         if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
4878                 return true;
4879
4880         netdev_for_each_uc_addr(ha, dev) {
4881                 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
4882                         return true;
4883
4884                 off += ETH_ALEN;
4885         }
4886         return false;
4887 }
4888
4889 static void bnxt_set_rx_mode(struct net_device *dev)
4890 {
4891         struct bnxt *bp = netdev_priv(dev);
4892         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4893         u32 mask = vnic->rx_mask;
4894         bool mc_update = false;
4895         bool uc_update;
4896
4897         if (!netif_running(dev))
4898                 return;
4899
4900         mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
4901                   CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
4902                   CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
4903
4904         /* Only allow PF to be in promiscuous mode */
4905         if ((dev->flags & IFF_PROMISC) && BNXT_PF(bp))
4906                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4907
4908         uc_update = bnxt_uc_list_updated(bp);
4909
4910         if (dev->flags & IFF_ALLMULTI) {
4911                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4912                 vnic->mc_list_count = 0;
4913         } else {
4914                 mc_update = bnxt_mc_list_updated(bp, &mask);
4915         }
4916
4917         if (mask != vnic->rx_mask || uc_update || mc_update) {
4918                 vnic->rx_mask = mask;
4919
4920                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
4921                 schedule_work(&bp->sp_task);
4922         }
4923 }
4924
4925 static int bnxt_cfg_rx_mode(struct bnxt *bp)
4926 {
4927         struct net_device *dev = bp->dev;
4928         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4929         struct netdev_hw_addr *ha;
4930         int i, off = 0, rc;
4931         bool uc_update;
4932
4933         netif_addr_lock_bh(dev);
4934         uc_update = bnxt_uc_list_updated(bp);
4935         netif_addr_unlock_bh(dev);
4936
4937         if (!uc_update)
4938                 goto skip_uc;
4939
4940         mutex_lock(&bp->hwrm_cmd_lock);
4941         for (i = 1; i < vnic->uc_filter_count; i++) {
4942                 struct hwrm_cfa_l2_filter_free_input req = {0};
4943
4944                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
4945                                        -1);
4946
4947                 req.l2_filter_id = vnic->fw_l2_filter_id[i];
4948
4949                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4950                                         HWRM_CMD_TIMEOUT);
4951         }
4952         mutex_unlock(&bp->hwrm_cmd_lock);
4953
4954         vnic->uc_filter_count = 1;
4955
4956         netif_addr_lock_bh(dev);
4957         if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
4958                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4959         } else {
4960                 netdev_for_each_uc_addr(ha, dev) {
4961                         memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
4962                         off += ETH_ALEN;
4963                         vnic->uc_filter_count++;
4964                 }
4965         }
4966         netif_addr_unlock_bh(dev);
4967
4968         for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
4969                 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
4970                 if (rc) {
4971                         netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
4972                                    rc);
4973                         vnic->uc_filter_count = i;
4974                         return rc;
4975                 }
4976         }
4977
4978 skip_uc:
4979         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
4980         if (rc)
4981                 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
4982                            rc);
4983
4984         return rc;
4985 }
4986
4987 static bool bnxt_rfs_capable(struct bnxt *bp)
4988 {
4989 #ifdef CONFIG_RFS_ACCEL
4990         struct bnxt_pf_info *pf = &bp->pf;
4991         int vnics;
4992
4993         if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_MSIX_CAP))
4994                 return false;
4995
4996         vnics = 1 + bp->rx_nr_rings;
4997         if (vnics > pf->max_rsscos_ctxs || vnics > pf->max_vnics)
4998                 return false;
4999
5000         return true;
5001 #else
5002         return false;
5003 #endif
5004 }
5005
5006 static netdev_features_t bnxt_fix_features(struct net_device *dev,
5007                                            netdev_features_t features)
5008 {
5009         struct bnxt *bp = netdev_priv(dev);
5010
5011         if (!bnxt_rfs_capable(bp))
5012                 features &= ~NETIF_F_NTUPLE;
5013         return features;
5014 }
5015
5016 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
5017 {
5018         struct bnxt *bp = netdev_priv(dev);
5019         u32 flags = bp->flags;
5020         u32 changes;
5021         int rc = 0;
5022         bool re_init = false;
5023         bool update_tpa = false;
5024
5025         flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
5026         if ((features & NETIF_F_GRO) && (bp->pdev->revision > 0))
5027                 flags |= BNXT_FLAG_GRO;
5028         if (features & NETIF_F_LRO)
5029                 flags |= BNXT_FLAG_LRO;
5030
5031         if (features & NETIF_F_HW_VLAN_CTAG_RX)
5032                 flags |= BNXT_FLAG_STRIP_VLAN;
5033
5034         if (features & NETIF_F_NTUPLE)
5035                 flags |= BNXT_FLAG_RFS;
5036
5037         changes = flags ^ bp->flags;
5038         if (changes & BNXT_FLAG_TPA) {
5039                 update_tpa = true;
5040                 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
5041                     (flags & BNXT_FLAG_TPA) == 0)
5042                         re_init = true;
5043         }
5044
5045         if (changes & ~BNXT_FLAG_TPA)
5046                 re_init = true;
5047
5048         if (flags != bp->flags) {
5049                 u32 old_flags = bp->flags;
5050
5051                 bp->flags = flags;
5052
5053                 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
5054                         if (update_tpa)
5055                                 bnxt_set_ring_params(bp);
5056                         return rc;
5057                 }
5058
5059                 if (re_init) {
5060                         bnxt_close_nic(bp, false, false);
5061                         if (update_tpa)
5062                                 bnxt_set_ring_params(bp);
5063
5064                         return bnxt_open_nic(bp, false, false);
5065                 }
5066                 if (update_tpa) {
5067                         rc = bnxt_set_tpa(bp,
5068                                           (flags & BNXT_FLAG_TPA) ?
5069                                           true : false);
5070                         if (rc)
5071                                 bp->flags = old_flags;
5072                 }
5073         }
5074         return rc;
5075 }
5076
5077 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
5078 {
5079         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
5080         int i = bnapi->index;
5081
5082         if (!txr)
5083                 return;
5084
5085         netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
5086                     i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
5087                     txr->tx_cons);
5088 }
5089
5090 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
5091 {
5092         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
5093         int i = bnapi->index;
5094
5095         if (!rxr)
5096                 return;
5097
5098         netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
5099                     i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
5100                     rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
5101                     rxr->rx_sw_agg_prod);
5102 }
5103
5104 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
5105 {
5106         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5107         int i = bnapi->index;
5108
5109         netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
5110                     i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
5111 }
5112
5113 static void bnxt_dbg_dump_states(struct bnxt *bp)
5114 {
5115         int i;
5116         struct bnxt_napi *bnapi;
5117
5118         for (i = 0; i < bp->cp_nr_rings; i++) {
5119                 bnapi = bp->bnapi[i];
5120                 if (netif_msg_drv(bp)) {
5121                         bnxt_dump_tx_sw_state(bnapi);
5122                         bnxt_dump_rx_sw_state(bnapi);
5123                         bnxt_dump_cp_sw_state(bnapi);
5124                 }
5125         }
5126 }
5127
5128 static void bnxt_reset_task(struct bnxt *bp)
5129 {
5130         bnxt_dbg_dump_states(bp);
5131         if (netif_running(bp->dev)) {
5132                 bnxt_close_nic(bp, false, false);
5133                 bnxt_open_nic(bp, false, false);
5134         }
5135 }
5136
5137 static void bnxt_tx_timeout(struct net_device *dev)
5138 {
5139         struct bnxt *bp = netdev_priv(dev);
5140
5141         netdev_err(bp->dev,  "TX timeout detected, starting reset task!\n");
5142         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
5143         schedule_work(&bp->sp_task);
5144 }
5145
5146 #ifdef CONFIG_NET_POLL_CONTROLLER
5147 static void bnxt_poll_controller(struct net_device *dev)
5148 {
5149         struct bnxt *bp = netdev_priv(dev);
5150         int i;
5151
5152         for (i = 0; i < bp->cp_nr_rings; i++) {
5153                 struct bnxt_irq *irq = &bp->irq_tbl[i];
5154
5155                 disable_irq(irq->vector);
5156                 irq->handler(irq->vector, bp->bnapi[i]);
5157                 enable_irq(irq->vector);
5158         }
5159 }
5160 #endif
5161
5162 static void bnxt_timer(unsigned long data)
5163 {
5164         struct bnxt *bp = (struct bnxt *)data;
5165         struct net_device *dev = bp->dev;
5166
5167         if (!netif_running(dev))
5168                 return;
5169
5170         if (atomic_read(&bp->intr_sem) != 0)
5171                 goto bnxt_restart_timer;
5172
5173 bnxt_restart_timer:
5174         mod_timer(&bp->timer, jiffies + bp->current_interval);
5175 }
5176
5177 static void bnxt_cfg_ntp_filters(struct bnxt *);
5178
5179 static void bnxt_sp_task(struct work_struct *work)
5180 {
5181         struct bnxt *bp = container_of(work, struct bnxt, sp_task);
5182         int rc;
5183
5184         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5185         smp_mb__after_atomic();
5186         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
5187                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5188                 return;
5189         }
5190
5191         if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
5192                 bnxt_cfg_rx_mode(bp);
5193
5194         if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
5195                 bnxt_cfg_ntp_filters(bp);
5196         if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
5197                 rc = bnxt_update_link(bp, true);
5198                 if (rc)
5199                         netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
5200                                    rc);
5201         }
5202         if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
5203                 bnxt_hwrm_exec_fwd_req(bp);
5204         if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
5205                 bnxt_hwrm_tunnel_dst_port_alloc(
5206                         bp, bp->vxlan_port,
5207                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5208         }
5209         if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
5210                 bnxt_hwrm_tunnel_dst_port_free(
5211                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5212         }
5213         if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) {
5214                 /* bnxt_reset_task() calls bnxt_close_nic() which waits
5215                  * for BNXT_STATE_IN_SP_TASK to clear.
5216                  */
5217                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5218                 rtnl_lock();
5219                 bnxt_reset_task(bp);
5220                 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5221                 rtnl_unlock();
5222         }
5223
5224         smp_mb__before_atomic();
5225         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5226 }
5227
5228 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
5229 {
5230         int rc;
5231         struct bnxt *bp = netdev_priv(dev);
5232
5233         SET_NETDEV_DEV(dev, &pdev->dev);
5234
5235         /* enable device (incl. PCI PM wakeup), and bus-mastering */
5236         rc = pci_enable_device(pdev);
5237         if (rc) {
5238                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
5239                 goto init_err;
5240         }
5241
5242         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5243                 dev_err(&pdev->dev,
5244                         "Cannot find PCI device base address, aborting\n");
5245                 rc = -ENODEV;
5246                 goto init_err_disable;
5247         }
5248
5249         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5250         if (rc) {
5251                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
5252                 goto init_err_disable;
5253         }
5254
5255         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
5256             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
5257                 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
5258                 goto init_err_disable;
5259         }
5260
5261         pci_set_master(pdev);
5262
5263         bp->dev = dev;
5264         bp->pdev = pdev;
5265
5266         bp->bar0 = pci_ioremap_bar(pdev, 0);
5267         if (!bp->bar0) {
5268                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
5269                 rc = -ENOMEM;
5270                 goto init_err_release;
5271         }
5272
5273         bp->bar1 = pci_ioremap_bar(pdev, 2);
5274         if (!bp->bar1) {
5275                 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
5276                 rc = -ENOMEM;
5277                 goto init_err_release;
5278         }
5279
5280         bp->bar2 = pci_ioremap_bar(pdev, 4);
5281         if (!bp->bar2) {
5282                 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
5283                 rc = -ENOMEM;
5284                 goto init_err_release;
5285         }
5286
5287         INIT_WORK(&bp->sp_task, bnxt_sp_task);
5288
5289         spin_lock_init(&bp->ntp_fltr_lock);
5290
5291         bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
5292         bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
5293
5294         bp->coal_ticks = BNXT_USEC_TO_COAL_TIMER(4);
5295         bp->coal_bufs = 20;
5296         bp->coal_ticks_irq = BNXT_USEC_TO_COAL_TIMER(1);
5297         bp->coal_bufs_irq = 2;
5298
5299         init_timer(&bp->timer);
5300         bp->timer.data = (unsigned long)bp;
5301         bp->timer.function = bnxt_timer;
5302         bp->current_interval = BNXT_TIMER_INTERVAL;
5303
5304         clear_bit(BNXT_STATE_OPEN, &bp->state);
5305
5306         return 0;
5307
5308 init_err_release:
5309         if (bp->bar2) {
5310                 pci_iounmap(pdev, bp->bar2);
5311                 bp->bar2 = NULL;
5312         }
5313
5314         if (bp->bar1) {
5315                 pci_iounmap(pdev, bp->bar1);
5316                 bp->bar1 = NULL;
5317         }
5318
5319         if (bp->bar0) {
5320                 pci_iounmap(pdev, bp->bar0);
5321                 bp->bar0 = NULL;
5322         }
5323
5324         pci_release_regions(pdev);
5325
5326 init_err_disable:
5327         pci_disable_device(pdev);
5328
5329 init_err:
5330         return rc;
5331 }
5332
5333 /* rtnl_lock held */
5334 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
5335 {
5336         struct sockaddr *addr = p;
5337         struct bnxt *bp = netdev_priv(dev);
5338         int rc = 0;
5339
5340         if (!is_valid_ether_addr(addr->sa_data))
5341                 return -EADDRNOTAVAIL;
5342
5343 #ifdef CONFIG_BNXT_SRIOV
5344         if (BNXT_VF(bp) && is_valid_ether_addr(bp->vf.mac_addr))
5345                 return -EADDRNOTAVAIL;
5346 #endif
5347
5348         if (ether_addr_equal(addr->sa_data, dev->dev_addr))
5349                 return 0;
5350
5351         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5352         if (netif_running(dev)) {
5353                 bnxt_close_nic(bp, false, false);
5354                 rc = bnxt_open_nic(bp, false, false);
5355         }
5356
5357         return rc;
5358 }
5359
5360 /* rtnl_lock held */
5361 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
5362 {
5363         struct bnxt *bp = netdev_priv(dev);
5364
5365         if (new_mtu < 60 || new_mtu > 9000)
5366                 return -EINVAL;
5367
5368         if (netif_running(dev))
5369                 bnxt_close_nic(bp, false, false);
5370
5371         dev->mtu = new_mtu;
5372         bnxt_set_ring_params(bp);
5373
5374         if (netif_running(dev))
5375                 return bnxt_open_nic(bp, false, false);
5376
5377         return 0;
5378 }
5379
5380 static int bnxt_setup_tc(struct net_device *dev, u8 tc)
5381 {
5382         struct bnxt *bp = netdev_priv(dev);
5383
5384         if (tc > bp->max_tc) {
5385                 netdev_err(dev, "too many traffic classes requested: %d Max supported is %d\n",
5386                            tc, bp->max_tc);
5387                 return -EINVAL;
5388         }
5389
5390         if (netdev_get_num_tc(dev) == tc)
5391                 return 0;
5392
5393         if (tc) {
5394                 int max_rx_rings, max_tx_rings, rc;
5395                 bool sh = false;
5396
5397                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5398                         sh = true;
5399
5400                 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
5401                 if (rc || bp->tx_nr_rings_per_tc * tc > max_tx_rings)
5402                         return -ENOMEM;
5403         }
5404
5405         /* Needs to close the device and do hw resource re-allocations */
5406         if (netif_running(bp->dev))
5407                 bnxt_close_nic(bp, true, false);
5408
5409         if (tc) {
5410                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
5411                 netdev_set_num_tc(dev, tc);
5412         } else {
5413                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
5414                 netdev_reset_tc(dev);
5415         }
5416         bp->cp_nr_rings = max_t(int, bp->tx_nr_rings, bp->rx_nr_rings);
5417         bp->num_stat_ctxs = bp->cp_nr_rings;
5418
5419         if (netif_running(bp->dev))
5420                 return bnxt_open_nic(bp, true, false);
5421
5422         return 0;
5423 }
5424
5425 #ifdef CONFIG_RFS_ACCEL
5426 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
5427                             struct bnxt_ntuple_filter *f2)
5428 {
5429         struct flow_keys *keys1 = &f1->fkeys;
5430         struct flow_keys *keys2 = &f2->fkeys;
5431
5432         if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
5433             keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
5434             keys1->ports.ports == keys2->ports.ports &&
5435             keys1->basic.ip_proto == keys2->basic.ip_proto &&
5436             keys1->basic.n_proto == keys2->basic.n_proto &&
5437             ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr))
5438                 return true;
5439
5440         return false;
5441 }
5442
5443 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
5444                               u16 rxq_index, u32 flow_id)
5445 {
5446         struct bnxt *bp = netdev_priv(dev);
5447         struct bnxt_ntuple_filter *fltr, *new_fltr;
5448         struct flow_keys *fkeys;
5449         struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
5450         int rc = 0, idx, bit_id;
5451         struct hlist_head *head;
5452
5453         if (skb->encapsulation)
5454                 return -EPROTONOSUPPORT;
5455
5456         new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
5457         if (!new_fltr)
5458                 return -ENOMEM;
5459
5460         fkeys = &new_fltr->fkeys;
5461         if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
5462                 rc = -EPROTONOSUPPORT;
5463                 goto err_free;
5464         }
5465
5466         if ((fkeys->basic.n_proto != htons(ETH_P_IP)) ||
5467             ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
5468              (fkeys->basic.ip_proto != IPPROTO_UDP))) {
5469                 rc = -EPROTONOSUPPORT;
5470                 goto err_free;
5471         }
5472
5473         memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
5474
5475         idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
5476         head = &bp->ntp_fltr_hash_tbl[idx];
5477         rcu_read_lock();
5478         hlist_for_each_entry_rcu(fltr, head, hash) {
5479                 if (bnxt_fltr_match(fltr, new_fltr)) {
5480                         rcu_read_unlock();
5481                         rc = 0;
5482                         goto err_free;
5483                 }
5484         }
5485         rcu_read_unlock();
5486
5487         spin_lock_bh(&bp->ntp_fltr_lock);
5488         bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
5489                                          BNXT_NTP_FLTR_MAX_FLTR, 0);
5490         if (bit_id < 0) {
5491                 spin_unlock_bh(&bp->ntp_fltr_lock);
5492                 rc = -ENOMEM;
5493                 goto err_free;
5494         }
5495
5496         new_fltr->sw_id = (u16)bit_id;
5497         new_fltr->flow_id = flow_id;
5498         new_fltr->rxq = rxq_index;
5499         hlist_add_head_rcu(&new_fltr->hash, head);
5500         bp->ntp_fltr_count++;
5501         spin_unlock_bh(&bp->ntp_fltr_lock);
5502
5503         set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
5504         schedule_work(&bp->sp_task);
5505
5506         return new_fltr->sw_id;
5507
5508 err_free:
5509         kfree(new_fltr);
5510         return rc;
5511 }
5512
5513 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
5514 {
5515         int i;
5516
5517         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
5518                 struct hlist_head *head;
5519                 struct hlist_node *tmp;
5520                 struct bnxt_ntuple_filter *fltr;
5521                 int rc;
5522
5523                 head = &bp->ntp_fltr_hash_tbl[i];
5524                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
5525                         bool del = false;
5526
5527                         if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
5528                                 if (rps_may_expire_flow(bp->dev, fltr->rxq,
5529                                                         fltr->flow_id,
5530                                                         fltr->sw_id)) {
5531                                         bnxt_hwrm_cfa_ntuple_filter_free(bp,
5532                                                                          fltr);
5533                                         del = true;
5534                                 }
5535                         } else {
5536                                 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
5537                                                                        fltr);
5538                                 if (rc)
5539                                         del = true;
5540                                 else
5541                                         set_bit(BNXT_FLTR_VALID, &fltr->state);
5542                         }
5543
5544                         if (del) {
5545                                 spin_lock_bh(&bp->ntp_fltr_lock);
5546                                 hlist_del_rcu(&fltr->hash);
5547                                 bp->ntp_fltr_count--;
5548                                 spin_unlock_bh(&bp->ntp_fltr_lock);
5549                                 synchronize_rcu();
5550                                 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
5551                                 kfree(fltr);
5552                         }
5553                 }
5554         }
5555 }
5556
5557 #else
5558
5559 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
5560 {
5561 }
5562
5563 #endif /* CONFIG_RFS_ACCEL */
5564
5565 static void bnxt_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
5566                                 __be16 port)
5567 {
5568         struct bnxt *bp = netdev_priv(dev);
5569
5570         if (!netif_running(dev))
5571                 return;
5572
5573         if (sa_family != AF_INET6 && sa_family != AF_INET)
5574                 return;
5575
5576         if (bp->vxlan_port_cnt && bp->vxlan_port != port)
5577                 return;
5578
5579         bp->vxlan_port_cnt++;
5580         if (bp->vxlan_port_cnt == 1) {
5581                 bp->vxlan_port = port;
5582                 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
5583                 schedule_work(&bp->sp_task);
5584         }
5585 }
5586
5587 static void bnxt_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
5588                                 __be16 port)
5589 {
5590         struct bnxt *bp = netdev_priv(dev);
5591
5592         if (!netif_running(dev))
5593                 return;
5594
5595         if (sa_family != AF_INET6 && sa_family != AF_INET)
5596                 return;
5597
5598         if (bp->vxlan_port_cnt && bp->vxlan_port == port) {
5599                 bp->vxlan_port_cnt--;
5600
5601                 if (bp->vxlan_port_cnt == 0) {
5602                         set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
5603                         schedule_work(&bp->sp_task);
5604                 }
5605         }
5606 }
5607
5608 static const struct net_device_ops bnxt_netdev_ops = {
5609         .ndo_open               = bnxt_open,
5610         .ndo_start_xmit         = bnxt_start_xmit,
5611         .ndo_stop               = bnxt_close,
5612         .ndo_get_stats64        = bnxt_get_stats64,
5613         .ndo_set_rx_mode        = bnxt_set_rx_mode,
5614         .ndo_do_ioctl           = bnxt_ioctl,
5615         .ndo_validate_addr      = eth_validate_addr,
5616         .ndo_set_mac_address    = bnxt_change_mac_addr,
5617         .ndo_change_mtu         = bnxt_change_mtu,
5618         .ndo_fix_features       = bnxt_fix_features,
5619         .ndo_set_features       = bnxt_set_features,
5620         .ndo_tx_timeout         = bnxt_tx_timeout,
5621 #ifdef CONFIG_BNXT_SRIOV
5622         .ndo_get_vf_config      = bnxt_get_vf_config,
5623         .ndo_set_vf_mac         = bnxt_set_vf_mac,
5624         .ndo_set_vf_vlan        = bnxt_set_vf_vlan,
5625         .ndo_set_vf_rate        = bnxt_set_vf_bw,
5626         .ndo_set_vf_link_state  = bnxt_set_vf_link_state,
5627         .ndo_set_vf_spoofchk    = bnxt_set_vf_spoofchk,
5628 #endif
5629 #ifdef CONFIG_NET_POLL_CONTROLLER
5630         .ndo_poll_controller    = bnxt_poll_controller,
5631 #endif
5632         .ndo_setup_tc           = bnxt_setup_tc,
5633 #ifdef CONFIG_RFS_ACCEL
5634         .ndo_rx_flow_steer      = bnxt_rx_flow_steer,
5635 #endif
5636         .ndo_add_vxlan_port     = bnxt_add_vxlan_port,
5637         .ndo_del_vxlan_port     = bnxt_del_vxlan_port,
5638 #ifdef CONFIG_NET_RX_BUSY_POLL
5639         .ndo_busy_poll          = bnxt_busy_poll,
5640 #endif
5641 };
5642
5643 static void bnxt_remove_one(struct pci_dev *pdev)
5644 {
5645         struct net_device *dev = pci_get_drvdata(pdev);
5646         struct bnxt *bp = netdev_priv(dev);
5647
5648         if (BNXT_PF(bp))
5649                 bnxt_sriov_disable(bp);
5650
5651         unregister_netdev(dev);
5652         cancel_work_sync(&bp->sp_task);
5653         bp->sp_event = 0;
5654
5655         bnxt_hwrm_func_drv_unrgtr(bp);
5656         bnxt_free_hwrm_resources(bp);
5657         pci_iounmap(pdev, bp->bar2);
5658         pci_iounmap(pdev, bp->bar1);
5659         pci_iounmap(pdev, bp->bar0);
5660         free_netdev(dev);
5661
5662         pci_release_regions(pdev);
5663         pci_disable_device(pdev);
5664 }
5665
5666 static int bnxt_probe_phy(struct bnxt *bp)
5667 {
5668         int rc = 0;
5669         struct bnxt_link_info *link_info = &bp->link_info;
5670         char phy_ver[PHY_VER_STR_LEN];
5671
5672         rc = bnxt_update_link(bp, false);
5673         if (rc) {
5674                 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
5675                            rc);
5676                 return rc;
5677         }
5678
5679         /*initialize the ethool setting copy with NVM settings */
5680         if (BNXT_AUTO_MODE(link_info->auto_mode)) {
5681                 link_info->autoneg = BNXT_AUTONEG_SPEED |
5682                                      BNXT_AUTONEG_FLOW_CTRL;
5683                 link_info->advertising = link_info->auto_link_speeds;
5684                 link_info->req_flow_ctrl = link_info->auto_pause_setting;
5685         } else {
5686                 link_info->req_link_speed = link_info->force_link_speed;
5687                 link_info->req_duplex = link_info->duplex_setting;
5688                 link_info->req_flow_ctrl = link_info->force_pause_setting;
5689         }
5690         snprintf(phy_ver, PHY_VER_STR_LEN, " ph %d.%d.%d",
5691                  link_info->phy_ver[0],
5692                  link_info->phy_ver[1],
5693                  link_info->phy_ver[2]);
5694         strcat(bp->fw_ver_str, phy_ver);
5695         return rc;
5696 }
5697
5698 static int bnxt_get_max_irq(struct pci_dev *pdev)
5699 {
5700         u16 ctrl;
5701
5702         if (!pdev->msix_cap)
5703                 return 1;
5704
5705         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
5706         return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
5707 }
5708
5709 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
5710                                 int *max_cp)
5711 {
5712         int max_ring_grps = 0;
5713
5714 #ifdef CONFIG_BNXT_SRIOV
5715         if (!BNXT_PF(bp)) {
5716                 *max_tx = bp->vf.max_tx_rings;
5717                 *max_rx = bp->vf.max_rx_rings;
5718                 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
5719                 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
5720                 max_ring_grps = bp->vf.max_hw_ring_grps;
5721         } else
5722 #endif
5723         {
5724                 *max_tx = bp->pf.max_tx_rings;
5725                 *max_rx = bp->pf.max_rx_rings;
5726                 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
5727                 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
5728                 max_ring_grps = bp->pf.max_hw_ring_grps;
5729         }
5730
5731         if (bp->flags & BNXT_FLAG_AGG_RINGS)
5732                 *max_rx >>= 1;
5733         *max_rx = min_t(int, *max_rx, max_ring_grps);
5734 }
5735
5736 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
5737 {
5738         int rx, tx, cp;
5739
5740         _bnxt_get_max_rings(bp, &rx, &tx, &cp);
5741         if (!rx || !tx || !cp)
5742                 return -ENOMEM;
5743
5744         *max_rx = rx;
5745         *max_tx = tx;
5746         return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
5747 }
5748
5749 static int bnxt_set_dflt_rings(struct bnxt *bp)
5750 {
5751         int dflt_rings, max_rx_rings, max_tx_rings, rc;
5752         bool sh = true;
5753
5754         if (sh)
5755                 bp->flags |= BNXT_FLAG_SHARED_RINGS;
5756         dflt_rings = netif_get_num_default_rss_queues();
5757         rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
5758         if (rc)
5759                 return rc;
5760         bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
5761         bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
5762         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
5763         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
5764                                bp->tx_nr_rings + bp->rx_nr_rings;
5765         bp->num_stat_ctxs = bp->cp_nr_rings;
5766         return rc;
5767 }
5768
5769 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5770 {
5771         static int version_printed;
5772         struct net_device *dev;
5773         struct bnxt *bp;
5774         int rc, max_irqs;
5775
5776         if (version_printed++ == 0)
5777                 pr_info("%s", version);
5778
5779         max_irqs = bnxt_get_max_irq(pdev);
5780         dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
5781         if (!dev)
5782                 return -ENOMEM;
5783
5784         bp = netdev_priv(dev);
5785
5786         if (bnxt_vf_pciid(ent->driver_data))
5787                 bp->flags |= BNXT_FLAG_VF;
5788
5789         if (pdev->msix_cap)
5790                 bp->flags |= BNXT_FLAG_MSIX_CAP;
5791
5792         rc = bnxt_init_board(pdev, dev);
5793         if (rc < 0)
5794                 goto init_err_free;
5795
5796         dev->netdev_ops = &bnxt_netdev_ops;
5797         dev->watchdog_timeo = BNXT_TX_TIMEOUT;
5798         dev->ethtool_ops = &bnxt_ethtool_ops;
5799
5800         pci_set_drvdata(pdev, dev);
5801
5802         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
5803                            NETIF_F_TSO | NETIF_F_TSO6 |
5804                            NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
5805                            NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT |
5806                            NETIF_F_RXHASH |
5807                            NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO;
5808
5809         dev->hw_enc_features =
5810                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
5811                         NETIF_F_TSO | NETIF_F_TSO6 |
5812                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
5813                         NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
5814         dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
5815         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
5816                             NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
5817         dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
5818         dev->priv_flags |= IFF_UNICAST_FLT;
5819
5820 #ifdef CONFIG_BNXT_SRIOV
5821         init_waitqueue_head(&bp->sriov_cfg_wait);
5822 #endif
5823         rc = bnxt_alloc_hwrm_resources(bp);
5824         if (rc)
5825                 goto init_err;
5826
5827         mutex_init(&bp->hwrm_cmd_lock);
5828         bnxt_hwrm_ver_get(bp);
5829
5830         rc = bnxt_hwrm_func_drv_rgtr(bp);
5831         if (rc)
5832                 goto init_err;
5833
5834         /* Get the MAX capabilities for this function */
5835         rc = bnxt_hwrm_func_qcaps(bp);
5836         if (rc) {
5837                 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
5838                            rc);
5839                 rc = -1;
5840                 goto init_err;
5841         }
5842
5843         rc = bnxt_hwrm_queue_qportcfg(bp);
5844         if (rc) {
5845                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
5846                            rc);
5847                 rc = -1;
5848                 goto init_err;
5849         }
5850
5851         bnxt_set_tpa_flags(bp);
5852         bnxt_set_ring_params(bp);
5853         if (BNXT_PF(bp))
5854                 bp->pf.max_irqs = max_irqs;
5855 #if defined(CONFIG_BNXT_SRIOV)
5856         else
5857                 bp->vf.max_irqs = max_irqs;
5858 #endif
5859         bnxt_set_dflt_rings(bp);
5860
5861         if (BNXT_PF(bp)) {
5862                 dev->hw_features |= NETIF_F_NTUPLE;
5863                 if (bnxt_rfs_capable(bp)) {
5864                         bp->flags |= BNXT_FLAG_RFS;
5865                         dev->features |= NETIF_F_NTUPLE;
5866                 }
5867         }
5868
5869         if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
5870                 bp->flags |= BNXT_FLAG_STRIP_VLAN;
5871
5872         rc = bnxt_probe_phy(bp);
5873         if (rc)
5874                 goto init_err;
5875
5876         rc = register_netdev(dev);
5877         if (rc)
5878                 goto init_err;
5879
5880         netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
5881                     board_info[ent->driver_data].name,
5882                     (long)pci_resource_start(pdev, 0), dev->dev_addr);
5883
5884         return 0;
5885
5886 init_err:
5887         pci_iounmap(pdev, bp->bar0);
5888         pci_release_regions(pdev);
5889         pci_disable_device(pdev);
5890
5891 init_err_free:
5892         free_netdev(dev);
5893         return rc;
5894 }
5895
5896 static struct pci_driver bnxt_pci_driver = {
5897         .name           = DRV_MODULE_NAME,
5898         .id_table       = bnxt_pci_tbl,
5899         .probe          = bnxt_init_one,
5900         .remove         = bnxt_remove_one,
5901 #if defined(CONFIG_BNXT_SRIOV)
5902         .sriov_configure = bnxt_sriov_configure,
5903 #endif
5904 };
5905
5906 module_pci_driver(bnxt_pci_driver);