drivers/net/ethernet/emulex/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2013 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 #include <linux/module.h>
  19 #include "be.h"
  20 #include "be_cmds.h"
  21
  22 static struct be_cmd_priv_map cmd_priv_map[] = {
  23         {
  24                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
  25                 CMD_SUBSYSTEM_ETH,
  26                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  27                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  28         },
  29         {
  30                 OPCODE_COMMON_GET_FLOW_CONTROL,
  31                 CMD_SUBSYSTEM_COMMON,
  32                 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
  33                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  34         },
  35         {
  36                 OPCODE_COMMON_SET_FLOW_CONTROL,
  37                 CMD_SUBSYSTEM_COMMON,
  38                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  39                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  40         },
  41         {
  42                 OPCODE_ETH_GET_PPORT_STATS,
  43                 CMD_SUBSYSTEM_ETH,
  44                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  45                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  46         },
  47         {
  48                 OPCODE_COMMON_GET_PHY_DETAILS,
  49                 CMD_SUBSYSTEM_COMMON,
  50                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  51                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  52         }
  53 };
  54
  55 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode,
  56                            u8 subsystem)
  57 {
  58         int i;
  59         int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
  60         u32 cmd_privileges = adapter->cmd_privileges;
  61
  62         for (i = 0; i < num_entries; i++)
  63                 if (opcode == cmd_priv_map[i].opcode &&
  64                     subsystem == cmd_priv_map[i].subsystem)
  65                         if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
  66                                 return false;
  67
  68         return true;
  69 }
  70
  71 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
  72 {
  73         return wrb->payload.embedded_payload;
  74 }
  75
  76 static void be_mcc_notify(struct be_adapter *adapter)
  77 {
  78         struct be_queue_info *mccq = &adapter->mcc_obj.q;
  79         u32 val = 0;
  80
  81         if (be_error(adapter))
  82                 return;
  83
  84         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
  85         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
  86
  87         wmb();
  88         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
  89 }
  90
  91 /* To check if valid bit is set, check the entire word as we don't know
  92  * the endianness of the data (old entry is host endian while a new entry is
  93  * little endian) */
  94 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
  95 {
  96         u32 flags;
  97
  98         if (compl->flags != 0) {
  99                 flags = le32_to_cpu(compl->flags);
 100                 if (flags & CQE_FLAGS_VALID_MASK) {
 101                         compl->flags = flags;
 102                         return true;
 103                 }
 104         }
 105         return false;
 106 }
 107
 108 /* Need to reset the entire word that houses the valid bit */
 109 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
 110 {
 111         compl->flags = 0;
 112 }
 113
 114 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
 115 {
 116         unsigned long addr;
 117
 118         addr = tag1;
 119         addr = ((addr << 16) << 16) | tag0;
 120         return (void *)addr;
 121 }
 122
 123 static int be_mcc_compl_process(struct be_adapter *adapter,
 124                                 struct be_mcc_compl *compl)
 125 {
 126         u16 compl_status, extd_status;
 127         struct be_cmd_resp_hdr *resp_hdr;
 128         u8 opcode = 0, subsystem = 0;
 129
 130         /* Just swap the status to host endian; mcc tag is opaquely copied
 131          * from mcc_wrb */
 132         be_dws_le_to_cpu(compl, 4);
 133
 134         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
 135                                 CQE_STATUS_COMPL_MASK;
 136
 137         resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
 138
 139         if (resp_hdr) {
 140                 opcode = resp_hdr->opcode;
 141                 subsystem = resp_hdr->subsystem;
 142         }
 143
 144         if (((opcode == OPCODE_COMMON_WRITE_FLASHROM) ||
 145              (opcode == OPCODE_COMMON_WRITE_OBJECT)) &&
 146             (subsystem == CMD_SUBSYSTEM_COMMON)) {
 147                 adapter->flash_status = compl_status;
 148                 complete(&adapter->flash_compl);
 149         }
 150
 151         if (compl_status == MCC_STATUS_SUCCESS) {
 152                 if (((opcode == OPCODE_ETH_GET_STATISTICS) ||
 153                      (opcode == OPCODE_ETH_GET_PPORT_STATS)) &&
 154                     (subsystem == CMD_SUBSYSTEM_ETH)) {
 155                         be_parse_stats(adapter);
 156                         adapter->stats_cmd_sent = false;
 157                 }
 158                 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
 159                     subsystem == CMD_SUBSYSTEM_COMMON) {
 160                         struct be_cmd_resp_get_cntl_addnl_attribs *resp =
 161                                 (void *)resp_hdr;
 162                         adapter->drv_stats.be_on_die_temperature =
 163                                 resp->on_die_temperature;
 164                 }
 165         } else {
 166                 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
 167                         adapter->be_get_temp_freq = 0;
 168
 169                 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
 170                         compl_status == MCC_STATUS_ILLEGAL_REQUEST)
 171                         goto done;
 172
 173                 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
 174                         dev_warn(&adapter->pdev->dev,
 175                                  "VF is not privileged to issue opcode %d-%d\n",
 176                                  opcode, subsystem);
 177                 } else {
 178                         extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
 179                                         CQE_STATUS_EXTD_MASK;
 180                         dev_err(&adapter->pdev->dev,
 181                                 "opcode %d-%d failed:status %d-%d\n",
 182                                 opcode, subsystem, compl_status, extd_status);
 183                 }
 184         }
 185 done:
 186         return compl_status;
 187 }
 188
 189 /* Link state evt is a string of bytes; no need for endian swapping */
 190 static void be_async_link_state_process(struct be_adapter *adapter,
 191                 struct be_async_event_link_state *evt)
 192 {
 193         /* When link status changes, link speed must be re-queried from FW */
 194         adapter->phy.link_speed = -1;
 195
 196         /* Ignore physical link event */
 197         if (lancer_chip(adapter) &&
 198             !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
 199                 return;
 200
 201         /* For the initial link status do not rely on the ASYNC event as
 202          * it may not be received in some cases.
 203          */
 204         if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
 205                 be_link_status_update(adapter, evt->port_link_status);
 206 }
 207
 208 /* Grp5 CoS Priority evt */
 209 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
 210                 struct be_async_event_grp5_cos_priority *evt)
 211 {
 212         if (evt->valid) {
 213                 adapter->vlan_prio_bmap = evt->available_priority_bmap;
 214                 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
 215                 adapter->recommended_prio =
 216                         evt->reco_default_priority << VLAN_PRIO_SHIFT;
 217         }
 218 }
 219
 220 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
 221 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
 222                 struct be_async_event_grp5_qos_link_speed *evt)
 223 {
 224         if (adapter->phy.link_speed >= 0 &&
 225             evt->physical_port == adapter->port_num)
 226                 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
 227 }
 228
 229 /*Grp5 PVID evt*/
 230 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
 231                 struct be_async_event_grp5_pvid_state *evt)
 232 {
 233         if (evt->enabled)
 234                 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
 235         else
 236                 adapter->pvid = 0;
 237 }
 238
 239 static void be_async_grp5_evt_process(struct be_adapter *adapter,
 240                 u32 trailer, struct be_mcc_compl *evt)
 241 {
 242         u8 event_type = 0;
 243
 244         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 245                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 246
 247         switch (event_type) {
 248         case ASYNC_EVENT_COS_PRIORITY:
 249                 be_async_grp5_cos_priority_process(adapter,
 250                 (struct be_async_event_grp5_cos_priority *)evt);
 251         break;
 252         case ASYNC_EVENT_QOS_SPEED:
 253                 be_async_grp5_qos_speed_process(adapter,
 254                 (struct be_async_event_grp5_qos_link_speed *)evt);
 255         break;
 256         case ASYNC_EVENT_PVID_STATE:
 257                 be_async_grp5_pvid_state_process(adapter,
 258                 (struct be_async_event_grp5_pvid_state *)evt);
 259         break;
 260         default:
 261                 dev_warn(&adapter->pdev->dev, "Unknown grp5 event 0x%x!\n",
 262                          event_type);
 263                 break;
 264         }
 265 }
 266
 267 static void be_async_dbg_evt_process(struct be_adapter *adapter,
 268                 u32 trailer, struct be_mcc_compl *cmp)
 269 {
 270         u8 event_type = 0;
 271         struct be_async_event_qnq *evt = (struct be_async_event_qnq *) cmp;
 272
 273         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 274                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 275
 276         switch (event_type) {
 277         case ASYNC_DEBUG_EVENT_TYPE_QNQ:
 278                 if (evt->valid)
 279                         adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
 280                 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
 281         break;
 282         default:
 283                 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
 284                          event_type);
 285         break;
 286         }
 287 }
 288
 289 static inline bool is_link_state_evt(u32 trailer)
 290 {
 291         return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 292                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 293                                 ASYNC_EVENT_CODE_LINK_STATE;
 294 }
 295
 296 static inline bool is_grp5_evt(u32 trailer)
 297 {
 298         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 299                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 300                                 ASYNC_EVENT_CODE_GRP_5);
 301 }
 302
 303 static inline bool is_dbg_evt(u32 trailer)
 304 {
 305         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 306                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 307                                 ASYNC_EVENT_CODE_QNQ);
 308 }
 309
 310 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 311 {
 312         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 313         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 314
 315         if (be_mcc_compl_is_new(compl)) {
 316                 queue_tail_inc(mcc_cq);
 317                 return compl;
 318         }
 319         return NULL;
 320 }
 321
 322 void be_async_mcc_enable(struct be_adapter *adapter)
 323 {
 324         spin_lock_bh(&adapter->mcc_cq_lock);
 325
 326         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 327         adapter->mcc_obj.rearm_cq = true;
 328
 329         spin_unlock_bh(&adapter->mcc_cq_lock);
 330 }
 331
 332 void be_async_mcc_disable(struct be_adapter *adapter)
 333 {
 334         spin_lock_bh(&adapter->mcc_cq_lock);
 335
 336         adapter->mcc_obj.rearm_cq = false;
 337         be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
 338
 339         spin_unlock_bh(&adapter->mcc_cq_lock);
 340 }
 341
 342 int be_process_mcc(struct be_adapter *adapter)
 343 {
 344         struct be_mcc_compl *compl;
 345         int num = 0, status = 0;
 346         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 347
 348         spin_lock(&adapter->mcc_cq_lock);
 349         while ((compl = be_mcc_compl_get(adapter))) {
 350                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 351                         /* Interpret flags as an async trailer */
 352                         if (is_link_state_evt(compl->flags))
 353                                 be_async_link_state_process(adapter,
 354                                 (struct be_async_event_link_state *) compl);
 355                         else if (is_grp5_evt(compl->flags))
 356                                 be_async_grp5_evt_process(adapter,
 357                                 compl->flags, compl);
 358                         else if (is_dbg_evt(compl->flags))
 359                                 be_async_dbg_evt_process(adapter,
 360                                 compl->flags, compl);
 361                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 362                                 status = be_mcc_compl_process(adapter, compl);
 363                                 atomic_dec(&mcc_obj->q.used);
 364                 }
 365                 be_mcc_compl_use(compl);
 366                 num++;
 367         }
 368
 369         if (num)
 370                 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
 371
 372         spin_unlock(&adapter->mcc_cq_lock);
 373         return status;
 374 }
 375
 376 /* Wait till no more pending mcc requests are present */
 377 static int be_mcc_wait_compl(struct be_adapter *adapter)
 378 {
 379 #define mcc_timeout             120000 /* 12s timeout */
 380         int i, status = 0;
 381         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 382
 383         for (i = 0; i < mcc_timeout; i++) {
 384                 if (be_error(adapter))
 385                         return -EIO;
 386
 387                 local_bh_disable();
 388                 status = be_process_mcc(adapter);
 389                 local_bh_enable();
 390
 391                 if (atomic_read(&mcc_obj->q.used) == 0)
 392                         break;
 393                 udelay(100);
 394         }
 395         if (i == mcc_timeout) {
 396                 dev_err(&adapter->pdev->dev, "FW not responding\n");
 397                 adapter->fw_timeout = true;
 398                 return -EIO;
 399         }
 400         return status;
 401 }
 402
 403 /* Notify MCC requests and wait for completion */
 404 static int be_mcc_notify_wait(struct be_adapter *adapter)
 405 {
 406         int status;
 407         struct be_mcc_wrb *wrb;
 408         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 409         u16 index = mcc_obj->q.head;
 410         struct be_cmd_resp_hdr *resp;
 411
 412         index_dec(&index, mcc_obj->q.len);
 413         wrb = queue_index_node(&mcc_obj->q, index);
 414
 415         resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
 416
 417         be_mcc_notify(adapter);
 418
 419         status = be_mcc_wait_compl(adapter);
 420         if (status == -EIO)
 421                 goto out;
 422
 423         status = resp->status;
 424 out:
 425         return status;
 426 }
 427
 428 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 429 {
 430         int msecs = 0;
 431         u32 ready;
 432
 433         do {
 434                 if (be_error(adapter))
 435                         return -EIO;
 436
 437                 ready = ioread32(db);
 438                 if (ready == 0xffffffff)
 439                         return -1;
 440
 441                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 442                 if (ready)
 443                         break;
 444
 445                 if (msecs > 4000) {
 446                         dev_err(&adapter->pdev->dev, "FW not responding\n");
 447                         adapter->fw_timeout = true;
 448                         be_detect_error(adapter);
 449                         return -1;
 450                 }
 451
 452                 msleep(1);
 453                 msecs++;
 454         } while (true);
 455
 456         return 0;
 457 }
 458
 459 /*
 460  * Insert the mailbox address into the doorbell in two steps
 461  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 462  */
 463 static int be_mbox_notify_wait(struct be_adapter *adapter)
 464 {
 465         int status;
 466         u32 val = 0;
 467         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 468         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 469         struct be_mcc_mailbox *mbox = mbox_mem->va;
 470         struct be_mcc_compl *compl = &mbox->compl;
 471
 472         /* wait for ready to be set */
 473         status = be_mbox_db_ready_wait(adapter, db);
 474         if (status != 0)
 475                 return status;
 476
 477         val |= MPU_MAILBOX_DB_HI_MASK;
 478         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 479         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 480         iowrite32(val, db);
 481
 482         /* wait for ready to be set */
 483         status = be_mbox_db_ready_wait(adapter, db);
 484         if (status != 0)
 485                 return status;
 486
 487         val = 0;
 488         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 489         val |= (u32)(mbox_mem->dma >> 4) << 2;
 490         iowrite32(val, db);
 491
 492         status = be_mbox_db_ready_wait(adapter, db);
 493         if (status != 0)
 494                 return status;
 495
 496         /* A cq entry has been made now */
 497         if (be_mcc_compl_is_new(compl)) {
 498                 status = be_mcc_compl_process(adapter, &mbox->compl);
 499                 be_mcc_compl_use(compl);
 500                 if (status)
 501                         return status;
 502         } else {
 503                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 504                 return -1;
 505         }
 506         return 0;
 507 }
 508
 509 static u16 be_POST_stage_get(struct be_adapter *adapter)
 510 {
 511         u32 sem;
 512
 513         if (BEx_chip(adapter))
 514                 sem  = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
 515         else
 516                 pci_read_config_dword(adapter->pdev,
 517                                       SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
 518
 519         return sem & POST_STAGE_MASK;
 520 }
 521
 522 int lancer_wait_ready(struct be_adapter *adapter)
 523 {
 524 #define SLIPORT_READY_TIMEOUT 30
 525         u32 sliport_status;
 526         int status = 0, i;
 527
 528         for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
 529                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 530                 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
 531                         break;
 532
 533                 msleep(1000);
 534         }
 535
 536         if (i == SLIPORT_READY_TIMEOUT)
 537                 status = -1;
 538
 539         return status;
 540 }
 541
 542 static bool lancer_provisioning_error(struct be_adapter *adapter)
 543 {
 544         u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
 545         sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 546         if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
 547                 sliport_err1 = ioread32(adapter->db +
 548                                         SLIPORT_ERROR1_OFFSET);
 549                 sliport_err2 = ioread32(adapter->db +
 550                                         SLIPORT_ERROR2_OFFSET);
 551
 552                 if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 &&
 553                     sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2)
 554                         return true;
 555         }
 556         return false;
 557 }
 558
 559 int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
 560 {
 561         int status;
 562         u32 sliport_status, err, reset_needed;
 563         bool resource_error;
 564
 565         resource_error = lancer_provisioning_error(adapter);
 566         if (resource_error)
 567                 return -EAGAIN;
 568
 569         status = lancer_wait_ready(adapter);
 570         if (!status) {
 571                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 572                 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
 573                 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
 574                 if (err && reset_needed) {
 575                         iowrite32(SLI_PORT_CONTROL_IP_MASK,
 576                                   adapter->db + SLIPORT_CONTROL_OFFSET);
 577
 578                         /* check adapter has corrected the error */
 579                         status = lancer_wait_ready(adapter);
 580                         sliport_status = ioread32(adapter->db +
 581                                                   SLIPORT_STATUS_OFFSET);
 582                         sliport_status &= (SLIPORT_STATUS_ERR_MASK |
 583                                                 SLIPORT_STATUS_RN_MASK);
 584                         if (status || sliport_status)
 585                                 status = -1;
 586                 } else if (err || reset_needed) {
 587                         status = -1;
 588                 }
 589         }
 590         /* Stop error recovery if error is not recoverable.
 591          * No resource error is temporary errors and will go away
 592          * when PF provisions resources.
 593          */
 594         resource_error = lancer_provisioning_error(adapter);
 595         if (resource_error)
 596                 status = -EAGAIN;
 597
 598         return status;
 599 }
 600
 601 int be_fw_wait_ready(struct be_adapter *adapter)
 602 {
 603         u16 stage;
 604         int status, timeout = 0;
 605         struct device *dev = &adapter->pdev->dev;
 606
 607         if (lancer_chip(adapter)) {
 608                 status = lancer_wait_ready(adapter);
 609                 return status;
 610         }
 611
 612         do {
 613                 stage = be_POST_stage_get(adapter);
 614                 if (stage == POST_STAGE_ARMFW_RDY)
 615                         return 0;
 616
 617                 dev_info(dev, "Waiting for POST, %ds elapsed\n",
 618                          timeout);
 619                 if (msleep_interruptible(2000)) {
 620                         dev_err(dev, "Waiting for POST aborted\n");
 621                         return -EINTR;
 622                 }
 623                 timeout += 2;
 624         } while (timeout < 60);
 625
 626         dev_err(dev, "POST timeout; stage=0x%x\n", stage);
 627         return -1;
 628 }
 629
 630
 631 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 632 {
 633         return &wrb->payload.sgl[0];
 634 }
 635
 636 static inline void fill_wrb_tags(struct be_mcc_wrb *wrb,
 637                                  unsigned long addr)
 638 {
 639         wrb->tag0 = addr & 0xFFFFFFFF;
 640         wrb->tag1 = upper_32_bits(addr);
 641 }
 642
 643 /* Don't touch the hdr after it's prepared */
 644 /* mem will be NULL for embedded commands */
 645 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 646                                 u8 subsystem, u8 opcode, int cmd_len,
 647                                 struct be_mcc_wrb *wrb, struct be_dma_mem *mem)
 648 {
 649         struct be_sge *sge;
 650
 651         req_hdr->opcode = opcode;
 652         req_hdr->subsystem = subsystem;
 653         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 654         req_hdr->version = 0;
 655         fill_wrb_tags(wrb, (ulong) req_hdr);
 656         wrb->payload_length = cmd_len;
 657         if (mem) {
 658                 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
 659                         MCC_WRB_SGE_CNT_SHIFT;
 660                 sge = nonembedded_sgl(wrb);
 661                 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
 662                 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
 663                 sge->len = cpu_to_le32(mem->size);
 664         } else
 665                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 666         be_dws_cpu_to_le(wrb, 8);
 667 }
 668
 669 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 670                         struct be_dma_mem *mem)
 671 {
 672         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 673         u64 dma = (u64)mem->dma;
 674
 675         for (i = 0; i < buf_pages; i++) {
 676                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 677                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 678                 dma += PAGE_SIZE_4K;
 679         }
 680 }
 681
 682 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 683 {
 684         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 685         struct be_mcc_wrb *wrb
 686                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 687         memset(wrb, 0, sizeof(*wrb));
 688         return wrb;
 689 }
 690
 691 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 692 {
 693         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 694         struct be_mcc_wrb *wrb;
 695
 696         if (!mccq->created)
 697                 return NULL;
 698
 699         if (atomic_read(&mccq->used) >= mccq->len)
 700                 return NULL;
 701
 702         wrb = queue_head_node(mccq);
 703         queue_head_inc(mccq);
 704         atomic_inc(&mccq->used);
 705         memset(wrb, 0, sizeof(*wrb));
 706         return wrb;
 707 }
 708
 709 static bool use_mcc(struct be_adapter *adapter)
 710 {
 711         return adapter->mcc_obj.q.created;
 712 }
 713
 714 /* Must be used only in process context */
 715 static int be_cmd_lock(struct be_adapter *adapter)
 716 {
 717         if (use_mcc(adapter)) {
 718                 spin_lock_bh(&adapter->mcc_lock);
 719                 return 0;
 720         } else {
 721                 return mutex_lock_interruptible(&adapter->mbox_lock);
 722         }
 723 }
 724
 725 /* Must be used only in process context */
 726 static void be_cmd_unlock(struct be_adapter *adapter)
 727 {
 728         if (use_mcc(adapter))
 729                 spin_unlock_bh(&adapter->mcc_lock);
 730         else
 731                 return mutex_unlock(&adapter->mbox_lock);
 732 }
 733
 734 static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
 735                                       struct be_mcc_wrb *wrb)
 736 {
 737         struct be_mcc_wrb *dest_wrb;
 738
 739         if (use_mcc(adapter)) {
 740                 dest_wrb = wrb_from_mccq(adapter);
 741                 if (!dest_wrb)
 742                         return NULL;
 743         } else {
 744                 dest_wrb = wrb_from_mbox(adapter);
 745         }
 746
 747         memcpy(dest_wrb, wrb, sizeof(*wrb));
 748         if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
 749                 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
 750
 751         return dest_wrb;
 752 }
 753
 754 /* Must be used only in process context */
 755 static int be_cmd_notify_wait(struct be_adapter *adapter,
 756                               struct be_mcc_wrb *wrb)
 757 {
 758         struct be_mcc_wrb *dest_wrb;
 759         int status;
 760
 761         status = be_cmd_lock(adapter);
 762         if (status)
 763                 return status;
 764
 765         dest_wrb = be_cmd_copy(adapter, wrb);
 766         if (!dest_wrb)
 767                 return -EBUSY;
 768
 769         if (use_mcc(adapter))
 770                 status = be_mcc_notify_wait(adapter);
 771         else
 772                 status = be_mbox_notify_wait(adapter);
 773
 774         if (!status)
 775                 memcpy(wrb, dest_wrb, sizeof(*wrb));
 776
 777         be_cmd_unlock(adapter);
 778         return status;
 779 }
 780
 781 /* Tell fw we're about to start firing cmds by writing a
 782  * special pattern across the wrb hdr; uses mbox
 783  */
 784 int be_cmd_fw_init(struct be_adapter *adapter)
 785 {
 786         u8 *wrb;
 787         int status;
 788
 789         if (lancer_chip(adapter))
 790                 return 0;
 791
 792         if (mutex_lock_interruptible(&adapter->mbox_lock))
 793                 return -1;
 794
 795         wrb = (u8 *)wrb_from_mbox(adapter);
 796         *wrb++ = 0xFF;
 797         *wrb++ = 0x12;
 798         *wrb++ = 0x34;
 799         *wrb++ = 0xFF;
 800         *wrb++ = 0xFF;
 801         *wrb++ = 0x56;
 802         *wrb++ = 0x78;
 803         *wrb = 0xFF;
 804
 805         status = be_mbox_notify_wait(adapter);
 806
 807         mutex_unlock(&adapter->mbox_lock);
 808         return status;
 809 }
 810
 811 /* Tell fw we're done with firing cmds by writing a
 812  * special pattern across the wrb hdr; uses mbox
 813  */
 814 int be_cmd_fw_clean(struct be_adapter *adapter)
 815 {
 816         u8 *wrb;
 817         int status;
 818
 819         if (lancer_chip(adapter))
 820                 return 0;
 821
 822         if (mutex_lock_interruptible(&adapter->mbox_lock))
 823                 return -1;
 824
 825         wrb = (u8 *)wrb_from_mbox(adapter);
 826         *wrb++ = 0xFF;
 827         *wrb++ = 0xAA;
 828         *wrb++ = 0xBB;
 829         *wrb++ = 0xFF;
 830         *wrb++ = 0xFF;
 831         *wrb++ = 0xCC;
 832         *wrb++ = 0xDD;
 833         *wrb = 0xFF;
 834
 835         status = be_mbox_notify_wait(adapter);
 836
 837         mutex_unlock(&adapter->mbox_lock);
 838         return status;
 839 }
 840
 841 int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
 842 {
 843         struct be_mcc_wrb *wrb;
 844         struct be_cmd_req_eq_create *req;
 845         struct be_dma_mem *q_mem = &eqo->q.dma_mem;
 846         int status, ver = 0;
 847
 848         if (mutex_lock_interruptible(&adapter->mbox_lock))
 849                 return -1;
 850
 851         wrb = wrb_from_mbox(adapter);
 852         req = embedded_payload(wrb);
 853
 854         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 855                 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL);
 856
 857         /* Support for EQ_CREATEv2 available only SH-R onwards */
 858         if (!(BEx_chip(adapter) || lancer_chip(adapter)))
 859                 ver = 2;
 860
 861         req->hdr.version = ver;
 862         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 863
 864         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 865         /* 4byte eqe*/
 866         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 867         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 868                       __ilog2_u32(eqo->q.len / 256));
 869         be_dws_cpu_to_le(req->context, sizeof(req->context));
 870
 871         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 872
 873         status = be_mbox_notify_wait(adapter);
 874         if (!status) {
 875                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 876                 eqo->q.id = le16_to_cpu(resp->eq_id);
 877                 eqo->msix_idx =
 878                         (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
 879                 eqo->q.created = true;
 880         }
 881
 882         mutex_unlock(&adapter->mbox_lock);
 883         return status;
 884 }
 885
 886 /* Use MCC */
 887 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 888                           bool permanent, u32 if_handle, u32 pmac_id)
 889 {
 890         struct be_mcc_wrb *wrb;
 891         struct be_cmd_req_mac_query *req;
 892         int status;
 893
 894         spin_lock_bh(&adapter->mcc_lock);
 895
 896         wrb = wrb_from_mccq(adapter);
 897         if (!wrb) {
 898                 status = -EBUSY;
 899                 goto err;
 900         }
 901         req = embedded_payload(wrb);
 902
 903         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 904                 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL);
 905         req->type = MAC_ADDRESS_TYPE_NETWORK;
 906         if (permanent) {
 907                 req->permanent = 1;
 908         } else {
 909                 req->if_id = cpu_to_le16((u16) if_handle);
 910                 req->pmac_id = cpu_to_le32(pmac_id);
 911                 req->permanent = 0;
 912         }
 913
 914         status = be_mcc_notify_wait(adapter);
 915         if (!status) {
 916                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
 917                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
 918         }
 919
 920 err:
 921         spin_unlock_bh(&adapter->mcc_lock);
 922         return status;
 923 }
 924
 925 /* Uses synchronous MCCQ */
 926 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
 927                 u32 if_id, u32 *pmac_id, u32 domain)
 928 {
 929         struct be_mcc_wrb *wrb;
 930         struct be_cmd_req_pmac_add *req;
 931         int status;
 932
 933         spin_lock_bh(&adapter->mcc_lock);
 934
 935         wrb = wrb_from_mccq(adapter);
 936         if (!wrb) {
 937                 status = -EBUSY;
 938                 goto err;
 939         }
 940         req = embedded_payload(wrb);
 941
 942         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 943                 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL);
 944
 945         req->hdr.domain = domain;
 946         req->if_id = cpu_to_le32(if_id);
 947         memcpy(req->mac_address, mac_addr, ETH_ALEN);
 948
 949         status = be_mcc_notify_wait(adapter);
 950         if (!status) {
 951                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
 952                 *pmac_id = le32_to_cpu(resp->pmac_id);
 953         }
 954
 955 err:
 956         spin_unlock_bh(&adapter->mcc_lock);
 957
 958          if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
 959                 status = -EPERM;
 960
 961         return status;
 962 }
 963
 964 /* Uses synchronous MCCQ */
 965 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
 966 {
 967         struct be_mcc_wrb *wrb;
 968         struct be_cmd_req_pmac_del *req;
 969         int status;
 970
 971         if (pmac_id == -1)
 972                 return 0;
 973
 974         spin_lock_bh(&adapter->mcc_lock);
 975
 976         wrb = wrb_from_mccq(adapter);
 977         if (!wrb) {
 978                 status = -EBUSY;
 979                 goto err;
 980         }
 981         req = embedded_payload(wrb);
 982
 983         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 984                 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
 985
 986         req->hdr.domain = dom;
 987         req->if_id = cpu_to_le32(if_id);
 988         req->pmac_id = cpu_to_le32(pmac_id);
 989
 990         status = be_mcc_notify_wait(adapter);
 991
 992 err:
 993         spin_unlock_bh(&adapter->mcc_lock);
 994         return status;
 995 }
 996
 997 /* Uses Mbox */
 998 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
 999                 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
1000 {
1001         struct be_mcc_wrb *wrb;
1002         struct be_cmd_req_cq_create *req;
1003         struct be_dma_mem *q_mem = &cq->dma_mem;
1004         void *ctxt;
1005         int status;
1006
1007         if (mutex_lock_interruptible(&adapter->mbox_lock))
1008                 return -1;
1009
1010         wrb = wrb_from_mbox(adapter);
1011         req = embedded_payload(wrb);
1012         ctxt = &req->context;
1013
1014         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1015                 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL);
1016
1017         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1018
1019         if (BEx_chip(adapter)) {
1020                 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
1021                                                                 coalesce_wm);
1022                 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
1023                                                                 ctxt, no_delay);
1024                 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
1025                                                 __ilog2_u32(cq->len/256));
1026                 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
1027                 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1028                 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
1029         } else {
1030                 req->hdr.version = 2;
1031                 req->page_size = 1; /* 1 for 4K */
1032                 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
1033                                                                 no_delay);
1034                 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
1035                                                 __ilog2_u32(cq->len/256));
1036                 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
1037                 AMAP_SET_BITS(struct amap_cq_context_v2, eventable,
1038                                                                 ctxt, 1);
1039                 AMAP_SET_BITS(struct amap_cq_context_v2, eqid,
1040                                                                 ctxt, eq->id);
1041         }
1042
1043         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1044
1045         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1046
1047         status = be_mbox_notify_wait(adapter);
1048         if (!status) {
1049                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
1050                 cq->id = le16_to_cpu(resp->cq_id);
1051                 cq->created = true;
1052         }
1053
1054         mutex_unlock(&adapter->mbox_lock);
1055
1056         return status;
1057 }
1058
1059 static u32 be_encoded_q_len(int q_len)
1060 {
1061         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1062         if (len_encoded == 16)
1063                 len_encoded = 0;
1064         return len_encoded;
1065 }
1066
1067 static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
1068                                 struct be_queue_info *mccq,
1069                                 struct be_queue_info *cq)
1070 {
1071         struct be_mcc_wrb *wrb;
1072         struct be_cmd_req_mcc_ext_create *req;
1073         struct be_dma_mem *q_mem = &mccq->dma_mem;
1074         void *ctxt;
1075         int status;
1076
1077         if (mutex_lock_interruptible(&adapter->mbox_lock))
1078                 return -1;
1079
1080         wrb = wrb_from_mbox(adapter);
1081         req = embedded_payload(wrb);
1082         ctxt = &req->context;
1083
1084         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1085                         OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL);
1086
1087         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1088         if (lancer_chip(adapter)) {
1089                 req->hdr.version = 1;
1090                 req->cq_id = cpu_to_le16(cq->id);
1091
1092                 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
1093                                                 be_encoded_q_len(mccq->len));
1094                 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
1095                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
1096                                                                 ctxt, cq->id);
1097                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
1098                                                                  ctxt, 1);
1099
1100         } else {
1101                 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1102                 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1103                                                 be_encoded_q_len(mccq->len));
1104                 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1105         }
1106
1107         /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
1108         req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
1109         req->async_event_bitmap[0] |= cpu_to_le32(1 << ASYNC_EVENT_CODE_QNQ);
1110         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1111
1112         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1113
1114         status = be_mbox_notify_wait(adapter);
1115         if (!status) {
1116                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1117                 mccq->id = le16_to_cpu(resp->id);
1118                 mccq->created = true;
1119         }
1120         mutex_unlock(&adapter->mbox_lock);
1121
1122         return status;
1123 }
1124
1125 static int be_cmd_mccq_org_create(struct be_adapter *adapter,
1126                                 struct be_queue_info *mccq,
1127                                 struct be_queue_info *cq)
1128 {
1129         struct be_mcc_wrb *wrb;
1130         struct be_cmd_req_mcc_create *req;
1131         struct be_dma_mem *q_mem = &mccq->dma_mem;
1132         void *ctxt;
1133         int status;
1134
1135         if (mutex_lock_interruptible(&adapter->mbox_lock))
1136                 return -1;
1137
1138         wrb = wrb_from_mbox(adapter);
1139         req = embedded_payload(wrb);
1140         ctxt = &req->context;
1141
1142         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1143                         OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL);
1144
1145         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1146
1147         AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1148         AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1149                         be_encoded_q_len(mccq->len));
1150         AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1151
1152         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1153
1154         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1155
1156         status = be_mbox_notify_wait(adapter);
1157         if (!status) {
1158                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1159                 mccq->id = le16_to_cpu(resp->id);
1160                 mccq->created = true;
1161         }
1162
1163         mutex_unlock(&adapter->mbox_lock);
1164         return status;
1165 }
1166
1167 int be_cmd_mccq_create(struct be_adapter *adapter,
1168                         struct be_queue_info *mccq,
1169                         struct be_queue_info *cq)
1170 {
1171         int status;
1172
1173         status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1174         if (status && !lancer_chip(adapter)) {
1175                 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1176                         "or newer to avoid conflicting priorities between NIC "
1177                         "and FCoE traffic");
1178                 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1179         }
1180         return status;
1181 }
1182
1183 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
1184 {
1185         struct be_mcc_wrb wrb = {0};
1186         struct be_cmd_req_eth_tx_create *req;
1187         struct be_queue_info *txq = &txo->q;
1188         struct be_queue_info *cq = &txo->cq;
1189         struct be_dma_mem *q_mem = &txq->dma_mem;
1190         int status, ver = 0;
1191
1192         req = embedded_payload(&wrb);
1193         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1194                                 OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
1195
1196         if (lancer_chip(adapter)) {
1197                 req->hdr.version = 1;
1198                 req->if_id = cpu_to_le16(adapter->if_handle);
1199         } else if (BEx_chip(adapter)) {
1200                 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1201                         req->hdr.version = 2;
1202         } else { /* For SH */
1203                 req->hdr.version = 2;
1204         }
1205
1206         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1207         req->ulp_num = BE_ULP1_NUM;
1208         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1209         req->cq_id = cpu_to_le16(cq->id);
1210         req->queue_size = be_encoded_q_len(txq->len);
1211         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1212         ver = req->hdr.version;
1213
1214         status = be_cmd_notify_wait(adapter, &wrb);
1215         if (!status) {
1216                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
1217                 txq->id = le16_to_cpu(resp->cid);
1218                 if (ver == 2)
1219                         txo->db_offset = le32_to_cpu(resp->db_offset);
1220                 else
1221                         txo->db_offset = DB_TXULP1_OFFSET;
1222                 txq->created = true;
1223         }
1224
1225         return status;
1226 }
1227
1228 /* Uses MCC */
1229 int be_cmd_rxq_create(struct be_adapter *adapter,
1230                 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1231                 u32 if_id, u32 rss, u8 *rss_id)
1232 {
1233         struct be_mcc_wrb *wrb;
1234         struct be_cmd_req_eth_rx_create *req;
1235         struct be_dma_mem *q_mem = &rxq->dma_mem;
1236         int status;
1237
1238         spin_lock_bh(&adapter->mcc_lock);
1239
1240         wrb = wrb_from_mccq(adapter);
1241         if (!wrb) {
1242                 status = -EBUSY;
1243                 goto err;
1244         }
1245         req = embedded_payload(wrb);
1246
1247         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1248                                 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1249
1250         req->cq_id = cpu_to_le16(cq_id);
1251         req->frag_size = fls(frag_size) - 1;
1252         req->num_pages = 2;
1253         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1254         req->interface_id = cpu_to_le32(if_id);
1255         req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1256         req->rss_queue = cpu_to_le32(rss);
1257
1258         status = be_mcc_notify_wait(adapter);
1259         if (!status) {
1260                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1261                 rxq->id = le16_to_cpu(resp->id);
1262                 rxq->created = true;
1263                 *rss_id = resp->rss_id;
1264         }
1265
1266 err:
1267         spin_unlock_bh(&adapter->mcc_lock);
1268         return status;
1269 }
1270
1271 /* Generic destroyer function for all types of queues
1272  * Uses Mbox
1273  */
1274 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1275                 int queue_type)
1276 {
1277         struct be_mcc_wrb *wrb;
1278         struct be_cmd_req_q_destroy *req;
1279         u8 subsys = 0, opcode = 0;
1280         int status;
1281
1282         if (mutex_lock_interruptible(&adapter->mbox_lock))
1283                 return -1;
1284
1285         wrb = wrb_from_mbox(adapter);
1286         req = embedded_payload(wrb);
1287
1288         switch (queue_type) {
1289         case QTYPE_EQ:
1290                 subsys = CMD_SUBSYSTEM_COMMON;
1291                 opcode = OPCODE_COMMON_EQ_DESTROY;
1292                 break;
1293         case QTYPE_CQ:
1294                 subsys = CMD_SUBSYSTEM_COMMON;
1295                 opcode = OPCODE_COMMON_CQ_DESTROY;
1296                 break;
1297         case QTYPE_TXQ:
1298                 subsys = CMD_SUBSYSTEM_ETH;
1299                 opcode = OPCODE_ETH_TX_DESTROY;
1300                 break;
1301         case QTYPE_RXQ:
1302                 subsys = CMD_SUBSYSTEM_ETH;
1303                 opcode = OPCODE_ETH_RX_DESTROY;
1304                 break;
1305         case QTYPE_MCCQ:
1306                 subsys = CMD_SUBSYSTEM_COMMON;
1307                 opcode = OPCODE_COMMON_MCC_DESTROY;
1308                 break;
1309         default:
1310                 BUG();
1311         }
1312
1313         be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1314                                 NULL);
1315         req->id = cpu_to_le16(q->id);
1316
1317         status = be_mbox_notify_wait(adapter);
1318         q->created = false;
1319
1320         mutex_unlock(&adapter->mbox_lock);
1321         return status;
1322 }
1323
1324 /* Uses MCC */
1325 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1326 {
1327         struct be_mcc_wrb *wrb;
1328         struct be_cmd_req_q_destroy *req;
1329         int status;
1330
1331         spin_lock_bh(&adapter->mcc_lock);
1332
1333         wrb = wrb_from_mccq(adapter);
1334         if (!wrb) {
1335                 status = -EBUSY;
1336                 goto err;
1337         }
1338         req = embedded_payload(wrb);
1339
1340         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1341                         OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1342         req->id = cpu_to_le16(q->id);
1343
1344         status = be_mcc_notify_wait(adapter);
1345         q->created = false;
1346
1347 err:
1348         spin_unlock_bh(&adapter->mcc_lock);
1349         return status;
1350 }
1351
1352 /* Create an rx filtering policy configuration on an i/f
1353  * Will use MBOX only if MCCQ has not been created.
1354  */
1355 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1356                      u32 *if_handle, u32 domain)
1357 {
1358         struct be_mcc_wrb wrb = {0};
1359         struct be_cmd_req_if_create *req;
1360         int status;
1361
1362         req = embedded_payload(&wrb);
1363         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1364                 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), &wrb, NULL);
1365         req->hdr.domain = domain;
1366         req->capability_flags = cpu_to_le32(cap_flags);
1367         req->enable_flags = cpu_to_le32(en_flags);
1368         req->pmac_invalid = true;
1369
1370         status = be_cmd_notify_wait(adapter, &wrb);
1371         if (!status) {
1372                 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
1373                 *if_handle = le32_to_cpu(resp->interface_id);
1374
1375                 /* Hack to retrieve VF's pmac-id on BE3 */
1376                 if (BE3_chip(adapter) && !be_physfn(adapter))
1377                         adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
1378         }
1379         return status;
1380 }
1381
1382 /* Uses MCCQ */
1383 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1384 {
1385         struct be_mcc_wrb *wrb;
1386         struct be_cmd_req_if_destroy *req;
1387         int status;
1388
1389         if (interface_id == -1)
1390                 return 0;
1391
1392         spin_lock_bh(&adapter->mcc_lock);
1393
1394         wrb = wrb_from_mccq(adapter);
1395         if (!wrb) {
1396                 status = -EBUSY;
1397                 goto err;
1398         }
1399         req = embedded_payload(wrb);
1400
1401         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1402                 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL);
1403         req->hdr.domain = domain;
1404         req->interface_id = cpu_to_le32(interface_id);
1405
1406         status = be_mcc_notify_wait(adapter);
1407 err:
1408         spin_unlock_bh(&adapter->mcc_lock);
1409         return status;
1410 }
1411
1412 /* Get stats is a non embedded command: the request is not embedded inside
1413  * WRB but is a separate dma memory block
1414  * Uses asynchronous MCC
1415  */
1416 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1417 {
1418         struct be_mcc_wrb *wrb;
1419         struct be_cmd_req_hdr *hdr;
1420         int status = 0;
1421
1422         spin_lock_bh(&adapter->mcc_lock);
1423
1424         wrb = wrb_from_mccq(adapter);
1425         if (!wrb) {
1426                 status = -EBUSY;
1427                 goto err;
1428         }
1429         hdr = nonemb_cmd->va;
1430
1431         be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1432                 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd);
1433
1434         /* version 1 of the cmd is not supported only by BE2 */
1435         if (!BE2_chip(adapter))
1436                 hdr->version = 1;
1437
1438         be_mcc_notify(adapter);
1439         adapter->stats_cmd_sent = true;
1440
1441 err:
1442         spin_unlock_bh(&adapter->mcc_lock);
1443         return status;
1444 }
1445
1446 /* Lancer Stats */
1447 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1448                                 struct be_dma_mem *nonemb_cmd)
1449 {
1450
1451         struct be_mcc_wrb *wrb;
1452         struct lancer_cmd_req_pport_stats *req;
1453         int status = 0;
1454
1455         if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1456                             CMD_SUBSYSTEM_ETH))
1457                 return -EPERM;
1458
1459         spin_lock_bh(&adapter->mcc_lock);
1460
1461         wrb = wrb_from_mccq(adapter);
1462         if (!wrb) {
1463                 status = -EBUSY;
1464                 goto err;
1465         }
1466         req = nonemb_cmd->va;
1467
1468         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1469                         OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb,
1470                         nonemb_cmd);
1471
1472         req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1473         req->cmd_params.params.reset_stats = 0;
1474
1475         be_mcc_notify(adapter);
1476         adapter->stats_cmd_sent = true;
1477
1478 err:
1479         spin_unlock_bh(&adapter->mcc_lock);
1480         return status;
1481 }
1482
1483 static int be_mac_to_link_speed(int mac_speed)
1484 {
1485         switch (mac_speed) {
1486         case PHY_LINK_SPEED_ZERO:
1487                 return 0;
1488         case PHY_LINK_SPEED_10MBPS:
1489                 return 10;
1490         case PHY_LINK_SPEED_100MBPS:
1491                 return 100;
1492         case PHY_LINK_SPEED_1GBPS:
1493                 return 1000;
1494         case PHY_LINK_SPEED_10GBPS:
1495                 return 10000;
1496         case PHY_LINK_SPEED_20GBPS:
1497                 return 20000;
1498         case PHY_LINK_SPEED_25GBPS:
1499                 return 25000;
1500         case PHY_LINK_SPEED_40GBPS:
1501                 return 40000;
1502         }
1503         return 0;
1504 }
1505
1506 /* Uses synchronous mcc
1507  * Returns link_speed in Mbps
1508  */
1509 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1510                              u8 *link_status, u32 dom)
1511 {
1512         struct be_mcc_wrb *wrb;
1513         struct be_cmd_req_link_status *req;
1514         int status;
1515
1516         spin_lock_bh(&adapter->mcc_lock);
1517
1518         if (link_status)
1519                 *link_status = LINK_DOWN;
1520
1521         wrb = wrb_from_mccq(adapter);
1522         if (!wrb) {
1523                 status = -EBUSY;
1524                 goto err;
1525         }
1526         req = embedded_payload(wrb);
1527
1528         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1529                 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL);
1530
1531         /* version 1 of the cmd is not supported only by BE2 */
1532         if (!BE2_chip(adapter))
1533                 req->hdr.version = 1;
1534
1535         req->hdr.domain = dom;
1536
1537         status = be_mcc_notify_wait(adapter);
1538         if (!status) {
1539                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1540                 if (link_speed) {
1541                         *link_speed = resp->link_speed ?
1542                                       le16_to_cpu(resp->link_speed) * 10 :
1543                                       be_mac_to_link_speed(resp->mac_speed);
1544
1545                         if (!resp->logical_link_status)
1546                                 *link_speed = 0;
1547                 }
1548                 if (link_status)
1549                         *link_status = resp->logical_link_status;
1550         }
1551
1552 err:
1553         spin_unlock_bh(&adapter->mcc_lock);
1554         return status;
1555 }
1556
1557 /* Uses synchronous mcc */
1558 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1559 {
1560         struct be_mcc_wrb *wrb;
1561         struct be_cmd_req_get_cntl_addnl_attribs *req;
1562         int status = 0;
1563
1564         spin_lock_bh(&adapter->mcc_lock);
1565
1566         wrb = wrb_from_mccq(adapter);
1567         if (!wrb) {
1568                 status = -EBUSY;
1569                 goto err;
1570         }
1571         req = embedded_payload(wrb);
1572
1573         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1574                 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req),
1575                 wrb, NULL);
1576
1577         be_mcc_notify(adapter);
1578
1579 err:
1580         spin_unlock_bh(&adapter->mcc_lock);
1581         return status;
1582 }
1583
1584 /* Uses synchronous mcc */
1585 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1586 {
1587         struct be_mcc_wrb *wrb;
1588         struct be_cmd_req_get_fat *req;
1589         int status;
1590
1591         spin_lock_bh(&adapter->mcc_lock);
1592
1593         wrb = wrb_from_mccq(adapter);
1594         if (!wrb) {
1595                 status = -EBUSY;
1596                 goto err;
1597         }
1598         req = embedded_payload(wrb);
1599
1600         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1601                 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL);
1602         req->fat_operation = cpu_to_le32(QUERY_FAT);
1603         status = be_mcc_notify_wait(adapter);
1604         if (!status) {
1605                 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1606                 if (log_size && resp->log_size)
1607                         *log_size = le32_to_cpu(resp->log_size) -
1608                                         sizeof(u32);
1609         }
1610 err:
1611         spin_unlock_bh(&adapter->mcc_lock);
1612         return status;
1613 }
1614
1615 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1616 {
1617         struct be_dma_mem get_fat_cmd;
1618         struct be_mcc_wrb *wrb;
1619         struct be_cmd_req_get_fat *req;
1620         u32 offset = 0, total_size, buf_size,
1621                                 log_offset = sizeof(u32), payload_len;
1622         int status;
1623
1624         if (buf_len == 0)
1625                 return;
1626
1627         total_size = buf_len;
1628
1629         get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1630         get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1631                         get_fat_cmd.size,
1632                         &get_fat_cmd.dma);
1633         if (!get_fat_cmd.va) {
1634                 status = -ENOMEM;
1635                 dev_err(&adapter->pdev->dev,
1636                 "Memory allocation failure while retrieving FAT data\n");
1637                 return;
1638         }
1639
1640         spin_lock_bh(&adapter->mcc_lock);
1641
1642         while (total_size) {
1643                 buf_size = min(total_size, (u32)60*1024);
1644                 total_size -= buf_size;
1645
1646                 wrb = wrb_from_mccq(adapter);
1647                 if (!wrb) {
1648                         status = -EBUSY;
1649                         goto err;
1650                 }
1651                 req = get_fat_cmd.va;
1652
1653                 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1654                 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1655                                 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb,
1656                                 &get_fat_cmd);
1657
1658                 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1659                 req->read_log_offset = cpu_to_le32(log_offset);
1660                 req->read_log_length = cpu_to_le32(buf_size);
1661                 req->data_buffer_size = cpu_to_le32(buf_size);
1662
1663                 status = be_mcc_notify_wait(adapter);
1664                 if (!status) {
1665                         struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1666                         memcpy(buf + offset,
1667                                 resp->data_buffer,
1668                                 le32_to_cpu(resp->read_log_length));
1669                 } else {
1670                         dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1671                         goto err;
1672                 }
1673                 offset += buf_size;
1674                 log_offset += buf_size;
1675         }
1676 err:
1677         pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1678                         get_fat_cmd.va,
1679                         get_fat_cmd.dma);
1680         spin_unlock_bh(&adapter->mcc_lock);
1681 }
1682
1683 /* Uses synchronous mcc */
1684 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1685                         char *fw_on_flash)
1686 {
1687         struct be_mcc_wrb *wrb;
1688         struct be_cmd_req_get_fw_version *req;
1689         int status;
1690
1691         spin_lock_bh(&adapter->mcc_lock);
1692
1693         wrb = wrb_from_mccq(adapter);
1694         if (!wrb) {
1695                 status = -EBUSY;
1696                 goto err;
1697         }
1698
1699         req = embedded_payload(wrb);
1700
1701         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1702                 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL);
1703         status = be_mcc_notify_wait(adapter);
1704         if (!status) {
1705                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1706                 strcpy(fw_ver, resp->firmware_version_string);
1707                 if (fw_on_flash)
1708                         strcpy(fw_on_flash, resp->fw_on_flash_version_string);
1709         }
1710 err:
1711         spin_unlock_bh(&adapter->mcc_lock);
1712         return status;
1713 }
1714
1715 /* set the EQ delay interval of an EQ to specified value
1716  * Uses async mcc
1717  */
1718 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1719 {
1720         struct be_mcc_wrb *wrb;
1721         struct be_cmd_req_modify_eq_delay *req;
1722         int status = 0;
1723
1724         spin_lock_bh(&adapter->mcc_lock);
1725
1726         wrb = wrb_from_mccq(adapter);
1727         if (!wrb) {
1728                 status = -EBUSY;
1729                 goto err;
1730         }
1731         req = embedded_payload(wrb);
1732
1733         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1734                 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL);
1735
1736         req->num_eq = cpu_to_le32(1);
1737         req->delay[0].eq_id = cpu_to_le32(eq_id);
1738         req->delay[0].phase = 0;
1739         req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1740
1741         be_mcc_notify(adapter);
1742
1743 err:
1744         spin_unlock_bh(&adapter->mcc_lock);
1745         return status;
1746 }
1747
1748 /* Uses sycnhronous mcc */
1749 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1750                         u32 num, bool untagged, bool promiscuous)
1751 {
1752         struct be_mcc_wrb *wrb;
1753         struct be_cmd_req_vlan_config *req;
1754         int status;
1755
1756         spin_lock_bh(&adapter->mcc_lock);
1757
1758         wrb = wrb_from_mccq(adapter);
1759         if (!wrb) {
1760                 status = -EBUSY;
1761                 goto err;
1762         }
1763         req = embedded_payload(wrb);
1764
1765         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1766                 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL);
1767
1768         req->interface_id = if_id;
1769         req->promiscuous = promiscuous;
1770         req->untagged = untagged;
1771         req->num_vlan = num;
1772         if (!promiscuous) {
1773                 memcpy(req->normal_vlan, vtag_array,
1774                         req->num_vlan * sizeof(vtag_array[0]));
1775         }
1776
1777         status = be_mcc_notify_wait(adapter);
1778
1779 err:
1780         spin_unlock_bh(&adapter->mcc_lock);
1781         return status;
1782 }
1783
1784 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1785 {
1786         struct be_mcc_wrb *wrb;
1787         struct be_dma_mem *mem = &adapter->rx_filter;
1788         struct be_cmd_req_rx_filter *req = mem->va;
1789         int status;
1790
1791         spin_lock_bh(&adapter->mcc_lock);
1792
1793         wrb = wrb_from_mccq(adapter);
1794         if (!wrb) {
1795                 status = -EBUSY;
1796                 goto err;
1797         }
1798         memset(req, 0, sizeof(*req));
1799         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1800                                 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1801                                 wrb, mem);
1802
1803         req->if_id = cpu_to_le32(adapter->if_handle);
1804         if (flags & IFF_PROMISC) {
1805                 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1806                                         BE_IF_FLAGS_VLAN_PROMISCUOUS |
1807                                         BE_IF_FLAGS_MCAST_PROMISCUOUS);
1808                 if (value == ON)
1809                         req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1810                                                 BE_IF_FLAGS_VLAN_PROMISCUOUS |
1811                                                 BE_IF_FLAGS_MCAST_PROMISCUOUS);
1812         } else if (flags & IFF_ALLMULTI) {
1813                 req->if_flags_mask = req->if_flags =
1814                                 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1815         } else {
1816                 struct netdev_hw_addr *ha;
1817                 int i = 0;
1818
1819                 req->if_flags_mask = req->if_flags =
1820                                 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1821
1822                 /* Reset mcast promisc mode if already set by setting mask
1823                  * and not setting flags field
1824                  */
1825                 req->if_flags_mask |=
1826                         cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
1827                                     be_if_cap_flags(adapter));
1828                 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
1829                 netdev_for_each_mc_addr(ha, adapter->netdev)
1830                         memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1831         }
1832
1833         status = be_mcc_notify_wait(adapter);
1834 err:
1835         spin_unlock_bh(&adapter->mcc_lock);
1836         return status;
1837 }
1838
1839 /* Uses synchrounous mcc */
1840 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1841 {
1842         struct be_mcc_wrb *wrb;
1843         struct be_cmd_req_set_flow_control *req;
1844         int status;
1845
1846         if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
1847                             CMD_SUBSYSTEM_COMMON))
1848                 return -EPERM;
1849
1850         spin_lock_bh(&adapter->mcc_lock);
1851
1852         wrb = wrb_from_mccq(adapter);
1853         if (!wrb) {
1854                 status = -EBUSY;
1855                 goto err;
1856         }
1857         req = embedded_payload(wrb);
1858
1859         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1860                 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1861
1862         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1863         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1864
1865         status = be_mcc_notify_wait(adapter);
1866
1867 err:
1868         spin_unlock_bh(&adapter->mcc_lock);
1869         return status;
1870 }
1871
1872 /* Uses sycn mcc */
1873 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1874 {
1875         struct be_mcc_wrb *wrb;
1876         struct be_cmd_req_get_flow_control *req;
1877         int status;
1878
1879         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
1880                             CMD_SUBSYSTEM_COMMON))
1881                 return -EPERM;
1882
1883         spin_lock_bh(&adapter->mcc_lock);
1884
1885         wrb = wrb_from_mccq(adapter);
1886         if (!wrb) {
1887                 status = -EBUSY;
1888                 goto err;
1889         }
1890         req = embedded_payload(wrb);
1891
1892         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1893                 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1894
1895         status = be_mcc_notify_wait(adapter);
1896         if (!status) {
1897                 struct be_cmd_resp_get_flow_control *resp =
1898                                                 embedded_payload(wrb);
1899                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1900                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1901         }
1902
1903 err:
1904         spin_unlock_bh(&adapter->mcc_lock);
1905         return status;
1906 }
1907
1908 /* Uses mbox */
1909 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1910                         u32 *mode, u32 *caps, u16 *asic_rev)
1911 {
1912         struct be_mcc_wrb *wrb;
1913         struct be_cmd_req_query_fw_cfg *req;
1914         int status;
1915
1916         if (mutex_lock_interruptible(&adapter->mbox_lock))
1917                 return -1;
1918
1919         wrb = wrb_from_mbox(adapter);
1920         req = embedded_payload(wrb);
1921
1922         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1923                 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL);
1924
1925         status = be_mbox_notify_wait(adapter);
1926         if (!status) {
1927                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1928                 *port_num = le32_to_cpu(resp->phys_port);
1929                 *mode = le32_to_cpu(resp->function_mode);
1930                 *caps = le32_to_cpu(resp->function_caps);
1931                 *asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
1932         }
1933
1934         mutex_unlock(&adapter->mbox_lock);
1935         return status;
1936 }
1937
1938 /* Uses mbox */
1939 int be_cmd_reset_function(struct be_adapter *adapter)
1940 {
1941         struct be_mcc_wrb *wrb;
1942         struct be_cmd_req_hdr *req;
1943         int status;
1944
1945         if (lancer_chip(adapter)) {
1946                 status = lancer_wait_ready(adapter);
1947                 if (!status) {
1948                         iowrite32(SLI_PORT_CONTROL_IP_MASK,
1949                                   adapter->db + SLIPORT_CONTROL_OFFSET);
1950                         status = lancer_test_and_set_rdy_state(adapter);
1951                 }
1952                 if (status) {
1953                         dev_err(&adapter->pdev->dev,
1954                                 "Adapter in non recoverable error\n");
1955                 }
1956                 return status;
1957         }
1958
1959         if (mutex_lock_interruptible(&adapter->mbox_lock))
1960                 return -1;
1961
1962         wrb = wrb_from_mbox(adapter);
1963         req = embedded_payload(wrb);
1964
1965         be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1966                 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL);
1967
1968         status = be_mbox_notify_wait(adapter);
1969
1970         mutex_unlock(&adapter->mbox_lock);
1971         return status;
1972 }
1973
1974 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
1975                         u32 rss_hash_opts, u16 table_size)
1976 {
1977         struct be_mcc_wrb *wrb;
1978         struct be_cmd_req_rss_config *req;
1979         u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e,
1980                         0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2,
1981                         0x3ea83c02, 0x4a110304};
1982         int status;
1983
1984         if (mutex_lock_interruptible(&adapter->mbox_lock))
1985                 return -1;
1986
1987         wrb = wrb_from_mbox(adapter);
1988         req = embedded_payload(wrb);
1989
1990         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1991                 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
1992
1993         req->if_id = cpu_to_le32(adapter->if_handle);
1994         req->enable_rss = cpu_to_le16(rss_hash_opts);
1995         req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1996
1997         if (lancer_chip(adapter) || skyhawk_chip(adapter))
1998                 req->hdr.version = 1;
1999
2000         memcpy(req->cpu_table, rsstable, table_size);
2001         memcpy(req->hash, myhash, sizeof(myhash));
2002         be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2003
2004         status = be_mbox_notify_wait(adapter);
2005
2006         mutex_unlock(&adapter->mbox_lock);
2007         return status;
2008 }
2009
2010 /* Uses sync mcc */
2011 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
2012                         u8 bcn, u8 sts, u8 state)
2013 {
2014         struct be_mcc_wrb *wrb;
2015         struct be_cmd_req_enable_disable_beacon *req;
2016         int status;
2017
2018         spin_lock_bh(&adapter->mcc_lock);
2019
2020         wrb = wrb_from_mccq(adapter);
2021         if (!wrb) {
2022                 status = -EBUSY;
2023                 goto err;
2024         }
2025         req = embedded_payload(wrb);
2026
2027         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2028                 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL);
2029
2030         req->port_num = port_num;
2031         req->beacon_state = state;
2032         req->beacon_duration = bcn;
2033         req->status_duration = sts;
2034
2035         status = be_mcc_notify_wait(adapter);
2036
2037 err:
2038         spin_unlock_bh(&adapter->mcc_lock);
2039         return status;
2040 }
2041
2042 /* Uses sync mcc */
2043 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2044 {
2045         struct be_mcc_wrb *wrb;
2046         struct be_cmd_req_get_beacon_state *req;
2047         int status;
2048
2049         spin_lock_bh(&adapter->mcc_lock);
2050
2051         wrb = wrb_from_mccq(adapter);
2052         if (!wrb) {
2053                 status = -EBUSY;
2054                 goto err;
2055         }
2056         req = embedded_payload(wrb);
2057
2058         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2059                 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL);
2060
2061         req->port_num = port_num;
2062
2063         status = be_mcc_notify_wait(adapter);
2064         if (!status) {
2065                 struct be_cmd_resp_get_beacon_state *resp =
2066                                                 embedded_payload(wrb);
2067                 *state = resp->beacon_state;
2068         }
2069
2070 err:
2071         spin_unlock_bh(&adapter->mcc_lock);
2072         return status;
2073 }
2074
2075 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2076                             u32 data_size, u32 data_offset,
2077                             const char *obj_name, u32 *data_written,
2078                             u8 *change_status, u8 *addn_status)
2079 {
2080         struct be_mcc_wrb *wrb;
2081         struct lancer_cmd_req_write_object *req;
2082         struct lancer_cmd_resp_write_object *resp;
2083         void *ctxt = NULL;
2084         int status;
2085
2086         spin_lock_bh(&adapter->mcc_lock);
2087         adapter->flash_status = 0;
2088
2089         wrb = wrb_from_mccq(adapter);
2090         if (!wrb) {
2091                 status = -EBUSY;
2092                 goto err_unlock;
2093         }
2094
2095         req = embedded_payload(wrb);
2096
2097         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2098                                 OPCODE_COMMON_WRITE_OBJECT,
2099                                 sizeof(struct lancer_cmd_req_write_object), wrb,
2100                                 NULL);
2101
2102         ctxt = &req->context;
2103         AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2104                         write_length, ctxt, data_size);
2105
2106         if (data_size == 0)
2107                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2108                                 eof, ctxt, 1);
2109         else
2110                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2111                                 eof, ctxt, 0);
2112
2113         be_dws_cpu_to_le(ctxt, sizeof(req->context));
2114         req->write_offset = cpu_to_le32(data_offset);
2115         strcpy(req->object_name, obj_name);
2116         req->descriptor_count = cpu_to_le32(1);
2117         req->buf_len = cpu_to_le32(data_size);
2118         req->addr_low = cpu_to_le32((cmd->dma +
2119                                 sizeof(struct lancer_cmd_req_write_object))
2120                                 & 0xFFFFFFFF);
2121         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2122                                 sizeof(struct lancer_cmd_req_write_object)));
2123
2124         be_mcc_notify(adapter);
2125         spin_unlock_bh(&adapter->mcc_lock);
2126
2127         if (!wait_for_completion_timeout(&adapter->flash_compl,
2128                                          msecs_to_jiffies(60000)))
2129                 status = -1;
2130         else
2131                 status = adapter->flash_status;
2132
2133         resp = embedded_payload(wrb);
2134         if (!status) {
2135                 *data_written = le32_to_cpu(resp->actual_write_len);
2136                 *change_status = resp->change_status;
2137         } else {
2138                 *addn_status = resp->additional_status;
2139         }
2140
2141         return status;
2142
2143 err_unlock:
2144         spin_unlock_bh(&adapter->mcc_lock);
2145         return status;
2146 }
2147
2148 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2149                 u32 data_size, u32 data_offset, const char *obj_name,
2150                 u32 *data_read, u32 *eof, u8 *addn_status)
2151 {
2152         struct be_mcc_wrb *wrb;
2153         struct lancer_cmd_req_read_object *req;
2154         struct lancer_cmd_resp_read_object *resp;
2155         int status;
2156
2157         spin_lock_bh(&adapter->mcc_lock);
2158
2159         wrb = wrb_from_mccq(adapter);
2160         if (!wrb) {
2161                 status = -EBUSY;
2162                 goto err_unlock;
2163         }
2164
2165         req = embedded_payload(wrb);
2166
2167         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2168                         OPCODE_COMMON_READ_OBJECT,
2169                         sizeof(struct lancer_cmd_req_read_object), wrb,
2170                         NULL);
2171
2172         req->desired_read_len = cpu_to_le32(data_size);
2173         req->read_offset = cpu_to_le32(data_offset);
2174         strcpy(req->object_name, obj_name);
2175         req->descriptor_count = cpu_to_le32(1);
2176         req->buf_len = cpu_to_le32(data_size);
2177         req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2178         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2179
2180         status = be_mcc_notify_wait(adapter);
2181
2182         resp = embedded_payload(wrb);
2183         if (!status) {
2184                 *data_read = le32_to_cpu(resp->actual_read_len);
2185                 *eof = le32_to_cpu(resp->eof);
2186         } else {
2187                 *addn_status = resp->additional_status;
2188         }
2189
2190 err_unlock:
2191         spin_unlock_bh(&adapter->mcc_lock);
2192         return status;
2193 }
2194
2195 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2196                         u32 flash_type, u32 flash_opcode, u32 buf_size)
2197 {
2198         struct be_mcc_wrb *wrb;
2199         struct be_cmd_write_flashrom *req;
2200         int status;
2201
2202         spin_lock_bh(&adapter->mcc_lock);
2203         adapter->flash_status = 0;
2204
2205         wrb = wrb_from_mccq(adapter);
2206         if (!wrb) {
2207                 status = -EBUSY;
2208                 goto err_unlock;
2209         }
2210         req = cmd->va;
2211
2212         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2213                 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd);
2214
2215         req->params.op_type = cpu_to_le32(flash_type);
2216         req->params.op_code = cpu_to_le32(flash_opcode);
2217         req->params.data_buf_size = cpu_to_le32(buf_size);
2218
2219         be_mcc_notify(adapter);
2220         spin_unlock_bh(&adapter->mcc_lock);
2221
2222         if (!wait_for_completion_timeout(&adapter->flash_compl,
2223                         msecs_to_jiffies(40000)))
2224                 status = -1;
2225         else
2226                 status = adapter->flash_status;
2227
2228         return status;
2229
2230 err_unlock:
2231         spin_unlock_bh(&adapter->mcc_lock);
2232         return status;
2233 }
2234
2235 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2236                          int offset)
2237 {
2238         struct be_mcc_wrb *wrb;
2239         struct be_cmd_read_flash_crc *req;
2240         int status;
2241
2242         spin_lock_bh(&adapter->mcc_lock);
2243
2244         wrb = wrb_from_mccq(adapter);
2245         if (!wrb) {
2246                 status = -EBUSY;
2247                 goto err;
2248         }
2249         req = embedded_payload(wrb);
2250
2251         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2252                                OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2253                                wrb, NULL);
2254
2255         req->params.op_type = cpu_to_le32(OPTYPE_REDBOOT);
2256         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2257         req->params.offset = cpu_to_le32(offset);
2258         req->params.data_buf_size = cpu_to_le32(0x4);
2259
2260         status = be_mcc_notify_wait(adapter);
2261         if (!status)
2262                 memcpy(flashed_crc, req->crc, 4);
2263
2264 err:
2265         spin_unlock_bh(&adapter->mcc_lock);
2266         return status;
2267 }
2268
2269 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2270                                 struct be_dma_mem *nonemb_cmd)
2271 {
2272         struct be_mcc_wrb *wrb;
2273         struct be_cmd_req_acpi_wol_magic_config *req;
2274         int status;
2275
2276         spin_lock_bh(&adapter->mcc_lock);
2277
2278         wrb = wrb_from_mccq(adapter);
2279         if (!wrb) {
2280                 status = -EBUSY;
2281                 goto err;
2282         }
2283         req = nonemb_cmd->va;
2284
2285         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2286                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb,
2287                 nonemb_cmd);
2288         memcpy(req->magic_mac, mac, ETH_ALEN);
2289
2290         status = be_mcc_notify_wait(adapter);
2291
2292 err:
2293         spin_unlock_bh(&adapter->mcc_lock);
2294         return status;
2295 }
2296
2297 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2298                         u8 loopback_type, u8 enable)
2299 {
2300         struct be_mcc_wrb *wrb;
2301         struct be_cmd_req_set_lmode *req;
2302         int status;
2303
2304         spin_lock_bh(&adapter->mcc_lock);
2305
2306         wrb = wrb_from_mccq(adapter);
2307         if (!wrb) {
2308                 status = -EBUSY;
2309                 goto err;
2310         }
2311
2312         req = embedded_payload(wrb);
2313
2314         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2315                         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb,
2316                         NULL);
2317
2318         req->src_port = port_num;
2319         req->dest_port = port_num;
2320         req->loopback_type = loopback_type;
2321         req->loopback_state = enable;
2322
2323         status = be_mcc_notify_wait(adapter);
2324 err:
2325         spin_unlock_bh(&adapter->mcc_lock);
2326         return status;
2327 }
2328
2329 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2330                 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2331 {
2332         struct be_mcc_wrb *wrb;
2333         struct be_cmd_req_loopback_test *req;
2334         int status;
2335
2336         spin_lock_bh(&adapter->mcc_lock);
2337
2338         wrb = wrb_from_mccq(adapter);
2339         if (!wrb) {
2340                 status = -EBUSY;
2341                 goto err;
2342         }
2343
2344         req = embedded_payload(wrb);
2345
2346         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2347                         OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL);
2348         req->hdr.timeout = cpu_to_le32(4);
2349
2350         req->pattern = cpu_to_le64(pattern);
2351         req->src_port = cpu_to_le32(port_num);
2352         req->dest_port = cpu_to_le32(port_num);
2353         req->pkt_size = cpu_to_le32(pkt_size);
2354         req->num_pkts = cpu_to_le32(num_pkts);
2355         req->loopback_type = cpu_to_le32(loopback_type);
2356
2357         status = be_mcc_notify_wait(adapter);
2358         if (!status) {
2359                 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
2360                 status = le32_to_cpu(resp->status);
2361         }
2362
2363 err:
2364         spin_unlock_bh(&adapter->mcc_lock);
2365         return status;
2366 }
2367
2368 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2369                                 u32 byte_cnt, struct be_dma_mem *cmd)
2370 {
2371         struct be_mcc_wrb *wrb;
2372         struct be_cmd_req_ddrdma_test *req;
2373         int status;
2374         int i, j = 0;
2375
2376         spin_lock_bh(&adapter->mcc_lock);
2377
2378         wrb = wrb_from_mccq(adapter);
2379         if (!wrb) {
2380                 status = -EBUSY;
2381                 goto err;
2382         }
2383         req = cmd->va;
2384         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2385                         OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd);
2386
2387         req->pattern = cpu_to_le64(pattern);
2388         req->byte_count = cpu_to_le32(byte_cnt);
2389         for (i = 0; i < byte_cnt; i++) {
2390                 req->snd_buff[i] = (u8)(pattern >> (j*8));
2391                 j++;
2392                 if (j > 7)
2393                         j = 0;
2394         }
2395
2396         status = be_mcc_notify_wait(adapter);
2397
2398         if (!status) {
2399                 struct be_cmd_resp_ddrdma_test *resp;
2400                 resp = cmd->va;
2401                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2402                                 resp->snd_err) {
2403                         status = -1;
2404                 }
2405         }
2406
2407 err:
2408         spin_unlock_bh(&adapter->mcc_lock);
2409         return status;
2410 }
2411
2412 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2413                                 struct be_dma_mem *nonemb_cmd)
2414 {
2415         struct be_mcc_wrb *wrb;
2416         struct be_cmd_req_seeprom_read *req;
2417         int status;
2418
2419         spin_lock_bh(&adapter->mcc_lock);
2420
2421         wrb = wrb_from_mccq(adapter);
2422         if (!wrb) {
2423                 status = -EBUSY;
2424                 goto err;
2425         }
2426         req = nonemb_cmd->va;
2427
2428         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2429                         OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2430                         nonemb_cmd);
2431
2432         status = be_mcc_notify_wait(adapter);
2433
2434 err:
2435         spin_unlock_bh(&adapter->mcc_lock);
2436         return status;
2437 }
2438
2439 int be_cmd_get_phy_info(struct be_adapter *adapter)
2440 {
2441         struct be_mcc_wrb *wrb;
2442         struct be_cmd_req_get_phy_info *req;
2443         struct be_dma_mem cmd;
2444         int status;
2445
2446         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
2447                             CMD_SUBSYSTEM_COMMON))
2448                 return -EPERM;
2449
2450         spin_lock_bh(&adapter->mcc_lock);
2451
2452         wrb = wrb_from_mccq(adapter);
2453         if (!wrb) {
2454                 status = -EBUSY;
2455                 goto err;
2456         }
2457         cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2458         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2459                                         &cmd.dma);
2460         if (!cmd.va) {
2461                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2462                 status = -ENOMEM;
2463                 goto err;
2464         }
2465
2466         req = cmd.va;
2467
2468         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2469                         OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2470                         wrb, &cmd);
2471
2472         status = be_mcc_notify_wait(adapter);
2473         if (!status) {
2474                 struct be_phy_info *resp_phy_info =
2475                                 cmd.va + sizeof(struct be_cmd_req_hdr);
2476                 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2477                 adapter->phy.interface_type =
2478                         le16_to_cpu(resp_phy_info->interface_type);
2479                 adapter->phy.auto_speeds_supported =
2480                         le16_to_cpu(resp_phy_info->auto_speeds_supported);
2481                 adapter->phy.fixed_speeds_supported =
2482                         le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2483                 adapter->phy.misc_params =
2484                         le32_to_cpu(resp_phy_info->misc_params);
2485
2486                 if (BE2_chip(adapter)) {
2487                         adapter->phy.fixed_speeds_supported =
2488                                 BE_SUPPORTED_SPEED_10GBPS |
2489                                 BE_SUPPORTED_SPEED_1GBPS;
2490                 }
2491         }
2492         pci_free_consistent(adapter->pdev, cmd.size,
2493                                 cmd.va, cmd.dma);
2494 err:
2495         spin_unlock_bh(&adapter->mcc_lock);
2496         return status;
2497 }
2498
2499 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2500 {
2501         struct be_mcc_wrb *wrb;
2502         struct be_cmd_req_set_qos *req;
2503         int status;
2504
2505         spin_lock_bh(&adapter->mcc_lock);
2506
2507         wrb = wrb_from_mccq(adapter);
2508         if (!wrb) {
2509                 status = -EBUSY;
2510                 goto err;
2511         }
2512
2513         req = embedded_payload(wrb);
2514
2515         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2516                         OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
2517
2518         req->hdr.domain = domain;
2519         req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2520         req->max_bps_nic = cpu_to_le32(bps);
2521
2522         status = be_mcc_notify_wait(adapter);
2523
2524 err:
2525         spin_unlock_bh(&adapter->mcc_lock);
2526         return status;
2527 }
2528
2529 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2530 {
2531         struct be_mcc_wrb *wrb;
2532         struct be_cmd_req_cntl_attribs *req;
2533         struct be_cmd_resp_cntl_attribs *resp;
2534         int status;
2535         int payload_len = max(sizeof(*req), sizeof(*resp));
2536         struct mgmt_controller_attrib *attribs;
2537         struct be_dma_mem attribs_cmd;
2538
2539         if (mutex_lock_interruptible(&adapter->mbox_lock))
2540                 return -1;
2541
2542         memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2543         attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2544         attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2545                                                 &attribs_cmd.dma);
2546         if (!attribs_cmd.va) {
2547                 dev_err(&adapter->pdev->dev,
2548                                 "Memory allocation failure\n");
2549                 status = -ENOMEM;
2550                 goto err;
2551         }
2552
2553         wrb = wrb_from_mbox(adapter);
2554         if (!wrb) {
2555                 status = -EBUSY;
2556                 goto err;
2557         }
2558         req = attribs_cmd.va;
2559
2560         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2561                          OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb,
2562                         &attribs_cmd);
2563
2564         status = be_mbox_notify_wait(adapter);
2565         if (!status) {
2566                 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
2567                 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2568         }
2569
2570 err:
2571         mutex_unlock(&adapter->mbox_lock);
2572         if (attribs_cmd.va)
2573                 pci_free_consistent(adapter->pdev, attribs_cmd.size,
2574                                     attribs_cmd.va, attribs_cmd.dma);
2575         return status;
2576 }
2577
2578 /* Uses mbox */
2579 int be_cmd_req_native_mode(struct be_adapter *adapter)
2580 {
2581         struct be_mcc_wrb *wrb;
2582         struct be_cmd_req_set_func_cap *req;
2583         int status;
2584
2585         if (mutex_lock_interruptible(&adapter->mbox_lock))
2586                 return -1;
2587
2588         wrb = wrb_from_mbox(adapter);
2589         if (!wrb) {
2590                 status = -EBUSY;
2591                 goto err;
2592         }
2593
2594         req = embedded_payload(wrb);
2595
2596         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2597                 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL);
2598
2599         req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2600                                 CAPABILITY_BE3_NATIVE_ERX_API);
2601         req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2602
2603         status = be_mbox_notify_wait(adapter);
2604         if (!status) {
2605                 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2606                 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2607                                         CAPABILITY_BE3_NATIVE_ERX_API;
2608                 if (!adapter->be3_native)
2609                         dev_warn(&adapter->pdev->dev,
2610                                  "adapter not in advanced mode\n");
2611         }
2612 err:
2613         mutex_unlock(&adapter->mbox_lock);
2614         return status;
2615 }
2616
2617 /* Get privilege(s) for a function */
2618 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2619                              u32 domain)
2620 {
2621         struct be_mcc_wrb *wrb;
2622         struct be_cmd_req_get_fn_privileges *req;
2623         int status;
2624
2625         spin_lock_bh(&adapter->mcc_lock);
2626
2627         wrb = wrb_from_mccq(adapter);
2628         if (!wrb) {
2629                 status = -EBUSY;
2630                 goto err;
2631         }
2632
2633         req = embedded_payload(wrb);
2634
2635         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2636                                OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
2637                                wrb, NULL);
2638
2639         req->hdr.domain = domain;
2640
2641         status = be_mcc_notify_wait(adapter);
2642         if (!status) {
2643                 struct be_cmd_resp_get_fn_privileges *resp =
2644                                                 embedded_payload(wrb);
2645                 *privilege = le32_to_cpu(resp->privilege_mask);
2646         }
2647
2648 err:
2649         spin_unlock_bh(&adapter->mcc_lock);
2650         return status;
2651 }
2652
2653 /* Set privilege(s) for a function */
2654 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
2655                              u32 domain)
2656 {
2657         struct be_mcc_wrb *wrb;
2658         struct be_cmd_req_set_fn_privileges *req;
2659         int status;
2660
2661         spin_lock_bh(&adapter->mcc_lock);
2662
2663         wrb = wrb_from_mccq(adapter);
2664         if (!wrb) {
2665                 status = -EBUSY;
2666                 goto err;
2667         }
2668
2669         req = embedded_payload(wrb);
2670         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2671                                OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
2672                                wrb, NULL);
2673         req->hdr.domain = domain;
2674         if (lancer_chip(adapter))
2675                 req->privileges_lancer = cpu_to_le32(privileges);
2676         else
2677                 req->privileges = cpu_to_le32(privileges);
2678
2679         status = be_mcc_notify_wait(adapter);
2680 err:
2681         spin_unlock_bh(&adapter->mcc_lock);
2682         return status;
2683 }
2684
2685 /* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
2686  * pmac_id_valid: false => pmac_id or MAC address is requested.
2687  *                If pmac_id is returned, pmac_id_valid is returned as true
2688  */
2689 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
2690                              bool *pmac_id_valid, u32 *pmac_id, u8 domain)
2691 {
2692         struct be_mcc_wrb *wrb;
2693         struct be_cmd_req_get_mac_list *req;
2694         int status;
2695         int mac_count;
2696         struct be_dma_mem get_mac_list_cmd;
2697         int i;
2698
2699         memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
2700         get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
2701         get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
2702                         get_mac_list_cmd.size,
2703                         &get_mac_list_cmd.dma);
2704
2705         if (!get_mac_list_cmd.va) {
2706                 dev_err(&adapter->pdev->dev,
2707                                 "Memory allocation failure during GET_MAC_LIST\n");
2708                 return -ENOMEM;
2709         }
2710
2711         spin_lock_bh(&adapter->mcc_lock);
2712
2713         wrb = wrb_from_mccq(adapter);
2714         if (!wrb) {
2715                 status = -EBUSY;
2716                 goto out;
2717         }
2718
2719         req = get_mac_list_cmd.va;
2720
2721         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2722                                OPCODE_COMMON_GET_MAC_LIST,
2723                                get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
2724         req->hdr.domain = domain;
2725         req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
2726         if (*pmac_id_valid) {
2727                 req->mac_id = cpu_to_le32(*pmac_id);
2728                 req->iface_id = cpu_to_le16(adapter->if_handle);
2729                 req->perm_override = 0;
2730         } else {
2731                 req->perm_override = 1;
2732         }
2733
2734         status = be_mcc_notify_wait(adapter);
2735         if (!status) {
2736                 struct be_cmd_resp_get_mac_list *resp =
2737                                                 get_mac_list_cmd.va;
2738
2739                 if (*pmac_id_valid) {
2740                         memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
2741                                ETH_ALEN);
2742                         goto out;
2743                 }
2744
2745                 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
2746                 /* Mac list returned could contain one or more active mac_ids
2747                  * or one or more true or pseudo permanant mac addresses.
2748                  * If an active mac_id is present, return first active mac_id
2749                  * found.
2750                  */
2751                 for (i = 0; i < mac_count; i++) {
2752                         struct get_list_macaddr *mac_entry;
2753                         u16 mac_addr_size;
2754                         u32 mac_id;
2755
2756                         mac_entry = &resp->macaddr_list[i];
2757                         mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
2758                         /* mac_id is a 32 bit value and mac_addr size
2759                          * is 6 bytes
2760                          */
2761                         if (mac_addr_size == sizeof(u32)) {
2762                                 *pmac_id_valid = true;
2763                                 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
2764                                 *pmac_id = le32_to_cpu(mac_id);
2765                                 goto out;
2766                         }
2767                 }
2768                 /* If no active mac_id found, return first mac addr */
2769                 *pmac_id_valid = false;
2770                 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
2771                                                                 ETH_ALEN);
2772         }
2773
2774 out:
2775         spin_unlock_bh(&adapter->mcc_lock);
2776         pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
2777                         get_mac_list_cmd.va, get_mac_list_cmd.dma);
2778         return status;
2779 }
2780
2781 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id, u8 *mac)
2782 {
2783         bool active = true;
2784
2785         if (BEx_chip(adapter))
2786                 return be_cmd_mac_addr_query(adapter, mac, false,
2787                                              adapter->if_handle, curr_pmac_id);
2788         else
2789                 /* Fetch the MAC address using pmac_id */
2790                 return be_cmd_get_mac_from_list(adapter, mac, &active,
2791                                                 &curr_pmac_id, 0);
2792 }
2793
2794 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
2795 {
2796         int status;
2797         bool pmac_valid = false;
2798
2799         memset(mac, 0, ETH_ALEN);
2800
2801         if (BEx_chip(adapter)) {
2802                 if (be_physfn(adapter))
2803                         status = be_cmd_mac_addr_query(adapter, mac, true, 0,
2804                                                        0);
2805                 else
2806                         status = be_cmd_mac_addr_query(adapter, mac, false,
2807                                                        adapter->if_handle, 0);
2808         } else {
2809                 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
2810                                                   NULL, 0);
2811         }
2812
2813         return status;
2814 }
2815
2816 /* Uses synchronous MCCQ */
2817 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2818                         u8 mac_count, u32 domain)
2819 {
2820         struct be_mcc_wrb *wrb;
2821         struct be_cmd_req_set_mac_list *req;
2822         int status;
2823         struct be_dma_mem cmd;
2824
2825         memset(&cmd, 0, sizeof(struct be_dma_mem));
2826         cmd.size = sizeof(struct be_cmd_req_set_mac_list);
2827         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
2828                         &cmd.dma, GFP_KERNEL);
2829         if (!cmd.va)
2830                 return -ENOMEM;
2831
2832         spin_lock_bh(&adapter->mcc_lock);
2833
2834         wrb = wrb_from_mccq(adapter);
2835         if (!wrb) {
2836                 status = -EBUSY;
2837                 goto err;
2838         }
2839
2840         req = cmd.va;
2841         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2842                                 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
2843                                 wrb, &cmd);
2844
2845         req->hdr.domain = domain;
2846         req->mac_count = mac_count;
2847         if (mac_count)
2848                 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
2849
2850         status = be_mcc_notify_wait(adapter);
2851
2852 err:
2853         dma_free_coherent(&adapter->pdev->dev, cmd.size,
2854                                 cmd.va, cmd.dma);
2855         spin_unlock_bh(&adapter->mcc_lock);
2856         return status;
2857 }
2858
2859 /* Wrapper to delete any active MACs and provision the new mac.
2860  * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
2861  * current list are active.
2862  */
2863 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
2864 {
2865         bool active_mac = false;
2866         u8 old_mac[ETH_ALEN];
2867         u32 pmac_id;
2868         int status;
2869
2870         status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
2871                                           &pmac_id, dom);
2872         if (!status && active_mac)
2873                 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
2874
2875         return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
2876 }
2877
2878 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
2879                           u32 domain, u16 intf_id, u16 hsw_mode)
2880 {
2881         struct be_mcc_wrb *wrb;
2882         struct be_cmd_req_set_hsw_config *req;
2883         void *ctxt;
2884         int status;
2885
2886         spin_lock_bh(&adapter->mcc_lock);
2887
2888         wrb = wrb_from_mccq(adapter);
2889         if (!wrb) {
2890                 status = -EBUSY;
2891                 goto err;
2892         }
2893
2894         req = embedded_payload(wrb);
2895         ctxt = &req->context;
2896
2897         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2898                         OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2899
2900         req->hdr.domain = domain;
2901         AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
2902         if (pvid) {
2903                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
2904                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
2905         }
2906         if (!BEx_chip(adapter) && hsw_mode) {
2907                 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
2908                               ctxt, adapter->hba_port_num);
2909                 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
2910                 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
2911                               ctxt, hsw_mode);
2912         }
2913
2914         be_dws_cpu_to_le(req->context, sizeof(req->context));
2915         status = be_mcc_notify_wait(adapter);
2916
2917 err:
2918         spin_unlock_bh(&adapter->mcc_lock);
2919         return status;
2920 }
2921
2922 /* Get Hyper switch config */
2923 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
2924                           u32 domain, u16 intf_id, u8 *mode)
2925 {
2926         struct be_mcc_wrb *wrb;
2927         struct be_cmd_req_get_hsw_config *req;
2928         void *ctxt;
2929         int status;
2930         u16 vid;
2931
2932         spin_lock_bh(&adapter->mcc_lock);
2933
2934         wrb = wrb_from_mccq(adapter);
2935         if (!wrb) {
2936                 status = -EBUSY;
2937                 goto err;
2938         }
2939
2940         req = embedded_payload(wrb);
2941         ctxt = &req->context;
2942
2943         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2944                         OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2945
2946         req->hdr.domain = domain;
2947         AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
2948                       ctxt, intf_id);
2949         AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
2950
2951         if (!BEx_chip(adapter)) {
2952                 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
2953                               ctxt, adapter->hba_port_num);
2954                 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
2955         }
2956         be_dws_cpu_to_le(req->context, sizeof(req->context));
2957
2958         status = be_mcc_notify_wait(adapter);
2959         if (!status) {
2960                 struct be_cmd_resp_get_hsw_config *resp =
2961                                                 embedded_payload(wrb);
2962                 be_dws_le_to_cpu(&resp->context,
2963                                                 sizeof(resp->context));
2964                 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
2965                                                         pvid, &resp->context);
2966                 if (pvid)
2967                         *pvid = le16_to_cpu(vid);
2968                 if (mode)
2969                         *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
2970                                               port_fwd_type, &resp->context);
2971         }
2972
2973 err:
2974         spin_unlock_bh(&adapter->mcc_lock);
2975         return status;
2976 }
2977
2978 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
2979 {
2980         struct be_mcc_wrb *wrb;
2981         struct be_cmd_req_acpi_wol_magic_config_v1 *req;
2982         int status;
2983         int payload_len = sizeof(*req);
2984         struct be_dma_mem cmd;
2985
2986         if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
2987                             CMD_SUBSYSTEM_ETH))
2988                 return -EPERM;
2989
2990         if (mutex_lock_interruptible(&adapter->mbox_lock))
2991                 return -1;
2992
2993         memset(&cmd, 0, sizeof(struct be_dma_mem));
2994         cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
2995         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2996                                                &cmd.dma);
2997         if (!cmd.va) {
2998                 dev_err(&adapter->pdev->dev,
2999                                 "Memory allocation failure\n");
3000                 status = -ENOMEM;
3001                 goto err;
3002         }
3003
3004         wrb = wrb_from_mbox(adapter);
3005         if (!wrb) {
3006                 status = -EBUSY;
3007                 goto err;
3008         }
3009
3010         req = cmd.va;
3011
3012         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3013                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3014                                payload_len, wrb, &cmd);
3015
3016         req->hdr.version = 1;
3017         req->query_options = BE_GET_WOL_CAP;
3018
3019         status = be_mbox_notify_wait(adapter);
3020         if (!status) {
3021                 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
3022                 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va;
3023
3024                 /* the command could succeed misleadingly on old f/w
3025                  * which is not aware of the V1 version. fake an error. */
3026                 if (resp->hdr.response_length < payload_len) {
3027                         status = -1;
3028                         goto err;
3029                 }
3030                 adapter->wol_cap = resp->wol_settings;
3031         }
3032 err:
3033         mutex_unlock(&adapter->mbox_lock);
3034         if (cmd.va)
3035                 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3036         return status;
3037
3038 }
3039 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
3040                                    struct be_dma_mem *cmd)
3041 {
3042         struct be_mcc_wrb *wrb;
3043         struct be_cmd_req_get_ext_fat_caps *req;
3044         int status;
3045
3046         if (mutex_lock_interruptible(&adapter->mbox_lock))
3047                 return -1;
3048
3049         wrb = wrb_from_mbox(adapter);
3050         if (!wrb) {
3051                 status = -EBUSY;
3052                 goto err;
3053         }
3054
3055         req = cmd->va;
3056         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3057                                OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
3058                                cmd->size, wrb, cmd);
3059         req->parameter_type = cpu_to_le32(1);
3060
3061         status = be_mbox_notify_wait(adapter);
3062 err:
3063         mutex_unlock(&adapter->mbox_lock);
3064         return status;
3065 }
3066
3067 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
3068                                    struct be_dma_mem *cmd,
3069                                    struct be_fat_conf_params *configs)
3070 {
3071         struct be_mcc_wrb *wrb;
3072         struct be_cmd_req_set_ext_fat_caps *req;
3073         int status;
3074
3075         spin_lock_bh(&adapter->mcc_lock);
3076
3077         wrb = wrb_from_mccq(adapter);
3078         if (!wrb) {
3079                 status = -EBUSY;
3080                 goto err;
3081         }
3082
3083         req = cmd->va;
3084         memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
3085         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3086                                OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
3087                                cmd->size, wrb, cmd);
3088
3089         status = be_mcc_notify_wait(adapter);
3090 err:
3091         spin_unlock_bh(&adapter->mcc_lock);
3092         return status;
3093 }
3094
3095 int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name)
3096 {
3097         struct be_mcc_wrb *wrb;
3098         struct be_cmd_req_get_port_name *req;
3099         int status;
3100
3101         if (!lancer_chip(adapter)) {
3102                 *port_name = adapter->hba_port_num + '0';
3103                 return 0;
3104         }
3105
3106         spin_lock_bh(&adapter->mcc_lock);
3107
3108         wrb = wrb_from_mccq(adapter);
3109         if (!wrb) {
3110                 status = -EBUSY;
3111                 goto err;
3112         }
3113
3114         req = embedded_payload(wrb);
3115
3116         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3117                                OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
3118                                NULL);
3119         req->hdr.version = 1;
3120
3121         status = be_mcc_notify_wait(adapter);
3122         if (!status) {
3123                 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
3124                 *port_name = resp->port_name[adapter->hba_port_num];
3125         } else {
3126                 *port_name = adapter->hba_port_num + '0';
3127         }
3128 err:
3129         spin_unlock_bh(&adapter->mcc_lock);
3130         return status;
3131 }
3132
3133 static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count)
3134 {
3135         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3136         int i;
3137
3138         for (i = 0; i < desc_count; i++) {
3139                 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
3140                     hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1)
3141                         return (struct be_nic_res_desc *)hdr;
3142
3143                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3144                 hdr = (void *)hdr + hdr->desc_len;
3145         }
3146         return NULL;
3147 }
3148
3149 static struct be_pcie_res_desc *be_get_pcie_desc(u8 devfn, u8 *buf,
3150                                                  u32 desc_count)
3151 {
3152         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3153         struct be_pcie_res_desc *pcie;
3154         int i;
3155
3156         for (i = 0; i < desc_count; i++) {
3157                 if ((hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
3158                      hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1)) {
3159                         pcie = (struct be_pcie_res_desc *)hdr;
3160                         if (pcie->pf_num == devfn)
3161                                 return pcie;
3162                 }
3163
3164                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3165                 hdr = (void *)hdr + hdr->desc_len;
3166         }
3167         return NULL;
3168 }
3169
3170 static void be_copy_nic_desc(struct be_resources *res,
3171                              struct be_nic_res_desc *desc)
3172 {
3173         res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
3174         res->max_vlans = le16_to_cpu(desc->vlan_count);
3175         res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
3176         res->max_tx_qs = le16_to_cpu(desc->txq_count);
3177         res->max_rss_qs = le16_to_cpu(desc->rssq_count);
3178         res->max_rx_qs = le16_to_cpu(desc->rq_count);
3179         res->max_evt_qs = le16_to_cpu(desc->eq_count);
3180         /* Clear flags that driver is not interested in */
3181         res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
3182                                 BE_IF_CAP_FLAGS_WANT;
3183         /* Need 1 RXQ as the default RXQ */
3184         if (res->max_rss_qs && res->max_rss_qs == res->max_rx_qs)
3185                 res->max_rss_qs -= 1;
3186 }
3187
3188 /* Uses Mbox */
3189 int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
3190 {
3191         struct be_mcc_wrb *wrb;
3192         struct be_cmd_req_get_func_config *req;
3193         int status;
3194         struct be_dma_mem cmd;
3195
3196         if (mutex_lock_interruptible(&adapter->mbox_lock))
3197                 return -1;
3198
3199         memset(&cmd, 0, sizeof(struct be_dma_mem));
3200         cmd.size = sizeof(struct be_cmd_resp_get_func_config);
3201         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
3202                                       &cmd.dma);
3203         if (!cmd.va) {
3204                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3205                 status = -ENOMEM;
3206                 goto err;
3207         }
3208
3209         wrb = wrb_from_mbox(adapter);
3210         if (!wrb) {
3211                 status = -EBUSY;
3212                 goto err;
3213         }
3214
3215         req = cmd.va;
3216
3217         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3218                                OPCODE_COMMON_GET_FUNC_CONFIG,
3219                                cmd.size, wrb, &cmd);
3220
3221         if (skyhawk_chip(adapter))
3222                 req->hdr.version = 1;
3223
3224         status = be_mbox_notify_wait(adapter);
3225         if (!status) {
3226                 struct be_cmd_resp_get_func_config *resp = cmd.va;
3227                 u32 desc_count = le32_to_cpu(resp->desc_count);
3228                 struct be_nic_res_desc *desc;
3229
3230                 desc = be_get_nic_desc(resp->func_param, desc_count);
3231                 if (!desc) {
3232                         status = -EINVAL;
3233                         goto err;
3234                 }
3235
3236                 adapter->pf_number = desc->pf_num;
3237                 be_copy_nic_desc(res, desc);
3238         }
3239 err:
3240         mutex_unlock(&adapter->mbox_lock);
3241         if (cmd.va)
3242                 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3243         return status;
3244 }
3245
3246 /* Uses mbox */
3247 static int be_cmd_get_profile_config_mbox(struct be_adapter *adapter,
3248                                         u8 domain, struct be_dma_mem *cmd)
3249 {
3250         struct be_mcc_wrb *wrb;
3251         struct be_cmd_req_get_profile_config *req;
3252         int status;
3253
3254         if (mutex_lock_interruptible(&adapter->mbox_lock))
3255                 return -1;
3256         wrb = wrb_from_mbox(adapter);
3257
3258         req = cmd->va;
3259         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3260                                OPCODE_COMMON_GET_PROFILE_CONFIG,
3261                                cmd->size, wrb, cmd);
3262
3263         req->type = ACTIVE_PROFILE_TYPE;
3264         req->hdr.domain = domain;
3265         if (!lancer_chip(adapter))
3266                 req->hdr.version = 1;
3267
3268         status = be_mbox_notify_wait(adapter);
3269
3270         mutex_unlock(&adapter->mbox_lock);
3271         return status;
3272 }
3273
3274 /* Uses sync mcc */
3275 static int be_cmd_get_profile_config_mccq(struct be_adapter *adapter,
3276                                         u8 domain, struct be_dma_mem *cmd)
3277 {
3278         struct be_mcc_wrb *wrb;
3279         struct be_cmd_req_get_profile_config *req;
3280         int status;
3281
3282         spin_lock_bh(&adapter->mcc_lock);
3283
3284         wrb = wrb_from_mccq(adapter);
3285         if (!wrb) {
3286                 status = -EBUSY;
3287                 goto err;
3288         }
3289
3290         req = cmd->va;
3291         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3292                                OPCODE_COMMON_GET_PROFILE_CONFIG,
3293                                cmd->size, wrb, cmd);
3294
3295         req->type = ACTIVE_PROFILE_TYPE;
3296         req->hdr.domain = domain;
3297         if (!lancer_chip(adapter))
3298                 req->hdr.version = 1;
3299
3300         status = be_mcc_notify_wait(adapter);
3301
3302 err:
3303         spin_unlock_bh(&adapter->mcc_lock);
3304         return status;
3305 }
3306
3307 /* Uses sync mcc, if MCCQ is already created otherwise mbox */
3308 int be_cmd_get_profile_config(struct be_adapter *adapter,
3309                               struct be_resources *res, u8 domain)
3310 {
3311         struct be_cmd_resp_get_profile_config *resp;
3312         struct be_pcie_res_desc *pcie;
3313         struct be_nic_res_desc *nic;
3314         struct be_queue_info *mccq = &adapter->mcc_obj.q;
3315         struct be_dma_mem cmd;
3316         u32 desc_count;
3317         int status;
3318
3319         memset(&cmd, 0, sizeof(struct be_dma_mem));
3320         cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
3321         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
3322         if (!cmd.va)
3323                 return -ENOMEM;
3324
3325         if (!mccq->created)
3326                 status = be_cmd_get_profile_config_mbox(adapter, domain, &cmd);
3327         else
3328                 status = be_cmd_get_profile_config_mccq(adapter, domain, &cmd);
3329         if (status)
3330                 goto err;
3331
3332         resp = cmd.va;
3333         desc_count = le32_to_cpu(resp->desc_count);
3334
3335         pcie =  be_get_pcie_desc(adapter->pdev->devfn, resp->func_param,
3336                                  desc_count);
3337         if (pcie)
3338                 res->max_vfs = le16_to_cpu(pcie->num_vfs);
3339
3340         nic = be_get_nic_desc(resp->func_param, desc_count);
3341         if (nic)
3342                 be_copy_nic_desc(res, nic);
3343
3344 err:
3345         if (cmd.va)
3346                 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3347         return status;
3348 }
3349
3350 /* Currently only Lancer uses this command and it supports version 0 only
3351  * Uses sync mcc
3352  */
3353 int be_cmd_set_profile_config(struct be_adapter *adapter, u32 bps,
3354                               u8 domain)
3355 {
3356         struct be_mcc_wrb *wrb;
3357         struct be_cmd_req_set_profile_config *req;
3358         int status;
3359
3360         spin_lock_bh(&adapter->mcc_lock);
3361
3362         wrb = wrb_from_mccq(adapter);
3363         if (!wrb) {
3364                 status = -EBUSY;
3365                 goto err;
3366         }
3367
3368         req = embedded_payload(wrb);
3369
3370         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3371                                OPCODE_COMMON_SET_PROFILE_CONFIG, sizeof(*req),
3372                                wrb, NULL);
3373         req->hdr.domain = domain;
3374         req->desc_count = cpu_to_le32(1);
3375         req->nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
3376         req->nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
3377         req->nic_desc.flags = (1 << QUN) | (1 << IMM) | (1 << NOSV);
3378         req->nic_desc.pf_num = adapter->pf_number;
3379         req->nic_desc.vf_num = domain;
3380
3381         /* Mark fields invalid */
3382         req->nic_desc.unicast_mac_count = 0xFFFF;
3383         req->nic_desc.mcc_count = 0xFFFF;
3384         req->nic_desc.vlan_count = 0xFFFF;
3385         req->nic_desc.mcast_mac_count = 0xFFFF;
3386         req->nic_desc.txq_count = 0xFFFF;
3387         req->nic_desc.rq_count = 0xFFFF;
3388         req->nic_desc.rssq_count = 0xFFFF;
3389         req->nic_desc.lro_count = 0xFFFF;
3390         req->nic_desc.cq_count = 0xFFFF;
3391         req->nic_desc.toe_conn_count = 0xFFFF;
3392         req->nic_desc.eq_count = 0xFFFF;
3393         req->nic_desc.link_param = 0xFF;
3394         req->nic_desc.bw_min = 0xFFFFFFFF;
3395         req->nic_desc.acpi_params = 0xFF;
3396         req->nic_desc.wol_param = 0x0F;
3397
3398         /* Change BW */
3399         req->nic_desc.bw_min = cpu_to_le32(bps);
3400         req->nic_desc.bw_max = cpu_to_le32(bps);
3401         status = be_mcc_notify_wait(adapter);
3402 err:
3403         spin_unlock_bh(&adapter->mcc_lock);
3404         return status;
3405 }
3406
3407 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
3408                      int vf_num)
3409 {
3410         struct be_mcc_wrb *wrb;
3411         struct be_cmd_req_get_iface_list *req;
3412         struct be_cmd_resp_get_iface_list *resp;
3413         int status;
3414
3415         spin_lock_bh(&adapter->mcc_lock);
3416
3417         wrb = wrb_from_mccq(adapter);
3418         if (!wrb) {
3419                 status = -EBUSY;
3420                 goto err;
3421         }
3422         req = embedded_payload(wrb);
3423
3424         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3425                                OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
3426                                wrb, NULL);
3427         req->hdr.domain = vf_num + 1;
3428
3429         status = be_mcc_notify_wait(adapter);
3430         if (!status) {
3431                 resp = (struct be_cmd_resp_get_iface_list *)req;
3432                 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
3433         }
3434
3435 err:
3436         spin_unlock_bh(&adapter->mcc_lock);
3437         return status;
3438 }
3439
3440 static int lancer_wait_idle(struct be_adapter *adapter)
3441 {
3442 #define SLIPORT_IDLE_TIMEOUT 30
3443         u32 reg_val;
3444         int status = 0, i;
3445
3446         for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
3447                 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
3448                 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
3449                         break;
3450
3451                 ssleep(1);
3452         }
3453
3454         if (i == SLIPORT_IDLE_TIMEOUT)
3455                 status = -1;
3456
3457         return status;
3458 }
3459
3460 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
3461 {
3462         int status = 0;
3463
3464         status = lancer_wait_idle(adapter);
3465         if (status)
3466                 return status;
3467
3468         iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
3469
3470         return status;
3471 }
3472
3473 /* Routine to check whether dump image is present or not */
3474 bool dump_present(struct be_adapter *adapter)
3475 {
3476         u32 sliport_status = 0;
3477
3478         sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
3479         return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
3480 }
3481
3482 int lancer_initiate_dump(struct be_adapter *adapter)
3483 {
3484         int status;
3485
3486         /* give firmware reset and diagnostic dump */
3487         status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
3488                                      PHYSDEV_CONTROL_DD_MASK);
3489         if (status < 0) {
3490                 dev_err(&adapter->pdev->dev, "Firmware reset failed\n");
3491                 return status;
3492         }
3493
3494         status = lancer_wait_idle(adapter);
3495         if (status)
3496                 return status;
3497
3498         if (!dump_present(adapter)) {
3499                 dev_err(&adapter->pdev->dev, "Dump image not present\n");
3500                 return -1;
3501         }
3502
3503         return 0;
3504 }
3505
3506 /* Uses sync mcc */
3507 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
3508 {
3509         struct be_mcc_wrb *wrb;
3510         struct be_cmd_enable_disable_vf *req;
3511         int status;
3512
3513         if (!lancer_chip(adapter))
3514                 return 0;
3515
3516         spin_lock_bh(&adapter->mcc_lock);
3517
3518         wrb = wrb_from_mccq(adapter);
3519         if (!wrb) {
3520                 status = -EBUSY;
3521                 goto err;
3522         }
3523
3524         req = embedded_payload(wrb);
3525
3526         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3527                                OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
3528                                wrb, NULL);
3529
3530         req->hdr.domain = domain;
3531         req->enable = 1;
3532         status = be_mcc_notify_wait(adapter);
3533 err:
3534         spin_unlock_bh(&adapter->mcc_lock);
3535         return status;
3536 }
3537
3538 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
3539 {
3540         struct be_mcc_wrb *wrb;
3541         struct be_cmd_req_intr_set *req;
3542         int status;
3543
3544         if (mutex_lock_interruptible(&adapter->mbox_lock))
3545                 return -1;
3546
3547         wrb = wrb_from_mbox(adapter);
3548
3549         req = embedded_payload(wrb);
3550
3551         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3552                                OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
3553                                wrb, NULL);
3554
3555         req->intr_enabled = intr_enable;
3556
3557         status = be_mbox_notify_wait(adapter);
3558
3559         mutex_unlock(&adapter->mbox_lock);
3560         return status;
3561 }
3562
3563 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
3564                         int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
3565 {
3566         struct be_adapter *adapter = netdev_priv(netdev_handle);
3567         struct be_mcc_wrb *wrb;
3568         struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload;
3569         struct be_cmd_req_hdr *req;
3570         struct be_cmd_resp_hdr *resp;
3571         int status;
3572
3573         spin_lock_bh(&adapter->mcc_lock);
3574
3575         wrb = wrb_from_mccq(adapter);
3576         if (!wrb) {
3577                 status = -EBUSY;
3578                 goto err;
3579         }
3580         req = embedded_payload(wrb);
3581         resp = embedded_payload(wrb);
3582
3583         be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
3584                                hdr->opcode, wrb_payload_size, wrb, NULL);
3585         memcpy(req, wrb_payload, wrb_payload_size);
3586         be_dws_cpu_to_le(req, wrb_payload_size);
3587
3588         status = be_mcc_notify_wait(adapter);
3589         if (cmd_status)
3590                 *cmd_status = (status & 0xffff);
3591         if (ext_status)
3592                 *ext_status = 0;
3593         memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
3594         be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
3595 err:
3596         spin_unlock_bh(&adapter->mcc_lock);
3597         return status;
3598 }
3599 EXPORT_SYMBOL(be_roce_mcc_cmd);