drivers/net/ethernet/intel/i40e/i40e_type.h

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Driver
   4  * Copyright(c) 2013 - 2014 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #ifndef _I40E_TYPE_H_
  28 #define _I40E_TYPE_H_
  29
  30 #include "i40e_status.h"
  31 #include "i40e_osdep.h"
  32 #include "i40e_register.h"
  33 #include "i40e_adminq.h"
  34 #include "i40e_hmc.h"
  35 #include "i40e_lan_hmc.h"
  36
  37 /* Device IDs */
  38 #define I40E_DEV_ID_SFP_XL710           0x1572
  39 #define I40E_DEV_ID_QEMU                0x1574
  40 #define I40E_DEV_ID_KX_A                0x157F
  41 #define I40E_DEV_ID_KX_B                0x1580
  42 #define I40E_DEV_ID_KX_C                0x1581
  43 #define I40E_DEV_ID_QSFP_A              0x1583
  44 #define I40E_DEV_ID_QSFP_B              0x1584
  45 #define I40E_DEV_ID_QSFP_C              0x1585
  46 #define I40E_DEV_ID_10G_BASE_T          0x1586
  47 #define I40E_DEV_ID_VF                  0x154C
  48 #define I40E_DEV_ID_VF_HV               0x1571
  49
  50 #define i40e_is_40G_device(d)           ((d) == I40E_DEV_ID_QSFP_A  || \
  51                                          (d) == I40E_DEV_ID_QSFP_B  || \
  52                                          (d) == I40E_DEV_ID_QSFP_C)
  53
  54 /* I40E_MASK is a macro used on 32 bit registers */
  55 #define I40E_MASK(mask, shift) (mask << shift)
  56
  57 #define I40E_MAX_VSI_QP                 16
  58 #define I40E_MAX_VF_VSI                 3
  59 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  60 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  61
  62 /* Max default timeout in ms, */
  63 #define I40E_MAX_NVM_TIMEOUT            18000
  64
  65 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  66 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  67
  68 /* forward declaration */
  69 struct i40e_hw;
  70 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  71
  72 /* Data type manipulation macros. */
  73
  74 #define I40E_DESC_UNUSED(R)     \
  75         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  76         (R)->next_to_clean - (R)->next_to_use - 1)
  77
  78 /* bitfields for Tx queue mapping in QTX_CTL */
  79 #define I40E_QTX_CTL_VF_QUEUE   0x0
  80 #define I40E_QTX_CTL_VM_QUEUE   0x1
  81 #define I40E_QTX_CTL_PF_QUEUE   0x2
  82
  83 /* debug masks - set these bits in hw->debug_mask to control output */
  84 enum i40e_debug_mask {
  85         I40E_DEBUG_INIT                 = 0x00000001,
  86         I40E_DEBUG_RELEASE              = 0x00000002,
  87
  88         I40E_DEBUG_LINK                 = 0x00000010,
  89         I40E_DEBUG_PHY                  = 0x00000020,
  90         I40E_DEBUG_HMC                  = 0x00000040,
  91         I40E_DEBUG_NVM                  = 0x00000080,
  92         I40E_DEBUG_LAN                  = 0x00000100,
  93         I40E_DEBUG_FLOW                 = 0x00000200,
  94         I40E_DEBUG_DCB                  = 0x00000400,
  95         I40E_DEBUG_DIAG                 = 0x00000800,
  96         I40E_DEBUG_FD                   = 0x00001000,
  97
  98         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
  99         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 100         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 101         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 102         I40E_DEBUG_AQ                   = 0x0F000000,
 103
 104         I40E_DEBUG_USER                 = 0xF0000000,
 105
 106         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 107 };
 108
 109 /* These are structs for managing the hardware information and the operations.
 110  * The structures of function pointers are filled out at init time when we
 111  * know for sure exactly which hardware we're working with.  This gives us the
 112  * flexibility of using the same main driver code but adapting to slightly
 113  * different hardware needs as new parts are developed.  For this architecture,
 114  * the Firmware and AdminQ are intended to insulate the driver from most of the
 115  * future changes, but these structures will also do part of the job.
 116  */
 117 enum i40e_mac_type {
 118         I40E_MAC_UNKNOWN = 0,
 119         I40E_MAC_X710,
 120         I40E_MAC_XL710,
 121         I40E_MAC_VF,
 122         I40E_MAC_GENERIC,
 123 };
 124
 125 enum i40e_media_type {
 126         I40E_MEDIA_TYPE_UNKNOWN = 0,
 127         I40E_MEDIA_TYPE_FIBER,
 128         I40E_MEDIA_TYPE_BASET,
 129         I40E_MEDIA_TYPE_BACKPLANE,
 130         I40E_MEDIA_TYPE_CX4,
 131         I40E_MEDIA_TYPE_DA,
 132         I40E_MEDIA_TYPE_VIRTUAL
 133 };
 134
 135 enum i40e_fc_mode {
 136         I40E_FC_NONE = 0,
 137         I40E_FC_RX_PAUSE,
 138         I40E_FC_TX_PAUSE,
 139         I40E_FC_FULL,
 140         I40E_FC_PFC,
 141         I40E_FC_DEFAULT
 142 };
 143
 144 enum i40e_set_fc_aq_failures {
 145         I40E_SET_FC_AQ_FAIL_NONE = 0,
 146         I40E_SET_FC_AQ_FAIL_GET = 1,
 147         I40E_SET_FC_AQ_FAIL_SET = 2,
 148         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 149         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 150 };
 151
 152 enum i40e_vsi_type {
 153         I40E_VSI_MAIN = 0,
 154         I40E_VSI_VMDQ1,
 155         I40E_VSI_VMDQ2,
 156         I40E_VSI_CTRL,
 157         I40E_VSI_FCOE,
 158         I40E_VSI_MIRROR,
 159         I40E_VSI_SRIOV,
 160         I40E_VSI_FDIR,
 161         I40E_VSI_TYPE_UNKNOWN
 162 };
 163
 164 enum i40e_queue_type {
 165         I40E_QUEUE_TYPE_RX = 0,
 166         I40E_QUEUE_TYPE_TX,
 167         I40E_QUEUE_TYPE_PE_CEQ,
 168         I40E_QUEUE_TYPE_UNKNOWN
 169 };
 170
 171 struct i40e_link_status {
 172         enum i40e_aq_phy_type phy_type;
 173         enum i40e_aq_link_speed link_speed;
 174         u8 link_info;
 175         u8 an_info;
 176         u8 ext_info;
 177         u8 loopback;
 178         bool an_enabled;
 179         /* is Link Status Event notification to SW enabled */
 180         bool lse_enable;
 181         u16 max_frame_size;
 182         bool crc_enable;
 183         u8 pacing;
 184 };
 185
 186 struct i40e_phy_info {
 187         struct i40e_link_status link_info;
 188         struct i40e_link_status link_info_old;
 189         u32 autoneg_advertised;
 190         u32 phy_id;
 191         u32 module_type;
 192         bool get_link_info;
 193         enum i40e_media_type media_type;
 194 };
 195
 196 #define I40E_HW_CAP_MAX_GPIO                    30
 197 /* Capabilities of a PF or a VF or the whole device */
 198 struct i40e_hw_capabilities {
 199         u32  switch_mode;
 200 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 201 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 202 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 203
 204         u32  management_mode;
 205         u32  npar_enable;
 206         u32  os2bmc;
 207         u32  valid_functions;
 208         bool sr_iov_1_1;
 209         bool vmdq;
 210         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 211         bool evb_802_1_qbh; /* Bridge Port Extension */
 212         bool dcb;
 213         bool fcoe;
 214         bool mfp_mode_1;
 215         bool mgmt_cem;
 216         bool ieee_1588;
 217         bool iwarp;
 218         bool fd;
 219         u32 fd_filters_guaranteed;
 220         u32 fd_filters_best_effort;
 221         bool rss;
 222         u32 rss_table_size;
 223         u32 rss_table_entry_width;
 224         bool led[I40E_HW_CAP_MAX_GPIO];
 225         bool sdp[I40E_HW_CAP_MAX_GPIO];
 226         u32 nvm_image_type;
 227         u32 num_flow_director_filters;
 228         u32 num_vfs;
 229         u32 vf_base_id;
 230         u32 num_vsis;
 231         u32 num_rx_qp;
 232         u32 num_tx_qp;
 233         u32 base_queue;
 234         u32 num_msix_vectors;
 235         u32 num_msix_vectors_vf;
 236         u32 led_pin_num;
 237         u32 sdp_pin_num;
 238         u32 mdio_port_num;
 239         u32 mdio_port_mode;
 240         u8 rx_buf_chain_len;
 241         u32 enabled_tcmap;
 242         u32 maxtc;
 243 };
 244
 245 struct i40e_mac_info {
 246         enum i40e_mac_type type;
 247         u8 addr[ETH_ALEN];
 248         u8 perm_addr[ETH_ALEN];
 249         u8 san_addr[ETH_ALEN];
 250         u8 port_addr[ETH_ALEN];
 251         u16 max_fcoeq;
 252 };
 253
 254 enum i40e_aq_resources_ids {
 255         I40E_NVM_RESOURCE_ID = 1
 256 };
 257
 258 enum i40e_aq_resource_access_type {
 259         I40E_RESOURCE_READ = 1,
 260         I40E_RESOURCE_WRITE
 261 };
 262
 263 struct i40e_nvm_info {
 264         u64 hw_semaphore_timeout; /* 2usec global time (GTIME resolution) */
 265         u64 hw_semaphore_wait;    /* - || - */
 266         u32 timeout;              /* [ms] */
 267         u16 sr_size;              /* Shadow RAM size in words */
 268         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 269         u16 version;              /* NVM package version */
 270         u32 eetrack;              /* NVM data version */
 271 };
 272
 273 /* definitions used in NVM update support */
 274
 275 enum i40e_nvmupd_cmd {
 276         I40E_NVMUPD_INVALID,
 277         I40E_NVMUPD_READ_CON,
 278         I40E_NVMUPD_READ_SNT,
 279         I40E_NVMUPD_READ_LCB,
 280         I40E_NVMUPD_READ_SA,
 281         I40E_NVMUPD_WRITE_ERA,
 282         I40E_NVMUPD_WRITE_CON,
 283         I40E_NVMUPD_WRITE_SNT,
 284         I40E_NVMUPD_WRITE_LCB,
 285         I40E_NVMUPD_WRITE_SA,
 286         I40E_NVMUPD_CSUM_CON,
 287         I40E_NVMUPD_CSUM_SA,
 288         I40E_NVMUPD_CSUM_LCB,
 289 };
 290
 291 enum i40e_nvmupd_state {
 292         I40E_NVMUPD_STATE_INIT,
 293         I40E_NVMUPD_STATE_READING,
 294         I40E_NVMUPD_STATE_WRITING
 295 };
 296
 297 /* nvm_access definition and its masks/shifts need to be accessible to
 298  * application, core driver, and shared code.  Where is the right file?
 299  */
 300 #define I40E_NVM_READ   0xB
 301 #define I40E_NVM_WRITE  0xC
 302
 303 #define I40E_NVM_MOD_PNT_MASK 0xFF
 304
 305 #define I40E_NVM_TRANS_SHIFT    8
 306 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 307 #define I40E_NVM_CON            0x0
 308 #define I40E_NVM_SNT            0x1
 309 #define I40E_NVM_LCB            0x2
 310 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 311 #define I40E_NVM_ERA            0x4
 312 #define I40E_NVM_CSUM           0x8
 313
 314 #define I40E_NVM_ADAPT_SHIFT    16
 315 #define I40E_NVM_ADAPT_MASK     (0xffff << I40E_NVM_ADAPT_SHIFT)
 316
 317 #define I40E_NVMUPD_MAX_DATA    4096
 318 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 319
 320 struct i40e_nvm_access {
 321         u32 command;
 322         u32 config;
 323         u32 offset;     /* in bytes */
 324         u32 data_size;  /* in bytes */
 325         u8 data[1];
 326 };
 327
 328 /* PCI bus types */
 329 enum i40e_bus_type {
 330         i40e_bus_type_unknown = 0,
 331         i40e_bus_type_pci,
 332         i40e_bus_type_pcix,
 333         i40e_bus_type_pci_express,
 334         i40e_bus_type_reserved
 335 };
 336
 337 /* PCI bus speeds */
 338 enum i40e_bus_speed {
 339         i40e_bus_speed_unknown  = 0,
 340         i40e_bus_speed_33       = 33,
 341         i40e_bus_speed_66       = 66,
 342         i40e_bus_speed_100      = 100,
 343         i40e_bus_speed_120      = 120,
 344         i40e_bus_speed_133      = 133,
 345         i40e_bus_speed_2500     = 2500,
 346         i40e_bus_speed_5000     = 5000,
 347         i40e_bus_speed_8000     = 8000,
 348         i40e_bus_speed_reserved
 349 };
 350
 351 /* PCI bus widths */
 352 enum i40e_bus_width {
 353         i40e_bus_width_unknown  = 0,
 354         i40e_bus_width_pcie_x1  = 1,
 355         i40e_bus_width_pcie_x2  = 2,
 356         i40e_bus_width_pcie_x4  = 4,
 357         i40e_bus_width_pcie_x8  = 8,
 358         i40e_bus_width_32       = 32,
 359         i40e_bus_width_64       = 64,
 360         i40e_bus_width_reserved
 361 };
 362
 363 /* Bus parameters */
 364 struct i40e_bus_info {
 365         enum i40e_bus_speed speed;
 366         enum i40e_bus_width width;
 367         enum i40e_bus_type type;
 368
 369         u16 func;
 370         u16 device;
 371         u16 lan_id;
 372 };
 373
 374 /* Flow control (FC) parameters */
 375 struct i40e_fc_info {
 376         enum i40e_fc_mode current_mode; /* FC mode in effect */
 377         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 378 };
 379
 380 #define I40E_MAX_TRAFFIC_CLASS          8
 381 #define I40E_MAX_USER_PRIORITY          8
 382 #define I40E_DCBX_MAX_APPS              32
 383 #define I40E_LLDPDU_SIZE                1500
 384 #define I40E_TLV_STATUS_OPER            0x1
 385 #define I40E_TLV_STATUS_SYNC            0x2
 386 #define I40E_TLV_STATUS_ERR             0x4
 387 #define I40E_CEE_OPER_MAX_APPS          3
 388 #define I40E_APP_PROTOID_FCOE           0x8906
 389 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 390 #define I40E_APP_PROTOID_FIP            0x8914
 391 #define I40E_APP_SEL_ETHTYPE            0x1
 392 #define I40E_APP_SEL_TCPIP              0x2
 393
 394 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 395 struct i40e_dcb_ets_config {
 396         u8 willing;
 397         u8 cbs;
 398         u8 maxtcs;
 399         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 400         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 401         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 402 };
 403
 404 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 405 struct i40e_dcb_pfc_config {
 406         u8 willing;
 407         u8 mbc;
 408         u8 pfccap;
 409         u8 pfcenable;
 410 };
 411
 412 /* CEE or IEEE 802.1Qaz Application Priority data */
 413 struct i40e_dcb_app_priority_table {
 414         u8  priority;
 415         u8  selector;
 416         u16 protocolid;
 417 };
 418
 419 struct i40e_dcbx_config {
 420         u8  dcbx_mode;
 421 #define I40E_DCBX_MODE_CEE      0x1
 422 #define I40E_DCBX_MODE_IEEE     0x2
 423         u32 numapps;
 424         struct i40e_dcb_ets_config etscfg;
 425         struct i40e_dcb_ets_config etsrec;
 426         struct i40e_dcb_pfc_config pfc;
 427         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 428 };
 429
 430 /* Port hardware description */
 431 struct i40e_hw {
 432         u8 __iomem *hw_addr;
 433         void *back;
 434
 435         /* function pointer structs */
 436         struct i40e_phy_info phy;
 437         struct i40e_mac_info mac;
 438         struct i40e_bus_info bus;
 439         struct i40e_nvm_info nvm;
 440         struct i40e_fc_info fc;
 441
 442         /* pci info */
 443         u16 device_id;
 444         u16 vendor_id;
 445         u16 subsystem_device_id;
 446         u16 subsystem_vendor_id;
 447         u8 revision_id;
 448         u8 port;
 449         bool adapter_stopped;
 450
 451         /* capabilities for entire device and PCI func */
 452         struct i40e_hw_capabilities dev_caps;
 453         struct i40e_hw_capabilities func_caps;
 454
 455         /* Flow Director shared filter space */
 456         u16 fdir_shared_filter_count;
 457
 458         /* device profile info */
 459         u8  pf_id;
 460         u16 main_vsi_seid;
 461
 462         /* Closest numa node to the device */
 463         u16 numa_node;
 464
 465         /* Admin Queue info */
 466         struct i40e_adminq_info aq;
 467
 468         /* state of nvm update process */
 469         enum i40e_nvmupd_state nvmupd_state;
 470
 471         /* HMC info */
 472         struct i40e_hmc_info hmc; /* HMC info struct */
 473
 474         /* LLDP/DCBX Status */
 475         u16 dcbx_status;
 476
 477         /* DCBX info */
 478         struct i40e_dcbx_config local_dcbx_config;
 479         struct i40e_dcbx_config remote_dcbx_config;
 480
 481         /* debug mask */
 482         u32 debug_mask;
 483 };
 484
 485 struct i40e_driver_version {
 486         u8 major_version;
 487         u8 minor_version;
 488         u8 build_version;
 489         u8 subbuild_version;
 490         u8 driver_string[32];
 491 };
 492
 493 /* RX Descriptors */
 494 union i40e_16byte_rx_desc {
 495         struct {
 496                 __le64 pkt_addr; /* Packet buffer address */
 497                 __le64 hdr_addr; /* Header buffer address */
 498         } read;
 499         struct {
 500                 struct {
 501                         struct {
 502                                 union {
 503                                         __le16 mirroring_status;
 504                                         __le16 fcoe_ctx_id;
 505                                 } mirr_fcoe;
 506                                 __le16 l2tag1;
 507                         } lo_dword;
 508                         union {
 509                                 __le32 rss; /* RSS Hash */
 510                                 __le32 fd_id; /* Flow director filter id */
 511                                 __le32 fcoe_param; /* FCoE DDP Context id */
 512                         } hi_dword;
 513                 } qword0;
 514                 struct {
 515                         /* ext status/error/pktype/length */
 516                         __le64 status_error_len;
 517                 } qword1;
 518         } wb;  /* writeback */
 519 };
 520
 521 union i40e_32byte_rx_desc {
 522         struct {
 523                 __le64  pkt_addr; /* Packet buffer address */
 524                 __le64  hdr_addr; /* Header buffer address */
 525                         /* bit 0 of hdr_buffer_addr is DD bit */
 526                 __le64  rsvd1;
 527                 __le64  rsvd2;
 528         } read;
 529         struct {
 530                 struct {
 531                         struct {
 532                                 union {
 533                                         __le16 mirroring_status;
 534                                         __le16 fcoe_ctx_id;
 535                                 } mirr_fcoe;
 536                                 __le16 l2tag1;
 537                         } lo_dword;
 538                         union {
 539                                 __le32 rss; /* RSS Hash */
 540                                 __le32 fcoe_param; /* FCoE DDP Context id */
 541                                 /* Flow director filter id in case of
 542                                  * Programming status desc WB
 543                                  */
 544                                 __le32 fd_id;
 545                         } hi_dword;
 546                 } qword0;
 547                 struct {
 548                         /* status/error/pktype/length */
 549                         __le64 status_error_len;
 550                 } qword1;
 551                 struct {
 552                         __le16 ext_status; /* extended status */
 553                         __le16 rsvd;
 554                         __le16 l2tag2_1;
 555                         __le16 l2tag2_2;
 556                 } qword2;
 557                 struct {
 558                         union {
 559                                 __le32 flex_bytes_lo;
 560                                 __le32 pe_status;
 561                         } lo_dword;
 562                         union {
 563                                 __le32 flex_bytes_hi;
 564                                 __le32 fd_id;
 565                         } hi_dword;
 566                 } qword3;
 567         } wb;  /* writeback */
 568 };
 569
 570 enum i40e_rx_desc_status_bits {
 571         /* Note: These are predefined bit offsets */
 572         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 573         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 574         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 575         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 576         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 577         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 578         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 579         I40E_RX_DESC_STATUS_PIF_SHIFT           = 8,
 580         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 581         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 582         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 583         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 584         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 585         I40E_RX_DESC_STATUS_RESERVED_SHIFT      = 16, /* 2 BITS */
 586         I40E_RX_DESC_STATUS_UDP_0_SHIFT         = 18,
 587         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 588 };
 589
 590 #define I40E_RXD_QW1_STATUS_SHIFT       0
 591 #define I40E_RXD_QW1_STATUS_MASK        (((1 << I40E_RX_DESC_STATUS_LAST) - 1) \
 592                                          << I40E_RXD_QW1_STATUS_SHIFT)
 593
 594 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 595 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 596                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 597
 598 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 599 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK      (0x1UL << \
 600                                          I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 601
 602 enum i40e_rx_desc_fltstat_values {
 603         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 604         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 605         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 606         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 607 };
 608
 609 #define I40E_RXD_QW1_ERROR_SHIFT        19
 610 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 611
 612 enum i40e_rx_desc_error_bits {
 613         /* Note: These are predefined bit offsets */
 614         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 615         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 616         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 617         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 618         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 619         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 620         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 621         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 622         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 623 };
 624
 625 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 626         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 627         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 628         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 629         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 630         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 631 };
 632
 633 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 634 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 635
 636 /* Packet type non-ip values */
 637 enum i40e_rx_l2_ptype {
 638         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 639         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 640         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 641         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 642         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 643         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 644         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 645         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 646         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 647         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 648         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 649         I40E_RX_PTYPE_L2_ARP                            = 11,
 650         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 651         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 652         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 653         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 654         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 655         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 656         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 657         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 658         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 659         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 660         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 661         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 662         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 663         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 664 };
 665
 666 struct i40e_rx_ptype_decoded {
 667         u32 ptype:8;
 668         u32 known:1;
 669         u32 outer_ip:1;
 670         u32 outer_ip_ver:1;
 671         u32 outer_frag:1;
 672         u32 tunnel_type:3;
 673         u32 tunnel_end_prot:2;
 674         u32 tunnel_end_frag:1;
 675         u32 inner_prot:4;
 676         u32 payload_layer:3;
 677 };
 678
 679 enum i40e_rx_ptype_outer_ip {
 680         I40E_RX_PTYPE_OUTER_L2  = 0,
 681         I40E_RX_PTYPE_OUTER_IP  = 1
 682 };
 683
 684 enum i40e_rx_ptype_outer_ip_ver {
 685         I40E_RX_PTYPE_OUTER_NONE        = 0,
 686         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 687         I40E_RX_PTYPE_OUTER_IPV6        = 1
 688 };
 689
 690 enum i40e_rx_ptype_outer_fragmented {
 691         I40E_RX_PTYPE_NOT_FRAG  = 0,
 692         I40E_RX_PTYPE_FRAG      = 1
 693 };
 694
 695 enum i40e_rx_ptype_tunnel_type {
 696         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 697         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 698         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 699         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 700         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 701 };
 702
 703 enum i40e_rx_ptype_tunnel_end_prot {
 704         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 705         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 706         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 707 };
 708
 709 enum i40e_rx_ptype_inner_prot {
 710         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 711         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 712         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 713         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 714         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 715         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 716 };
 717
 718 enum i40e_rx_ptype_payload_layer {
 719         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 720         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 721         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 722         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 723 };
 724
 725 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 726 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 727                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 728
 729 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 730 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 731                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 732
 733 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 734 #define I40E_RXD_QW1_LENGTH_SPH_MASK    (0x1ULL << \
 735                                          I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 736
 737 enum i40e_rx_desc_ext_status_bits {
 738         /* Note: These are predefined bit offsets */
 739         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 740         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 741         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 742         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 743         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 744         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 745         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 746 };
 747
 748 enum i40e_rx_desc_pe_status_bits {
 749         /* Note: These are predefined bit offsets */
 750         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 751         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 752         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 753         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 754         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 755         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 756         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 757         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 758         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 759 };
 760
 761 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
 762 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 763
 764 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 765 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 766                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 767
 768 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 769 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 770                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 771
 772 enum i40e_rx_prog_status_desc_status_bits {
 773         /* Note: These are predefined bit offsets */
 774         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 775         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 776 };
 777
 778 enum i40e_rx_prog_status_desc_prog_id_masks {
 779         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 780         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 781         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 782 };
 783
 784 enum i40e_rx_prog_status_desc_error_bits {
 785         /* Note: These are predefined bit offsets */
 786         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 787         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
 788         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 789         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 790 };
 791
 792 /* TX Descriptor */
 793 struct i40e_tx_desc {
 794         __le64 buffer_addr; /* Address of descriptor's data buf */
 795         __le64 cmd_type_offset_bsz;
 796 };
 797
 798 #define I40E_TXD_QW1_DTYPE_SHIFT        0
 799 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
 800
 801 enum i40e_tx_desc_dtype_value {
 802         I40E_TX_DESC_DTYPE_DATA         = 0x0,
 803         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
 804         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
 805         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
 806         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
 807         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
 808         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
 809         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
 810         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
 811         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
 812 };
 813
 814 #define I40E_TXD_QW1_CMD_SHIFT  4
 815 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
 816
 817 enum i40e_tx_desc_cmd_bits {
 818         I40E_TX_DESC_CMD_EOP                    = 0x0001,
 819         I40E_TX_DESC_CMD_RS                     = 0x0002,
 820         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
 821         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
 822         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
 823         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
 824         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
 825         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
 826         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
 827         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
 828         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
 829         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
 830         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
 831         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
 832         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
 833         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
 834         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
 835         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
 836 };
 837
 838 #define I40E_TXD_QW1_OFFSET_SHIFT       16
 839 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
 840                                          I40E_TXD_QW1_OFFSET_SHIFT)
 841
 842 enum i40e_tx_desc_length_fields {
 843         /* Note: These are predefined bit offsets */
 844         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
 845         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
 846         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
 847 };
 848
 849 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
 850 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
 851                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
 852
 853 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
 854 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
 855
 856 /* Context descriptors */
 857 struct i40e_tx_context_desc {
 858         __le32 tunneling_params;
 859         __le16 l2tag2;
 860         __le16 rsvd;
 861         __le64 type_cmd_tso_mss;
 862 };
 863
 864 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
 865 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
 866
 867 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
 868 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
 869
 870 enum i40e_tx_ctx_desc_cmd_bits {
 871         I40E_TX_CTX_DESC_TSO            = 0x01,
 872         I40E_TX_CTX_DESC_TSYN           = 0x02,
 873         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
 874         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
 875         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
 876         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
 877         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
 878         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
 879         I40E_TX_CTX_DESC_SWPE           = 0x40
 880 };
 881
 882 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
 883 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
 884                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
 885
 886 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
 887 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
 888                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
 889
 890 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
 891 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
 892
 893 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
 894 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
 895                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
 896
 897 enum i40e_tx_ctx_desc_eipt_offload {
 898         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
 899         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
 900         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
 901         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
 902 };
 903
 904 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
 905 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
 906                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
 907
 908 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
 909 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 910
 911 #define I40E_TXD_CTX_UDP_TUNNELING      (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 912 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 913
 914 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
 915 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
 916                                          I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
 917
 918 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
 919
 920 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
 921 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
 922                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
 923
 924 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
 925 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
 926                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
 927
 928 struct i40e_filter_program_desc {
 929         __le32 qindex_flex_ptype_vsi;
 930         __le32 rsvd;
 931         __le32 dtype_cmd_cntindex;
 932         __le32 fd_id;
 933 };
 934 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
 935 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
 936                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
 937 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
 938 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
 939                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
 940 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
 941 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
 942                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
 943
 944 /* Packet Classifier Types for filters */
 945 enum i40e_filter_pctype {
 946         /* Note: Values 0-30 are reserved for future use */
 947         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
 948         /* Note: Value 32 is reserved for future use */
 949         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
 950         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
 951         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
 952         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
 953         /* Note: Values 37-40 are reserved for future use */
 954         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
 955         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
 956         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
 957         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
 958         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
 959         /* Note: Value 47 is reserved for future use */
 960         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
 961         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
 962         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
 963         /* Note: Values 51-62 are reserved for future use */
 964         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
 965 };
 966
 967 enum i40e_filter_program_desc_dest {
 968         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
 969         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
 970         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
 971 };
 972
 973 enum i40e_filter_program_desc_fd_status {
 974         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
 975         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
 976         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
 977         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
 978 };
 979
 980 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
 981 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
 982                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
 983
 984 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
 985 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
 986                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
 987
 988 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
 989 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
 990
 991 enum i40e_filter_program_desc_pcmd {
 992         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
 993         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
 994 };
 995
 996 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
 997 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
 998
 999 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1000 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  (0x1ULL << \
1001                                          I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1002
1003 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1004                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1005 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1006                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1007
1008 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1009 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1010                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1011
1012 enum i40e_filter_type {
1013         I40E_FLOW_DIRECTOR_FLTR = 0,
1014         I40E_PE_QUAD_HASH_FLTR = 1,
1015         I40E_ETHERTYPE_FLTR,
1016         I40E_FCOE_CTX_FLTR,
1017         I40E_MAC_VLAN_FLTR,
1018         I40E_HASH_FLTR
1019 };
1020
1021 struct i40e_vsi_context {
1022         u16 seid;
1023         u16 uplink_seid;
1024         u16 vsi_number;
1025         u16 vsis_allocated;
1026         u16 vsis_unallocated;
1027         u16 flags;
1028         u8 pf_num;
1029         u8 vf_num;
1030         u8 connection_type;
1031         struct i40e_aqc_vsi_properties_data info;
1032 };
1033
1034 struct i40e_veb_context {
1035         u16 seid;
1036         u16 uplink_seid;
1037         u16 veb_number;
1038         u16 vebs_allocated;
1039         u16 vebs_unallocated;
1040         u16 flags;
1041         struct i40e_aqc_get_veb_parameters_completion info;
1042 };
1043
1044 /* Statistics collected by each port, VSI, VEB, and S-channel */
1045 struct i40e_eth_stats {
1046         u64 rx_bytes;                   /* gorc */
1047         u64 rx_unicast;                 /* uprc */
1048         u64 rx_multicast;               /* mprc */
1049         u64 rx_broadcast;               /* bprc */
1050         u64 rx_discards;                /* rdpc */
1051         u64 rx_unknown_protocol;        /* rupp */
1052         u64 tx_bytes;                   /* gotc */
1053         u64 tx_unicast;                 /* uptc */
1054         u64 tx_multicast;               /* mptc */
1055         u64 tx_broadcast;               /* bptc */
1056         u64 tx_discards;                /* tdpc */
1057         u64 tx_errors;                  /* tepc */
1058 };
1059
1060 #ifdef I40E_FCOE
1061 /* Statistics collected per function for FCoE */
1062 struct i40e_fcoe_stats {
1063         u64 rx_fcoe_packets;            /* fcoeprc */
1064         u64 rx_fcoe_dwords;             /* focedwrc */
1065         u64 rx_fcoe_dropped;            /* fcoerpdc */
1066         u64 tx_fcoe_packets;            /* fcoeptc */
1067         u64 tx_fcoe_dwords;             /* focedwtc */
1068         u64 fcoe_bad_fccrc;             /* fcoecrc */
1069         u64 fcoe_last_error;            /* fcoelast */
1070         u64 fcoe_ddp_count;             /* fcoeddpc */
1071 };
1072
1073 /* offset to per function FCoE statistics block */
1074 #define I40E_FCOE_VF_STAT_OFFSET        0
1075 #define I40E_FCOE_PF_STAT_OFFSET        128
1076 #define I40E_FCOE_STAT_MAX              (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1077
1078 #endif
1079 /* Statistics collected by the MAC */
1080 struct i40e_hw_port_stats {
1081         /* eth stats collected by the port */
1082         struct i40e_eth_stats eth;
1083
1084         /* additional port specific stats */
1085         u64 tx_dropped_link_down;       /* tdold */
1086         u64 crc_errors;                 /* crcerrs */
1087         u64 illegal_bytes;              /* illerrc */
1088         u64 error_bytes;                /* errbc */
1089         u64 mac_local_faults;           /* mlfc */
1090         u64 mac_remote_faults;          /* mrfc */
1091         u64 rx_length_errors;           /* rlec */
1092         u64 link_xon_rx;                /* lxonrxc */
1093         u64 link_xoff_rx;               /* lxoffrxc */
1094         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1095         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1096         u64 link_xon_tx;                /* lxontxc */
1097         u64 link_xoff_tx;               /* lxofftxc */
1098         u64 priority_xon_tx[8];         /* pxontxc[8] */
1099         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1100         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1101         u64 rx_size_64;                 /* prc64 */
1102         u64 rx_size_127;                /* prc127 */
1103         u64 rx_size_255;                /* prc255 */
1104         u64 rx_size_511;                /* prc511 */
1105         u64 rx_size_1023;               /* prc1023 */
1106         u64 rx_size_1522;               /* prc1522 */
1107         u64 rx_size_big;                /* prc9522 */
1108         u64 rx_undersize;               /* ruc */
1109         u64 rx_fragments;               /* rfc */
1110         u64 rx_oversize;                /* roc */
1111         u64 rx_jabber;                  /* rjc */
1112         u64 tx_size_64;                 /* ptc64 */
1113         u64 tx_size_127;                /* ptc127 */
1114         u64 tx_size_255;                /* ptc255 */
1115         u64 tx_size_511;                /* ptc511 */
1116         u64 tx_size_1023;               /* ptc1023 */
1117         u64 tx_size_1522;               /* ptc1522 */
1118         u64 tx_size_big;                /* ptc9522 */
1119         u64 mac_short_packet_dropped;   /* mspdc */
1120         u64 checksum_error;             /* xec */
1121         /* flow director stats */
1122         u64 fd_atr_match;
1123         u64 fd_sb_match;
1124         /* EEE LPI */
1125         u32 tx_lpi_status;
1126         u32 rx_lpi_status;
1127         u64 tx_lpi_count;               /* etlpic */
1128         u64 rx_lpi_count;               /* erlpic */
1129 };
1130
1131 /* Checksum and Shadow RAM pointers */
1132 #define I40E_SR_NVM_CONTROL_WORD                0x00
1133 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1134 #define I40E_SR_NVM_IMAGE_VERSION               0x18
1135 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1136 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1137 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1138 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1139 #define I40E_SR_VPD_PTR                         0x2F
1140 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1141 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1142
1143 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1144 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1145 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1146 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1147 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1148
1149 /* Shadow RAM related */
1150 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1151 #define I40E_SR_WORDS_IN_1KB            512
1152 /* Checksum should be calculated such that after adding all the words,
1153  * including the checksum word itself, the sum should be 0xBABA.
1154  */
1155 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1156
1157 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1158
1159 #ifdef I40E_FCOE
1160 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1161
1162 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1163         I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND        = 0x00, /* 4 BITS */
1164         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2      = 0x01, /* 4 BITS */
1165         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3      = 0x05, /* 4 BITS */
1166         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2     = 0x02, /* 4 BITS */
1167         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3     = 0x06, /* 4 BITS */
1168         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2      = 0x03, /* 4 BITS */
1169         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3      = 0x07, /* 4 BITS */
1170         I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL       = 0x08, /* 4 BITS */
1171         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL       = 0x09, /* 4 BITS */
1172         I40E_FCOE_TX_CTX_DESC_RELOFF                    = 0x10,
1173         I40E_FCOE_TX_CTX_DESC_CLRSEQ                    = 0x20,
1174         I40E_FCOE_TX_CTX_DESC_DIFENA                    = 0x40,
1175         I40E_FCOE_TX_CTX_DESC_IL2TAG2                   = 0x80
1176 };
1177
1178 /* FCoE DDP Context descriptor */
1179 struct i40e_fcoe_ddp_context_desc {
1180         __le64 rsvd;
1181         __le64 type_cmd_foff_lsize;
1182 };
1183
1184 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT       0
1185 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK        (0xFULL << \
1186                                         I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1187
1188 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1189 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK  (0xFULL << \
1190                                          I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1191
1192 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1193         I40E_FCOE_DDP_CTX_DESC_BSIZE_512B       = 0x00, /* 2 BITS */
1194         I40E_FCOE_DDP_CTX_DESC_BSIZE_4K         = 0x01, /* 2 BITS */
1195         I40E_FCOE_DDP_CTX_DESC_BSIZE_8K         = 0x02, /* 2 BITS */
1196         I40E_FCOE_DDP_CTX_DESC_BSIZE_16K        = 0x03, /* 2 BITS */
1197         I40E_FCOE_DDP_CTX_DESC_DIFENA           = 0x04, /* 1 BIT  */
1198         I40E_FCOE_DDP_CTX_DESC_LASTSEQH         = 0x08, /* 1 BIT  */
1199 };
1200
1201 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT        16
1202 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1203                                          I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1204
1205 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT       32
1206 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK        (0x3FFFULL << \
1207                                         I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1208
1209 /* FCoE DDP/DWO Queue Context descriptor */
1210 struct i40e_fcoe_queue_context_desc {
1211         __le64 dmaindx_fbase;           /* 0:11 DMAINDX, 12:63 FBASE */
1212         __le64 flen_tph;                /* 0:12 FLEN, 13:15 TPH */
1213 };
1214
1215 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT   0
1216 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK    (0xFFFULL << \
1217                                         I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1218
1219 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT     12
1220 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK      (0xFFFFFFFFFFFFFULL << \
1221                                         I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1222
1223 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT      0
1224 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK       (0x1FFFULL << \
1225                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1226
1227 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT       13
1228 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK        (0x7ULL << \
1229                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1230
1231 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1232         I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC       = 0x1,
1233         I40E_FCOE_QUEUE_CTX_DESC_TPHDATA        = 0x2
1234 };
1235
1236 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT    30
1237 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK     (0x3ULL << \
1238                                         I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1239
1240 /* FCoE DDP/DWO Filter Context descriptor */
1241 struct i40e_fcoe_filter_context_desc {
1242         __le32 param;
1243         __le16 seqn;
1244
1245         /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1246         __le16 rsvd_dmaindx;
1247
1248         /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1249         __le64 flags_rsvd_lanq;
1250 };
1251
1252 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT  4
1253 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK   (0xFFF << \
1254                                         I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1255
1256 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1257         I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP      = 0x00,
1258         I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO      = 0x01,
1259         I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT    = 0x00,
1260         I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP     = 0x02,
1261         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2     = 0x00,
1262         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3     = 0x04
1263 };
1264
1265 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT    0
1266 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK     (0xFFULL << \
1267                                         I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1268
1269 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT     8
1270 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK      (0x3FULL << \
1271                         I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1272
1273 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT     53
1274 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK      (0x7FFULL << \
1275                         I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1276
1277 #endif /* I40E_FCOE */
1278 enum i40e_switch_element_types {
1279         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1280         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1281         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1282         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1283         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1284         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1285         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1286         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1287         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1288 };
1289
1290 /* Supported EtherType filters */
1291 enum i40e_ether_type_index {
1292         I40E_ETHER_TYPE_1588            = 0,
1293         I40E_ETHER_TYPE_FIP             = 1,
1294         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1295         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1296         I40E_ETHER_TYPE_LLDP            = 4,
1297         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1298         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1299         I40E_ETHER_TYPE_QCN_CNM         = 7,
1300         I40E_ETHER_TYPE_8021X           = 8,
1301         I40E_ETHER_TYPE_ARP             = 9,
1302         I40E_ETHER_TYPE_RSV1            = 10,
1303         I40E_ETHER_TYPE_RSV2            = 11,
1304 };
1305
1306 /* Filter context base size is 1K */
1307 #define I40E_HASH_FILTER_BASE_SIZE      1024
1308 /* Supported Hash filter values */
1309 enum i40e_hash_filter_size {
1310         I40E_HASH_FILTER_SIZE_1K        = 0,
1311         I40E_HASH_FILTER_SIZE_2K        = 1,
1312         I40E_HASH_FILTER_SIZE_4K        = 2,
1313         I40E_HASH_FILTER_SIZE_8K        = 3,
1314         I40E_HASH_FILTER_SIZE_16K       = 4,
1315         I40E_HASH_FILTER_SIZE_32K       = 5,
1316         I40E_HASH_FILTER_SIZE_64K       = 6,
1317         I40E_HASH_FILTER_SIZE_128K      = 7,
1318         I40E_HASH_FILTER_SIZE_256K      = 8,
1319         I40E_HASH_FILTER_SIZE_512K      = 9,
1320         I40E_HASH_FILTER_SIZE_1M        = 10,
1321 };
1322
1323 /* DMA context base size is 0.5K */
1324 #define I40E_DMA_CNTX_BASE_SIZE         512
1325 /* Supported DMA context values */
1326 enum i40e_dma_cntx_size {
1327         I40E_DMA_CNTX_SIZE_512          = 0,
1328         I40E_DMA_CNTX_SIZE_1K           = 1,
1329         I40E_DMA_CNTX_SIZE_2K           = 2,
1330         I40E_DMA_CNTX_SIZE_4K           = 3,
1331         I40E_DMA_CNTX_SIZE_8K           = 4,
1332         I40E_DMA_CNTX_SIZE_16K          = 5,
1333         I40E_DMA_CNTX_SIZE_32K          = 6,
1334         I40E_DMA_CNTX_SIZE_64K          = 7,
1335         I40E_DMA_CNTX_SIZE_128K         = 8,
1336         I40E_DMA_CNTX_SIZE_256K         = 9,
1337 };
1338
1339 /* Supported Hash look up table (LUT) sizes */
1340 enum i40e_hash_lut_size {
1341         I40E_HASH_LUT_SIZE_128          = 0,
1342         I40E_HASH_LUT_SIZE_512          = 1,
1343 };
1344
1345 /* Structure to hold a per PF filter control settings */
1346 struct i40e_filter_control_settings {
1347         /* number of PE Quad Hash filter buckets */
1348         enum i40e_hash_filter_size pe_filt_num;
1349         /* number of PE Quad Hash contexts */
1350         enum i40e_dma_cntx_size pe_cntx_num;
1351         /* number of FCoE filter buckets */
1352         enum i40e_hash_filter_size fcoe_filt_num;
1353         /* number of FCoE DDP contexts */
1354         enum i40e_dma_cntx_size fcoe_cntx_num;
1355         /* size of the Hash LUT */
1356         enum i40e_hash_lut_size hash_lut_size;
1357         /* enable FDIR filters for PF and its VFs */
1358         bool enable_fdir;
1359         /* enable Ethertype filters for PF and its VFs */
1360         bool enable_ethtype;
1361         /* enable MAC/VLAN filters for PF and its VFs */
1362         bool enable_macvlan;
1363 };
1364
1365 /* Structure to hold device level control filter counts */
1366 struct i40e_control_filter_stats {
1367         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1368         u16 etype_used;       /* Used perfect EtherType filters */
1369         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1370         u16 etype_free;       /* Un-used perfect EtherType filters */
1371 };
1372
1373 enum i40e_reset_type {
1374         I40E_RESET_POR          = 0,
1375         I40E_RESET_CORER        = 1,
1376         I40E_RESET_GLOBR        = 2,
1377         I40E_RESET_EMPR         = 3,
1378 };
1379
1380 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1381 #define I40E_NVM_LLDP_CFG_PTR           0xD
1382 struct i40e_lldp_variables {
1383         u16 length;
1384         u16 adminstatus;
1385         u16 msgfasttx;
1386         u16 msgtxinterval;
1387         u16 txparams;
1388         u16 timers;
1389         u16 crc8;
1390 };
1391
1392 /* RSS Hash Table Size */
1393 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1394 #endif /* _I40E_TYPE_H_ */