2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 #include <linux/bitops.h>
38 #include <linux/compiler.h>
39 #include <linux/list.h>
40 #include <linux/mutex.h>
41 #include <linux/netdevice.h>
42 #include <linux/if_vlan.h>
43 #include <linux/net_tstamp.h>
44 #ifdef CONFIG_MLX4_EN_DCB
45 #include <linux/dcbnl.h>
47 #include <linux/cpu_rmap.h>
48 #include <linux/ptp_clock_kernel.h>
50 #include <linux/mlx4/device.h>
51 #include <linux/mlx4/qp.h>
52 #include <linux/mlx4/cq.h>
53 #include <linux/mlx4/srq.h>
54 #include <linux/mlx4/doorbell.h>
55 #include <linux/mlx4/cmd.h>
59 #define DRV_NAME "mlx4_en"
60 #define DRV_VERSION "2.2-1"
61 #define DRV_RELDATE "Feb 2014"
63 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
70 #define MLX4_EN_PAGE_SHIFT 12
71 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
72 #define DEF_RX_RINGS 16
73 #define MAX_RX_RINGS 128
74 #define MIN_RX_RINGS 4
76 #define HEADROOM (2048 / TXBB_SIZE + 1)
77 #define STAMP_STRIDE 64
78 #define STAMP_DWORDS (STAMP_STRIDE / 4)
79 #define STAMP_SHIFT 31
80 #define STAMP_VAL 0x7fffffff
81 #define STATS_DELAY (HZ / 4)
82 #define SERVICE_TASK_DELAY (HZ / 4)
83 #define MAX_NUM_OF_FS_RULES 256
85 #define MLX4_EN_FILTER_HASH_SHIFT 4
86 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
88 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
89 #define MAX_DESC_SIZE 512
90 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
93 * OS related constants and tunables
96 #define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1
98 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
100 /* Use the maximum between 16384 and a single page */
101 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384)
103 #define MLX4_EN_ALLOC_PREFER_ORDER PAGE_ALLOC_COSTLY_ORDER
105 /* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU
106 * and 4K allocations) */
108 FRAG_SZ0 = 1536 - NET_IP_ALIGN,
111 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
113 #define MLX4_EN_MAX_RX_FRAGS 4
115 /* Maximum ring sizes */
116 #define MLX4_EN_MAX_TX_SIZE 8192
117 #define MLX4_EN_MAX_RX_SIZE 8192
119 /* Minimum ring size for our page-allocation scheme to work */
120 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
121 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
123 #define MLX4_EN_SMALL_PKT_SIZE 64
124 #define MLX4_EN_MAX_TX_RING_P_UP 32
125 #define MLX4_EN_NUM_UP 8
126 #define MLX4_EN_DEF_TX_RING_SIZE 512
127 #define MLX4_EN_DEF_RX_RING_SIZE 1024
128 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \
131 #define MLX4_EN_DEFAULT_TX_WORK 256
133 /* Target number of packets to coalesce with interrupt moderation */
134 #define MLX4_EN_RX_COAL_TARGET 44
135 #define MLX4_EN_RX_COAL_TIME 0x10
137 #define MLX4_EN_TX_COAL_PKTS 16
138 #define MLX4_EN_TX_COAL_TIME 0x10
140 #define MLX4_EN_RX_RATE_LOW 400000
141 #define MLX4_EN_RX_COAL_TIME_LOW 0
142 #define MLX4_EN_RX_RATE_HIGH 450000
143 #define MLX4_EN_RX_COAL_TIME_HIGH 128
144 #define MLX4_EN_RX_SIZE_THRESH 1024
145 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
146 #define MLX4_EN_SAMPLE_INTERVAL 0
147 #define MLX4_EN_AVG_PKT_SMALL 256
149 #define MLX4_EN_AUTO_CONF 0xffff
151 #define MLX4_EN_DEF_RX_PAUSE 1
152 #define MLX4_EN_DEF_TX_PAUSE 1
154 /* Interval between successive polls in the Tx routine when polling is used
155 instead of interrupts (in per-core Tx rings) - should be power of 2 */
156 #define MLX4_EN_TX_POLL_MODER 16
157 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
159 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
160 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
161 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
163 #define MLX4_EN_MIN_MTU 46
164 #define ETH_BCAST 0xffffffffffffULL
166 #define MLX4_EN_LOOPBACK_RETRIES 5
167 #define MLX4_EN_LOOPBACK_TIMEOUT 100
169 #ifdef MLX4_EN_PERF_STAT
170 /* Number of samples to 'average' */
172 #define AVG_FACTOR 1024
173 #define NUM_PERF_STATS NUM_PERF_COUNTERS
175 #define INC_PERF_COUNTER(cnt) (++(cnt))
176 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
177 #define AVG_PERF_COUNTER(cnt, sample) \
178 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
179 #define GET_PERF_COUNTER(cnt) (cnt)
180 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
184 #define NUM_PERF_STATS 0
185 #define INC_PERF_COUNTER(cnt) do {} while (0)
186 #define ADD_PERF_COUNTER(cnt, add) do {} while (0)
187 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
188 #define GET_PERF_COUNTER(cnt) (0)
189 #define GET_AVG_PERF_COUNTER(cnt) (0)
190 #endif /* MLX4_EN_PERF_STAT */
192 /* Constants for TX flow */
194 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
212 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
213 #define XNOR(x, y) (!(x) == !(y))
216 struct mlx4_en_tx_info {
227 #define MLX4_EN_BIT_DESC_OWN 0x80000000
228 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
229 #define MLX4_EN_MEMTYPE_PAD 0x100
230 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
233 struct mlx4_en_tx_desc {
234 struct mlx4_wqe_ctrl_seg ctrl;
236 struct mlx4_wqe_data_seg data; /* at least one data segment */
237 struct mlx4_wqe_lso_seg lso;
238 struct mlx4_wqe_inline_seg inl;
242 #define MLX4_EN_USE_SRQ 0x01000000
244 #define MLX4_EN_CX3_LOW_ID 0x1000
245 #define MLX4_EN_CX3_HIGH_ID 0x1005
247 struct mlx4_en_rx_alloc {
254 struct mlx4_en_tx_ring {
255 struct mlx4_hwq_resources wqres;
256 u32 size ; /* number of TXBBs */
259 u16 cqn; /* index of port CQ associated with this ring */
266 struct mlx4_en_tx_info *tx_info;
269 cpumask_t affinity_mask;
272 struct mlx4_qp_context context;
274 enum mlx4_qp_state qp_state;
275 struct mlx4_srq dummy;
277 unsigned long packets;
278 unsigned long tx_csum;
279 unsigned long queue_stopped;
280 unsigned long wake_queue;
284 struct netdev_queue *tx_queue;
285 int hwtstamp_tx_type;
289 struct mlx4_en_rx_desc {
290 /* actual number of entries depends on rx ring stride */
291 struct mlx4_wqe_data_seg data[0];
294 struct mlx4_en_rx_ring {
295 struct mlx4_hwq_resources wqres;
296 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
297 u32 size ; /* number of Rx descs*/
302 u16 cqn; /* index of port CQ associated with this ring */
310 unsigned long packets;
311 #ifdef CONFIG_NET_RX_BUSY_POLL
312 unsigned long yields;
313 unsigned long misses;
314 unsigned long cleaned;
316 unsigned long csum_ok;
317 unsigned long csum_none;
318 int hwtstamp_rx_filter;
319 cpumask_var_t affinity_mask;
324 struct mlx4_hwq_resources wqres;
326 struct net_device *dev;
327 struct napi_struct napi;
334 struct mlx4_cqe *buf;
335 #define MLX4_EN_OPCODE_ERROR 0x1e
337 #ifdef CONFIG_NET_RX_BUSY_POLL
339 #define MLX4_EN_CQ_STATE_IDLE 0
340 #define MLX4_EN_CQ_STATE_NAPI 1 /* NAPI owns this CQ */
341 #define MLX4_EN_CQ_STATE_POLL 2 /* poll owns this CQ */
342 #define MLX4_CQ_LOCKED (MLX4_EN_CQ_STATE_NAPI | MLX4_EN_CQ_STATE_POLL)
343 #define MLX4_EN_CQ_STATE_NAPI_YIELD 4 /* NAPI yielded this CQ */
344 #define MLX4_EN_CQ_STATE_POLL_YIELD 8 /* poll yielded this CQ */
345 #define CQ_YIELD (MLX4_EN_CQ_STATE_NAPI_YIELD | MLX4_EN_CQ_STATE_POLL_YIELD)
346 #define CQ_USER_PEND (MLX4_EN_CQ_STATE_POLL | MLX4_EN_CQ_STATE_POLL_YIELD)
347 spinlock_t poll_lock; /* protects from LLS/napi conflicts */
348 #endif /* CONFIG_NET_RX_BUSY_POLL */
349 struct irq_desc *irq_desc;
352 struct mlx4_en_port_profile {
366 struct mlx4_en_profile {
373 u8 num_tx_rings_p_up;
374 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
378 struct mlx4_dev *dev;
379 struct pci_dev *pdev;
380 struct mutex state_lock;
381 struct net_device *pndev[MLX4_MAX_PORTS + 1];
384 struct mlx4_en_profile profile;
386 struct workqueue_struct *workqueue;
387 struct device *dma_device;
388 void __iomem *uar_map;
389 struct mlx4_uar priv_uar;
393 u8 mac_removed[MLX4_MAX_PORTS + 1];
396 struct cyclecounter cycles;
397 struct timecounter clock;
398 unsigned long last_overflow_check;
399 unsigned long overflow_period;
400 struct ptp_clock *ptp_clock;
401 struct ptp_clock_info ptp_clock_info;
405 struct mlx4_en_rss_map {
407 struct mlx4_qp qps[MAX_RX_RINGS];
408 enum mlx4_qp_state state[MAX_RX_RINGS];
409 struct mlx4_qp indir_qp;
410 enum mlx4_qp_state indir_state;
413 struct mlx4_en_port_state {
419 struct mlx4_en_pkt_stats {
420 unsigned long broadcast;
421 unsigned long rx_prio[8];
422 unsigned long tx_prio[8];
423 #define NUM_PKT_STATS 17
426 struct mlx4_en_port_stats {
427 unsigned long tso_packets;
428 unsigned long queue_stopped;
429 unsigned long wake_queue;
430 unsigned long tx_timeout;
431 unsigned long rx_alloc_failed;
432 unsigned long rx_chksum_good;
433 unsigned long rx_chksum_none;
434 unsigned long tx_chksum_offload;
435 #define NUM_PORT_STATS 8
438 struct mlx4_en_perf_stats {
445 #define NUM_PERF_COUNTERS 6
448 enum mlx4_en_mclist_act {
454 struct mlx4_en_mc_list {
455 struct list_head list;
456 enum mlx4_en_mclist_act action;
462 struct mlx4_en_frag_info {
464 u16 frag_prefix_size;
469 #ifdef CONFIG_MLX4_EN_DCB
470 /* Minimal TC BW - setting to 0 will block traffic */
471 #define MLX4_EN_BW_MIN 1
472 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
474 #define MLX4_EN_TC_ETS 7
478 struct ethtool_flow_id {
479 struct list_head list;
480 struct ethtool_rx_flow_spec flow_spec;
485 MLX4_EN_FLAG_PROMISC = (1 << 0),
486 MLX4_EN_FLAG_MC_PROMISC = (1 << 1),
487 /* whether we need to enable hardware loopback by putting dmac
490 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),
491 /* whether we need to drop packets that hardware loopback-ed */
492 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3),
493 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4)
496 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
497 #define MLX4_EN_MAC_HASH_IDX 5
499 struct mlx4_en_priv {
500 struct mlx4_en_dev *mdev;
501 struct mlx4_en_port_profile *prof;
502 struct net_device *dev;
503 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
504 struct net_device_stats stats;
505 struct net_device_stats ret_stats;
506 struct mlx4_en_port_state port_state;
507 spinlock_t stats_lock;
508 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
509 /* To allow rules removal while port is going down */
510 struct list_head ethtool_list;
512 unsigned long last_moder_packets[MAX_RX_RINGS];
513 unsigned long last_moder_tx_packets;
514 unsigned long last_moder_bytes[MAX_RX_RINGS];
515 unsigned long last_moder_jiffies;
516 int last_moder_time[MAX_RX_RINGS];
526 u16 adaptive_rx_coal;
529 u32 validate_loopback;
531 struct mlx4_hwq_resources res;
539 unsigned char current_mac[ETH_ALEN + 2];
545 struct mlx4_en_rss_map rss_map;
548 u8 num_tx_rings_p_up;
553 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
557 struct mlx4_en_tx_ring **tx_ring;
558 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
559 struct mlx4_en_cq **tx_cq;
560 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
561 struct mlx4_qp drop_qp;
562 struct work_struct rx_mode_task;
563 struct work_struct watchdog_task;
564 struct work_struct linkstate_task;
565 struct delayed_work stats_task;
566 struct delayed_work service_task;
567 #ifdef CONFIG_MLX4_EN_VXLAN
568 struct work_struct vxlan_add_task;
569 struct work_struct vxlan_del_task;
571 struct mlx4_en_perf_stats pstats;
572 struct mlx4_en_pkt_stats pkstats;
573 struct mlx4_en_port_stats port_stats;
575 struct list_head mc_list;
576 struct list_head curr_list;
578 struct mlx4_en_stat_out_mbox hw_stats;
583 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];
584 struct hwtstamp_config hwtstamp_config;
586 #ifdef CONFIG_MLX4_EN_DCB
588 u16 maxrate[IEEE_8021QAZ_MAX_TCS];
590 #ifdef CONFIG_RFS_ACCEL
591 spinlock_t filters_lock;
593 struct list_head filters;
594 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
603 MLX4_EN_WOL_MAGIC = (1ULL << 61),
604 MLX4_EN_WOL_ENABLED = (1ULL << 62),
607 struct mlx4_mac_entry {
608 struct hlist_node hlist;
609 unsigned char mac[ETH_ALEN + 2];
614 #ifdef CONFIG_NET_RX_BUSY_POLL
615 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
617 spin_lock_init(&cq->poll_lock);
618 cq->state = MLX4_EN_CQ_STATE_IDLE;
621 /* called from the device poll rutine to get ownership of a cq */
622 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
625 spin_lock(&cq->poll_lock);
626 if (cq->state & MLX4_CQ_LOCKED) {
627 WARN_ON(cq->state & MLX4_EN_CQ_STATE_NAPI);
628 cq->state |= MLX4_EN_CQ_STATE_NAPI_YIELD;
631 /* we don't care if someone yielded */
632 cq->state = MLX4_EN_CQ_STATE_NAPI;
633 spin_unlock(&cq->poll_lock);
637 /* returns true is someone tried to get the cq while napi had it */
638 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
641 spin_lock(&cq->poll_lock);
642 WARN_ON(cq->state & (MLX4_EN_CQ_STATE_POLL |
643 MLX4_EN_CQ_STATE_NAPI_YIELD));
645 if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD)
647 cq->state = MLX4_EN_CQ_STATE_IDLE;
648 spin_unlock(&cq->poll_lock);
652 /* called from mlx4_en_low_latency_poll() */
653 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
656 spin_lock_bh(&cq->poll_lock);
657 if ((cq->state & MLX4_CQ_LOCKED)) {
658 struct net_device *dev = cq->dev;
659 struct mlx4_en_priv *priv = netdev_priv(dev);
660 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring];
662 cq->state |= MLX4_EN_CQ_STATE_POLL_YIELD;
666 /* preserve yield marks */
667 cq->state |= MLX4_EN_CQ_STATE_POLL;
668 spin_unlock_bh(&cq->poll_lock);
672 /* returns true if someone tried to get the cq while it was locked */
673 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
676 spin_lock_bh(&cq->poll_lock);
677 WARN_ON(cq->state & (MLX4_EN_CQ_STATE_NAPI));
679 if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD)
681 cq->state = MLX4_EN_CQ_STATE_IDLE;
682 spin_unlock_bh(&cq->poll_lock);
686 /* true if a socket is polling, even if it did not get the lock */
687 static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq)
689 WARN_ON(!(cq->state & MLX4_CQ_LOCKED));
690 return cq->state & CQ_USER_PEND;
693 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
697 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
702 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
707 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
712 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
717 static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq)
721 #endif /* CONFIG_NET_RX_BUSY_POLL */
723 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
725 void mlx4_en_update_loopback_state(struct net_device *dev,
726 netdev_features_t features);
728 void mlx4_en_destroy_netdev(struct net_device *dev);
729 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
730 struct mlx4_en_port_profile *prof);
732 int mlx4_en_start_port(struct net_device *dev);
733 void mlx4_en_stop_port(struct net_device *dev, int detach);
735 void mlx4_en_free_resources(struct mlx4_en_priv *priv);
736 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
738 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
739 int entries, int ring, enum cq_type mode, int node);
740 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
741 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
743 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
744 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
745 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
747 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
748 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
749 void *accel_priv, select_queue_fallback_t fallback);
750 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
752 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
753 struct mlx4_en_tx_ring **pring,
754 int qpn, u32 size, u16 stride,
755 int node, int queue_index);
756 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
757 struct mlx4_en_tx_ring **pring);
758 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
759 struct mlx4_en_tx_ring *ring,
760 int cq, int user_prio);
761 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
762 struct mlx4_en_tx_ring *ring);
763 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev);
764 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
765 struct mlx4_en_rx_ring **pring,
766 u32 size, u16 stride, int node);
767 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
768 struct mlx4_en_rx_ring **pring,
769 u32 size, u16 stride);
770 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
771 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
772 struct mlx4_en_rx_ring *ring);
773 int mlx4_en_process_rx_cq(struct net_device *dev,
774 struct mlx4_en_cq *cq,
776 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
777 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget);
778 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
779 int is_tx, int rss, int qpn, int cqn, int user_prio,
780 struct mlx4_qp_context *context);
781 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
782 int mlx4_en_map_buffer(struct mlx4_buf *buf);
783 void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
785 void mlx4_en_calc_rx_buf(struct net_device *dev);
786 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
787 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
788 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
789 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
790 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
791 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
793 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
794 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
796 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
797 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
799 #ifdef CONFIG_MLX4_EN_DCB
800 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
801 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
804 int mlx4_en_setup_tc(struct net_device *dev, u8 up);
806 #ifdef CONFIG_RFS_ACCEL
807 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv);
810 #define MLX4_EN_NUM_SELF_TEST 5
811 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
812 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
815 * Functions for time stamping
817 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
818 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,
819 struct skb_shared_hwtstamps *hwts,
821 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev);
822 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev);
823 int mlx4_en_timestamp_config(struct net_device *dev,
829 extern const struct ethtool_ops mlx4_en_ethtool_ops;
834 * printk / logging functions
838 int en_print(const char *level, const struct mlx4_en_priv *priv,
839 const char *format, ...);
841 #define en_dbg(mlevel, priv, format, ...) \
843 if (NETIF_MSG_##mlevel & (priv)->msg_enable) \
844 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__); \
846 #define en_warn(priv, format, ...) \
847 en_print(KERN_WARNING, priv, format, ##__VA_ARGS__)
848 #define en_err(priv, format, ...) \
849 en_print(KERN_ERR, priv, format, ##__VA_ARGS__)
850 #define en_info(priv, format, ...) \
851 en_print(KERN_INFO, priv, format, ##__VA_ARGS__)
853 #define mlx4_err(mdev, format, ...) \
854 pr_err(DRV_NAME " %s: " format, \
855 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
856 #define mlx4_info(mdev, format, ...) \
857 pr_info(DRV_NAME " %s: " format, \
858 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
859 #define mlx4_warn(mdev, format, ...) \
860 pr_warn(DRV_NAME " %s: " format, \
861 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)