2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 #include <linux/bitops.h>
38 #include <linux/compiler.h>
39 #include <linux/list.h>
40 #include <linux/mutex.h>
41 #include <linux/netdevice.h>
42 #include <linux/if_vlan.h>
43 #include <linux/net_tstamp.h>
44 #ifdef CONFIG_MLX4_EN_DCB
45 #include <linux/dcbnl.h>
47 #include <linux/cpu_rmap.h>
48 #include <linux/ptp_clock_kernel.h>
50 #include <linux/mlx4/device.h>
51 #include <linux/mlx4/qp.h>
52 #include <linux/mlx4/cq.h>
53 #include <linux/mlx4/srq.h>
54 #include <linux/mlx4/doorbell.h>
55 #include <linux/mlx4/cmd.h>
59 #define DRV_NAME "mlx4_en"
60 #define DRV_VERSION "2.2-1"
61 #define DRV_RELDATE "Feb 2014"
63 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
70 #define MLX4_EN_PAGE_SHIFT 12
71 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
72 #define DEF_RX_RINGS 16
73 #define MAX_RX_RINGS 128
74 #define MIN_RX_RINGS 4
76 #define HEADROOM (2048 / TXBB_SIZE + 1)
77 #define STAMP_STRIDE 64
78 #define STAMP_DWORDS (STAMP_STRIDE / 4)
79 #define STAMP_SHIFT 31
80 #define STAMP_VAL 0x7fffffff
81 #define STATS_DELAY (HZ / 4)
82 #define SERVICE_TASK_DELAY (HZ / 4)
83 #define MAX_NUM_OF_FS_RULES 256
85 #define MLX4_EN_FILTER_HASH_SHIFT 4
86 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
88 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
89 #define MAX_DESC_SIZE 512
90 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
93 * OS related constants and tunables
96 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
98 /* Use the maximum between 16384 and a single page */
99 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384)
101 #define MLX4_EN_ALLOC_PREFER_ORDER PAGE_ALLOC_COSTLY_ORDER
103 /* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU
104 * and 4K allocations) */
106 FRAG_SZ0 = 1536 - NET_IP_ALIGN,
109 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
111 #define MLX4_EN_MAX_RX_FRAGS 4
113 /* Maximum ring sizes */
114 #define MLX4_EN_MAX_TX_SIZE 8192
115 #define MLX4_EN_MAX_RX_SIZE 8192
117 /* Minimum ring size for our page-allocation scheme to work */
118 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
119 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
121 #define MLX4_EN_SMALL_PKT_SIZE 64
122 #define MLX4_EN_MAX_TX_RING_P_UP 32
123 #define MLX4_EN_NUM_UP 8
124 #define MLX4_EN_DEF_TX_RING_SIZE 512
125 #define MLX4_EN_DEF_RX_RING_SIZE 1024
126 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \
129 /* Target number of packets to coalesce with interrupt moderation */
130 #define MLX4_EN_RX_COAL_TARGET 44
131 #define MLX4_EN_RX_COAL_TIME 0x10
133 #define MLX4_EN_TX_COAL_PKTS 16
134 #define MLX4_EN_TX_COAL_TIME 0x10
136 #define MLX4_EN_RX_RATE_LOW 400000
137 #define MLX4_EN_RX_COAL_TIME_LOW 0
138 #define MLX4_EN_RX_RATE_HIGH 450000
139 #define MLX4_EN_RX_COAL_TIME_HIGH 128
140 #define MLX4_EN_RX_SIZE_THRESH 1024
141 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
142 #define MLX4_EN_SAMPLE_INTERVAL 0
143 #define MLX4_EN_AVG_PKT_SMALL 256
145 #define MLX4_EN_AUTO_CONF 0xffff
147 #define MLX4_EN_DEF_RX_PAUSE 1
148 #define MLX4_EN_DEF_TX_PAUSE 1
150 /* Interval between successive polls in the Tx routine when polling is used
151 instead of interrupts (in per-core Tx rings) - should be power of 2 */
152 #define MLX4_EN_TX_POLL_MODER 16
153 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
155 #define ETH_LLC_SNAP_SIZE 8
157 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
158 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
159 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
161 #define MLX4_EN_MIN_MTU 46
162 #define ETH_BCAST 0xffffffffffffULL
164 #define MLX4_EN_LOOPBACK_RETRIES 5
165 #define MLX4_EN_LOOPBACK_TIMEOUT 100
167 #ifdef MLX4_EN_PERF_STAT
168 /* Number of samples to 'average' */
170 #define AVG_FACTOR 1024
171 #define NUM_PERF_STATS NUM_PERF_COUNTERS
173 #define INC_PERF_COUNTER(cnt) (++(cnt))
174 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
175 #define AVG_PERF_COUNTER(cnt, sample) \
176 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
177 #define GET_PERF_COUNTER(cnt) (cnt)
178 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
182 #define NUM_PERF_STATS 0
183 #define INC_PERF_COUNTER(cnt) do {} while (0)
184 #define ADD_PERF_COUNTER(cnt, add) do {} while (0)
185 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
186 #define GET_PERF_COUNTER(cnt) (0)
187 #define GET_AVG_PERF_COUNTER(cnt) (0)
188 #endif /* MLX4_EN_PERF_STAT */
190 /* Constants for TX flow */
192 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
210 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
211 #define XNOR(x, y) (!(x) == !(y))
214 struct mlx4_en_tx_info {
225 #define MLX4_EN_BIT_DESC_OWN 0x80000000
226 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
227 #define MLX4_EN_MEMTYPE_PAD 0x100
228 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
231 struct mlx4_en_tx_desc {
232 struct mlx4_wqe_ctrl_seg ctrl;
234 struct mlx4_wqe_data_seg data; /* at least one data segment */
235 struct mlx4_wqe_lso_seg lso;
236 struct mlx4_wqe_inline_seg inl;
240 #define MLX4_EN_USE_SRQ 0x01000000
242 #define MLX4_EN_CX3_LOW_ID 0x1000
243 #define MLX4_EN_CX3_HIGH_ID 0x1005
245 struct mlx4_en_rx_alloc {
252 struct mlx4_en_tx_ring {
253 struct mlx4_hwq_resources wqres;
254 u32 size ; /* number of TXBBs */
257 u16 cqn; /* index of port CQ associated with this ring */
264 struct mlx4_en_tx_info *tx_info;
267 cpumask_t affinity_mask;
270 struct mlx4_qp_context context;
272 enum mlx4_qp_state qp_state;
273 struct mlx4_srq dummy;
275 unsigned long packets;
276 unsigned long tx_csum;
277 unsigned long queue_stopped;
278 unsigned long wake_queue;
281 struct netdev_queue *tx_queue;
282 int hwtstamp_tx_type;
286 struct mlx4_en_rx_desc {
287 /* actual number of entries depends on rx ring stride */
288 struct mlx4_wqe_data_seg data[0];
291 struct mlx4_en_rx_ring {
292 struct mlx4_hwq_resources wqres;
293 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
294 u32 size ; /* number of Rx descs*/
299 u16 cqn; /* index of port CQ associated with this ring */
307 unsigned long packets;
308 #ifdef CONFIG_NET_RX_BUSY_POLL
309 unsigned long yields;
310 unsigned long misses;
311 unsigned long cleaned;
313 unsigned long csum_ok;
314 unsigned long csum_none;
315 int hwtstamp_rx_filter;
316 cpumask_var_t affinity_mask;
321 struct mlx4_hwq_resources wqres;
323 struct net_device *dev;
324 struct napi_struct napi;
331 struct mlx4_cqe *buf;
332 #define MLX4_EN_OPCODE_ERROR 0x1e
334 #ifdef CONFIG_NET_RX_BUSY_POLL
336 #define MLX4_EN_CQ_STATE_IDLE 0
337 #define MLX4_EN_CQ_STATE_NAPI 1 /* NAPI owns this CQ */
338 #define MLX4_EN_CQ_STATE_POLL 2 /* poll owns this CQ */
339 #define MLX4_CQ_LOCKED (MLX4_EN_CQ_STATE_NAPI | MLX4_EN_CQ_STATE_POLL)
340 #define MLX4_EN_CQ_STATE_NAPI_YIELD 4 /* NAPI yielded this CQ */
341 #define MLX4_EN_CQ_STATE_POLL_YIELD 8 /* poll yielded this CQ */
342 #define CQ_YIELD (MLX4_EN_CQ_STATE_NAPI_YIELD | MLX4_EN_CQ_STATE_POLL_YIELD)
343 #define CQ_USER_PEND (MLX4_EN_CQ_STATE_POLL | MLX4_EN_CQ_STATE_POLL_YIELD)
344 spinlock_t poll_lock; /* protects from LLS/napi conflicts */
345 #endif /* CONFIG_NET_RX_BUSY_POLL */
346 struct irq_desc *irq_desc;
349 struct mlx4_en_port_profile {
363 struct mlx4_en_profile {
370 u8 num_tx_rings_p_up;
371 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
375 struct mlx4_dev *dev;
376 struct pci_dev *pdev;
377 struct mutex state_lock;
378 struct net_device *pndev[MLX4_MAX_PORTS + 1];
381 struct mlx4_en_profile profile;
383 struct workqueue_struct *workqueue;
384 struct device *dma_device;
385 void __iomem *uar_map;
386 struct mlx4_uar priv_uar;
390 u8 mac_removed[MLX4_MAX_PORTS + 1];
393 struct cyclecounter cycles;
394 struct timecounter clock;
395 unsigned long last_overflow_check;
396 unsigned long overflow_period;
397 struct ptp_clock *ptp_clock;
398 struct ptp_clock_info ptp_clock_info;
402 struct mlx4_en_rss_map {
404 struct mlx4_qp qps[MAX_RX_RINGS];
405 enum mlx4_qp_state state[MAX_RX_RINGS];
406 struct mlx4_qp indir_qp;
407 enum mlx4_qp_state indir_state;
410 struct mlx4_en_port_state {
416 struct mlx4_en_pkt_stats {
417 unsigned long broadcast;
418 unsigned long rx_prio[8];
419 unsigned long tx_prio[8];
420 #define NUM_PKT_STATS 17
423 struct mlx4_en_port_stats {
424 unsigned long tso_packets;
425 unsigned long queue_stopped;
426 unsigned long wake_queue;
427 unsigned long tx_timeout;
428 unsigned long rx_alloc_failed;
429 unsigned long rx_chksum_good;
430 unsigned long rx_chksum_none;
431 unsigned long tx_chksum_offload;
432 #define NUM_PORT_STATS 8
435 struct mlx4_en_perf_stats {
442 #define NUM_PERF_COUNTERS 6
445 enum mlx4_en_mclist_act {
451 struct mlx4_en_mc_list {
452 struct list_head list;
453 enum mlx4_en_mclist_act action;
459 struct mlx4_en_frag_info {
461 u16 frag_prefix_size;
466 #ifdef CONFIG_MLX4_EN_DCB
467 /* Minimal TC BW - setting to 0 will block traffic */
468 #define MLX4_EN_BW_MIN 1
469 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
471 #define MLX4_EN_TC_ETS 7
475 struct ethtool_flow_id {
476 struct list_head list;
477 struct ethtool_rx_flow_spec flow_spec;
482 MLX4_EN_FLAG_PROMISC = (1 << 0),
483 MLX4_EN_FLAG_MC_PROMISC = (1 << 1),
484 /* whether we need to enable hardware loopback by putting dmac
487 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),
488 /* whether we need to drop packets that hardware loopback-ed */
489 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3),
490 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4)
493 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
494 #define MLX4_EN_MAC_HASH_IDX 5
496 struct mlx4_en_priv {
497 struct mlx4_en_dev *mdev;
498 struct mlx4_en_port_profile *prof;
499 struct net_device *dev;
500 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
501 struct net_device_stats stats;
502 struct net_device_stats ret_stats;
503 struct mlx4_en_port_state port_state;
504 spinlock_t stats_lock;
505 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
506 /* To allow rules removal while port is going down */
507 struct list_head ethtool_list;
509 unsigned long last_moder_packets[MAX_RX_RINGS];
510 unsigned long last_moder_tx_packets;
511 unsigned long last_moder_bytes[MAX_RX_RINGS];
512 unsigned long last_moder_jiffies;
513 int last_moder_time[MAX_RX_RINGS];
523 u16 adaptive_rx_coal;
526 u32 validate_loopback;
528 struct mlx4_hwq_resources res;
536 unsigned char prev_mac[ETH_ALEN + 2];
542 struct mlx4_en_rss_map rss_map;
545 u8 num_tx_rings_p_up;
549 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
553 struct mlx4_en_tx_ring **tx_ring;
554 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
555 struct mlx4_en_cq **tx_cq;
556 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
557 struct mlx4_qp drop_qp;
558 struct work_struct rx_mode_task;
559 struct work_struct watchdog_task;
560 struct work_struct linkstate_task;
561 struct delayed_work stats_task;
562 struct delayed_work service_task;
563 #ifdef CONFIG_MLX4_EN_VXLAN
564 struct work_struct vxlan_add_task;
565 struct work_struct vxlan_del_task;
567 struct mlx4_en_perf_stats pstats;
568 struct mlx4_en_pkt_stats pkstats;
569 struct mlx4_en_port_stats port_stats;
571 struct list_head mc_list;
572 struct list_head curr_list;
574 struct mlx4_en_stat_out_mbox hw_stats;
579 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];
580 struct hwtstamp_config hwtstamp_config;
582 #ifdef CONFIG_MLX4_EN_DCB
584 u16 maxrate[IEEE_8021QAZ_MAX_TCS];
586 #ifdef CONFIG_RFS_ACCEL
587 spinlock_t filters_lock;
589 struct list_head filters;
590 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
597 MLX4_EN_WOL_MAGIC = (1ULL << 61),
598 MLX4_EN_WOL_ENABLED = (1ULL << 62),
601 struct mlx4_mac_entry {
602 struct hlist_node hlist;
603 unsigned char mac[ETH_ALEN + 2];
608 #ifdef CONFIG_NET_RX_BUSY_POLL
609 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
611 spin_lock_init(&cq->poll_lock);
612 cq->state = MLX4_EN_CQ_STATE_IDLE;
615 /* called from the device poll rutine to get ownership of a cq */
616 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
619 spin_lock(&cq->poll_lock);
620 if (cq->state & MLX4_CQ_LOCKED) {
621 WARN_ON(cq->state & MLX4_EN_CQ_STATE_NAPI);
622 cq->state |= MLX4_EN_CQ_STATE_NAPI_YIELD;
625 /* we don't care if someone yielded */
626 cq->state = MLX4_EN_CQ_STATE_NAPI;
627 spin_unlock(&cq->poll_lock);
631 /* returns true is someone tried to get the cq while napi had it */
632 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
635 spin_lock(&cq->poll_lock);
636 WARN_ON(cq->state & (MLX4_EN_CQ_STATE_POLL |
637 MLX4_EN_CQ_STATE_NAPI_YIELD));
639 if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD)
641 cq->state = MLX4_EN_CQ_STATE_IDLE;
642 spin_unlock(&cq->poll_lock);
646 /* called from mlx4_en_low_latency_poll() */
647 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
650 spin_lock_bh(&cq->poll_lock);
651 if ((cq->state & MLX4_CQ_LOCKED)) {
652 struct net_device *dev = cq->dev;
653 struct mlx4_en_priv *priv = netdev_priv(dev);
654 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring];
656 cq->state |= MLX4_EN_CQ_STATE_POLL_YIELD;
660 /* preserve yield marks */
661 cq->state |= MLX4_EN_CQ_STATE_POLL;
662 spin_unlock_bh(&cq->poll_lock);
666 /* returns true if someone tried to get the cq while it was locked */
667 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
670 spin_lock_bh(&cq->poll_lock);
671 WARN_ON(cq->state & (MLX4_EN_CQ_STATE_NAPI));
673 if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD)
675 cq->state = MLX4_EN_CQ_STATE_IDLE;
676 spin_unlock_bh(&cq->poll_lock);
680 /* true if a socket is polling, even if it did not get the lock */
681 static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq)
683 WARN_ON(!(cq->state & MLX4_CQ_LOCKED));
684 return cq->state & CQ_USER_PEND;
687 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
691 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
696 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
701 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
706 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
711 static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq)
715 #endif /* CONFIG_NET_RX_BUSY_POLL */
717 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
719 void mlx4_en_update_loopback_state(struct net_device *dev,
720 netdev_features_t features);
722 void mlx4_en_destroy_netdev(struct net_device *dev);
723 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
724 struct mlx4_en_port_profile *prof);
726 int mlx4_en_start_port(struct net_device *dev);
727 void mlx4_en_stop_port(struct net_device *dev, int detach);
729 void mlx4_en_free_resources(struct mlx4_en_priv *priv);
730 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
732 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
733 int entries, int ring, enum cq_type mode, int node);
734 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
735 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
737 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
738 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
739 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
741 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
742 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
743 void *accel_priv, select_queue_fallback_t fallback);
744 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
746 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
747 struct mlx4_en_tx_ring **pring,
748 int qpn, u32 size, u16 stride,
749 int node, int queue_index);
750 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
751 struct mlx4_en_tx_ring **pring);
752 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
753 struct mlx4_en_tx_ring *ring,
754 int cq, int user_prio);
755 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
756 struct mlx4_en_tx_ring *ring);
757 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev);
758 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
759 struct mlx4_en_rx_ring **pring,
760 u32 size, u16 stride, int node);
761 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
762 struct mlx4_en_rx_ring **pring,
763 u32 size, u16 stride);
764 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
765 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
766 struct mlx4_en_rx_ring *ring);
767 int mlx4_en_process_rx_cq(struct net_device *dev,
768 struct mlx4_en_cq *cq,
770 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
771 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget);
772 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
773 int is_tx, int rss, int qpn, int cqn, int user_prio,
774 struct mlx4_qp_context *context);
775 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
776 int mlx4_en_map_buffer(struct mlx4_buf *buf);
777 void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
779 void mlx4_en_calc_rx_buf(struct net_device *dev);
780 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
781 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
782 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
783 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
784 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
785 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
787 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
788 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
790 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
791 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
793 #ifdef CONFIG_MLX4_EN_DCB
794 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
795 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
798 int mlx4_en_setup_tc(struct net_device *dev, u8 up);
800 #ifdef CONFIG_RFS_ACCEL
801 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv);
804 #define MLX4_EN_NUM_SELF_TEST 5
805 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
806 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
809 * Functions for time stamping
811 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
812 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,
813 struct skb_shared_hwtstamps *hwts,
815 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev);
816 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev);
817 int mlx4_en_timestamp_config(struct net_device *dev,
823 extern const struct ethtool_ops mlx4_en_ethtool_ops;
828 * printk / logging functions
832 int en_print(const char *level, const struct mlx4_en_priv *priv,
833 const char *format, ...);
835 #define en_dbg(mlevel, priv, format, ...) \
837 if (NETIF_MSG_##mlevel & (priv)->msg_enable) \
838 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__); \
840 #define en_warn(priv, format, ...) \
841 en_print(KERN_WARNING, priv, format, ##__VA_ARGS__)
842 #define en_err(priv, format, ...) \
843 en_print(KERN_ERR, priv, format, ##__VA_ARGS__)
844 #define en_info(priv, format, ...) \
845 en_print(KERN_INFO, priv, format, ##__VA_ARGS__)
847 #define mlx4_err(mdev, format, ...) \
848 pr_err(DRV_NAME " %s: " format, \
849 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
850 #define mlx4_info(mdev, format, ...) \
851 pr_info(DRV_NAME " %s: " format, \
852 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
853 #define mlx4_warn(mdev, format, ...) \
854 pr_warn(DRV_NAME " %s: " format, \
855 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)