drivers/net/ethernet/qlogic/qed/qed.h

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef _QED_H
  34 #define _QED_H
  35
  36 #include <linux/types.h>
  37 #include <linux/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/firmware.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/list.h>
  42 #include <linux/mutex.h>
  43 #include <linux/pci.h>
  44 #include <linux/slab.h>
  45 #include <linux/string.h>
  46 #include <linux/workqueue.h>
  47 #include <linux/zlib.h>
  48 #include <linux/hashtable.h>
  49 #include <linux/qed/qed_if.h>
  50 #include "qed_debug.h"
  51 #include "qed_hsi.h"
  52
  53 extern const struct qed_common_ops qed_common_ops_pass;
  54
  55 #define QED_MAJOR_VERSION               8
  56 #define QED_MINOR_VERSION               10
  57 #define QED_REVISION_VERSION            10
  58 #define QED_ENGINEERING_VERSION 21
  59
  60 #define QED_VERSION                                              \
  61         ((QED_MAJOR_VERSION << 24) | (QED_MINOR_VERSION << 16) | \
  62          (QED_REVISION_VERSION << 8) | QED_ENGINEERING_VERSION)
  63
  64 #define STORM_FW_VERSION                                       \
  65         ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \
  66          (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
  67
  68 #define MAX_HWFNS_PER_DEVICE    (4)
  69 #define NAME_SIZE 16
  70 #define VER_SIZE 16
  71
  72 #define QED_WFQ_UNIT    100
  73
  74 #define QED_WID_SIZE            (1024)
  75 #define QED_PF_DEMS_SIZE        (4)
  76
  77 /* cau states */
  78 enum qed_coalescing_mode {
  79         QED_COAL_MODE_DISABLE,
  80         QED_COAL_MODE_ENABLE
  81 };
  82
  83 struct qed_eth_cb_ops;
  84 struct qed_dev_info;
  85 union qed_mcp_protocol_stats;
  86 enum qed_mcp_protocol_type;
  87
  88 /* helpers */
  89 #define QED_MFW_GET_FIELD(name, field) \
  90         (((name) & (field ## _MASK)) >> (field ## _SHIFT))
  91
  92 #define QED_MFW_SET_FIELD(name, field, value)                                  \
  93         do {                                                                   \
  94                 (name)  &= ~((field ## _MASK) << (field ## _SHIFT));           \
  95                 (name)  |= (((value) << (field ## _SHIFT)) & (field ## _MASK));\
  96         } while (0)
  97
  98 static inline u32 qed_db_addr(u32 cid, u32 DEMS)
  99 {
 100         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 101                       (cid * QED_PF_DEMS_SIZE);
 102
 103         return db_addr;
 104 }
 105
 106 static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS)
 107 {
 108         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 109                       FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
 110
 111         return db_addr;
 112 }
 113
 114 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn)                                 \
 115         ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
 116          ~((1 << (p_hwfn->cdev->cache_shift)) - 1))
 117
 118 #define for_each_hwfn(cdev, i)  for (i = 0; i < cdev->num_hwfns; i++)
 119
 120 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
 121         (val == (cond1) ? true1 :                     \
 122          (val == (cond2) ? true2 : def))
 123
 124 /* forward */
 125 struct qed_ptt_pool;
 126 struct qed_spq;
 127 struct qed_sb_info;
 128 struct qed_sb_attn_info;
 129 struct qed_cxt_mngr;
 130 struct qed_sb_sp_info;
 131 struct qed_ll2_info;
 132 struct qed_mcp_info;
 133
 134 struct qed_rt_data {
 135         u32     *init_val;
 136         bool    *b_valid;
 137 };
 138
 139 enum qed_tunn_mode {
 140         QED_MODE_L2GENEVE_TUNN,
 141         QED_MODE_IPGENEVE_TUNN,
 142         QED_MODE_L2GRE_TUNN,
 143         QED_MODE_IPGRE_TUNN,
 144         QED_MODE_VXLAN_TUNN,
 145 };
 146
 147 enum qed_tunn_clss {
 148         QED_TUNN_CLSS_MAC_VLAN,
 149         QED_TUNN_CLSS_MAC_VNI,
 150         QED_TUNN_CLSS_INNER_MAC_VLAN,
 151         QED_TUNN_CLSS_INNER_MAC_VNI,
 152         QED_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
 153         MAX_QED_TUNN_CLSS,
 154 };
 155
 156 struct qed_tunn_update_type {
 157         bool b_update_mode;
 158         bool b_mode_enabled;
 159         enum qed_tunn_clss tun_cls;
 160 };
 161
 162 struct qed_tunn_update_udp_port {
 163         bool b_update_port;
 164         u16 port;
 165 };
 166
 167 struct qed_tunnel_info {
 168         struct qed_tunn_update_type vxlan;
 169         struct qed_tunn_update_type l2_geneve;
 170         struct qed_tunn_update_type ip_geneve;
 171         struct qed_tunn_update_type l2_gre;
 172         struct qed_tunn_update_type ip_gre;
 173
 174         struct qed_tunn_update_udp_port vxlan_port;
 175         struct qed_tunn_update_udp_port geneve_port;
 176
 177         bool b_update_rx_cls;
 178         bool b_update_tx_cls;
 179 };
 180
 181 struct qed_tunn_start_params {
 182         unsigned long   tunn_mode;
 183         u16             vxlan_udp_port;
 184         u16             geneve_udp_port;
 185         u8              update_vxlan_udp_port;
 186         u8              update_geneve_udp_port;
 187         u8              tunn_clss_vxlan;
 188         u8              tunn_clss_l2geneve;
 189         u8              tunn_clss_ipgeneve;
 190         u8              tunn_clss_l2gre;
 191         u8              tunn_clss_ipgre;
 192 };
 193
 194 struct qed_tunn_update_params {
 195         unsigned long   tunn_mode_update_mask;
 196         unsigned long   tunn_mode;
 197         u16             vxlan_udp_port;
 198         u16             geneve_udp_port;
 199         u8              update_rx_pf_clss;
 200         u8              update_tx_pf_clss;
 201         u8              update_vxlan_udp_port;
 202         u8              update_geneve_udp_port;
 203         u8              tunn_clss_vxlan;
 204         u8              tunn_clss_l2geneve;
 205         u8              tunn_clss_ipgeneve;
 206         u8              tunn_clss_l2gre;
 207         u8              tunn_clss_ipgre;
 208 };
 209
 210 /* The PCI personality is not quite synonymous to protocol ID:
 211  * 1. All personalities need CORE connections
 212  * 2. The Ethernet personality may support also the RoCE protocol
 213  */
 214 enum qed_pci_personality {
 215         QED_PCI_ETH,
 216         QED_PCI_FCOE,
 217         QED_PCI_ISCSI,
 218         QED_PCI_ETH_ROCE,
 219         QED_PCI_DEFAULT /* default in shmem */
 220 };
 221
 222 /* All VFs are symmetric, all counters are PF + all VFs */
 223 struct qed_qm_iids {
 224         u32 cids;
 225         u32 vf_cids;
 226         u32 tids;
 227 };
 228
 229 /* HW / FW resources, output of features supported below, most information
 230  * is received from MFW.
 231  */
 232 enum qed_resources {
 233         QED_SB,
 234         QED_L2_QUEUE,
 235         QED_VPORT,
 236         QED_RSS_ENG,
 237         QED_PQ,
 238         QED_RL,
 239         QED_MAC,
 240         QED_VLAN,
 241         QED_RDMA_CNQ_RAM,
 242         QED_ILT,
 243         QED_LL2_QUEUE,
 244         QED_CMDQS_CQS,
 245         QED_RDMA_STATS_QUEUE,
 246         QED_BDQ,
 247         QED_MAX_RESC,
 248 };
 249
 250 enum QED_FEATURE {
 251         QED_PF_L2_QUE,
 252         QED_VF,
 253         QED_RDMA_CNQ,
 254         QED_ISCSI_CQ,
 255         QED_FCOE_CQ,
 256         QED_VF_L2_QUE,
 257         QED_MAX_FEATURES,
 258 };
 259
 260 enum QED_PORT_MODE {
 261         QED_PORT_MODE_DE_2X40G,
 262         QED_PORT_MODE_DE_2X50G,
 263         QED_PORT_MODE_DE_1X100G,
 264         QED_PORT_MODE_DE_4X10G_F,
 265         QED_PORT_MODE_DE_4X10G_E,
 266         QED_PORT_MODE_DE_4X20G,
 267         QED_PORT_MODE_DE_1X40G,
 268         QED_PORT_MODE_DE_2X25G,
 269         QED_PORT_MODE_DE_1X25G,
 270         QED_PORT_MODE_DE_4X25G,
 271         QED_PORT_MODE_DE_2X10G,
 272 };
 273
 274 enum qed_dev_cap {
 275         QED_DEV_CAP_ETH,
 276         QED_DEV_CAP_FCOE,
 277         QED_DEV_CAP_ISCSI,
 278         QED_DEV_CAP_ROCE,
 279 };
 280
 281 enum qed_wol_support {
 282         QED_WOL_SUPPORT_NONE,
 283         QED_WOL_SUPPORT_PME,
 284 };
 285
 286 struct qed_hw_info {
 287         /* PCI personality */
 288         enum qed_pci_personality        personality;
 289
 290         /* Resource Allocation scheme results */
 291         u32                             resc_start[QED_MAX_RESC];
 292         u32                             resc_num[QED_MAX_RESC];
 293         u32                             feat_num[QED_MAX_FEATURES];
 294
 295 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
 296 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
 297 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
 298                                  RESC_NUM(_p_hwfn, resc))
 299 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
 300
 301         /* Amount of traffic classes HW supports */
 302         u8 num_hw_tc;
 303
 304         /* Amount of TCs which should be active according to DCBx or upper
 305          * layer driver configuration.
 306          */
 307         u8 num_active_tc;
 308         u8                              offload_tc;
 309
 310         u32                             concrete_fid;
 311         u16                             opaque_fid;
 312         u16                             ovlan;
 313         u32                             part_num[4];
 314
 315         unsigned char                   hw_mac_addr[ETH_ALEN];
 316         u64                             node_wwn;
 317         u64                             port_wwn;
 318
 319         u16                             num_fcoe_conns;
 320
 321         struct qed_igu_info             *p_igu_info;
 322
 323         u32                             port_mode;
 324         u32                             hw_mode;
 325         unsigned long           device_capabilities;
 326         u16                             mtu;
 327
 328         enum qed_wol_support b_wol_support;
 329 };
 330
 331 /* maximun size of read/write commands (HW limit) */
 332 #define DMAE_MAX_RW_SIZE        0x2000
 333
 334 struct qed_dmae_info {
 335         /* Mutex for synchronizing access to functions */
 336         struct mutex    mutex;
 337
 338         u8              channel;
 339
 340         dma_addr_t      completion_word_phys_addr;
 341
 342         /* The memory location where the DMAE writes the completion
 343          * value when an operation is finished on this context.
 344          */
 345         u32             *p_completion_word;
 346
 347         dma_addr_t      intermediate_buffer_phys_addr;
 348
 349         /* An intermediate buffer for DMAE operations that use virtual
 350          * addresses - data is DMA'd to/from this buffer and then
 351          * memcpy'd to/from the virtual address
 352          */
 353         u32             *p_intermediate_buffer;
 354
 355         dma_addr_t      dmae_cmd_phys_addr;
 356         struct dmae_cmd *p_dmae_cmd;
 357 };
 358
 359 struct qed_wfq_data {
 360         /* when feature is configured for at least 1 vport */
 361         u32     min_speed;
 362         bool    configured;
 363 };
 364
 365 struct qed_qm_info {
 366         struct init_qm_pq_params        *qm_pq_params;
 367         struct init_qm_vport_params     *qm_vport_params;
 368         struct init_qm_port_params      *qm_port_params;
 369         u16                             start_pq;
 370         u8                              start_vport;
 371         u16                              pure_lb_pq;
 372         u16                             offload_pq;
 373         u16                             low_latency_pq;
 374         u16                             pure_ack_pq;
 375         u16                             ooo_pq;
 376         u16                             first_vf_pq;
 377         u16                             first_mcos_pq;
 378         u16                             first_rl_pq;
 379         u16                             num_pqs;
 380         u16                             num_vf_pqs;
 381         u8                              num_vports;
 382         u8                              max_phys_tcs_per_port;
 383         u8                              ooo_tc;
 384         bool                            pf_rl_en;
 385         bool                            pf_wfq_en;
 386         bool                            vport_rl_en;
 387         bool                            vport_wfq_en;
 388         u8                              pf_wfq;
 389         u32                             pf_rl;
 390         struct qed_wfq_data             *wfq_data;
 391         u8 num_pf_rls;
 392 };
 393
 394 struct storm_stats {
 395         u32     address;
 396         u32     len;
 397 };
 398
 399 struct qed_storm_stats {
 400         struct storm_stats mstats;
 401         struct storm_stats pstats;
 402         struct storm_stats tstats;
 403         struct storm_stats ustats;
 404 };
 405
 406 struct qed_fw_data {
 407         struct fw_ver_info      *fw_ver_info;
 408         const u8                *modes_tree_buf;
 409         union init_op           *init_ops;
 410         const u32               *arr_data;
 411         u32                     init_ops_size;
 412 };
 413
 414 #define DRV_MODULE_VERSION                    \
 415         __stringify(QED_MAJOR_VERSION) "."    \
 416         __stringify(QED_MINOR_VERSION) "."    \
 417         __stringify(QED_REVISION_VERSION) "." \
 418         __stringify(QED_ENGINEERING_VERSION)
 419
 420 struct qed_simd_fp_handler {
 421         void    *token;
 422         void    (*func)(void *);
 423 };
 424
 425 struct qed_hwfn {
 426         struct qed_dev                  *cdev;
 427         u8                              my_id;          /* ID inside the PF */
 428 #define IS_LEAD_HWFN(edev)              (!((edev)->my_id))
 429         u8                              rel_pf_id;      /* Relative to engine*/
 430         u8                              abs_pf_id;
 431 #define QED_PATH_ID(_p_hwfn) \
 432         (QED_IS_K2((_p_hwfn)->cdev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
 433         u8                              port_id;
 434         bool                            b_active;
 435
 436         u32                             dp_module;
 437         u8                              dp_level;
 438         char                            name[NAME_SIZE];
 439
 440         bool                            first_on_engine;
 441         bool                            hw_init_done;
 442
 443         u8                              num_funcs_on_engine;
 444         u8 enabled_func_idx;
 445
 446         /* BAR access */
 447         void __iomem                    *regview;
 448         void __iomem                    *doorbells;
 449         u64                             db_phys_addr;
 450         unsigned long                   db_size;
 451
 452         /* PTT pool */
 453         struct qed_ptt_pool             *p_ptt_pool;
 454
 455         /* HW info */
 456         struct qed_hw_info              hw_info;
 457
 458         /* rt_array (for init-tool) */
 459         struct qed_rt_data              rt_data;
 460
 461         /* SPQ */
 462         struct qed_spq                  *p_spq;
 463
 464         /* EQ */
 465         struct qed_eq                   *p_eq;
 466
 467         /* Consolidate Q*/
 468         struct qed_consq                *p_consq;
 469
 470         /* Slow-Path definitions */
 471         struct tasklet_struct           *sp_dpc;
 472         bool                            b_sp_dpc_enabled;
 473
 474         struct qed_ptt                  *p_main_ptt;
 475         struct qed_ptt                  *p_dpc_ptt;
 476
 477         struct qed_sb_sp_info           *p_sp_sb;
 478         struct qed_sb_attn_info         *p_sb_attn;
 479
 480         /* Protocol related */
 481         bool                            using_ll2;
 482         struct qed_ll2_info             *p_ll2_info;
 483         struct qed_ooo_info             *p_ooo_info;
 484         struct qed_rdma_info            *p_rdma_info;
 485         struct qed_iscsi_info           *p_iscsi_info;
 486         struct qed_fcoe_info            *p_fcoe_info;
 487         struct qed_pf_params            pf_params;
 488
 489         bool b_rdma_enabled_in_prs;
 490         u32 rdma_prs_search_reg;
 491
 492         /* Array of sb_info of all status blocks */
 493         struct qed_sb_info              *sbs_info[MAX_SB_PER_PF_MIMD];
 494         u16                             num_sbs;
 495
 496         struct qed_cxt_mngr             *p_cxt_mngr;
 497
 498         /* Flag indicating whether interrupts are enabled or not*/
 499         bool                            b_int_enabled;
 500         bool                            b_int_requested;
 501
 502         /* True if the driver requests for the link */
 503         bool                            b_drv_link_init;
 504
 505         struct qed_vf_iov               *vf_iov_info;
 506         struct qed_pf_iov               *pf_iov_info;
 507         struct qed_mcp_info             *mcp_info;
 508
 509         struct qed_dcbx_info            *p_dcbx_info;
 510
 511         struct qed_dmae_info            dmae_info;
 512
 513         /* QM init */
 514         struct qed_qm_info              qm_info;
 515         struct qed_storm_stats          storm_stats;
 516
 517         /* Buffer for unzipping firmware data */
 518         void                            *unzip_buf;
 519
 520         struct dbg_tools_data           dbg_info;
 521
 522         /* PWM region specific data */
 523         u32                             dpi_size;
 524         u32                             dpi_count;
 525
 526         /* This is used to calculate the doorbell address */
 527         u32 dpi_start_offset;
 528
 529         /* If one of the following is set then EDPM shouldn't be used */
 530         u8 dcbx_no_edpm;
 531         u8 db_bar_no_edpm;
 532
 533         struct qed_ptt *p_arfs_ptt;
 534
 535         /* p_ptp_ptt is valid for leading HWFN only */
 536         struct qed_ptt *p_ptp_ptt;
 537         struct qed_simd_fp_handler      simd_proto_handler[64];
 538
 539 #ifdef CONFIG_QED_SRIOV
 540         struct workqueue_struct *iov_wq;
 541         struct delayed_work iov_task;
 542         unsigned long iov_task_flags;
 543 #endif
 544
 545         struct z_stream_s               *stream;
 546         struct qed_roce_ll2_info        *ll2;
 547 };
 548
 549 struct pci_params {
 550         int             pm_cap;
 551
 552         unsigned long   mem_start;
 553         unsigned long   mem_end;
 554         unsigned int    irq;
 555         u8              pf_num;
 556 };
 557
 558 struct qed_int_param {
 559         u32     int_mode;
 560         u8      num_vectors;
 561         u8      min_msix_cnt; /* for minimal functionality */
 562 };
 563
 564 struct qed_int_params {
 565         struct qed_int_param    in;
 566         struct qed_int_param    out;
 567         struct msix_entry       *msix_table;
 568         bool                    fp_initialized;
 569         u8                      fp_msix_base;
 570         u8                      fp_msix_cnt;
 571         u8                      rdma_msix_base;
 572         u8                      rdma_msix_cnt;
 573 };
 574
 575 struct qed_dbg_feature {
 576         struct dentry *dentry;
 577         u8 *dump_buf;
 578         u32 buf_size;
 579         u32 dumped_dwords;
 580 };
 581
 582 struct qed_dbg_params {
 583         struct qed_dbg_feature features[DBG_FEATURE_NUM];
 584         u8 engine_for_debug;
 585         bool print_data;
 586 };
 587
 588 struct qed_dev {
 589         u32     dp_module;
 590         u8      dp_level;
 591         char    name[NAME_SIZE];
 592
 593         enum    qed_dev_type type;
 594 /* Translate type/revision combo into the proper conditions */
 595 #define QED_IS_BB(dev)  ((dev)->type == QED_DEV_TYPE_BB)
 596 #define QED_IS_BB_A0(dev)       (QED_IS_BB(dev) && \
 597                                  CHIP_REV_IS_A0(dev))
 598 #define QED_IS_BB_B0(dev)       (QED_IS_BB(dev) && \
 599                                  CHIP_REV_IS_B0(dev))
 600 #define QED_IS_AH(dev)  ((dev)->type == QED_DEV_TYPE_AH)
 601 #define QED_IS_K2(dev)  QED_IS_AH(dev)
 602
 603 #define QED_GET_TYPE(dev)       (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \
 604                                  QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2)
 605
 606         u16     vendor_id;
 607         u16     device_id;
 608 #define QED_DEV_ID_MASK         0xff00
 609 #define QED_DEV_ID_MASK_BB      0x1600
 610 #define QED_DEV_ID_MASK_AH      0x8000
 611
 612         u16     chip_num;
 613 #define CHIP_NUM_MASK                   0xffff
 614 #define CHIP_NUM_SHIFT                  16
 615
 616         u16     chip_rev;
 617 #define CHIP_REV_MASK                   0xf
 618 #define CHIP_REV_SHIFT                  12
 619 #define CHIP_REV_IS_A0(_cdev)   (!(_cdev)->chip_rev)
 620 #define CHIP_REV_IS_B0(_cdev)   ((_cdev)->chip_rev == 1)
 621
 622         u16                             chip_metal;
 623 #define CHIP_METAL_MASK                 0xff
 624 #define CHIP_METAL_SHIFT                4
 625
 626         u16                             chip_bond_id;
 627 #define CHIP_BOND_ID_MASK               0xf
 628 #define CHIP_BOND_ID_SHIFT              0
 629
 630         u8                              num_engines;
 631         u8                              num_ports_in_engines;
 632         u8                              num_funcs_in_port;
 633
 634         u8                              path_id;
 635         enum qed_mf_mode                mf_mode;
 636 #define IS_MF_DEFAULT(_p_hwfn)  (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT)
 637 #define IS_MF_SI(_p_hwfn)       (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR)
 638 #define IS_MF_SD(_p_hwfn)       (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN)
 639
 640         int                             pcie_width;
 641         int                             pcie_speed;
 642         u8                              ver_str[VER_SIZE];
 643
 644         /* Add MF related configuration */
 645         u8                              mcp_rev;
 646         u8                              boot_mode;
 647
 648         /* WoL related configurations */
 649         u8 wol_config;
 650         u8 wol_mac[ETH_ALEN];
 651
 652         u32                             int_mode;
 653         enum qed_coalescing_mode        int_coalescing_mode;
 654         u16                             rx_coalesce_usecs;
 655         u16                             tx_coalesce_usecs;
 656
 657         /* Start Bar offset of first hwfn */
 658         void __iomem                    *regview;
 659         void __iomem                    *doorbells;
 660         u64                             db_phys_addr;
 661         unsigned long                   db_size;
 662
 663         /* PCI */
 664         u8                              cache_shift;
 665
 666         /* Init */
 667         const struct iro                *iro_arr;
 668 #define IRO (p_hwfn->cdev->iro_arr)
 669
 670         /* HW functions */
 671         u8                              num_hwfns;
 672         struct qed_hwfn                 hwfns[MAX_HWFNS_PER_DEVICE];
 673
 674         /* SRIOV */
 675         struct qed_hw_sriov_info *p_iov_info;
 676 #define IS_QED_SRIOV(cdev)              (!!(cdev)->p_iov_info)
 677         struct qed_tunnel_info          tunnel;
 678         bool                            b_is_vf;
 679         u32                             drv_type;
 680         struct qed_eth_stats            *reset_stats;
 681         struct qed_fw_data              *fw_data;
 682
 683         u32                             mcp_nvm_resp;
 684
 685         /* Linux specific here */
 686         struct  qede_dev                *edev;
 687         struct  pci_dev                 *pdev;
 688         u32 flags;
 689 #define QED_FLAG_STORAGE_STARTED        (BIT(0))
 690         int                             msg_enable;
 691
 692         struct pci_params               pci_params;
 693
 694         struct qed_int_params           int_params;
 695
 696         u8                              protocol;
 697 #define IS_QED_ETH_IF(cdev)     ((cdev)->protocol == QED_PROTOCOL_ETH)
 698 #define IS_QED_FCOE_IF(cdev)    ((cdev)->protocol == QED_PROTOCOL_FCOE)
 699
 700         /* Callbacks to protocol driver */
 701         union {
 702                 struct qed_common_cb_ops        *common;
 703                 struct qed_eth_cb_ops           *eth;
 704                 struct qed_fcoe_cb_ops          *fcoe;
 705                 struct qed_iscsi_cb_ops         *iscsi;
 706         } protocol_ops;
 707         void                            *ops_cookie;
 708
 709         struct qed_dbg_params           dbg_params;
 710
 711 #ifdef CONFIG_QED_LL2
 712         struct qed_cb_ll2_info          *ll2;
 713         u8                              ll2_mac_address[ETH_ALEN];
 714 #endif
 715         DECLARE_HASHTABLE(connections, 10);
 716         const struct firmware           *firmware;
 717
 718         u32 rdma_max_sge;
 719         u32 rdma_max_inline;
 720         u32 rdma_max_srq_sge;
 721         u16 tunn_feature_mask;
 722 };
 723
 724 #define NUM_OF_VFS(dev)         (QED_IS_BB(dev) ? MAX_NUM_VFS_BB \
 725                                                 : MAX_NUM_VFS_K2)
 726 #define NUM_OF_L2_QUEUES(dev)   (QED_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
 727                                                 : MAX_NUM_L2_QUEUES_K2)
 728 #define NUM_OF_PORTS(dev)       (QED_IS_BB(dev) ? MAX_NUM_PORTS_BB \
 729                                                 : MAX_NUM_PORTS_K2)
 730 #define NUM_OF_SBS(dev)         (QED_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
 731                                                 : MAX_SB_PER_PATH_K2)
 732 #define NUM_OF_ENG_PFS(dev)     (QED_IS_BB(dev) ? MAX_NUM_PFS_BB \
 733                                                 : MAX_NUM_PFS_K2)
 734
 735 /**
 736  * @brief qed_concrete_to_sw_fid - get the sw function id from
 737  *        the concrete value.
 738  *
 739  * @param concrete_fid
 740  *
 741  * @return inline u8
 742  */
 743 static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
 744                                         u32 concrete_fid)
 745 {
 746         u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
 747         u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
 748         u8 vf_valid = GET_FIELD(concrete_fid,
 749                                 PXP_CONCRETE_FID_VFVALID);
 750         u8 sw_fid;
 751
 752         if (vf_valid)
 753                 sw_fid = vfid + MAX_NUM_PFS;
 754         else
 755                 sw_fid = pfid;
 756
 757         return sw_fid;
 758 }
 759
 760 #define PURE_LB_TC 8
 761 #define OOO_LB_TC 9
 762
 763 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate);
 764 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
 765                                          struct qed_ptt *p_ptt,
 766                                          u32 min_pf_rate);
 767
 768 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
 769 int qed_device_num_engines(struct qed_dev *cdev);
 770
 771 #define QED_LEADING_HWFN(dev)   (&dev->hwfns[0])
 772
 773 /* Flags for indication of required queues */
 774 #define PQ_FLAGS_RLS    (BIT(0))
 775 #define PQ_FLAGS_MCOS   (BIT(1))
 776 #define PQ_FLAGS_LB     (BIT(2))
 777 #define PQ_FLAGS_OOO    (BIT(3))
 778 #define PQ_FLAGS_ACK    (BIT(4))
 779 #define PQ_FLAGS_OFLD   (BIT(5))
 780 #define PQ_FLAGS_VFS    (BIT(6))
 781 #define PQ_FLAGS_LLT    (BIT(7))
 782
 783 /* physical queue index for cm context intialization */
 784 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags);
 785 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc);
 786 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf);
 787
 788 #define QED_LEADING_HWFN(dev)   (&dev->hwfns[0])
 789
 790 /* Other Linux specific common definitions */
 791 #define DP_NAME(cdev) ((cdev)->name)
 792
 793 #define REG_ADDR(cdev, offset)          (void __iomem *)((u8 __iomem *)\
 794                                                 (cdev->regview) + \
 795                                                          (offset))
 796
 797 #define REG_RD(cdev, offset)            readl(REG_ADDR(cdev, offset))
 798 #define REG_WR(cdev, offset, val)       writel((u32)val, REG_ADDR(cdev, offset))
 799 #define REG_WR16(cdev, offset, val)     writew((u16)val, REG_ADDR(cdev, offset))
 800
 801 #define DOORBELL(cdev, db_addr, val)                     \
 802         writel((u32)val, (void __iomem *)((u8 __iomem *)\
 803                                           (cdev->doorbells) + (db_addr)))
 804
 805 /* Prototypes */
 806 int qed_fill_dev_info(struct qed_dev *cdev,
 807                       struct qed_dev_info *dev_info);
 808 void qed_link_update(struct qed_hwfn *hwfn);
 809 u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
 810                    u32 input_len, u8 *input_buf,
 811                    u32 max_size, u8 *unzip_buf);
 812 void qed_get_protocol_stats(struct qed_dev *cdev,
 813                             enum qed_mcp_protocol_type type,
 814                             union qed_mcp_protocol_stats *stats);
 815 int qed_slowpath_irq_req(struct qed_hwfn *hwfn);
 816 void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn);
 817
 818 #endif /* _QED_H */