drivers/net/ethernet/qlogic/qed/qed_dev.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/types.h>
  34 #include <asm/byteorder.h>
  35 #include <linux/io.h>
  36 #include <linux/delay.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/errno.h>
  39 #include <linux/kernel.h>
  40 #include <linux/mutex.h>
  41 #include <linux/pci.h>
  42 #include <linux/slab.h>
  43 #include <linux/string.h>
  44 #include <linux/vmalloc.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/qed/qed_chain.h>
  47 #include <linux/qed/qed_if.h>
  48 #include "qed.h"
  49 #include "qed_cxt.h"
  50 #include "qed_dcbx.h"
  51 #include "qed_dev_api.h"
  52 #include "qed_fcoe.h"
  53 #include "qed_hsi.h"
  54 #include "qed_hw.h"
  55 #include "qed_init_ops.h"
  56 #include "qed_int.h"
  57 #include "qed_iscsi.h"
  58 #include "qed_ll2.h"
  59 #include "qed_mcp.h"
  60 #include "qed_ooo.h"
  61 #include "qed_reg_addr.h"
  62 #include "qed_sp.h"
  63 #include "qed_sriov.h"
  64 #include "qed_vf.h"
  65 #include "qed_roce.h"
  66
  67 static DEFINE_SPINLOCK(qm_lock);
  68
  69 #define QED_MIN_DPIS            (4)
  70 #define QED_MIN_PWM_REGION      (QED_WID_SIZE * QED_MIN_DPIS)
  71
  72 /* API common to all protocols */
  73 enum BAR_ID {
  74         BAR_ID_0,       /* used for GRC */
  75         BAR_ID_1        /* Used for doorbells */
  76 };
  77
  78 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
  79                            struct qed_ptt *p_ptt, enum BAR_ID bar_id)
  80 {
  81         u32 bar_reg = (bar_id == BAR_ID_0 ?
  82                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  83         u32 val;
  84
  85         if (IS_VF(p_hwfn->cdev))
  86                 return 1 << 17;
  87
  88         val = qed_rd(p_hwfn, p_ptt, bar_reg);
  89         if (val)
  90                 return 1 << (val + 15);
  91
  92         /* Old MFW initialized above registered only conditionally */
  93         if (p_hwfn->cdev->num_hwfns > 1) {
  94                 DP_INFO(p_hwfn,
  95                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
  96                         return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  97         } else {
  98                 DP_INFO(p_hwfn,
  99                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
 100                         return 512 * 1024;
 101         }
 102 }
 103
 104 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
 105 {
 106         u32 i;
 107
 108         cdev->dp_level = dp_level;
 109         cdev->dp_module = dp_module;
 110         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 111                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 112
 113                 p_hwfn->dp_level = dp_level;
 114                 p_hwfn->dp_module = dp_module;
 115         }
 116 }
 117
 118 void qed_init_struct(struct qed_dev *cdev)
 119 {
 120         u8 i;
 121
 122         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 123                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 124
 125                 p_hwfn->cdev = cdev;
 126                 p_hwfn->my_id = i;
 127                 p_hwfn->b_active = false;
 128
 129                 mutex_init(&p_hwfn->dmae_info.mutex);
 130         }
 131
 132         /* hwfn 0 is always active */
 133         cdev->hwfns[0].b_active = true;
 134
 135         /* set the default cache alignment to 128 */
 136         cdev->cache_shift = 7;
 137 }
 138
 139 static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
 140 {
 141         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 142
 143         kfree(qm_info->qm_pq_params);
 144         qm_info->qm_pq_params = NULL;
 145         kfree(qm_info->qm_vport_params);
 146         qm_info->qm_vport_params = NULL;
 147         kfree(qm_info->qm_port_params);
 148         qm_info->qm_port_params = NULL;
 149         kfree(qm_info->wfq_data);
 150         qm_info->wfq_data = NULL;
 151 }
 152
 153 void qed_resc_free(struct qed_dev *cdev)
 154 {
 155         int i;
 156
 157         if (IS_VF(cdev))
 158                 return;
 159
 160         kfree(cdev->fw_data);
 161         cdev->fw_data = NULL;
 162
 163         kfree(cdev->reset_stats);
 164         cdev->reset_stats = NULL;
 165
 166         for_each_hwfn(cdev, i) {
 167                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 168
 169                 qed_cxt_mngr_free(p_hwfn);
 170                 qed_qm_info_free(p_hwfn);
 171                 qed_spq_free(p_hwfn);
 172                 qed_eq_free(p_hwfn);
 173                 qed_consq_free(p_hwfn);
 174                 qed_int_free(p_hwfn);
 175 #ifdef CONFIG_QED_LL2
 176                 qed_ll2_free(p_hwfn);
 177 #endif
 178                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
 179                         qed_fcoe_free(p_hwfn);
 180
 181                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 182                         qed_iscsi_free(p_hwfn);
 183                         qed_ooo_free(p_hwfn);
 184                 }
 185                 qed_iov_free(p_hwfn);
 186                 qed_dmae_info_free(p_hwfn);
 187                 qed_dcbx_info_free(p_hwfn);
 188         }
 189 }
 190
 191 /******************** QM initialization *******************/
 192 #define ACTIVE_TCS_BMAP 0x9f
 193 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 194
 195 /* determines the physical queue flags for a given PF. */
 196 static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn)
 197 {
 198         u32 flags;
 199
 200         /* common flags */
 201         flags = PQ_FLAGS_LB;
 202
 203         /* feature flags */
 204         if (IS_QED_SRIOV(p_hwfn->cdev))
 205                 flags |= PQ_FLAGS_VFS;
 206
 207         /* protocol flags */
 208         switch (p_hwfn->hw_info.personality) {
 209         case QED_PCI_ETH:
 210                 flags |= PQ_FLAGS_MCOS;
 211                 break;
 212         case QED_PCI_FCOE:
 213                 flags |= PQ_FLAGS_OFLD;
 214                 break;
 215         case QED_PCI_ISCSI:
 216                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 217                 break;
 218         case QED_PCI_ETH_ROCE:
 219                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
 220                 break;
 221         default:
 222                 DP_ERR(p_hwfn,
 223                        "unknown personality %d\n", p_hwfn->hw_info.personality);
 224                 return 0;
 225         }
 226
 227         return flags;
 228 }
 229
 230 /* Getters for resource amounts necessary for qm initialization */
 231 u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn)
 232 {
 233         return p_hwfn->hw_info.num_hw_tc;
 234 }
 235
 236 u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn)
 237 {
 238         return IS_QED_SRIOV(p_hwfn->cdev) ?
 239                p_hwfn->cdev->p_iov_info->total_vfs : 0;
 240 }
 241
 242 #define NUM_DEFAULT_RLS 1
 243
 244 u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn)
 245 {
 246         u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
 247
 248         /* num RLs can't exceed resource amount of rls or vports */
 249         num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL),
 250                                  RESC_NUM(p_hwfn, QED_VPORT));
 251
 252         /* Make sure after we reserve there's something left */
 253         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS)
 254                 return 0;
 255
 256         /* subtract rls necessary for VFs and one default one for the PF */
 257         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 258
 259         return num_pf_rls;
 260 }
 261
 262 u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn)
 263 {
 264         u32 pq_flags = qed_get_pq_flags(p_hwfn);
 265
 266         /* all pqs share the same vport, except for vfs and pf_rl pqs */
 267         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 268                qed_init_qm_get_num_pf_rls(p_hwfn) +
 269                (!!(PQ_FLAGS_VFS & pq_flags)) *
 270                qed_init_qm_get_num_vfs(p_hwfn) + 1;
 271 }
 272
 273 /* calc amount of PQs according to the requested flags */
 274 u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn)
 275 {
 276         u32 pq_flags = qed_get_pq_flags(p_hwfn);
 277
 278         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 279                qed_init_qm_get_num_pf_rls(p_hwfn) +
 280                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 281                qed_init_qm_get_num_tcs(p_hwfn) +
 282                (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) +
 283                (!!(PQ_FLAGS_ACK & pq_flags)) + (!!(PQ_FLAGS_OFLD & pq_flags)) +
 284                (!!(PQ_FLAGS_LLT & pq_flags)) +
 285                (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn);
 286 }
 287
 288 /* initialize the top level QM params */
 289 static void qed_init_qm_params(struct qed_hwfn *p_hwfn)
 290 {
 291         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 292         bool four_port;
 293
 294         /* pq and vport bases for this PF */
 295         qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ);
 296         qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
 297
 298         /* rate limiting and weighted fair queueing are always enabled */
 299         qm_info->vport_rl_en = 1;
 300         qm_info->vport_wfq_en = 1;
 301
 302         /* TC config is different for AH 4 port */
 303         four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2;
 304
 305         /* in AH 4 port we have fewer TCs per port */
 306         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
 307                                                      NUM_OF_PHYS_TCS;
 308
 309         /* unless MFW indicated otherwise, ooo_tc == 3 for
 310          * AH 4-port and 4 otherwise.
 311          */
 312         if (!qm_info->ooo_tc)
 313                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
 314                                               DCBX_TCP_OOO_TC;
 315 }
 316
 317 /* initialize qm vport params */
 318 static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn)
 319 {
 320         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 321         u8 i;
 322
 323         /* all vports participate in weighted fair queueing */
 324         for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++)
 325                 qm_info->qm_vport_params[i].vport_wfq = 1;
 326 }
 327
 328 /* initialize qm port params */
 329 static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn)
 330 {
 331         /* Initialize qm port parameters */
 332         u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine;
 333
 334         /* indicate how ooo and high pri traffic is dealt with */
 335         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 336                           ACTIVE_TCS_BMAP_4PORT_K2 :
 337                           ACTIVE_TCS_BMAP;
 338
 339         for (i = 0; i < num_ports; i++) {
 340                 struct init_qm_port_params *p_qm_port =
 341                     &p_hwfn->qm_info.qm_port_params[i];
 342
 343                 p_qm_port->active = 1;
 344                 p_qm_port->active_phys_tcs = active_phys_tcs;
 345                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 346                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 347         }
 348 }
 349
 350 /* Reset the params which must be reset for qm init. QM init may be called as
 351  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 352  * params may be affected by the init but would simply recalculate to the same
 353  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 354  * affected as these amounts stay the same.
 355  */
 356 static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn)
 357 {
 358         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 359
 360         qm_info->num_pqs = 0;
 361         qm_info->num_vports = 0;
 362         qm_info->num_pf_rls = 0;
 363         qm_info->num_vf_pqs = 0;
 364         qm_info->first_vf_pq = 0;
 365         qm_info->first_mcos_pq = 0;
 366         qm_info->first_rl_pq = 0;
 367 }
 368
 369 static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn)
 370 {
 371         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 372
 373         qm_info->num_vports++;
 374
 375         if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
 376                 DP_ERR(p_hwfn,
 377                        "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
 378                        qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
 379 }
 380
 381 /* initialize a single pq and manage qm_info resources accounting.
 382  * The pq_init_flags param determines whether the PQ is rate limited
 383  * (for VF or PF) and whether a new vport is allocated to the pq or not
 384  * (i.e. vport will be shared).
 385  */
 386
 387 /* flags for pq init */
 388 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 389 #define PQ_INIT_PF_RL           (1 << 1)
 390 #define PQ_INIT_VF_RL           (1 << 2)
 391
 392 /* defines for pq init */
 393 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 394 #define PQ_INIT_DEFAULT_TC              0
 395 #define PQ_INIT_OFLD_TC                 (p_hwfn->hw_info.offload_tc)
 396
 397 static void qed_init_qm_pq(struct qed_hwfn *p_hwfn,
 398                            struct qed_qm_info *qm_info,
 399                            u8 tc, u32 pq_init_flags)
 400 {
 401         u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn);
 402
 403         if (pq_idx > max_pq)
 404                 DP_ERR(p_hwfn,
 405                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 406
 407         /* init pq params */
 408         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 409             qm_info->num_vports;
 410         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 411         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 412         qm_info->qm_pq_params[pq_idx].rl_valid =
 413             (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL);
 414
 415         /* qm params accounting */
 416         qm_info->num_pqs++;
 417         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 418                 qm_info->num_vports++;
 419
 420         if (pq_init_flags & PQ_INIT_PF_RL)
 421                 qm_info->num_pf_rls++;
 422
 423         if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
 424                 DP_ERR(p_hwfn,
 425                        "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
 426                        qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
 427
 428         if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn))
 429                 DP_ERR(p_hwfn,
 430                        "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n",
 431                        qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn));
 432 }
 433
 434 /* get pq index according to PQ_FLAGS */
 435 static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn,
 436                                            u32 pq_flags)
 437 {
 438         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 439
 440         /* Can't have multiple flags set here */
 441         if (bitmap_weight((unsigned long *)&pq_flags, sizeof(pq_flags)) > 1)
 442                 goto err;
 443
 444         switch (pq_flags) {
 445         case PQ_FLAGS_RLS:
 446                 return &qm_info->first_rl_pq;
 447         case PQ_FLAGS_MCOS:
 448                 return &qm_info->first_mcos_pq;
 449         case PQ_FLAGS_LB:
 450                 return &qm_info->pure_lb_pq;
 451         case PQ_FLAGS_OOO:
 452                 return &qm_info->ooo_pq;
 453         case PQ_FLAGS_ACK:
 454                 return &qm_info->pure_ack_pq;
 455         case PQ_FLAGS_OFLD:
 456                 return &qm_info->offload_pq;
 457         case PQ_FLAGS_LLT:
 458                 return &qm_info->low_latency_pq;
 459         case PQ_FLAGS_VFS:
 460                 return &qm_info->first_vf_pq;
 461         default:
 462                 goto err;
 463         }
 464
 465 err:
 466         DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
 467         return NULL;
 468 }
 469
 470 /* save pq index in qm info */
 471 static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn,
 472                                 u32 pq_flags, u16 pq_val)
 473 {
 474         u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 475
 476         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 477 }
 478
 479 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 480 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags)
 481 {
 482         u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 483
 484         return *base_pq_idx + CM_TX_PQ_BASE;
 485 }
 486
 487 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc)
 488 {
 489         u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn);
 490
 491         if (tc > max_tc)
 492                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 493
 494         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
 495 }
 496
 497 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf)
 498 {
 499         u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn);
 500
 501         if (vf > max_vf)
 502                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 503
 504         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
 505 }
 506
 507 u16 qed_get_cm_pq_idx_rl(struct qed_hwfn *p_hwfn, u8 rl)
 508 {
 509         u16 max_rl = qed_init_qm_get_num_pf_rls(p_hwfn);
 510
 511         if (rl > max_rl)
 512                 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
 513
 514         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
 515 }
 516
 517 /* Functions for creating specific types of pqs */
 518 static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn)
 519 {
 520         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 521
 522         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 523                 return;
 524
 525         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 526         qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 527 }
 528
 529 static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn)
 530 {
 531         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 532
 533         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 534                 return;
 535
 536         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 537         qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
 538 }
 539
 540 static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn)
 541 {
 542         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 543
 544         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 545                 return;
 546
 547         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 548         qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 549 }
 550
 551 static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn)
 552 {
 553         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 554
 555         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 556                 return;
 557
 558         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 559         qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 560 }
 561
 562 static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn)
 563 {
 564         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 565
 566         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT))
 567                 return;
 568
 569         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs);
 570         qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 571 }
 572
 573 static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn)
 574 {
 575         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 576         u8 tc_idx;
 577
 578         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 579                 return;
 580
 581         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 582         for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 583                 qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 584 }
 585
 586 static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn)
 587 {
 588         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 589         u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
 590
 591         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
 592                 return;
 593
 594         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
 595         qm_info->num_vf_pqs = num_vfs;
 596         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
 597                 qed_init_qm_pq(p_hwfn,
 598                                qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL);
 599 }
 600
 601 static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn)
 602 {
 603         u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn);
 604         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 605
 606         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
 607                 return;
 608
 609         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
 610         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
 611                 qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_PF_RL);
 612 }
 613
 614 static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn)
 615 {
 616         /* rate limited pqs, must come first (FW assumption) */
 617         qed_init_qm_rl_pqs(p_hwfn);
 618
 619         /* pqs for multi cos */
 620         qed_init_qm_mcos_pqs(p_hwfn);
 621
 622         /* pure loopback pq */
 623         qed_init_qm_lb_pq(p_hwfn);
 624
 625         /* out of order pq */
 626         qed_init_qm_ooo_pq(p_hwfn);
 627
 628         /* pure ack pq */
 629         qed_init_qm_pure_ack_pq(p_hwfn);
 630
 631         /* pq for offloaded protocol */
 632         qed_init_qm_offload_pq(p_hwfn);
 633
 634         /* low latency pq */
 635         qed_init_qm_low_latency_pq(p_hwfn);
 636
 637         /* done sharing vports */
 638         qed_init_qm_advance_vport(p_hwfn);
 639
 640         /* pqs for vfs */
 641         qed_init_qm_vf_pqs(p_hwfn);
 642 }
 643
 644 /* compare values of getters against resources amounts */
 645 static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn)
 646 {
 647         if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) {
 648                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
 649                 return -EINVAL;
 650         }
 651
 652         if (qed_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, QED_PQ)) {
 653                 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
 654                 return -EINVAL;
 655         }
 656
 657         return 0;
 658 }
 659
 660 static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn)
 661 {
 662         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 663         struct init_qm_vport_params *vport;
 664         struct init_qm_port_params *port;
 665         struct init_qm_pq_params *pq;
 666         int i, tc;
 667
 668         /* top level params */
 669         DP_VERBOSE(p_hwfn,
 670                    NETIF_MSG_HW,
 671                    "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
 672                    qm_info->start_pq,
 673                    qm_info->start_vport,
 674                    qm_info->pure_lb_pq,
 675                    qm_info->offload_pq, qm_info->pure_ack_pq);
 676         DP_VERBOSE(p_hwfn,
 677                    NETIF_MSG_HW,
 678                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n",
 679                    qm_info->ooo_pq,
 680                    qm_info->first_vf_pq,
 681                    qm_info->num_pqs,
 682                    qm_info->num_vf_pqs,
 683                    qm_info->num_vports, qm_info->max_phys_tcs_per_port);
 684         DP_VERBOSE(p_hwfn,
 685                    NETIF_MSG_HW,
 686                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
 687                    qm_info->pf_rl_en,
 688                    qm_info->pf_wfq_en,
 689                    qm_info->vport_rl_en,
 690                    qm_info->vport_wfq_en,
 691                    qm_info->pf_wfq,
 692                    qm_info->pf_rl,
 693                    qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn));
 694
 695         /* port table */
 696         for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) {
 697                 port = &(qm_info->qm_port_params[i]);
 698                 DP_VERBOSE(p_hwfn,
 699                            NETIF_MSG_HW,
 700                            "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n",
 701                            i,
 702                            port->active,
 703                            port->active_phys_tcs,
 704                            port->num_pbf_cmd_lines,
 705                            port->num_btb_blocks, port->reserved);
 706         }
 707
 708         /* vport table */
 709         for (i = 0; i < qm_info->num_vports; i++) {
 710                 vport = &(qm_info->qm_vport_params[i]);
 711                 DP_VERBOSE(p_hwfn,
 712                            NETIF_MSG_HW,
 713                            "vport idx %d, vport_rl %d, wfq %d, first_tx_pq_id [ ",
 714                            qm_info->start_vport + i,
 715                            vport->vport_rl, vport->vport_wfq);
 716                 for (tc = 0; tc < NUM_OF_TCS; tc++)
 717                         DP_VERBOSE(p_hwfn,
 718                                    NETIF_MSG_HW,
 719                                    "%d ", vport->first_tx_pq_id[tc]);
 720                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n");
 721         }
 722
 723         /* pq table */
 724         for (i = 0; i < qm_info->num_pqs; i++) {
 725                 pq = &(qm_info->qm_pq_params[i]);
 726                 DP_VERBOSE(p_hwfn,
 727                            NETIF_MSG_HW,
 728                            "pq idx %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
 729                            qm_info->start_pq + i,
 730                            pq->vport_id,
 731                            pq->tc_id, pq->wrr_group, pq->rl_valid);
 732         }
 733 }
 734
 735 static void qed_init_qm_info(struct qed_hwfn *p_hwfn)
 736 {
 737         /* reset params required for init run */
 738         qed_init_qm_reset_params(p_hwfn);
 739
 740         /* init QM top level params */
 741         qed_init_qm_params(p_hwfn);
 742
 743         /* init QM port params */
 744         qed_init_qm_port_params(p_hwfn);
 745
 746         /* init QM vport params */
 747         qed_init_qm_vport_params(p_hwfn);
 748
 749         /* init QM physical queue params */
 750         qed_init_qm_pq_params(p_hwfn);
 751
 752         /* display all that init */
 753         qed_dp_init_qm_params(p_hwfn);
 754 }
 755
 756 /* This function reconfigures the QM pf on the fly.
 757  * For this purpose we:
 758  * 1. reconfigure the QM database
 759  * 2. set new values to runtime arrat
 760  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 761  * 4. activate init tool in QM_PF stage
 762  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 763  */
 764 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 765 {
 766         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 767         bool b_rc;
 768         int rc;
 769
 770         /* initialize qed's qm data structure */
 771         qed_init_qm_info(p_hwfn);
 772
 773         /* stop PF's qm queues */
 774         spin_lock_bh(&qm_lock);
 775         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 776                                     qm_info->start_pq, qm_info->num_pqs);
 777         spin_unlock_bh(&qm_lock);
 778         if (!b_rc)
 779                 return -EINVAL;
 780
 781         /* clear the QM_PF runtime phase leftovers from previous init */
 782         qed_init_clear_rt_data(p_hwfn);
 783
 784         /* prepare QM portion of runtime array */
 785         qed_qm_init_pf(p_hwfn, p_ptt);
 786
 787         /* activate init tool on runtime array */
 788         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 789                           p_hwfn->hw_info.hw_mode);
 790         if (rc)
 791                 return rc;
 792
 793         /* start PF's qm queues */
 794         spin_lock_bh(&qm_lock);
 795         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 796                                     qm_info->start_pq, qm_info->num_pqs);
 797         spin_unlock_bh(&qm_lock);
 798         if (!b_rc)
 799                 return -EINVAL;
 800
 801         return 0;
 802 }
 803
 804 static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn)
 805 {
 806         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 807         int rc;
 808
 809         rc = qed_init_qm_sanity(p_hwfn);
 810         if (rc)
 811                 goto alloc_err;
 812
 813         qm_info->qm_pq_params = kzalloc(sizeof(*qm_info->qm_pq_params) *
 814                                         qed_init_qm_get_num_pqs(p_hwfn),
 815                                         GFP_KERNEL);
 816         if (!qm_info->qm_pq_params)
 817                 goto alloc_err;
 818
 819         qm_info->qm_vport_params = kzalloc(sizeof(*qm_info->qm_vport_params) *
 820                                            qed_init_qm_get_num_vports(p_hwfn),
 821                                            GFP_KERNEL);
 822         if (!qm_info->qm_vport_params)
 823                 goto alloc_err;
 824
 825         qm_info->qm_port_params = kzalloc(sizeof(*qm_info->qm_port_params) *
 826                                           p_hwfn->cdev->num_ports_in_engine,
 827                                           GFP_KERNEL);
 828         if (!qm_info->qm_port_params)
 829                 goto alloc_err;
 830
 831         qm_info->wfq_data = kzalloc(sizeof(*qm_info->wfq_data) *
 832                                     qed_init_qm_get_num_vports(p_hwfn),
 833                                     GFP_KERNEL);
 834         if (!qm_info->wfq_data)
 835                 goto alloc_err;
 836
 837         return 0;
 838
 839 alloc_err:
 840         DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
 841         qed_qm_info_free(p_hwfn);
 842         return -ENOMEM;
 843 }
 844
 845 int qed_resc_alloc(struct qed_dev *cdev)
 846 {
 847         u32 rdma_tasks, excess_tasks;
 848         u32 line_count;
 849         int i, rc = 0;
 850
 851         if (IS_VF(cdev))
 852                 return rc;
 853
 854         cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
 855         if (!cdev->fw_data)
 856                 return -ENOMEM;
 857
 858         for_each_hwfn(cdev, i) {
 859                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 860                 u32 n_eqes, num_cons;
 861
 862                 /* First allocate the context manager structure */
 863                 rc = qed_cxt_mngr_alloc(p_hwfn);
 864                 if (rc)
 865                         goto alloc_err;
 866
 867                 /* Set the HW cid/tid numbers (in the contest manager)
 868                  * Must be done prior to any further computations.
 869                  */
 870                 rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS);
 871                 if (rc)
 872                         goto alloc_err;
 873
 874                 rc = qed_alloc_qm_data(p_hwfn);
 875                 if (rc)
 876                         goto alloc_err;
 877
 878                 /* init qm info */
 879                 qed_init_qm_info(p_hwfn);
 880
 881                 /* Compute the ILT client partition */
 882                 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
 883                 if (rc) {
 884                         DP_NOTICE(p_hwfn,
 885                                   "too many ILT lines; re-computing with less lines\n");
 886                         /* In case there are not enough ILT lines we reduce the
 887                          * number of RDMA tasks and re-compute.
 888                          */
 889                         excess_tasks =
 890                             qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count);
 891                         if (!excess_tasks)
 892                                 goto alloc_err;
 893
 894                         rdma_tasks = RDMA_MAX_TIDS - excess_tasks;
 895                         rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks);
 896                         if (rc)
 897                                 goto alloc_err;
 898
 899                         rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
 900                         if (rc) {
 901                                 DP_ERR(p_hwfn,
 902                                        "failed ILT compute. Requested too many lines: %u\n",
 903                                        line_count);
 904
 905                                 goto alloc_err;
 906                         }
 907                 }
 908
 909                 /* CID map / ILT shadow table / T2
 910                  * The talbes sizes are determined by the computations above
 911                  */
 912                 rc = qed_cxt_tables_alloc(p_hwfn);
 913                 if (rc)
 914                         goto alloc_err;
 915
 916                 /* SPQ, must follow ILT because initializes SPQ context */
 917                 rc = qed_spq_alloc(p_hwfn);
 918                 if (rc)
 919                         goto alloc_err;
 920
 921                 /* SP status block allocation */
 922                 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
 923                                                          RESERVED_PTT_DPC);
 924
 925                 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 926                 if (rc)
 927                         goto alloc_err;
 928
 929                 rc = qed_iov_alloc(p_hwfn);
 930                 if (rc)
 931                         goto alloc_err;
 932
 933                 /* EQ */
 934                 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
 935                 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
 936                         num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
 937                                                                PROTOCOLID_ROCE,
 938                                                                NULL) * 2;
 939                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
 940                 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 941                         num_cons =
 942                             qed_cxt_get_proto_cid_count(p_hwfn,
 943                                                         PROTOCOLID_ISCSI,
 944                                                         NULL);
 945                         n_eqes += 2 * num_cons;
 946                 }
 947
 948                 if (n_eqes > 0xFFFF) {
 949                         DP_ERR(p_hwfn,
 950                                "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
 951                                n_eqes, 0xFFFF);
 952                         goto alloc_no_mem;
 953                 }
 954
 955                 rc = qed_eq_alloc(p_hwfn, (u16) n_eqes);
 956                 if (rc)
 957                         goto alloc_err;
 958
 959                 rc = qed_consq_alloc(p_hwfn);
 960                 if (rc)
 961                         goto alloc_err;
 962
 963 #ifdef CONFIG_QED_LL2
 964                 if (p_hwfn->using_ll2) {
 965                         rc = qed_ll2_alloc(p_hwfn);
 966                         if (rc)
 967                                 goto alloc_err;
 968                 }
 969 #endif
 970
 971                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
 972                         rc = qed_fcoe_alloc(p_hwfn);
 973                         if (rc)
 974                                 goto alloc_err;
 975                 }
 976
 977                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 978                         rc = qed_iscsi_alloc(p_hwfn);
 979                         if (rc)
 980                                 goto alloc_err;
 981                         rc = qed_ooo_alloc(p_hwfn);
 982                         if (rc)
 983                                 goto alloc_err;
 984                 }
 985
 986                 /* DMA info initialization */
 987                 rc = qed_dmae_info_alloc(p_hwfn);
 988                 if (rc)
 989                         goto alloc_err;
 990
 991                 /* DCBX initialization */
 992                 rc = qed_dcbx_info_alloc(p_hwfn);
 993                 if (rc)
 994                         goto alloc_err;
 995         }
 996
 997         cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
 998         if (!cdev->reset_stats)
 999                 goto alloc_no_mem;
1000
1001         return 0;
1002
1003 alloc_no_mem:
1004         rc = -ENOMEM;
1005 alloc_err:
1006         qed_resc_free(cdev);
1007         return rc;
1008 }
1009
1010 void qed_resc_setup(struct qed_dev *cdev)
1011 {
1012         int i;
1013
1014         if (IS_VF(cdev))
1015                 return;
1016
1017         for_each_hwfn(cdev, i) {
1018                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1019
1020                 qed_cxt_mngr_setup(p_hwfn);
1021                 qed_spq_setup(p_hwfn);
1022                 qed_eq_setup(p_hwfn);
1023                 qed_consq_setup(p_hwfn);
1024
1025                 /* Read shadow of current MFW mailbox */
1026                 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1027                 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1028                        p_hwfn->mcp_info->mfw_mb_cur,
1029                        p_hwfn->mcp_info->mfw_mb_length);
1030
1031                 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1032
1033                 qed_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
1034 #ifdef CONFIG_QED_LL2
1035                 if (p_hwfn->using_ll2)
1036                         qed_ll2_setup(p_hwfn);
1037 #endif
1038                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
1039                         qed_fcoe_setup(p_hwfn);
1040
1041                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1042                         qed_iscsi_setup(p_hwfn);
1043                         qed_ooo_setup(p_hwfn);
1044                 }
1045         }
1046 }
1047
1048 #define FINAL_CLEANUP_POLL_CNT          (100)
1049 #define FINAL_CLEANUP_POLL_TIME         (10)
1050 int qed_final_cleanup(struct qed_hwfn *p_hwfn,
1051                       struct qed_ptt *p_ptt, u16 id, bool is_vf)
1052 {
1053         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1054         int rc = -EBUSY;
1055
1056         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1057                 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1058
1059         if (is_vf)
1060                 id += 0x10;
1061
1062         command |= X_FINAL_CLEANUP_AGG_INT <<
1063                 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1064         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1065         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1066         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1067
1068         /* Make sure notification is not set before initiating final cleanup */
1069         if (REG_RD(p_hwfn, addr)) {
1070                 DP_NOTICE(p_hwfn,
1071                           "Unexpected; Found final cleanup notification before initiating final cleanup\n");
1072                 REG_WR(p_hwfn, addr, 0);
1073         }
1074
1075         DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1076                    "Sending final cleanup for PFVF[%d] [Command %08x\n]",
1077                    id, command);
1078
1079         qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1080
1081         /* Poll until completion */
1082         while (!REG_RD(p_hwfn, addr) && count--)
1083                 msleep(FINAL_CLEANUP_POLL_TIME);
1084
1085         if (REG_RD(p_hwfn, addr))
1086                 rc = 0;
1087         else
1088                 DP_NOTICE(p_hwfn,
1089                           "Failed to receive FW final cleanup notification\n");
1090
1091         /* Cleanup afterwards */
1092         REG_WR(p_hwfn, addr, 0);
1093
1094         return rc;
1095 }
1096
1097 static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
1098 {
1099         int hw_mode = 0;
1100
1101         if (QED_IS_BB_B0(p_hwfn->cdev)) {
1102                 hw_mode |= 1 << MODE_BB;
1103         } else if (QED_IS_AH(p_hwfn->cdev)) {
1104                 hw_mode |= 1 << MODE_K2;
1105         } else {
1106                 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n",
1107                           p_hwfn->cdev->type);
1108                 return -EINVAL;
1109         }
1110
1111         switch (p_hwfn->cdev->num_ports_in_engine) {
1112         case 1:
1113                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1114                 break;
1115         case 2:
1116                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1117                 break;
1118         case 4:
1119                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1120                 break;
1121         default:
1122                 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
1123                           p_hwfn->cdev->num_ports_in_engine);
1124                 return -EINVAL;
1125         }
1126
1127         switch (p_hwfn->cdev->mf_mode) {
1128         case QED_MF_DEFAULT:
1129         case QED_MF_NPAR:
1130                 hw_mode |= 1 << MODE_MF_SI;
1131                 break;
1132         case QED_MF_OVLAN:
1133                 hw_mode |= 1 << MODE_MF_SD;
1134                 break;
1135         default:
1136                 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
1137                 hw_mode |= 1 << MODE_MF_SI;
1138         }
1139
1140         hw_mode |= 1 << MODE_ASIC;
1141
1142         if (p_hwfn->cdev->num_hwfns > 1)
1143                 hw_mode |= 1 << MODE_100G;
1144
1145         p_hwfn->hw_info.hw_mode = hw_mode;
1146
1147         DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
1148                    "Configuring function for hw_mode: 0x%08x\n",
1149                    p_hwfn->hw_info.hw_mode);
1150
1151         return 0;
1152 }
1153
1154 /* Init run time data for all PFs on an engine. */
1155 static void qed_init_cau_rt_data(struct qed_dev *cdev)
1156 {
1157         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1158         int i, igu_sb_id;
1159
1160         for_each_hwfn(cdev, i) {
1161                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1162                 struct qed_igu_info *p_igu_info;
1163                 struct qed_igu_block *p_block;
1164                 struct cau_sb_entry sb_entry;
1165
1166                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1167
1168                 for (igu_sb_id = 0;
1169                      igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) {
1170                         p_block = &p_igu_info->entry[igu_sb_id];
1171
1172                         if (!p_block->is_pf)
1173                                 continue;
1174
1175                         qed_init_cau_sb_entry(p_hwfn, &sb_entry,
1176                                               p_block->function_id, 0, 0);
1177                         STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1178                                          sb_entry);
1179                 }
1180         }
1181 }
1182
1183 static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn,
1184                                      struct qed_ptt *p_ptt)
1185 {
1186         u32 val, wr_mbs, cache_line_size;
1187
1188         val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1189         switch (val) {
1190         case 0:
1191                 wr_mbs = 128;
1192                 break;
1193         case 1:
1194                 wr_mbs = 256;
1195                 break;
1196         case 2:
1197                 wr_mbs = 512;
1198                 break;
1199         default:
1200                 DP_INFO(p_hwfn,
1201                         "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1202                         val);
1203                 return;
1204         }
1205
1206         cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs);
1207         switch (cache_line_size) {
1208         case 32:
1209                 val = 0;
1210                 break;
1211         case 64:
1212                 val = 1;
1213                 break;
1214         case 128:
1215                 val = 2;
1216                 break;
1217         case 256:
1218                 val = 3;
1219                 break;
1220         default:
1221                 DP_INFO(p_hwfn,
1222                         "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1223                         cache_line_size);
1224         }
1225
1226         if (L1_CACHE_BYTES > wr_mbs)
1227                 DP_INFO(p_hwfn,
1228                         "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1229                         L1_CACHE_BYTES, wr_mbs);
1230
1231         STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1232         if (val > 0) {
1233                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1234                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1235         }
1236 }
1237
1238 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
1239                               struct qed_ptt *p_ptt, int hw_mode)
1240 {
1241         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1242         struct qed_qm_common_rt_init_params params;
1243         struct qed_dev *cdev = p_hwfn->cdev;
1244         u8 vf_id, max_num_vfs;
1245         u16 num_pfs, pf_id;
1246         u32 concrete_fid;
1247         int rc = 0;
1248
1249         qed_init_cau_rt_data(cdev);
1250
1251         /* Program GTT windows */
1252         qed_gtt_init(p_hwfn);
1253
1254         if (p_hwfn->mcp_info) {
1255                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1256                         qm_info->pf_rl_en = 1;
1257                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1258                         qm_info->pf_wfq_en = 1;
1259         }
1260
1261         memset(&params, 0, sizeof(params));
1262         params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine;
1263         params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
1264         params.pf_rl_en = qm_info->pf_rl_en;
1265         params.pf_wfq_en = qm_info->pf_wfq_en;
1266         params.vport_rl_en = qm_info->vport_rl_en;
1267         params.vport_wfq_en = qm_info->vport_wfq_en;
1268         params.port_params = qm_info->qm_port_params;
1269
1270         qed_qm_common_rt_init(p_hwfn, &params);
1271
1272         qed_cxt_hw_init_common(p_hwfn);
1273
1274         qed_init_cache_line_size(p_hwfn, p_ptt);
1275
1276         rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1277         if (rc)
1278                 return rc;
1279
1280         qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1281         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1282
1283         if (QED_IS_BB(p_hwfn->cdev)) {
1284                 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
1285                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1286                         qed_fid_pretend(p_hwfn, p_ptt, pf_id);
1287                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1288                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1289                 }
1290                 /* pretend to original PF */
1291                 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1292         }
1293
1294         max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1295         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1296                 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
1297                 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
1298                 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1299                 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1300                 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1301                 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1302         }
1303         /* pretend to original PF */
1304         qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1305
1306         return rc;
1307 }
1308
1309 static int
1310 qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
1311                      struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1312 {
1313         u32 dpi_bit_shift, dpi_count, dpi_page_size;
1314         u32 min_dpis;
1315         u32 n_wids;
1316
1317         /* Calculate DPI size */
1318         n_wids = max_t(u32, QED_MIN_WIDS, n_cpus);
1319         dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids);
1320         dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
1321         dpi_bit_shift = ilog2(dpi_page_size / 4096);
1322         dpi_count = pwm_region_size / dpi_page_size;
1323
1324         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1325         min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
1326
1327         p_hwfn->dpi_size = dpi_page_size;
1328         p_hwfn->dpi_count = dpi_count;
1329
1330         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1331
1332         if (dpi_count < min_dpis)
1333                 return -EINVAL;
1334
1335         return 0;
1336 }
1337
1338 enum QED_ROCE_EDPM_MODE {
1339         QED_ROCE_EDPM_MODE_ENABLE = 0,
1340         QED_ROCE_EDPM_MODE_FORCE_ON = 1,
1341         QED_ROCE_EDPM_MODE_DISABLE = 2,
1342 };
1343
1344 static int
1345 qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1346 {
1347         u32 pwm_regsize, norm_regsize;
1348         u32 non_pwm_conn, min_addr_reg1;
1349         u32 db_bar_size, n_cpus = 1;
1350         u32 roce_edpm_mode;
1351         u32 pf_dems_shift;
1352         int rc = 0;
1353         u8 cond;
1354
1355         db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1356         if (p_hwfn->cdev->num_hwfns > 1)
1357                 db_bar_size /= 2;
1358
1359         /* Calculate doorbell regions */
1360         non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1361                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1362                                                    NULL) +
1363                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
1364                                                    NULL);
1365         norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE);
1366         min_addr_reg1 = norm_regsize / 4096;
1367         pwm_regsize = db_bar_size - norm_regsize;
1368
1369         /* Check that the normal and PWM sizes are valid */
1370         if (db_bar_size < norm_regsize) {
1371                 DP_ERR(p_hwfn->cdev,
1372                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1373                        db_bar_size, norm_regsize);
1374                 return -EINVAL;
1375         }
1376
1377         if (pwm_regsize < QED_MIN_PWM_REGION) {
1378                 DP_ERR(p_hwfn->cdev,
1379                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1380                        pwm_regsize,
1381                        QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
1382                 return -EINVAL;
1383         }
1384
1385         /* Calculate number of DPIs */
1386         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1387         if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
1388             ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
1389                 /* Either EDPM is mandatory, or we are attempting to allocate a
1390                  * WID per CPU.
1391                  */
1392                 n_cpus = num_present_cpus();
1393                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1394         }
1395
1396         cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
1397                (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
1398         if (cond || p_hwfn->dcbx_no_edpm) {
1399                 /* Either EDPM is disabled from user configuration, or it is
1400                  * disabled via DCBx, or it is not mandatory and we failed to
1401                  * allocated a WID per CPU.
1402                  */
1403                 n_cpus = 1;
1404                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1405
1406                 if (cond)
1407                         qed_rdma_dpm_bar(p_hwfn, p_ptt);
1408         }
1409
1410         p_hwfn->wid_count = (u16) n_cpus;
1411
1412         DP_INFO(p_hwfn,
1413                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1414                 norm_regsize,
1415                 pwm_regsize,
1416                 p_hwfn->dpi_size,
1417                 p_hwfn->dpi_count,
1418                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1419                 "disabled" : "enabled");
1420
1421         if (rc) {
1422                 DP_ERR(p_hwfn,
1423                        "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
1424                        p_hwfn->dpi_count,
1425                        p_hwfn->pf_params.rdma_pf_params.min_dpis);
1426                 return -EINVAL;
1427         }
1428
1429         p_hwfn->dpi_start_offset = norm_regsize;
1430
1431         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1432         pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
1433         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1434         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1435
1436         return 0;
1437 }
1438
1439 static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
1440                             struct qed_ptt *p_ptt, int hw_mode)
1441 {
1442         int rc = 0;
1443
1444         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode);
1445         if (rc)
1446                 return rc;
1447
1448         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
1449
1450         return 0;
1451 }
1452
1453 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
1454                           struct qed_ptt *p_ptt,
1455                           struct qed_tunnel_info *p_tunn,
1456                           int hw_mode,
1457                           bool b_hw_start,
1458                           enum qed_int_mode int_mode,
1459                           bool allow_npar_tx_switch)
1460 {
1461         u8 rel_pf_id = p_hwfn->rel_pf_id;
1462         int rc = 0;
1463
1464         if (p_hwfn->mcp_info) {
1465                 struct qed_mcp_function_info *p_info;
1466
1467                 p_info = &p_hwfn->mcp_info->func_info;
1468                 if (p_info->bandwidth_min)
1469                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1470
1471                 /* Update rate limit once we'll actually have a link */
1472                 p_hwfn->qm_info.pf_rl = 100000;
1473         }
1474
1475         qed_cxt_hw_init_pf(p_hwfn, p_ptt);
1476
1477         qed_int_igu_init_rt(p_hwfn);
1478
1479         /* Set VLAN in NIG if needed */
1480         if (hw_mode & BIT(MODE_MF_SD)) {
1481                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1482                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1483                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1484                              p_hwfn->hw_info.ovlan);
1485         }
1486
1487         /* Enable classification by MAC if needed */
1488         if (hw_mode & BIT(MODE_MF_SI)) {
1489                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1490                            "Configuring TAGMAC_CLS_TYPE\n");
1491                 STORE_RT_REG(p_hwfn,
1492                              NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
1493         }
1494
1495         /* Protocl Configuration  */
1496         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1497                      (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
1498         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1499                      (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0);
1500         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1501
1502         /* Cleanup chip from previous driver if such remains exist */
1503         rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1504         if (rc)
1505                 return rc;
1506
1507         /* PF Init sequence */
1508         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1509         if (rc)
1510                 return rc;
1511
1512         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1513         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1514         if (rc)
1515                 return rc;
1516
1517         /* Pure runtime initializations - directly to the HW  */
1518         qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1519
1520         rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1521         if (rc)
1522                 return rc;
1523
1524         if (b_hw_start) {
1525                 /* enable interrupts */
1526                 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
1527
1528                 /* send function start command */
1529                 rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn,
1530                                      p_hwfn->cdev->mf_mode,
1531                                      allow_npar_tx_switch);
1532                 if (rc) {
1533                         DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
1534                         return rc;
1535                 }
1536                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
1537                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2));
1538                         qed_wr(p_hwfn, p_ptt,
1539                                PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1540                                0x100);
1541                 }
1542         }
1543         return rc;
1544 }
1545
1546 static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
1547                                struct qed_ptt *p_ptt,
1548                                u8 enable)
1549 {
1550         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1551
1552         /* Change PF in PXP */
1553         qed_wr(p_hwfn, p_ptt,
1554                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1555
1556         /* wait until value is set - try for 1 second every 50us */
1557         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1558                 val = qed_rd(p_hwfn, p_ptt,
1559                              PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1560                 if (val == set_val)
1561                         break;
1562
1563                 usleep_range(50, 60);
1564         }
1565
1566         if (val != set_val) {
1567                 DP_NOTICE(p_hwfn,
1568                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1569                 return -EAGAIN;
1570         }
1571
1572         return 0;
1573 }
1574
1575 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
1576                                 struct qed_ptt *p_main_ptt)
1577 {
1578         /* Read shadow of current MFW mailbox */
1579         qed_mcp_read_mb(p_hwfn, p_main_ptt);
1580         memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1581                p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
1582 }
1583
1584 static void
1585 qed_fill_load_req_params(struct qed_load_req_params *p_load_req,
1586                          struct qed_drv_load_params *p_drv_load)
1587 {
1588         memset(p_load_req, 0, sizeof(*p_load_req));
1589
1590         p_load_req->drv_role = p_drv_load->is_crash_kernel ?
1591                                QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS;
1592         p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
1593         p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
1594         p_load_req->override_force_load = p_drv_load->override_force_load;
1595 }
1596
1597 static int qed_vf_start(struct qed_hwfn *p_hwfn,
1598                         struct qed_hw_init_params *p_params)
1599 {
1600         if (p_params->p_tunn) {
1601                 qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
1602                 qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
1603         }
1604
1605         p_hwfn->b_int_enabled = 1;
1606
1607         return 0;
1608 }
1609
1610 int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
1611 {
1612         struct qed_load_req_params load_req_params;
1613         u32 load_code, param, drv_mb_param;
1614         bool b_default_mtu = true;
1615         struct qed_hwfn *p_hwfn;
1616         int rc = 0, mfw_rc, i;
1617
1618         if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
1619                 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
1620                 return -EINVAL;
1621         }
1622
1623         if (IS_PF(cdev)) {
1624                 rc = qed_init_fw_data(cdev, p_params->bin_fw_data);
1625                 if (rc)
1626                         return rc;
1627         }
1628
1629         for_each_hwfn(cdev, i) {
1630                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1631
1632                 /* If management didn't provide a default, set one of our own */
1633                 if (!p_hwfn->hw_info.mtu) {
1634                         p_hwfn->hw_info.mtu = 1500;
1635                         b_default_mtu = false;
1636                 }
1637
1638                 if (IS_VF(cdev)) {
1639                         qed_vf_start(p_hwfn, p_params);
1640                         continue;
1641                 }
1642
1643                 /* Enable DMAE in PXP */
1644                 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1645
1646                 rc = qed_calc_hw_mode(p_hwfn);
1647                 if (rc)
1648                         return rc;
1649
1650                 qed_fill_load_req_params(&load_req_params,
1651                                          p_params->p_drv_load_params);
1652                 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
1653                                       &load_req_params);
1654                 if (rc) {
1655                         DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n");
1656                         return rc;
1657                 }
1658
1659                 load_code = load_req_params.load_code;
1660                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1661                            "Load request was sent. Load code: 0x%x\n",
1662                            load_code);
1663
1664                 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1665
1666                 p_hwfn->first_on_engine = (load_code ==
1667                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
1668
1669                 switch (load_code) {
1670                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1671                         rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1672                                                 p_hwfn->hw_info.hw_mode);
1673                         if (rc)
1674                                 break;
1675                 /* Fall into */
1676                 case FW_MSG_CODE_DRV_LOAD_PORT:
1677                         rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1678                                               p_hwfn->hw_info.hw_mode);
1679                         if (rc)
1680                                 break;
1681
1682                 /* Fall into */
1683                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1684                         rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1685                                             p_params->p_tunn,
1686                                             p_hwfn->hw_info.hw_mode,
1687                                             p_params->b_hw_start,
1688                                             p_params->int_mode,
1689                                             p_params->allow_npar_tx_switch);
1690                         break;
1691                 default:
1692                         DP_NOTICE(p_hwfn,
1693                                   "Unexpected load code [0x%08x]", load_code);
1694                         rc = -EINVAL;
1695                         break;
1696                 }
1697
1698                 if (rc)
1699                         DP_NOTICE(p_hwfn,
1700                                   "init phase failed for loadcode 0x%x (rc %d)\n",
1701                                    load_code, rc);
1702
1703                 /* ACK mfw regardless of success or failure of initialization */
1704                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1705                                      DRV_MSG_CODE_LOAD_DONE,
1706                                      0, &load_code, &param);
1707                 if (rc)
1708                         return rc;
1709                 if (mfw_rc) {
1710                         DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
1711                         return mfw_rc;
1712                 }
1713
1714                 /* Check if there is a DID mismatch between nvm-cfg/efuse */
1715                 if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
1716                         DP_NOTICE(p_hwfn,
1717                                   "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
1718
1719                 /* send DCBX attention request command */
1720                 DP_VERBOSE(p_hwfn,
1721                            QED_MSG_DCB,
1722                            "sending phony dcbx set command to trigger DCBx attention handling\n");
1723                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1724                                      DRV_MSG_CODE_SET_DCBX,
1725                                      1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1726                                      &load_code, &param);
1727                 if (mfw_rc) {
1728                         DP_NOTICE(p_hwfn,
1729                                   "Failed to send DCBX attention request\n");
1730                         return mfw_rc;
1731                 }
1732
1733                 p_hwfn->hw_init_done = true;
1734         }
1735
1736         if (IS_PF(cdev)) {
1737                 p_hwfn = QED_LEADING_HWFN(cdev);
1738                 drv_mb_param = STORM_FW_VERSION;
1739                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1740                                  DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
1741                                  drv_mb_param, &load_code, &param);
1742                 if (rc)
1743                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
1744
1745                 if (!b_default_mtu) {
1746                         rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
1747                                                    p_hwfn->hw_info.mtu);
1748                         if (rc)
1749                                 DP_INFO(p_hwfn,
1750                                         "Failed to update default mtu\n");
1751                 }
1752
1753                 rc = qed_mcp_ov_update_driver_state(p_hwfn,
1754                                                     p_hwfn->p_main_ptt,
1755                                                   QED_OV_DRIVER_STATE_DISABLED);
1756                 if (rc)
1757                         DP_INFO(p_hwfn, "Failed to update driver state\n");
1758
1759                 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
1760                                                QED_OV_ESWITCH_VEB);
1761                 if (rc)
1762                         DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
1763         }
1764
1765         return 0;
1766 }
1767
1768 #define QED_HW_STOP_RETRY_LIMIT (10)
1769 static void qed_hw_timers_stop(struct qed_dev *cdev,
1770                                struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1771 {
1772         int i;
1773
1774         /* close timers */
1775         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1776         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1777
1778         for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
1779                 if ((!qed_rd(p_hwfn, p_ptt,
1780                              TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1781                     (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1782                         break;
1783
1784                 /* Dependent on number of connection/tasks, possibly
1785                  * 1ms sleep is required between polls
1786                  */
1787                 usleep_range(1000, 2000);
1788         }
1789
1790         if (i < QED_HW_STOP_RETRY_LIMIT)
1791                 return;
1792
1793         DP_NOTICE(p_hwfn,
1794                   "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1795                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1796                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1797 }
1798
1799 void qed_hw_timers_stop_all(struct qed_dev *cdev)
1800 {
1801         int j;
1802
1803         for_each_hwfn(cdev, j) {
1804                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1805                 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1806
1807                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1808         }
1809 }
1810
1811 int qed_hw_stop(struct qed_dev *cdev)
1812 {
1813         struct qed_hwfn *p_hwfn;
1814         struct qed_ptt *p_ptt;
1815         int rc, rc2 = 0;
1816         int j;
1817
1818         for_each_hwfn(cdev, j) {
1819                 p_hwfn = &cdev->hwfns[j];
1820                 p_ptt = p_hwfn->p_main_ptt;
1821
1822                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
1823
1824                 if (IS_VF(cdev)) {
1825                         qed_vf_pf_int_cleanup(p_hwfn);
1826                         rc = qed_vf_pf_reset(p_hwfn);
1827                         if (rc) {
1828                                 DP_NOTICE(p_hwfn,
1829                                           "qed_vf_pf_reset failed. rc = %d.\n",
1830                                           rc);
1831                                 rc2 = -EINVAL;
1832                         }
1833                         continue;
1834                 }
1835
1836                 /* mark the hw as uninitialized... */
1837                 p_hwfn->hw_init_done = false;
1838
1839                 /* Send unload command to MCP */
1840                 rc = qed_mcp_unload_req(p_hwfn, p_ptt);
1841                 if (rc) {
1842                         DP_NOTICE(p_hwfn,
1843                                   "Failed sending a UNLOAD_REQ command. rc = %d.\n",
1844                                   rc);
1845                         rc2 = -EINVAL;
1846                 }
1847
1848                 qed_slowpath_irq_sync(p_hwfn);
1849
1850                 /* After this point no MFW attentions are expected, e.g. prevent
1851                  * race between pf stop and dcbx pf update.
1852                  */
1853                 rc = qed_sp_pf_stop(p_hwfn);
1854                 if (rc) {
1855                         DP_NOTICE(p_hwfn,
1856                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
1857                                   rc);
1858                         rc2 = -EINVAL;
1859                 }
1860
1861                 qed_wr(p_hwfn, p_ptt,
1862                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1863
1864                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1865                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1866                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1867                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1868                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1869
1870                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1871
1872                 /* Disable Attention Generation */
1873                 qed_int_igu_disable_int(p_hwfn, p_ptt);
1874
1875                 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1876                 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1877
1878                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1879
1880                 /* Need to wait 1ms to guarantee SBs are cleared */
1881                 usleep_range(1000, 2000);
1882
1883                 /* Disable PF in HW blocks */
1884                 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1885                 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
1886
1887                 qed_mcp_unload_done(p_hwfn, p_ptt);
1888                 if (rc) {
1889                         DP_NOTICE(p_hwfn,
1890                                   "Failed sending a UNLOAD_DONE command. rc = %d.\n",
1891                                   rc);
1892                         rc2 = -EINVAL;
1893                 }
1894         }
1895
1896         if (IS_PF(cdev)) {
1897                 p_hwfn = QED_LEADING_HWFN(cdev);
1898                 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt;
1899
1900                 /* Disable DMAE in PXP - in CMT, this should only be done for
1901                  * first hw-function, and only after all transactions have
1902                  * stopped for all active hw-functions.
1903                  */
1904                 rc = qed_change_pci_hwfn(p_hwfn, p_ptt, false);
1905                 if (rc) {
1906                         DP_NOTICE(p_hwfn,
1907                                   "qed_change_pci_hwfn failed. rc = %d.\n", rc);
1908                         rc2 = -EINVAL;
1909                 }
1910         }
1911
1912         return rc2;
1913 }
1914
1915 int qed_hw_stop_fastpath(struct qed_dev *cdev)
1916 {
1917         int j;
1918
1919         for_each_hwfn(cdev, j) {
1920                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1921                 struct qed_ptt *p_ptt;
1922
1923                 if (IS_VF(cdev)) {
1924                         qed_vf_pf_int_cleanup(p_hwfn);
1925                         continue;
1926                 }
1927                 p_ptt = qed_ptt_acquire(p_hwfn);
1928                 if (!p_ptt)
1929                         return -EAGAIN;
1930
1931                 DP_VERBOSE(p_hwfn,
1932                            NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
1933
1934                 qed_wr(p_hwfn, p_ptt,
1935                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1936
1937                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1938                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1939                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1940                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1941                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1942
1943                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1944
1945                 /* Need to wait 1ms to guarantee SBs are cleared */
1946                 usleep_range(1000, 2000);
1947                 qed_ptt_release(p_hwfn, p_ptt);
1948         }
1949
1950         return 0;
1951 }
1952
1953 int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
1954 {
1955         struct qed_ptt *p_ptt;
1956
1957         if (IS_VF(p_hwfn->cdev))
1958                 return 0;
1959
1960         p_ptt = qed_ptt_acquire(p_hwfn);
1961         if (!p_ptt)
1962                 return -EAGAIN;
1963
1964         /* If roce info is allocated it means roce is initialized and should
1965          * be enabled in searcher.
1966          */
1967         if (p_hwfn->p_rdma_info &&
1968             p_hwfn->b_rdma_enabled_in_prs)
1969                 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1);
1970
1971         /* Re-open incoming traffic */
1972         qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1973         qed_ptt_release(p_hwfn, p_ptt);
1974
1975         return 0;
1976 }
1977
1978 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
1979 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
1980 {
1981         qed_ptt_pool_free(p_hwfn);
1982         kfree(p_hwfn->hw_info.p_igu_info);
1983         p_hwfn->hw_info.p_igu_info = NULL;
1984 }
1985
1986 /* Setup bar access */
1987 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
1988 {
1989         /* clear indirect access */
1990         if (QED_IS_AH(p_hwfn->cdev)) {
1991                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1992                        PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
1993                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1994                        PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
1995                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1996                        PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
1997                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1998                        PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
1999         } else {
2000                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2001                        PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2002                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2003                        PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2004                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2005                        PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2006                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2007                        PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2008         }
2009
2010         /* Clean Previous errors if such exist */
2011         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2012                PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2013
2014         /* enable internal target-read */
2015         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2016                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2017 }
2018
2019 static void get_function_id(struct qed_hwfn *p_hwfn)
2020 {
2021         /* ME Register */
2022         p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
2023                                                   PXP_PF_ME_OPAQUE_ADDR);
2024
2025         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2026
2027         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2028         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2029                                       PXP_CONCRETE_FID_PFID);
2030         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2031                                     PXP_CONCRETE_FID_PORT);
2032
2033         DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
2034                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2035                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2036 }
2037
2038 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
2039 {
2040         u32 *feat_num = p_hwfn->hw_info.feat_num;
2041         struct qed_sb_cnt_info sb_cnt_info;
2042         u32 non_l2_sbs = 0;
2043
2044         if (IS_ENABLED(CONFIG_QED_RDMA) &&
2045             p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
2046                 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
2047                  * the status blocks equally between L2 / RoCE but with
2048                  * consideration as to how many l2 queues / cnqs we have.
2049                  */
2050                 feat_num[QED_RDMA_CNQ] =
2051                         min_t(u32, RESC_NUM(p_hwfn, QED_SB) / 2,
2052                               RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
2053
2054                 non_l2_sbs = feat_num[QED_RDMA_CNQ];
2055         }
2056
2057         if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE ||
2058             p_hwfn->hw_info.personality == QED_PCI_ETH) {
2059                 /* Start by allocating VF queues, then PF's */
2060                 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
2061                 qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2062                 feat_num[QED_VF_L2_QUE] = min_t(u32,
2063                                                 RESC_NUM(p_hwfn, QED_L2_QUEUE),
2064                                                 sb_cnt_info.iov_cnt);
2065                 feat_num[QED_PF_L2_QUE] = min_t(u32,
2066                                                 RESC_NUM(p_hwfn, QED_SB) -
2067                                                 non_l2_sbs,
2068                                                 RESC_NUM(p_hwfn,
2069                                                          QED_L2_QUEUE) -
2070                                                 FEAT_NUM(p_hwfn,
2071                                                          QED_VF_L2_QUE));
2072         }
2073
2074         if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
2075                 feat_num[QED_ISCSI_CQ] = min_t(u32, RESC_NUM(p_hwfn, QED_SB),
2076                                                RESC_NUM(p_hwfn,
2077                                                         QED_CMDQS_CQS));
2078         DP_VERBOSE(p_hwfn,
2079                    NETIF_MSG_PROBE,
2080                    "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d ISCSI_CQ=%d #SBS=%d\n",
2081                    (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
2082                    (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
2083                    (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
2084                    (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ),
2085                    RESC_NUM(p_hwfn, QED_SB));
2086 }
2087
2088 const char *qed_hw_get_resc_name(enum qed_resources res_id)
2089 {
2090         switch (res_id) {
2091         case QED_L2_QUEUE:
2092                 return "L2_QUEUE";
2093         case QED_VPORT:
2094                 return "VPORT";
2095         case QED_RSS_ENG:
2096                 return "RSS_ENG";
2097         case QED_PQ:
2098                 return "PQ";
2099         case QED_RL:
2100                 return "RL";
2101         case QED_MAC:
2102                 return "MAC";
2103         case QED_VLAN:
2104                 return "VLAN";
2105         case QED_RDMA_CNQ_RAM:
2106                 return "RDMA_CNQ_RAM";
2107         case QED_ILT:
2108                 return "ILT";
2109         case QED_LL2_QUEUE:
2110                 return "LL2_QUEUE";
2111         case QED_CMDQS_CQS:
2112                 return "CMDQS_CQS";
2113         case QED_RDMA_STATS_QUEUE:
2114                 return "RDMA_STATS_QUEUE";
2115         case QED_BDQ:
2116                 return "BDQ";
2117         case QED_SB:
2118                 return "SB";
2119         default:
2120                 return "UNKNOWN_RESOURCE";
2121         }
2122 }
2123
2124 static int
2125 __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn,
2126                             struct qed_ptt *p_ptt,
2127                             enum qed_resources res_id,
2128                             u32 resc_max_val, u32 *p_mcp_resp)
2129 {
2130         int rc;
2131
2132         rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2133                                       resc_max_val, p_mcp_resp);
2134         if (rc) {
2135                 DP_NOTICE(p_hwfn,
2136                           "MFW response failure for a max value setting of resource %d [%s]\n",
2137                           res_id, qed_hw_get_resc_name(res_id));
2138                 return rc;
2139         }
2140
2141         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2142                 DP_INFO(p_hwfn,
2143                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2144                         res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp);
2145
2146         return 0;
2147 }
2148
2149 static int
2150 qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2151 {
2152         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2153         u32 resc_max_val, mcp_resp;
2154         u8 res_id;
2155         int rc;
2156
2157         for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2158                 switch (res_id) {
2159                 case QED_LL2_QUEUE:
2160                         resc_max_val = MAX_NUM_LL2_RX_QUEUES;
2161                         break;
2162                 case QED_RDMA_CNQ_RAM:
2163                         /* No need for a case for QED_CMDQS_CQS since
2164                          * CNQ/CMDQS are the same resource.
2165                          */
2166                         resc_max_val = NUM_OF_CMDQS_CQS;
2167                         break;
2168                 case QED_RDMA_STATS_QUEUE:
2169                         resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2
2170                             : RDMA_NUM_STATISTIC_COUNTERS_BB;
2171                         break;
2172                 case QED_BDQ:
2173                         resc_max_val = BDQ_NUM_RESOURCES;
2174                         break;
2175                 default:
2176                         continue;
2177                 }
2178
2179                 rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2180                                                  resc_max_val, &mcp_resp);
2181                 if (rc)
2182                         return rc;
2183
2184                 /* There's no point to continue to the next resource if the
2185                  * command is not supported by the MFW.
2186                  * We do continue if the command is supported but the resource
2187                  * is unknown to the MFW. Such a resource will be later
2188                  * configured with the default allocation values.
2189                  */
2190                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2191                         return -EINVAL;
2192         }
2193
2194         return 0;
2195 }
2196
2197 static
2198 int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
2199                          enum qed_resources res_id,
2200                          u32 *p_resc_num, u32 *p_resc_start)
2201 {
2202         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2203         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2204         struct qed_sb_cnt_info sb_cnt_info;
2205
2206         switch (res_id) {
2207         case QED_L2_QUEUE:
2208                 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2209                                MAX_NUM_L2_QUEUES_BB) / num_funcs;
2210                 break;
2211         case QED_VPORT:
2212                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2213                                MAX_NUM_VPORTS_BB) / num_funcs;
2214                 break;
2215         case QED_RSS_ENG:
2216                 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2217                                ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2218                 break;
2219         case QED_PQ:
2220                 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2221                                MAX_QM_TX_QUEUES_BB) / num_funcs;
2222                 *p_resc_num &= ~0x7;    /* The granularity of the PQs is 8 */
2223                 break;
2224         case QED_RL:
2225                 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2226                 break;
2227         case QED_MAC:
2228         case QED_VLAN:
2229                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2230                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2231                 break;
2232         case QED_ILT:
2233                 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2234                                PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2235                 break;
2236         case QED_LL2_QUEUE:
2237                 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2238                 break;
2239         case QED_RDMA_CNQ_RAM:
2240         case QED_CMDQS_CQS:
2241                 /* CNQ/CMDQS are the same resource */
2242                 *p_resc_num = NUM_OF_CMDQS_CQS / num_funcs;
2243                 break;
2244         case QED_RDMA_STATS_QUEUE:
2245                 *p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 :
2246                                RDMA_NUM_STATISTIC_COUNTERS_BB) / num_funcs;
2247                 break;
2248         case QED_BDQ:
2249                 if (p_hwfn->hw_info.personality != QED_PCI_ISCSI &&
2250                     p_hwfn->hw_info.personality != QED_PCI_FCOE)
2251                         *p_resc_num = 0;
2252                 else
2253                         *p_resc_num = 1;
2254                 break;
2255         case QED_SB:
2256                 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
2257                 qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2258                 *p_resc_num = sb_cnt_info.cnt;
2259                 break;
2260         default:
2261                 return -EINVAL;
2262         }
2263
2264         switch (res_id) {
2265         case QED_BDQ:
2266                 if (!*p_resc_num)
2267                         *p_resc_start = 0;
2268                 else if (p_hwfn->cdev->num_ports_in_engine == 4)
2269                         *p_resc_start = p_hwfn->port_id;
2270                 else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
2271                         *p_resc_start = p_hwfn->port_id;
2272                 else if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
2273                         *p_resc_start = p_hwfn->port_id + 2;
2274                 break;
2275         default:
2276                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
2277                 break;
2278         }
2279
2280         return 0;
2281 }
2282
2283 static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
2284                                   enum qed_resources res_id)
2285 {
2286         u32 dflt_resc_num = 0, dflt_resc_start = 0;
2287         u32 mcp_resp, *p_resc_num, *p_resc_start;
2288         int rc;
2289
2290         p_resc_num = &RESC_NUM(p_hwfn, res_id);
2291         p_resc_start = &RESC_START(p_hwfn, res_id);
2292
2293         rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
2294                                   &dflt_resc_start);
2295         if (rc) {
2296                 DP_ERR(p_hwfn,
2297                        "Failed to get default amount for resource %d [%s]\n",
2298                        res_id, qed_hw_get_resc_name(res_id));
2299                 return rc;
2300         }
2301
2302         rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
2303                                    &mcp_resp, p_resc_num, p_resc_start);
2304         if (rc) {
2305                 DP_NOTICE(p_hwfn,
2306                           "MFW response failure for an allocation request for resource %d [%s]\n",
2307                           res_id, qed_hw_get_resc_name(res_id));
2308                 return rc;
2309         }
2310
2311         /* Default driver values are applied in the following cases:
2312          * - The resource allocation MB command is not supported by the MFW
2313          * - There is an internal error in the MFW while processing the request
2314          * - The resource ID is unknown to the MFW
2315          */
2316         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2317                 DP_INFO(p_hwfn,
2318                         "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n",
2319                         res_id,
2320                         qed_hw_get_resc_name(res_id),
2321                         mcp_resp, dflt_resc_num, dflt_resc_start);
2322                 *p_resc_num = dflt_resc_num;
2323                 *p_resc_start = dflt_resc_start;
2324                 goto out;
2325         }
2326
2327         /* Special handling for status blocks; Would be revised in future */
2328         if (res_id == QED_SB) {
2329                 *p_resc_num -= 1;
2330                 *p_resc_start -= p_hwfn->enabled_func_idx;
2331         }
2332 out:
2333         /* PQs have to divide by 8 [that's the HW granularity].
2334          * Reduce number so it would fit.
2335          */
2336         if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) {
2337                 DP_INFO(p_hwfn,
2338                         "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
2339                         *p_resc_num,
2340                         (*p_resc_num) & ~0x7,
2341                         *p_resc_start, (*p_resc_start) & ~0x7);
2342                 *p_resc_num &= ~0x7;
2343                 *p_resc_start &= ~0x7;
2344         }
2345
2346         return 0;
2347 }
2348
2349 static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn)
2350 {
2351         int rc;
2352         u8 res_id;
2353
2354         for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2355                 rc = __qed_hw_set_resc_info(p_hwfn, res_id);
2356                 if (rc)
2357                         return rc;
2358         }
2359
2360         return 0;
2361 }
2362
2363 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2364 {
2365         struct qed_resc_unlock_params resc_unlock_params;
2366         struct qed_resc_lock_params resc_lock_params;
2367         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2368         u8 res_id;
2369         int rc;
2370
2371         /* Setting the max values of the soft resources and the following
2372          * resources allocation queries should be atomic. Since several PFs can
2373          * run in parallel - a resource lock is needed.
2374          * If either the resource lock or resource set value commands are not
2375          * supported - skip the the max values setting, release the lock if
2376          * needed, and proceed to the queries. Other failures, including a
2377          * failure to acquire the lock, will cause this function to fail.
2378          */
2379         qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
2380                                        QED_RESC_LOCK_RESC_ALLOC, false);
2381
2382         rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
2383         if (rc && rc != -EINVAL) {
2384                 return rc;
2385         } else if (rc == -EINVAL) {
2386                 DP_INFO(p_hwfn,
2387                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
2388         } else if (!rc && !resc_lock_params.b_granted) {
2389                 DP_NOTICE(p_hwfn,
2390                           "Failed to acquire the resource lock for the resource allocation commands\n");
2391                 return -EBUSY;
2392         } else {
2393                 rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt);
2394                 if (rc && rc != -EINVAL) {
2395                         DP_NOTICE(p_hwfn,
2396                                   "Failed to set the max values of the soft resources\n");
2397                         goto unlock_and_exit;
2398                 } else if (rc == -EINVAL) {
2399                         DP_INFO(p_hwfn,
2400                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
2401                         rc = qed_mcp_resc_unlock(p_hwfn, p_ptt,
2402                                                  &resc_unlock_params);
2403                         if (rc)
2404                                 DP_INFO(p_hwfn,
2405                                         "Failed to release the resource lock for the resource allocation commands\n");
2406                 }
2407         }
2408
2409         rc = qed_hw_set_resc_info(p_hwfn);
2410         if (rc)
2411                 goto unlock_and_exit;
2412
2413         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
2414                 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2415                 if (rc)
2416                         DP_INFO(p_hwfn,
2417                                 "Failed to release the resource lock for the resource allocation commands\n");
2418         }
2419
2420         /* Sanity for ILT */
2421         if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2422             (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2423                 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
2424                           RESC_START(p_hwfn, QED_ILT),
2425                           RESC_END(p_hwfn, QED_ILT) - 1);
2426                 return -EINVAL;
2427         }
2428
2429         qed_hw_set_feat(p_hwfn);
2430
2431         for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
2432                 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
2433                            qed_hw_get_resc_name(res_id),
2434                            RESC_NUM(p_hwfn, res_id),
2435                            RESC_START(p_hwfn, res_id));
2436
2437         return 0;
2438
2439 unlock_and_exit:
2440         if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
2441                 qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2442         return rc;
2443 }
2444
2445 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2446 {
2447         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2448         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
2449         struct qed_mcp_link_params *link;
2450
2451         /* Read global nvm_cfg address */
2452         nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2453
2454         /* Verify MCP has initialized it */
2455         if (!nvm_cfg_addr) {
2456                 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
2457                 return -EINVAL;
2458         }
2459
2460         /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
2461         nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2462
2463         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2464                offsetof(struct nvm_cfg1, glob) +
2465                offsetof(struct nvm_cfg1_glob, core_cfg);
2466
2467         core_cfg = qed_rd(p_hwfn, p_ptt, addr);
2468
2469         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2470                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2471         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2472                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
2473                 break;
2474         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2475                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
2476                 break;
2477         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2478                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
2479                 break;
2480         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2481                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
2482                 break;
2483         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2484                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
2485                 break;
2486         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2487                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
2488                 break;
2489         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2490                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
2491                 break;
2492         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2493                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
2494                 break;
2495         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2496                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G;
2497                 break;
2498         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2499                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
2500                 break;
2501         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2502                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G;
2503                 break;
2504         default:
2505                 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
2506                 break;
2507         }
2508
2509         /* Read default link configuration */
2510         link = &p_hwfn->mcp_info->link_input;
2511         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2512                         offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2513         link_temp = qed_rd(p_hwfn, p_ptt,
2514                            port_cfg_addr +
2515                            offsetof(struct nvm_cfg1_port, speed_cap_mask));
2516         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2517         link->speed.advertised_speeds = link_temp;
2518
2519         link_temp = link->speed.advertised_speeds;
2520         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2521
2522         link_temp = qed_rd(p_hwfn, p_ptt,
2523                            port_cfg_addr +
2524                            offsetof(struct nvm_cfg1_port, link_settings));
2525         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2526                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2527         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2528                 link->speed.autoneg = true;
2529                 break;
2530         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2531                 link->speed.forced_speed = 1000;
2532                 break;
2533         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2534                 link->speed.forced_speed = 10000;
2535                 break;
2536         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2537                 link->speed.forced_speed = 25000;
2538                 break;
2539         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2540                 link->speed.forced_speed = 40000;
2541                 break;
2542         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2543                 link->speed.forced_speed = 50000;
2544                 break;
2545         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2546                 link->speed.forced_speed = 100000;
2547                 break;
2548         default:
2549                 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
2550         }
2551
2552         p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2553                 link->speed.autoneg;
2554
2555         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2556         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2557         link->pause.autoneg = !!(link_temp &
2558                                  NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2559         link->pause.forced_rx = !!(link_temp &
2560                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2561         link->pause.forced_tx = !!(link_temp &
2562                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2563         link->loopback_mode = 0;
2564
2565         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2566                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
2567                    link->speed.forced_speed, link->speed.advertised_speeds,
2568                    link->speed.autoneg, link->pause.autoneg);
2569
2570         /* Read Multi-function information from shmem */
2571         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2572                offsetof(struct nvm_cfg1, glob) +
2573                offsetof(struct nvm_cfg1_glob, generic_cont0);
2574
2575         generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
2576
2577         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2578                   NVM_CFG1_GLOB_MF_MODE_OFFSET;
2579
2580         switch (mf_mode) {
2581         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2582                 p_hwfn->cdev->mf_mode = QED_MF_OVLAN;
2583                 break;
2584         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2585                 p_hwfn->cdev->mf_mode = QED_MF_NPAR;
2586                 break;
2587         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2588                 p_hwfn->cdev->mf_mode = QED_MF_DEFAULT;
2589                 break;
2590         }
2591         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2592                 p_hwfn->cdev->mf_mode);
2593
2594         /* Read Multi-function information from shmem */
2595         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2596                 offsetof(struct nvm_cfg1, glob) +
2597                 offsetof(struct nvm_cfg1_glob, device_capabilities);
2598
2599         device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
2600         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2601                 __set_bit(QED_DEV_CAP_ETH,
2602                           &p_hwfn->hw_info.device_capabilities);
2603         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2604                 __set_bit(QED_DEV_CAP_FCOE,
2605                           &p_hwfn->hw_info.device_capabilities);
2606         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2607                 __set_bit(QED_DEV_CAP_ISCSI,
2608                           &p_hwfn->hw_info.device_capabilities);
2609         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2610                 __set_bit(QED_DEV_CAP_ROCE,
2611                           &p_hwfn->hw_info.device_capabilities);
2612
2613         return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2614 }
2615
2616 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2617 {
2618         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2619         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2620         struct qed_dev *cdev = p_hwfn->cdev;
2621
2622         num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2623
2624         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2625          * in the other bits are selected.
2626          * Bits 1-15 are for functions 1-15, respectively, and their value is
2627          * '0' only for enabled functions (function 0 always exists and
2628          * enabled).
2629          * In case of CMT, only the "even" functions are enabled, and thus the
2630          * number of functions for both hwfns is learnt from the same bits.
2631          */
2632         reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2633
2634         if (reg_function_hide & 0x1) {
2635                 if (QED_IS_BB(cdev)) {
2636                         if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {
2637                                 num_funcs = 0;
2638                                 eng_mask = 0xaaaa;
2639                         } else {
2640                                 num_funcs = 1;
2641                                 eng_mask = 0x5554;
2642                         }
2643                 } else {
2644                         num_funcs = 1;
2645                         eng_mask = 0xfffe;
2646                 }
2647
2648                 /* Get the number of the enabled functions on the engine */
2649                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2650                 while (tmp) {
2651                         if (tmp & 0x1)
2652                                 num_funcs++;
2653                         tmp >>= 0x1;
2654                 }
2655
2656                 /* Get the PF index within the enabled functions */
2657                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2658                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2659                 while (tmp) {
2660                         if (tmp & 0x1)
2661                                 enabled_func_idx--;
2662                         tmp >>= 0x1;
2663                 }
2664         }
2665
2666         p_hwfn->num_funcs_on_engine = num_funcs;
2667         p_hwfn->enabled_func_idx = enabled_func_idx;
2668
2669         DP_VERBOSE(p_hwfn,
2670                    NETIF_MSG_PROBE,
2671                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
2672                    p_hwfn->rel_pf_id,
2673                    p_hwfn->abs_pf_id,
2674                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
2675 }
2676
2677 static void qed_hw_info_port_num_bb(struct qed_hwfn *p_hwfn,
2678                                     struct qed_ptt *p_ptt)
2679 {
2680         u32 port_mode;
2681
2682         port_mode = qed_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0);
2683
2684         if (port_mode < 3) {
2685                 p_hwfn->cdev->num_ports_in_engine = 1;
2686         } else if (port_mode <= 5) {
2687                 p_hwfn->cdev->num_ports_in_engine = 2;
2688         } else {
2689                 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
2690                           p_hwfn->cdev->num_ports_in_engine);
2691
2692                 /* Default num_ports_in_engine to something */
2693                 p_hwfn->cdev->num_ports_in_engine = 1;
2694         }
2695 }
2696
2697 static void qed_hw_info_port_num_ah(struct qed_hwfn *p_hwfn,
2698                                     struct qed_ptt *p_ptt)
2699 {
2700         u32 port;
2701         int i;
2702
2703         p_hwfn->cdev->num_ports_in_engine = 0;
2704
2705         for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2706                 port = qed_rd(p_hwfn, p_ptt,
2707                               CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2708                 if (port & 1)
2709                         p_hwfn->cdev->num_ports_in_engine++;
2710         }
2711
2712         if (!p_hwfn->cdev->num_ports_in_engine) {
2713                 DP_NOTICE(p_hwfn, "All NIG ports are inactive\n");
2714
2715                 /* Default num_ports_in_engine to something */
2716                 p_hwfn->cdev->num_ports_in_engine = 1;
2717         }
2718 }
2719
2720 static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2721 {
2722         if (QED_IS_BB(p_hwfn->cdev))
2723                 qed_hw_info_port_num_bb(p_hwfn, p_ptt);
2724         else
2725                 qed_hw_info_port_num_ah(p_hwfn, p_ptt);
2726 }
2727
2728 static int
2729 qed_get_hw_info(struct qed_hwfn *p_hwfn,
2730                 struct qed_ptt *p_ptt,
2731                 enum qed_pci_personality personality)
2732 {
2733         int rc;
2734
2735         /* Since all information is common, only first hwfns should do this */
2736         if (IS_LEAD_HWFN(p_hwfn)) {
2737                 rc = qed_iov_hw_info(p_hwfn);
2738                 if (rc)
2739                         return rc;
2740         }
2741
2742         qed_hw_info_port_num(p_hwfn, p_ptt);
2743
2744         qed_hw_get_nvm_info(p_hwfn, p_ptt);
2745
2746         rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
2747         if (rc)
2748                 return rc;
2749
2750         if (qed_mcp_is_init(p_hwfn))
2751                 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
2752                                 p_hwfn->mcp_info->func_info.mac);
2753         else
2754                 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
2755
2756         if (qed_mcp_is_init(p_hwfn)) {
2757                 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
2758                         p_hwfn->hw_info.ovlan =
2759                                 p_hwfn->mcp_info->func_info.ovlan;
2760
2761                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
2762         }
2763
2764         if (qed_mcp_is_init(p_hwfn)) {
2765                 enum qed_pci_personality protocol;
2766
2767                 protocol = p_hwfn->mcp_info->func_info.protocol;
2768                 p_hwfn->hw_info.personality = protocol;
2769         }
2770
2771         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
2772         p_hwfn->hw_info.num_active_tc = 1;
2773
2774         qed_get_num_funcs(p_hwfn, p_ptt);
2775
2776         if (qed_mcp_is_init(p_hwfn))
2777                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
2778
2779         return qed_hw_get_resc(p_hwfn, p_ptt);
2780 }
2781
2782 static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2783 {
2784         struct qed_dev *cdev = p_hwfn->cdev;
2785         u16 device_id_mask;
2786         u32 tmp;
2787
2788         /* Read Vendor Id / Device Id */
2789         pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
2790         pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
2791
2792         /* Determine type */
2793         device_id_mask = cdev->device_id & QED_DEV_ID_MASK;
2794         switch (device_id_mask) {
2795         case QED_DEV_ID_MASK_BB:
2796                 cdev->type = QED_DEV_TYPE_BB;
2797                 break;
2798         case QED_DEV_ID_MASK_AH:
2799                 cdev->type = QED_DEV_TYPE_AH;
2800                 break;
2801         default:
2802                 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id);
2803                 return -EBUSY;
2804         }
2805
2806         cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
2807         cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
2808
2809         MASK_FIELD(CHIP_REV, cdev->chip_rev);
2810
2811         /* Learn number of HW-functions */
2812         tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
2813
2814         if (tmp & (1 << p_hwfn->rel_pf_id)) {
2815                 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
2816                 cdev->num_hwfns = 2;
2817         } else {
2818                 cdev->num_hwfns = 1;
2819         }
2820
2821         cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt,
2822                                     MISCS_REG_CHIP_TEST_REG) >> 4;
2823         MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
2824         cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
2825         MASK_FIELD(CHIP_METAL, cdev->chip_metal);
2826
2827         DP_INFO(cdev->hwfns,
2828                 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
2829                 QED_IS_BB(cdev) ? "BB" : "AH",
2830                 'A' + cdev->chip_rev,
2831                 (int)cdev->chip_metal,
2832                 cdev->chip_num, cdev->chip_rev,
2833                 cdev->chip_bond_id, cdev->chip_metal);
2834
2835         return 0;
2836 }
2837
2838 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
2839                                  void __iomem *p_regview,
2840                                  void __iomem *p_doorbells,
2841                                  enum qed_pci_personality personality)
2842 {
2843         int rc = 0;
2844
2845         /* Split PCI bars evenly between hwfns */
2846         p_hwfn->regview = p_regview;
2847         p_hwfn->doorbells = p_doorbells;
2848
2849         if (IS_VF(p_hwfn->cdev))
2850                 return qed_vf_hw_prepare(p_hwfn);
2851
2852         /* Validate that chip access is feasible */
2853         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
2854                 DP_ERR(p_hwfn,
2855                        "Reading the ME register returns all Fs; Preventing further chip access\n");
2856                 return -EINVAL;
2857         }
2858
2859         get_function_id(p_hwfn);
2860
2861         /* Allocate PTT pool */
2862         rc = qed_ptt_pool_alloc(p_hwfn);
2863         if (rc)
2864                 goto err0;
2865
2866         /* Allocate the main PTT */
2867         p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
2868
2869         /* First hwfn learns basic information, e.g., number of hwfns */
2870         if (!p_hwfn->my_id) {
2871                 rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
2872                 if (rc)
2873                         goto err1;
2874         }
2875
2876         qed_hw_hwfn_prepare(p_hwfn);
2877
2878         /* Initialize MCP structure */
2879         rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
2880         if (rc) {
2881                 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
2882                 goto err1;
2883         }
2884
2885         /* Read the device configuration information from the HW and SHMEM */
2886         rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
2887         if (rc) {
2888                 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
2889                 goto err2;
2890         }
2891
2892         /* Sending a mailbox to the MFW should be done after qed_get_hw_info()
2893          * is called as it sets the ports number in an engine.
2894          */
2895         if (IS_LEAD_HWFN(p_hwfn)) {
2896                 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
2897                 if (rc)
2898                         DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n");
2899         }
2900
2901         /* Allocate the init RT array and initialize the init-ops engine */
2902         rc = qed_init_alloc(p_hwfn);
2903         if (rc)
2904                 goto err2;
2905
2906         return rc;
2907 err2:
2908         if (IS_LEAD_HWFN(p_hwfn))
2909                 qed_iov_free_hw_info(p_hwfn->cdev);
2910         qed_mcp_free(p_hwfn);
2911 err1:
2912         qed_hw_hwfn_free(p_hwfn);
2913 err0:
2914         return rc;
2915 }
2916
2917 int qed_hw_prepare(struct qed_dev *cdev,
2918                    int personality)
2919 {
2920         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2921         int rc;
2922
2923         /* Store the precompiled init data ptrs */
2924         if (IS_PF(cdev))
2925                 qed_init_iro_array(cdev);
2926
2927         /* Initialize the first hwfn - will learn number of hwfns */
2928         rc = qed_hw_prepare_single(p_hwfn,
2929                                    cdev->regview,
2930                                    cdev->doorbells, personality);
2931         if (rc)
2932                 return rc;
2933
2934         personality = p_hwfn->hw_info.personality;
2935
2936         /* Initialize the rest of the hwfns */
2937         if (cdev->num_hwfns > 1) {
2938                 void __iomem *p_regview, *p_doorbell;
2939                 u8 __iomem *addr;
2940
2941                 /* adjust bar offset for second engine */
2942                 addr = cdev->regview +
2943                        qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
2944                                        BAR_ID_0) / 2;
2945                 p_regview = addr;
2946
2947                 addr = cdev->doorbells +
2948                        qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
2949                                        BAR_ID_1) / 2;
2950                 p_doorbell = addr;
2951
2952                 /* prepare second hw function */
2953                 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
2954                                            p_doorbell, personality);
2955
2956                 /* in case of error, need to free the previously
2957                  * initiliazed hwfn 0.
2958                  */
2959                 if (rc) {
2960                         if (IS_PF(cdev)) {
2961                                 qed_init_free(p_hwfn);
2962                                 qed_mcp_free(p_hwfn);
2963                                 qed_hw_hwfn_free(p_hwfn);
2964                         }
2965                 }
2966         }
2967
2968         return rc;
2969 }
2970
2971 void qed_hw_remove(struct qed_dev *cdev)
2972 {
2973         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2974         int i;
2975
2976         if (IS_PF(cdev))
2977                 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
2978                                                QED_OV_DRIVER_STATE_NOT_LOADED);
2979
2980         for_each_hwfn(cdev, i) {
2981                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2982
2983                 if (IS_VF(cdev)) {
2984                         qed_vf_pf_release(p_hwfn);
2985                         continue;
2986                 }
2987
2988                 qed_init_free(p_hwfn);
2989                 qed_hw_hwfn_free(p_hwfn);
2990                 qed_mcp_free(p_hwfn);
2991         }
2992
2993         qed_iov_free_hw_info(cdev);
2994 }
2995
2996 static void qed_chain_free_next_ptr(struct qed_dev *cdev,
2997                                     struct qed_chain *p_chain)
2998 {
2999         void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
3000         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3001         struct qed_chain_next *p_next;
3002         u32 size, i;
3003
3004         if (!p_virt)
3005                 return;
3006
3007         size = p_chain->elem_size * p_chain->usable_per_page;
3008
3009         for (i = 0; i < p_chain->page_cnt; i++) {
3010                 if (!p_virt)
3011                         break;
3012
3013                 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
3014                 p_virt_next = p_next->next_virt;
3015                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3016
3017                 dma_free_coherent(&cdev->pdev->dev,
3018                                   QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
3019
3020                 p_virt = p_virt_next;
3021                 p_phys = p_phys_next;
3022         }
3023 }
3024
3025 static void qed_chain_free_single(struct qed_dev *cdev,
3026                                   struct qed_chain *p_chain)
3027 {
3028         if (!p_chain->p_virt_addr)
3029                 return;
3030
3031         dma_free_coherent(&cdev->pdev->dev,
3032                           QED_CHAIN_PAGE_SIZE,
3033                           p_chain->p_virt_addr, p_chain->p_phys_addr);
3034 }
3035
3036 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
3037 {
3038         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3039         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3040         u8 *p_pbl_virt = p_chain->pbl_sp.p_virt_table;
3041
3042         if (!pp_virt_addr_tbl)
3043                 return;
3044
3045         if (!p_pbl_virt)
3046                 goto out;
3047
3048         for (i = 0; i < page_cnt; i++) {
3049                 if (!pp_virt_addr_tbl[i])
3050                         break;
3051
3052                 dma_free_coherent(&cdev->pdev->dev,
3053                                   QED_CHAIN_PAGE_SIZE,
3054                                   pp_virt_addr_tbl[i],
3055                                   *(dma_addr_t *)p_pbl_virt);
3056
3057                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3058         }
3059
3060         pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3061         dma_free_coherent(&cdev->pdev->dev,
3062                           pbl_size,
3063                           p_chain->pbl_sp.p_virt_table,
3064                           p_chain->pbl_sp.p_phys_table);
3065 out:
3066         vfree(p_chain->pbl.pp_virt_addr_tbl);
3067 }
3068
3069 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
3070 {
3071         switch (p_chain->mode) {
3072         case QED_CHAIN_MODE_NEXT_PTR:
3073                 qed_chain_free_next_ptr(cdev, p_chain);
3074                 break;
3075         case QED_CHAIN_MODE_SINGLE:
3076                 qed_chain_free_single(cdev, p_chain);
3077                 break;
3078         case QED_CHAIN_MODE_PBL:
3079                 qed_chain_free_pbl(cdev, p_chain);
3080                 break;
3081         }
3082 }
3083
3084 static int
3085 qed_chain_alloc_sanity_check(struct qed_dev *cdev,
3086                              enum qed_chain_cnt_type cnt_type,
3087                              size_t elem_size, u32 page_cnt)
3088 {
3089         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3090
3091         /* The actual chain size can be larger than the maximal possible value
3092          * after rounding up the requested elements number to pages, and after
3093          * taking into acount the unusuable elements (next-ptr elements).
3094          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3095          * size/capacity fields are of a u32 type.
3096          */
3097         if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
3098              chain_size > ((u32)U16_MAX + 1)) ||
3099             (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) {
3100                 DP_NOTICE(cdev,
3101                           "The actual chain size (0x%llx) is larger than the maximal possible value\n",
3102                           chain_size);
3103                 return -EINVAL;
3104         }
3105
3106         return 0;
3107 }
3108
3109 static int
3110 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
3111 {
3112         void *p_virt = NULL, *p_virt_prev = NULL;
3113         dma_addr_t p_phys = 0;
3114         u32 i;
3115
3116         for (i = 0; i < p_chain->page_cnt; i++) {
3117                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3118                                             QED_CHAIN_PAGE_SIZE,
3119                                             &p_phys, GFP_KERNEL);
3120                 if (!p_virt)
3121                         return -ENOMEM;
3122
3123                 if (i == 0) {
3124                         qed_chain_init_mem(p_chain, p_virt, p_phys);
3125                         qed_chain_reset(p_chain);
3126                 } else {
3127                         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3128                                                      p_virt, p_phys);
3129                 }
3130
3131                 p_virt_prev = p_virt;
3132         }
3133         /* Last page's next element should point to the beginning of the
3134          * chain.
3135          */
3136         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3137                                      p_chain->p_virt_addr,
3138                                      p_chain->p_phys_addr);
3139
3140         return 0;
3141 }
3142
3143 static int
3144 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
3145 {
3146         dma_addr_t p_phys = 0;
3147         void *p_virt = NULL;
3148
3149         p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3150                                     QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
3151         if (!p_virt)
3152                 return -ENOMEM;
3153
3154         qed_chain_init_mem(p_chain, p_virt, p_phys);
3155         qed_chain_reset(p_chain);
3156
3157         return 0;
3158 }
3159
3160 static int qed_chain_alloc_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
3161 {
3162         u32 page_cnt = p_chain->page_cnt, size, i;
3163         dma_addr_t p_phys = 0, p_pbl_phys = 0;
3164         void **pp_virt_addr_tbl = NULL;
3165         u8 *p_pbl_virt = NULL;
3166         void *p_virt = NULL;
3167
3168         size = page_cnt * sizeof(*pp_virt_addr_tbl);
3169         pp_virt_addr_tbl = vzalloc(size);
3170         if (!pp_virt_addr_tbl)
3171                 return -ENOMEM;
3172
3173         /* The allocation of the PBL table is done with its full size, since it
3174          * is expected to be successive.
3175          * qed_chain_init_pbl_mem() is called even in a case of an allocation
3176          * failure, since pp_virt_addr_tbl was previously allocated, and it
3177          * should be saved to allow its freeing during the error flow.
3178          */
3179         size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3180         p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
3181                                         size, &p_pbl_phys, GFP_KERNEL);
3182         qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3183                                pp_virt_addr_tbl);
3184         if (!p_pbl_virt)
3185                 return -ENOMEM;
3186
3187         for (i = 0; i < page_cnt; i++) {
3188                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3189                                             QED_CHAIN_PAGE_SIZE,
3190                                             &p_phys, GFP_KERNEL);
3191                 if (!p_virt)
3192                         return -ENOMEM;
3193
3194                 if (i == 0) {
3195                         qed_chain_init_mem(p_chain, p_virt, p_phys);
3196                         qed_chain_reset(p_chain);
3197                 }
3198
3199                 /* Fill the PBL table with the physical address of the page */
3200                 *(dma_addr_t *)p_pbl_virt = p_phys;
3201                 /* Keep the virtual address of the page */
3202                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3203
3204                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3205         }
3206
3207         return 0;
3208 }
3209
3210 int qed_chain_alloc(struct qed_dev *cdev,
3211                     enum qed_chain_use_mode intended_use,
3212                     enum qed_chain_mode mode,
3213                     enum qed_chain_cnt_type cnt_type,
3214                     u32 num_elems, size_t elem_size, struct qed_chain *p_chain)
3215 {
3216         u32 page_cnt;
3217         int rc = 0;
3218
3219         if (mode == QED_CHAIN_MODE_SINGLE)
3220                 page_cnt = 1;
3221         else
3222                 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3223
3224         rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
3225         if (rc) {
3226                 DP_NOTICE(cdev,
3227                           "Cannot allocate a chain with the given arguments:\n");
3228                 DP_NOTICE(cdev,
3229                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3230                           intended_use, mode, cnt_type, num_elems, elem_size);
3231                 return rc;
3232         }
3233
3234         qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
3235                               mode, cnt_type);
3236
3237         switch (mode) {
3238         case QED_CHAIN_MODE_NEXT_PTR:
3239                 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
3240                 break;
3241         case QED_CHAIN_MODE_SINGLE:
3242                 rc = qed_chain_alloc_single(cdev, p_chain);
3243                 break;
3244         case QED_CHAIN_MODE_PBL:
3245                 rc = qed_chain_alloc_pbl(cdev, p_chain);
3246                 break;
3247         }
3248         if (rc)
3249                 goto nomem;
3250
3251         return 0;
3252
3253 nomem:
3254         qed_chain_free(cdev, p_chain);
3255         return rc;
3256 }
3257
3258 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
3259 {
3260         if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
3261                 u16 min, max;
3262
3263                 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
3264                 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
3265                 DP_NOTICE(p_hwfn,
3266                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3267                           src_id, min, max);
3268
3269                 return -EINVAL;
3270         }
3271
3272         *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
3273
3274         return 0;
3275 }
3276
3277 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3278 {
3279         if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
3280                 u8 min, max;
3281
3282                 min = (u8)RESC_START(p_hwfn, QED_VPORT);
3283                 max = min + RESC_NUM(p_hwfn, QED_VPORT);
3284                 DP_NOTICE(p_hwfn,
3285                           "vport id [%d] is not valid, available indices [%d - %d]\n",
3286                           src_id, min, max);
3287
3288                 return -EINVAL;
3289         }
3290
3291         *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
3292
3293         return 0;
3294 }
3295
3296 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3297 {
3298         if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
3299                 u8 min, max;
3300
3301                 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
3302                 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
3303                 DP_NOTICE(p_hwfn,
3304                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3305                           src_id, min, max);
3306
3307                 return -EINVAL;
3308         }
3309
3310         *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
3311
3312         return 0;
3313 }
3314
3315 static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low,
3316                                   u8 *p_filter)
3317 {
3318         *p_high = p_filter[1] | (p_filter[0] << 8);
3319         *p_low = p_filter[5] | (p_filter[4] << 8) |
3320                  (p_filter[3] << 16) | (p_filter[2] << 24);
3321 }
3322
3323 int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
3324                            struct qed_ptt *p_ptt, u8 *p_filter)
3325 {
3326         u32 high = 0, low = 0, en;
3327         int i;
3328
3329         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3330                 return 0;
3331
3332         qed_llh_mac_to_filter(&high, &low, p_filter);
3333
3334         /* Find a free entry and utilize it */
3335         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3336                 en = qed_rd(p_hwfn, p_ptt,
3337                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3338                 if (en)
3339                         continue;
3340                 qed_wr(p_hwfn, p_ptt,
3341                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3342                        2 * i * sizeof(u32), low);
3343                 qed_wr(p_hwfn, p_ptt,
3344                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3345                        (2 * i + 1) * sizeof(u32), high);
3346                 qed_wr(p_hwfn, p_ptt,
3347                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3348                 qed_wr(p_hwfn, p_ptt,
3349                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3350                        i * sizeof(u32), 0);
3351                 qed_wr(p_hwfn, p_ptt,
3352                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3353                 break;
3354         }
3355         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3356                 DP_NOTICE(p_hwfn,
3357                           "Failed to find an empty LLH filter to utilize\n");
3358                 return -EINVAL;
3359         }
3360
3361         DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3362                    "mac: %pM is added at %d\n",
3363                    p_filter, i);
3364
3365         return 0;
3366 }
3367
3368 void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
3369                                struct qed_ptt *p_ptt, u8 *p_filter)
3370 {
3371         u32 high = 0, low = 0;
3372         int i;
3373
3374         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3375                 return;
3376
3377         qed_llh_mac_to_filter(&high, &low, p_filter);
3378
3379         /* Find the entry and clean it */
3380         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3381                 if (qed_rd(p_hwfn, p_ptt,
3382                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3383                            2 * i * sizeof(u32)) != low)
3384                         continue;
3385                 if (qed_rd(p_hwfn, p_ptt,
3386                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3387                            (2 * i + 1) * sizeof(u32)) != high)
3388                         continue;
3389
3390                 qed_wr(p_hwfn, p_ptt,
3391                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3392                 qed_wr(p_hwfn, p_ptt,
3393                        NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3394                 qed_wr(p_hwfn, p_ptt,
3395                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3396                        (2 * i + 1) * sizeof(u32), 0);
3397
3398                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3399                            "mac: %pM is removed from %d\n",
3400                            p_filter, i);
3401                 break;
3402         }
3403         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3404                 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3405 }
3406
3407 int
3408 qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn,
3409                             struct qed_ptt *p_ptt,
3410                             u16 source_port_or_eth_type,
3411                             u16 dest_port, enum qed_llh_port_filter_type_t type)
3412 {
3413         u32 high = 0, low = 0, en;
3414         int i;
3415
3416         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3417                 return 0;
3418
3419         switch (type) {
3420         case QED_LLH_FILTER_ETHERTYPE:
3421                 high = source_port_or_eth_type;
3422                 break;
3423         case QED_LLH_FILTER_TCP_SRC_PORT:
3424         case QED_LLH_FILTER_UDP_SRC_PORT:
3425                 low = source_port_or_eth_type << 16;
3426                 break;
3427         case QED_LLH_FILTER_TCP_DEST_PORT:
3428         case QED_LLH_FILTER_UDP_DEST_PORT:
3429                 low = dest_port;
3430                 break;
3431         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3432         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3433                 low = (source_port_or_eth_type << 16) | dest_port;
3434                 break;
3435         default:
3436                 DP_NOTICE(p_hwfn,
3437                           "Non valid LLH protocol filter type %d\n", type);
3438                 return -EINVAL;
3439         }
3440         /* Find a free entry and utilize it */
3441         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3442                 en = qed_rd(p_hwfn, p_ptt,
3443                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3444                 if (en)
3445                         continue;
3446                 qed_wr(p_hwfn, p_ptt,
3447                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3448                        2 * i * sizeof(u32), low);
3449                 qed_wr(p_hwfn, p_ptt,
3450                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3451                        (2 * i + 1) * sizeof(u32), high);
3452                 qed_wr(p_hwfn, p_ptt,
3453                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
3454                 qed_wr(p_hwfn, p_ptt,
3455                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3456                        i * sizeof(u32), 1 << type);
3457                 qed_wr(p_hwfn, p_ptt,
3458                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3459                 break;
3460         }
3461         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3462                 DP_NOTICE(p_hwfn,
3463                           "Failed to find an empty LLH filter to utilize\n");
3464                 return -EINVAL;
3465         }
3466         switch (type) {
3467         case QED_LLH_FILTER_ETHERTYPE:
3468                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3469                            "ETH type %x is added at %d\n",
3470                            source_port_or_eth_type, i);
3471                 break;
3472         case QED_LLH_FILTER_TCP_SRC_PORT:
3473                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3474                            "TCP src port %x is added at %d\n",
3475                            source_port_or_eth_type, i);
3476                 break;
3477         case QED_LLH_FILTER_UDP_SRC_PORT:
3478                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3479                            "UDP src port %x is added at %d\n",
3480                            source_port_or_eth_type, i);
3481                 break;
3482         case QED_LLH_FILTER_TCP_DEST_PORT:
3483                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3484                            "TCP dst port %x is added at %d\n", dest_port, i);
3485                 break;
3486         case QED_LLH_FILTER_UDP_DEST_PORT:
3487                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3488                            "UDP dst port %x is added at %d\n", dest_port, i);
3489                 break;
3490         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3491                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3492                            "TCP src/dst ports %x/%x are added at %d\n",
3493                            source_port_or_eth_type, dest_port, i);
3494                 break;
3495         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3496                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3497                            "UDP src/dst ports %x/%x are added at %d\n",
3498                            source_port_or_eth_type, dest_port, i);
3499                 break;
3500         }
3501         return 0;
3502 }
3503
3504 void
3505 qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn,
3506                                struct qed_ptt *p_ptt,
3507                                u16 source_port_or_eth_type,
3508                                u16 dest_port,
3509                                enum qed_llh_port_filter_type_t type)
3510 {
3511         u32 high = 0, low = 0;
3512         int i;
3513
3514         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3515                 return;
3516
3517         switch (type) {
3518         case QED_LLH_FILTER_ETHERTYPE:
3519                 high = source_port_or_eth_type;
3520                 break;
3521         case QED_LLH_FILTER_TCP_SRC_PORT:
3522         case QED_LLH_FILTER_UDP_SRC_PORT:
3523                 low = source_port_or_eth_type << 16;
3524                 break;
3525         case QED_LLH_FILTER_TCP_DEST_PORT:
3526         case QED_LLH_FILTER_UDP_DEST_PORT:
3527                 low = dest_port;
3528                 break;
3529         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3530         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3531                 low = (source_port_or_eth_type << 16) | dest_port;
3532                 break;
3533         default:
3534                 DP_NOTICE(p_hwfn,
3535                           "Non valid LLH protocol filter type %d\n", type);
3536                 return;
3537         }
3538
3539         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3540                 if (!qed_rd(p_hwfn, p_ptt,
3541                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
3542                         continue;
3543                 if (!qed_rd(p_hwfn, p_ptt,
3544                             NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
3545                         continue;
3546                 if (!(qed_rd(p_hwfn, p_ptt,
3547                              NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3548                              i * sizeof(u32)) & BIT(type)))
3549                         continue;
3550                 if (qed_rd(p_hwfn, p_ptt,
3551                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3552                            2 * i * sizeof(u32)) != low)
3553                         continue;
3554                 if (qed_rd(p_hwfn, p_ptt,
3555                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3556                            (2 * i + 1) * sizeof(u32)) != high)
3557                         continue;
3558
3559                 qed_wr(p_hwfn, p_ptt,
3560                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3561                 qed_wr(p_hwfn, p_ptt,
3562                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3563                 qed_wr(p_hwfn, p_ptt,
3564                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3565                        i * sizeof(u32), 0);
3566                 qed_wr(p_hwfn, p_ptt,
3567                        NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3568                 qed_wr(p_hwfn, p_ptt,
3569                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3570                        (2 * i + 1) * sizeof(u32), 0);
3571                 break;
3572         }
3573
3574         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3575                 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3576 }
3577
3578 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3579                             u32 hw_addr, void *p_eth_qzone,
3580                             size_t eth_qzone_size, u8 timeset)
3581 {
3582         struct coalescing_timeset *p_coal_timeset;
3583
3584         if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
3585                 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
3586                 return -EINVAL;
3587         }
3588
3589         p_coal_timeset = p_eth_qzone;
3590         memset(p_coal_timeset, 0, eth_qzone_size);
3591         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
3592         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
3593         qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
3594
3595         return 0;
3596 }
3597
3598 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3599                          u16 coalesce, u16 qid, u16 sb_id)
3600 {
3601         struct ustorm_eth_queue_zone eth_qzone;
3602         u8 timeset, timer_res;
3603         u16 fw_qid = 0;
3604         u32 address;
3605         int rc;
3606
3607         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3608         if (coalesce <= 0x7F) {
3609                 timer_res = 0;
3610         } else if (coalesce <= 0xFF) {
3611                 timer_res = 1;
3612         } else if (coalesce <= 0x1FF) {
3613                 timer_res = 2;
3614         } else {
3615                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3616                 return -EINVAL;
3617         }
3618         timeset = (u8)(coalesce >> timer_res);
3619
3620         rc = qed_fw_l2_queue(p_hwfn, qid, &fw_qid);
3621         if (rc)
3622                 return rc;
3623
3624         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
3625         if (rc)
3626                 goto out;
3627
3628         address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3629
3630         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3631                               sizeof(struct ustorm_eth_queue_zone), timeset);
3632         if (rc)
3633                 goto out;
3634
3635         p_hwfn->cdev->rx_coalesce_usecs = coalesce;
3636 out:
3637         return rc;
3638 }
3639
3640 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3641                          u16 coalesce, u16 qid, u16 sb_id)
3642 {
3643         struct xstorm_eth_queue_zone eth_qzone;
3644         u8 timeset, timer_res;
3645         u16 fw_qid = 0;
3646         u32 address;
3647         int rc;
3648
3649         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3650         if (coalesce <= 0x7F) {
3651                 timer_res = 0;
3652         } else if (coalesce <= 0xFF) {
3653                 timer_res = 1;
3654         } else if (coalesce <= 0x1FF) {
3655                 timer_res = 2;
3656         } else {
3657                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3658                 return -EINVAL;
3659         }
3660         timeset = (u8)(coalesce >> timer_res);
3661
3662         rc = qed_fw_l2_queue(p_hwfn, qid, &fw_qid);
3663         if (rc)
3664                 return rc;
3665
3666         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
3667         if (rc)
3668                 goto out;
3669
3670         address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3671
3672         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3673                               sizeof(struct xstorm_eth_queue_zone), timeset);
3674         if (rc)
3675                 goto out;
3676
3677         p_hwfn->cdev->tx_coalesce_usecs = coalesce;
3678 out:
3679         return rc;
3680 }
3681
3682 /* Calculate final WFQ values for all vports and configure them.
3683  * After this configuration each vport will have
3684  * approx min rate =  min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
3685  */
3686 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
3687                                              struct qed_ptt *p_ptt,
3688                                              u32 min_pf_rate)
3689 {
3690         struct init_qm_vport_params *vport_params;
3691         int i;
3692
3693         vport_params = p_hwfn->qm_info.qm_vport_params;
3694
3695         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3696                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3697
3698                 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
3699                                                 min_pf_rate;
3700                 qed_init_vport_wfq(p_hwfn, p_ptt,
3701                                    vport_params[i].first_tx_pq_id,
3702                                    vport_params[i].vport_wfq);
3703         }
3704 }
3705
3706 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
3707                                        u32 min_pf_rate)
3708
3709 {
3710         int i;
3711
3712         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
3713                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
3714 }
3715
3716 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
3717                                            struct qed_ptt *p_ptt,
3718                                            u32 min_pf_rate)
3719 {
3720         struct init_qm_vport_params *vport_params;
3721         int i;
3722
3723         vport_params = p_hwfn->qm_info.qm_vport_params;
3724
3725         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3726                 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
3727                 qed_init_vport_wfq(p_hwfn, p_ptt,
3728                                    vport_params[i].first_tx_pq_id,
3729                                    vport_params[i].vport_wfq);
3730         }
3731 }
3732
3733 /* This function performs several validations for WFQ
3734  * configuration and required min rate for a given vport
3735  * 1. req_rate must be greater than one percent of min_pf_rate.
3736  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
3737  *    rates to get less than one percent of min_pf_rate.
3738  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
3739  */
3740 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
3741                               u16 vport_id, u32 req_rate, u32 min_pf_rate)
3742 {
3743         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
3744         int non_requested_count = 0, req_count = 0, i, num_vports;
3745
3746         num_vports = p_hwfn->qm_info.num_vports;
3747
3748         /* Accounting for the vports which are configured for WFQ explicitly */
3749         for (i = 0; i < num_vports; i++) {
3750                 u32 tmp_speed;
3751
3752                 if ((i != vport_id) &&
3753                     p_hwfn->qm_info.wfq_data[i].configured) {
3754                         req_count++;
3755                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3756                         total_req_min_rate += tmp_speed;
3757                 }
3758         }
3759
3760         /* Include current vport data as well */
3761         req_count++;
3762         total_req_min_rate += req_rate;
3763         non_requested_count = num_vports - req_count;
3764
3765         if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
3766                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3767                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3768                            vport_id, req_rate, min_pf_rate);
3769                 return -EINVAL;
3770         }
3771
3772         if (num_vports > QED_WFQ_UNIT) {
3773                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3774                            "Number of vports is greater than %d\n",
3775                            QED_WFQ_UNIT);
3776                 return -EINVAL;
3777         }
3778
3779         if (total_req_min_rate > min_pf_rate) {
3780                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3781                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
3782                            total_req_min_rate, min_pf_rate);
3783                 return -EINVAL;
3784         }
3785
3786         total_left_rate = min_pf_rate - total_req_min_rate;
3787
3788         left_rate_per_vp = total_left_rate / non_requested_count;
3789         if (left_rate_per_vp <  min_pf_rate / QED_WFQ_UNIT) {
3790                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3791                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3792                            left_rate_per_vp, min_pf_rate);
3793                 return -EINVAL;
3794         }
3795
3796         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
3797         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
3798
3799         for (i = 0; i < num_vports; i++) {
3800                 if (p_hwfn->qm_info.wfq_data[i].configured)
3801                         continue;
3802
3803                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
3804         }
3805
3806         return 0;
3807 }
3808
3809 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
3810                                      struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
3811 {
3812         struct qed_mcp_link_state *p_link;
3813         int rc = 0;
3814
3815         p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
3816
3817         if (!p_link->min_pf_rate) {
3818                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
3819                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
3820                 return rc;
3821         }
3822
3823         rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
3824
3825         if (!rc)
3826                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
3827                                                  p_link->min_pf_rate);
3828         else
3829                 DP_NOTICE(p_hwfn,
3830                           "Validation failed while configuring min rate\n");
3831
3832         return rc;
3833 }
3834
3835 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
3836                                                  struct qed_ptt *p_ptt,
3837                                                  u32 min_pf_rate)
3838 {
3839         bool use_wfq = false;
3840         int rc = 0;
3841         u16 i;
3842
3843         /* Validate all pre configured vports for wfq */
3844         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3845                 u32 rate;
3846
3847                 if (!p_hwfn->qm_info.wfq_data[i].configured)
3848                         continue;
3849
3850                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
3851                 use_wfq = true;
3852
3853                 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
3854                 if (rc) {
3855                         DP_NOTICE(p_hwfn,
3856                                   "WFQ validation failed while configuring min rate\n");
3857                         break;
3858                 }
3859         }
3860
3861         if (!rc && use_wfq)
3862                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
3863         else
3864                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
3865
3866         return rc;
3867 }
3868
3869 /* Main API for qed clients to configure vport min rate.
3870  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
3871  * rate - Speed in Mbps needs to be assigned to a given vport.
3872  */
3873 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
3874 {
3875         int i, rc = -EINVAL;
3876
3877         /* Currently not supported; Might change in future */
3878         if (cdev->num_hwfns > 1) {
3879                 DP_NOTICE(cdev,
3880                           "WFQ configuration is not supported for this device\n");
3881                 return rc;
3882         }
3883
3884         for_each_hwfn(cdev, i) {
3885                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3886                 struct qed_ptt *p_ptt;
3887
3888                 p_ptt = qed_ptt_acquire(p_hwfn);
3889                 if (!p_ptt)
3890                         return -EBUSY;
3891
3892                 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
3893
3894                 if (rc) {
3895                         qed_ptt_release(p_hwfn, p_ptt);
3896                         return rc;
3897                 }
3898
3899                 qed_ptt_release(p_hwfn, p_ptt);
3900         }
3901
3902         return rc;
3903 }
3904
3905 /* API to configure WFQ from mcp link change */
3906 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
3907                                          struct qed_ptt *p_ptt, u32 min_pf_rate)
3908 {
3909         int i;
3910
3911         if (cdev->num_hwfns > 1) {
3912                 DP_VERBOSE(cdev,
3913                            NETIF_MSG_LINK,
3914                            "WFQ configuration is not supported for this device\n");
3915                 return;
3916         }
3917
3918         for_each_hwfn(cdev, i) {
3919                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3920
3921                 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
3922                                                       min_pf_rate);
3923         }
3924 }
3925
3926 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
3927                                      struct qed_ptt *p_ptt,
3928                                      struct qed_mcp_link_state *p_link,
3929                                      u8 max_bw)
3930 {
3931         int rc = 0;
3932
3933         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
3934
3935         if (!p_link->line_speed && (max_bw != 100))
3936                 return rc;
3937
3938         p_link->speed = (p_link->line_speed * max_bw) / 100;
3939         p_hwfn->qm_info.pf_rl = p_link->speed;
3940
3941         /* Since the limiter also affects Tx-switched traffic, we don't want it
3942          * to limit such traffic in case there's no actual limit.
3943          * In that case, set limit to imaginary high boundary.
3944          */
3945         if (max_bw == 100)
3946                 p_hwfn->qm_info.pf_rl = 100000;
3947
3948         rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
3949                             p_hwfn->qm_info.pf_rl);
3950
3951         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3952                    "Configured MAX bandwidth to be %08x Mb/sec\n",
3953                    p_link->speed);
3954
3955         return rc;
3956 }
3957
3958 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
3959 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
3960 {
3961         int i, rc = -EINVAL;
3962
3963         if (max_bw < 1 || max_bw > 100) {
3964                 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
3965                 return rc;
3966         }
3967
3968         for_each_hwfn(cdev, i) {
3969                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3970                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
3971                 struct qed_mcp_link_state *p_link;
3972                 struct qed_ptt *p_ptt;
3973
3974                 p_link = &p_lead->mcp_info->link_output;
3975
3976                 p_ptt = qed_ptt_acquire(p_hwfn);
3977                 if (!p_ptt)
3978                         return -EBUSY;
3979
3980                 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
3981                                                       p_link, max_bw);
3982
3983                 qed_ptt_release(p_hwfn, p_ptt);
3984
3985                 if (rc)
3986                         break;
3987         }
3988
3989         return rc;
3990 }
3991
3992 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
3993                                      struct qed_ptt *p_ptt,
3994                                      struct qed_mcp_link_state *p_link,
3995                                      u8 min_bw)
3996 {
3997         int rc = 0;
3998
3999         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4000         p_hwfn->qm_info.pf_wfq = min_bw;
4001
4002         if (!p_link->line_speed)
4003                 return rc;
4004
4005         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4006
4007         rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4008
4009         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4010                    "Configured MIN bandwidth to be %d Mb/sec\n",
4011                    p_link->min_pf_rate);
4012
4013         return rc;
4014 }
4015
4016 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4017 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
4018 {
4019         int i, rc = -EINVAL;
4020
4021         if (min_bw < 1 || min_bw > 100) {
4022                 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
4023                 return rc;
4024         }
4025
4026         for_each_hwfn(cdev, i) {
4027                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4028                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4029                 struct qed_mcp_link_state *p_link;
4030                 struct qed_ptt *p_ptt;
4031
4032                 p_link = &p_lead->mcp_info->link_output;
4033
4034                 p_ptt = qed_ptt_acquire(p_hwfn);
4035                 if (!p_ptt)
4036                         return -EBUSY;
4037
4038                 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4039                                                       p_link, min_bw);
4040                 if (rc) {
4041                         qed_ptt_release(p_hwfn, p_ptt);
4042                         return rc;
4043                 }
4044
4045                 if (p_link->min_pf_rate) {
4046                         u32 min_rate = p_link->min_pf_rate;
4047
4048                         rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
4049                                                                    p_ptt,
4050                                                                    min_rate);
4051                 }
4052
4053                 qed_ptt_release(p_hwfn, p_ptt);
4054         }
4055
4056         return rc;
4057 }
4058
4059 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4060 {
4061         struct qed_mcp_link_state *p_link;
4062
4063         p_link = &p_hwfn->mcp_info->link_output;
4064
4065         if (p_link->min_pf_rate)
4066                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4067                                                p_link->min_pf_rate);
4068
4069         memset(p_hwfn->qm_info.wfq_data, 0,
4070                sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
4071 }
4072
4073 int qed_device_num_engines(struct qed_dev *cdev)
4074 {
4075         return QED_IS_BB(cdev) ? 2 : 1;
4076 }
4077
4078 static int qed_device_num_ports(struct qed_dev *cdev)
4079 {
4080         /* in CMT always only one port */
4081         if (cdev->num_hwfns > 1)
4082                 return 1;
4083
4084         return cdev->num_ports_in_engine * qed_device_num_engines(cdev);
4085 }
4086
4087 int qed_device_get_port_id(struct qed_dev *cdev)
4088 {
4089         return (QED_LEADING_HWFN(cdev)->abs_pf_id) % qed_device_num_ports(cdev);
4090 }