drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/firmware.h>
  28 #include <linux/pci-aspm.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <net/ip6_checksum.h>
  32
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38 #define PFX MODULENAME ": "
  39
  40 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  41 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  42 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  43 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  44 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  45 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  46 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  47 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  48 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  49 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  50 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  51 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  52 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  53 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  54 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  55 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  56 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  57 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  58 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  59
  60 #ifdef RTL8169_DEBUG
  61 #define assert(expr) \
  62         if (!(expr)) {                                  \
  63                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  64                 #expr,__FILE__,__func__,__LINE__);              \
  65         }
  66 #define dprintk(fmt, args...) \
  67         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  68 #else
  69 #define assert(expr) do {} while (0)
  70 #define dprintk(fmt, args...)   do {} while (0)
  71 #endif /* RTL8169_DEBUG */
  72
  73 #define R8169_MSG_DEFAULT \
  74         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  75
  76 #define TX_SLOTS_AVAIL(tp) \
  77         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  78
  79 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  80 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  81         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  82
  83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  84    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  85 static const int multicast_filter_limit = 32;
  86
  87 #define MAX_READ_REQUEST_SHIFT  12
  88 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  89 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  90
  91 #define R8169_REGS_SIZE         256
  92 #define R8169_NAPI_WEIGHT       64
  93 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  94 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  95 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  96 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  97
  98 #define RTL8169_TX_TIMEOUT      (6*HZ)
  99 #define RTL8169_PHY_TIMEOUT     (10*HZ)
 100
 101 /* write/read MMIO register */
 102 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
 103 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
 104 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 105 #define RTL_R8(reg)             readb (ioaddr + (reg))
 106 #define RTL_R16(reg)            readw (ioaddr + (reg))
 107 #define RTL_R32(reg)            readl (ioaddr + (reg))
 108
 109 enum mac_version {
 110         RTL_GIGA_MAC_VER_01 = 0,
 111         RTL_GIGA_MAC_VER_02,
 112         RTL_GIGA_MAC_VER_03,
 113         RTL_GIGA_MAC_VER_04,
 114         RTL_GIGA_MAC_VER_05,
 115         RTL_GIGA_MAC_VER_06,
 116         RTL_GIGA_MAC_VER_07,
 117         RTL_GIGA_MAC_VER_08,
 118         RTL_GIGA_MAC_VER_09,
 119         RTL_GIGA_MAC_VER_10,
 120         RTL_GIGA_MAC_VER_11,
 121         RTL_GIGA_MAC_VER_12,
 122         RTL_GIGA_MAC_VER_13,
 123         RTL_GIGA_MAC_VER_14,
 124         RTL_GIGA_MAC_VER_15,
 125         RTL_GIGA_MAC_VER_16,
 126         RTL_GIGA_MAC_VER_17,
 127         RTL_GIGA_MAC_VER_18,
 128         RTL_GIGA_MAC_VER_19,
 129         RTL_GIGA_MAC_VER_20,
 130         RTL_GIGA_MAC_VER_21,
 131         RTL_GIGA_MAC_VER_22,
 132         RTL_GIGA_MAC_VER_23,
 133         RTL_GIGA_MAC_VER_24,
 134         RTL_GIGA_MAC_VER_25,
 135         RTL_GIGA_MAC_VER_26,
 136         RTL_GIGA_MAC_VER_27,
 137         RTL_GIGA_MAC_VER_28,
 138         RTL_GIGA_MAC_VER_29,
 139         RTL_GIGA_MAC_VER_30,
 140         RTL_GIGA_MAC_VER_31,
 141         RTL_GIGA_MAC_VER_32,
 142         RTL_GIGA_MAC_VER_33,
 143         RTL_GIGA_MAC_VER_34,
 144         RTL_GIGA_MAC_VER_35,
 145         RTL_GIGA_MAC_VER_36,
 146         RTL_GIGA_MAC_VER_37,
 147         RTL_GIGA_MAC_VER_38,
 148         RTL_GIGA_MAC_VER_39,
 149         RTL_GIGA_MAC_VER_40,
 150         RTL_GIGA_MAC_VER_41,
 151         RTL_GIGA_MAC_VER_42,
 152         RTL_GIGA_MAC_VER_43,
 153         RTL_GIGA_MAC_VER_44,
 154         RTL_GIGA_MAC_VER_45,
 155         RTL_GIGA_MAC_VER_46,
 156         RTL_GIGA_MAC_VER_47,
 157         RTL_GIGA_MAC_VER_48,
 158         RTL_GIGA_MAC_VER_49,
 159         RTL_GIGA_MAC_VER_50,
 160         RTL_GIGA_MAC_VER_51,
 161         RTL_GIGA_MAC_NONE   = 0xff,
 162 };
 163
 164 enum rtl_tx_desc_version {
 165         RTL_TD_0        = 0,
 166         RTL_TD_1        = 1,
 167 };
 168
 169 #define JUMBO_1K        ETH_DATA_LEN
 170 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 171 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 172 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 173 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 174
 175 #define _R(NAME,TD,FW,SZ,B) {   \
 176         .name = NAME,           \
 177         .txd_version = TD,      \
 178         .fw_name = FW,          \
 179         .jumbo_max = SZ,        \
 180         .jumbo_tx_csum = B      \
 181 }
 182
 183 static const struct {
 184         const char *name;
 185         enum rtl_tx_desc_version txd_version;
 186         const char *fw_name;
 187         u16 jumbo_max;
 188         bool jumbo_tx_csum;
 189 } rtl_chip_infos[] = {
 190         /* PCI devices. */
 191         [RTL_GIGA_MAC_VER_01] =
 192                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 193         [RTL_GIGA_MAC_VER_02] =
 194                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 195         [RTL_GIGA_MAC_VER_03] =
 196                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 197         [RTL_GIGA_MAC_VER_04] =
 198                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 199         [RTL_GIGA_MAC_VER_05] =
 200                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 201         [RTL_GIGA_MAC_VER_06] =
 202                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 203         /* PCI-E devices. */
 204         [RTL_GIGA_MAC_VER_07] =
 205                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 206         [RTL_GIGA_MAC_VER_08] =
 207                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 208         [RTL_GIGA_MAC_VER_09] =
 209                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 210         [RTL_GIGA_MAC_VER_10] =
 211                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 212         [RTL_GIGA_MAC_VER_11] =
 213                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 214         [RTL_GIGA_MAC_VER_12] =
 215                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 216         [RTL_GIGA_MAC_VER_13] =
 217                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 218         [RTL_GIGA_MAC_VER_14] =
 219                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 220         [RTL_GIGA_MAC_VER_15] =
 221                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 222         [RTL_GIGA_MAC_VER_16] =
 223                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 224         [RTL_GIGA_MAC_VER_17] =
 225                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 226         [RTL_GIGA_MAC_VER_18] =
 227                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 228         [RTL_GIGA_MAC_VER_19] =
 229                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 230         [RTL_GIGA_MAC_VER_20] =
 231                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 232         [RTL_GIGA_MAC_VER_21] =
 233                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 234         [RTL_GIGA_MAC_VER_22] =
 235                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 236         [RTL_GIGA_MAC_VER_23] =
 237                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 238         [RTL_GIGA_MAC_VER_24] =
 239                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 240         [RTL_GIGA_MAC_VER_25] =
 241                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 242                                                         JUMBO_9K, false),
 243         [RTL_GIGA_MAC_VER_26] =
 244                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 245                                                         JUMBO_9K, false),
 246         [RTL_GIGA_MAC_VER_27] =
 247                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 248         [RTL_GIGA_MAC_VER_28] =
 249                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 250         [RTL_GIGA_MAC_VER_29] =
 251                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 252                                                         JUMBO_1K, true),
 253         [RTL_GIGA_MAC_VER_30] =
 254                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 255                                                         JUMBO_1K, true),
 256         [RTL_GIGA_MAC_VER_31] =
 257                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 258         [RTL_GIGA_MAC_VER_32] =
 259                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 260                                                         JUMBO_9K, false),
 261         [RTL_GIGA_MAC_VER_33] =
 262                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 263                                                         JUMBO_9K, false),
 264         [RTL_GIGA_MAC_VER_34] =
 265                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 266                                                         JUMBO_9K, false),
 267         [RTL_GIGA_MAC_VER_35] =
 268                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 269                                                         JUMBO_9K, false),
 270         [RTL_GIGA_MAC_VER_36] =
 271                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 272                                                         JUMBO_9K, false),
 273         [RTL_GIGA_MAC_VER_37] =
 274                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,
 275                                                         JUMBO_1K, true),
 276         [RTL_GIGA_MAC_VER_38] =
 277                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,
 278                                                         JUMBO_9K, false),
 279         [RTL_GIGA_MAC_VER_39] =
 280                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1,
 281                                                         JUMBO_1K, true),
 282         [RTL_GIGA_MAC_VER_40] =
 283                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_2,
 284                                                         JUMBO_9K, false),
 285         [RTL_GIGA_MAC_VER_41] =
 286                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K, false),
 287         [RTL_GIGA_MAC_VER_42] =
 288                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_3,
 289                                                         JUMBO_9K, false),
 290         [RTL_GIGA_MAC_VER_43] =
 291                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_2,
 292                                                         JUMBO_1K, true),
 293         [RTL_GIGA_MAC_VER_44] =
 294                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_2,
 295                                                         JUMBO_9K, false),
 296         [RTL_GIGA_MAC_VER_45] =
 297                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_1,
 298                                                         JUMBO_9K, false),
 299         [RTL_GIGA_MAC_VER_46] =
 300                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_2,
 301                                                         JUMBO_9K, false),
 302         [RTL_GIGA_MAC_VER_47] =
 303                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_1,
 304                                                         JUMBO_1K, false),
 305         [RTL_GIGA_MAC_VER_48] =
 306                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_2,
 307                                                         JUMBO_1K, false),
 308         [RTL_GIGA_MAC_VER_49] =
 309                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 310                                                         JUMBO_9K, false),
 311         [RTL_GIGA_MAC_VER_50] =
 312                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 313                                                         JUMBO_9K, false),
 314         [RTL_GIGA_MAC_VER_51] =
 315                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 316                                                         JUMBO_9K, false),
 317 };
 318 #undef _R
 319
 320 enum cfg_version {
 321         RTL_CFG_0 = 0x00,
 322         RTL_CFG_1,
 323         RTL_CFG_2
 324 };
 325
 326 static const struct pci_device_id rtl8169_pci_tbl[] = {
 327         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 328         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 329         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8161), 0, 0, RTL_CFG_1 },
 330         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 331         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 332         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 333         { PCI_VENDOR_ID_DLINK,                  0x4300,
 334                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
 335         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 336         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 337         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 338         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 339         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 340                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 341         { 0x0001,                               0x8168,
 342                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 343         {0,},
 344 };
 345
 346 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 347
 348 static int rx_buf_sz = 16383;
 349 static int use_dac = -1;
 350 static struct {
 351         u32 msg_enable;
 352 } debug = { -1 };
 353
 354 enum rtl_registers {
 355         MAC0            = 0,    /* Ethernet hardware address. */
 356         MAC4            = 4,
 357         MAR0            = 8,    /* Multicast filter. */
 358         CounterAddrLow          = 0x10,
 359         CounterAddrHigh         = 0x14,
 360         TxDescStartAddrLow      = 0x20,
 361         TxDescStartAddrHigh     = 0x24,
 362         TxHDescStartAddrLow     = 0x28,
 363         TxHDescStartAddrHigh    = 0x2c,
 364         FLASH           = 0x30,
 365         ERSR            = 0x36,
 366         ChipCmd         = 0x37,
 367         TxPoll          = 0x38,
 368         IntrMask        = 0x3c,
 369         IntrStatus      = 0x3e,
 370
 371         TxConfig        = 0x40,
 372 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 373 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 374
 375         RxConfig        = 0x44,
 376 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 377 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 378 #define RXCFG_FIFO_SHIFT                13
 379                                         /* No threshold before first PCI xfer */
 380 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 381 #define RX_EARLY_OFF                    (1 << 11)
 382 #define RXCFG_DMA_SHIFT                 8
 383                                         /* Unlimited maximum PCI burst. */
 384 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 385
 386         RxMissed        = 0x4c,
 387         Cfg9346         = 0x50,
 388         Config0         = 0x51,
 389         Config1         = 0x52,
 390         Config2         = 0x53,
 391 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 392
 393         Config3         = 0x54,
 394         Config4         = 0x55,
 395         Config5         = 0x56,
 396         MultiIntr       = 0x5c,
 397         PHYAR           = 0x60,
 398         PHYstatus       = 0x6c,
 399         RxMaxSize       = 0xda,
 400         CPlusCmd        = 0xe0,
 401         IntrMitigate    = 0xe2,
 402         RxDescAddrLow   = 0xe4,
 403         RxDescAddrHigh  = 0xe8,
 404         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 405
 406 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 407
 408         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 409
 410 #define TxPacketMax     (8064 >> 7)
 411 #define EarlySize       0x27
 412
 413         FuncEvent       = 0xf0,
 414         FuncEventMask   = 0xf4,
 415         FuncPresetState = 0xf8,
 416         IBCR0           = 0xf8,
 417         IBCR2           = 0xf9,
 418         IBIMR0          = 0xfa,
 419         IBISR0          = 0xfb,
 420         FuncForceEvent  = 0xfc,
 421 };
 422
 423 enum rtl8110_registers {
 424         TBICSR                  = 0x64,
 425         TBI_ANAR                = 0x68,
 426         TBI_LPAR                = 0x6a,
 427 };
 428
 429 enum rtl8168_8101_registers {
 430         CSIDR                   = 0x64,
 431         CSIAR                   = 0x68,
 432 #define CSIAR_FLAG                      0x80000000
 433 #define CSIAR_WRITE_CMD                 0x80000000
 434 #define CSIAR_BYTE_ENABLE               0x0f
 435 #define CSIAR_BYTE_ENABLE_SHIFT         12
 436 #define CSIAR_ADDR_MASK                 0x0fff
 437 #define CSIAR_FUNC_CARD                 0x00000000
 438 #define CSIAR_FUNC_SDIO                 0x00010000
 439 #define CSIAR_FUNC_NIC                  0x00020000
 440 #define CSIAR_FUNC_NIC2                 0x00010000
 441         PMCH                    = 0x6f,
 442         EPHYAR                  = 0x80,
 443 #define EPHYAR_FLAG                     0x80000000
 444 #define EPHYAR_WRITE_CMD                0x80000000
 445 #define EPHYAR_REG_MASK                 0x1f
 446 #define EPHYAR_REG_SHIFT                16
 447 #define EPHYAR_DATA_MASK                0xffff
 448         DLLPR                   = 0xd0,
 449 #define PFM_EN                          (1 << 6)
 450 #define TX_10M_PS_EN                    (1 << 7)
 451         DBG_REG                 = 0xd1,
 452 #define FIX_NAK_1                       (1 << 4)
 453 #define FIX_NAK_2                       (1 << 3)
 454         TWSI                    = 0xd2,
 455         MCU                     = 0xd3,
 456 #define NOW_IS_OOB                      (1 << 7)
 457 #define TX_EMPTY                        (1 << 5)
 458 #define RX_EMPTY                        (1 << 4)
 459 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 460 #define EN_NDP                          (1 << 3)
 461 #define EN_OOB_RESET                    (1 << 2)
 462 #define LINK_LIST_RDY                   (1 << 1)
 463         EFUSEAR                 = 0xdc,
 464 #define EFUSEAR_FLAG                    0x80000000
 465 #define EFUSEAR_WRITE_CMD               0x80000000
 466 #define EFUSEAR_READ_CMD                0x00000000
 467 #define EFUSEAR_REG_MASK                0x03ff
 468 #define EFUSEAR_REG_SHIFT               8
 469 #define EFUSEAR_DATA_MASK               0xff
 470         MISC_1                  = 0xf2,
 471 #define PFM_D3COLD_EN                   (1 << 6)
 472 };
 473
 474 enum rtl8168_registers {
 475         LED_FREQ                = 0x1a,
 476         EEE_LED                 = 0x1b,
 477         ERIDR                   = 0x70,
 478         ERIAR                   = 0x74,
 479 #define ERIAR_FLAG                      0x80000000
 480 #define ERIAR_WRITE_CMD                 0x80000000
 481 #define ERIAR_READ_CMD                  0x00000000
 482 #define ERIAR_ADDR_BYTE_ALIGN           4
 483 #define ERIAR_TYPE_SHIFT                16
 484 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 485 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 486 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 487 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 488 #define ERIAR_MASK_SHIFT                12
 489 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 490 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 491 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 492 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 493 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 494         EPHY_RXER_NUM           = 0x7c,
 495         OCPDR                   = 0xb0, /* OCP GPHY access */
 496 #define OCPDR_WRITE_CMD                 0x80000000
 497 #define OCPDR_READ_CMD                  0x00000000
 498 #define OCPDR_REG_MASK                  0x7f
 499 #define OCPDR_GPHY_REG_SHIFT            16
 500 #define OCPDR_DATA_MASK                 0xffff
 501         OCPAR                   = 0xb4,
 502 #define OCPAR_FLAG                      0x80000000
 503 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 504 #define OCPAR_GPHY_READ_CMD             0x0000f060
 505         GPHY_OCP                = 0xb8,
 506         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 507         MISC                    = 0xf0, /* 8168e only. */
 508 #define TXPLA_RST                       (1 << 29)
 509 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 510 #define PWM_EN                          (1 << 22)
 511 #define RXDV_GATED_EN                   (1 << 19)
 512 #define EARLY_TALLY_EN                  (1 << 16)
 513 };
 514
 515 enum rtl_register_content {
 516         /* InterruptStatusBits */
 517         SYSErr          = 0x8000,
 518         PCSTimeout      = 0x4000,
 519         SWInt           = 0x0100,
 520         TxDescUnavail   = 0x0080,
 521         RxFIFOOver      = 0x0040,
 522         LinkChg         = 0x0020,
 523         RxOverflow      = 0x0010,
 524         TxErr           = 0x0008,
 525         TxOK            = 0x0004,
 526         RxErr           = 0x0002,
 527         RxOK            = 0x0001,
 528
 529         /* RxStatusDesc */
 530         RxBOVF  = (1 << 24),
 531         RxFOVF  = (1 << 23),
 532         RxRWT   = (1 << 22),
 533         RxRES   = (1 << 21),
 534         RxRUNT  = (1 << 20),
 535         RxCRC   = (1 << 19),
 536
 537         /* ChipCmdBits */
 538         StopReq         = 0x80,
 539         CmdReset        = 0x10,
 540         CmdRxEnb        = 0x08,
 541         CmdTxEnb        = 0x04,
 542         RxBufEmpty      = 0x01,
 543
 544         /* TXPoll register p.5 */
 545         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 546         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 547         FSWInt          = 0x01,         /* Forced software interrupt */
 548
 549         /* Cfg9346Bits */
 550         Cfg9346_Lock    = 0x00,
 551         Cfg9346_Unlock  = 0xc0,
 552
 553         /* rx_mode_bits */
 554         AcceptErr       = 0x20,
 555         AcceptRunt      = 0x10,
 556         AcceptBroadcast = 0x08,
 557         AcceptMulticast = 0x04,
 558         AcceptMyPhys    = 0x02,
 559         AcceptAllPhys   = 0x01,
 560 #define RX_CONFIG_ACCEPT_MASK           0x3f
 561
 562         /* TxConfigBits */
 563         TxInterFrameGapShift = 24,
 564         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 565
 566         /* Config1 register p.24 */
 567         LEDS1           = (1 << 7),
 568         LEDS0           = (1 << 6),
 569         Speed_down      = (1 << 4),
 570         MEMMAP          = (1 << 3),
 571         IOMAP           = (1 << 2),
 572         VPD             = (1 << 1),
 573         PMEnable        = (1 << 0),     /* Power Management Enable */
 574
 575         /* Config2 register p. 25 */
 576         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 577         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 578         PCI_Clock_66MHz = 0x01,
 579         PCI_Clock_33MHz = 0x00,
 580
 581         /* Config3 register p.25 */
 582         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 583         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 584         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 585         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 586         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 587
 588         /* Config4 register */
 589         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 590
 591         /* Config5 register p.27 */
 592         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 593         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 594         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 595         Spi_en          = (1 << 3),
 596         LanWake         = (1 << 1),     /* LanWake enable/disable */
 597         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 598         ASPM_en         = (1 << 0),     /* ASPM enable */
 599
 600         /* TBICSR p.28 */
 601         TBIReset        = 0x80000000,
 602         TBILoopback     = 0x40000000,
 603         TBINwEnable     = 0x20000000,
 604         TBINwRestart    = 0x10000000,
 605         TBILinkOk       = 0x02000000,
 606         TBINwComplete   = 0x01000000,
 607
 608         /* CPlusCmd p.31 */
 609         EnableBist      = (1 << 15),    // 8168 8101
 610         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 611         Normal_mode     = (1 << 13),    // unused
 612         Force_half_dup  = (1 << 12),    // 8168 8101
 613         Force_rxflow_en = (1 << 11),    // 8168 8101
 614         Force_txflow_en = (1 << 10),    // 8168 8101
 615         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 616         ASF             = (1 << 8),     // 8168 8101
 617         PktCntrDisable  = (1 << 7),     // 8168 8101
 618         Mac_dbgo_sel    = 0x001c,       // 8168
 619         RxVlan          = (1 << 6),
 620         RxChkSum        = (1 << 5),
 621         PCIDAC          = (1 << 4),
 622         PCIMulRW        = (1 << 3),
 623         INTT_0          = 0x0000,       // 8168
 624         INTT_1          = 0x0001,       // 8168
 625         INTT_2          = 0x0002,       // 8168
 626         INTT_3          = 0x0003,       // 8168
 627
 628         /* rtl8169_PHYstatus */
 629         TBI_Enable      = 0x80,
 630         TxFlowCtrl      = 0x40,
 631         RxFlowCtrl      = 0x20,
 632         _1000bpsF       = 0x10,
 633         _100bps         = 0x08,
 634         _10bps          = 0x04,
 635         LinkStatus      = 0x02,
 636         FullDup         = 0x01,
 637
 638         /* _TBICSRBit */
 639         TBILinkOK       = 0x02000000,
 640
 641         /* ResetCounterCommand */
 642         CounterReset    = 0x1,
 643
 644         /* DumpCounterCommand */
 645         CounterDump     = 0x8,
 646
 647         /* magic enable v2 */
 648         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 649 };
 650
 651 enum rtl_desc_bit {
 652         /* First doubleword. */
 653         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 654         RingEnd         = (1 << 30), /* End of descriptor ring */
 655         FirstFrag       = (1 << 29), /* First segment of a packet */
 656         LastFrag        = (1 << 28), /* Final segment of a packet */
 657 };
 658
 659 /* Generic case. */
 660 enum rtl_tx_desc_bit {
 661         /* First doubleword. */
 662         TD_LSO          = (1 << 27),            /* Large Send Offload */
 663 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 664
 665         /* Second doubleword. */
 666         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 667 };
 668
 669 /* 8169, 8168b and 810x except 8102e. */
 670 enum rtl_tx_desc_bit_0 {
 671         /* First doubleword. */
 672 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 673         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 674         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 675         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 676 };
 677
 678 /* 8102e, 8168c and beyond. */
 679 enum rtl_tx_desc_bit_1 {
 680         /* First doubleword. */
 681         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 682         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 683 #define GTTCPHO_SHIFT                   18
 684 #define GTTCPHO_MAX                     0x7fU
 685
 686         /* Second doubleword. */
 687 #define TCPHO_SHIFT                     18
 688 #define TCPHO_MAX                       0x3ffU
 689 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 690         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 691         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 692         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 693         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 694 };
 695
 696 enum rtl_rx_desc_bit {
 697         /* Rx private */
 698         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 699         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 700
 701 #define RxProtoUDP      (PID1)
 702 #define RxProtoTCP      (PID0)
 703 #define RxProtoIP       (PID1 | PID0)
 704 #define RxProtoMask     RxProtoIP
 705
 706         IPFail          = (1 << 16), /* IP checksum failed */
 707         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 708         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 709         RxVlanTag       = (1 << 16), /* VLAN tag available */
 710 };
 711
 712 #define RsvdMask        0x3fffc000
 713
 714 struct TxDesc {
 715         __le32 opts1;
 716         __le32 opts2;
 717         __le64 addr;
 718 };
 719
 720 struct RxDesc {
 721         __le32 opts1;
 722         __le32 opts2;
 723         __le64 addr;
 724 };
 725
 726 struct ring_info {
 727         struct sk_buff  *skb;
 728         u32             len;
 729         u8              __pad[sizeof(void *) - sizeof(u32)];
 730 };
 731
 732 enum features {
 733         RTL_FEATURE_WOL         = (1 << 0),
 734         RTL_FEATURE_MSI         = (1 << 1),
 735         RTL_FEATURE_GMII        = (1 << 2),
 736 };
 737
 738 struct rtl8169_counters {
 739         __le64  tx_packets;
 740         __le64  rx_packets;
 741         __le64  tx_errors;
 742         __le32  rx_errors;
 743         __le16  rx_missed;
 744         __le16  align_errors;
 745         __le32  tx_one_collision;
 746         __le32  tx_multi_collision;
 747         __le64  rx_unicast;
 748         __le64  rx_broadcast;
 749         __le32  rx_multicast;
 750         __le16  tx_aborted;
 751         __le16  tx_underun;
 752 };
 753
 754 struct rtl8169_tc_offsets {
 755         bool    inited;
 756         __le64  tx_errors;
 757         __le32  tx_multi_collision;
 758         __le16  tx_aborted;
 759 };
 760
 761 enum rtl_flag {
 762         RTL_FLAG_TASK_ENABLED,
 763         RTL_FLAG_TASK_SLOW_PENDING,
 764         RTL_FLAG_TASK_RESET_PENDING,
 765         RTL_FLAG_TASK_PHY_PENDING,
 766         RTL_FLAG_MAX
 767 };
 768
 769 struct rtl8169_stats {
 770         u64                     packets;
 771         u64                     bytes;
 772         struct u64_stats_sync   syncp;
 773 };
 774
 775 struct rtl8169_private {
 776         void __iomem *mmio_addr;        /* memory map physical address */
 777         struct pci_dev *pci_dev;
 778         struct net_device *dev;
 779         struct napi_struct napi;
 780         u32 msg_enable;
 781         u16 txd_version;
 782         u16 mac_version;
 783         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 784         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 785         u32 dirty_tx;
 786         struct rtl8169_stats rx_stats;
 787         struct rtl8169_stats tx_stats;
 788         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 789         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 790         dma_addr_t TxPhyAddr;
 791         dma_addr_t RxPhyAddr;
 792         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 793         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 794         struct timer_list timer;
 795         u16 cp_cmd;
 796
 797         u16 event_slow;
 798
 799         struct mdio_ops {
 800                 void (*write)(struct rtl8169_private *, int, int);
 801                 int (*read)(struct rtl8169_private *, int);
 802         } mdio_ops;
 803
 804         struct pll_power_ops {
 805                 void (*down)(struct rtl8169_private *);
 806                 void (*up)(struct rtl8169_private *);
 807         } pll_power_ops;
 808
 809         struct jumbo_ops {
 810                 void (*enable)(struct rtl8169_private *);
 811                 void (*disable)(struct rtl8169_private *);
 812         } jumbo_ops;
 813
 814         struct csi_ops {
 815                 void (*write)(struct rtl8169_private *, int, int);
 816                 u32 (*read)(struct rtl8169_private *, int);
 817         } csi_ops;
 818
 819         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 820         int (*get_link_ksettings)(struct net_device *,
 821                                   struct ethtool_link_ksettings *);
 822         void (*phy_reset_enable)(struct rtl8169_private *tp);
 823         void (*hw_start)(struct net_device *);
 824         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 825         unsigned int (*link_ok)(void __iomem *);
 826         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 827         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 828
 829         struct {
 830                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 831                 struct mutex mutex;
 832                 struct work_struct work;
 833         } wk;
 834
 835         unsigned features;
 836
 837         struct mii_if_info mii;
 838         dma_addr_t counters_phys_addr;
 839         struct rtl8169_counters *counters;
 840         struct rtl8169_tc_offsets tc_offset;
 841         u32 saved_wolopts;
 842         u32 opts1_mask;
 843
 844         struct rtl_fw {
 845                 const struct firmware *fw;
 846
 847 #define RTL_VER_SIZE            32
 848
 849                 char version[RTL_VER_SIZE];
 850
 851                 struct rtl_fw_phy_action {
 852                         __le32 *code;
 853                         size_t size;
 854                 } phy_action;
 855         } *rtl_fw;
 856 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 857
 858         u32 ocp_base;
 859 };
 860
 861 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 862 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 863 module_param(use_dac, int, 0);
 864 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 865 module_param_named(debug, debug.msg_enable, int, 0);
 866 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 867 MODULE_LICENSE("GPL");
 868 MODULE_VERSION(RTL8169_VERSION);
 869 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 870 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 871 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 872 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 873 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 874 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 875 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 876 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 877 MODULE_FIRMWARE(FIRMWARE_8402_1);
 878 MODULE_FIRMWARE(FIRMWARE_8411_1);
 879 MODULE_FIRMWARE(FIRMWARE_8411_2);
 880 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 881 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 882 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 883 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 884 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 885 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 886 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 887 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 888
 889 static void rtl_lock_work(struct rtl8169_private *tp)
 890 {
 891         mutex_lock(&tp->wk.mutex);
 892 }
 893
 894 static void rtl_unlock_work(struct rtl8169_private *tp)
 895 {
 896         mutex_unlock(&tp->wk.mutex);
 897 }
 898
 899 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 900 {
 901         pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
 902                                            PCI_EXP_DEVCTL_READRQ, force);
 903 }
 904
 905 struct rtl_cond {
 906         bool (*check)(struct rtl8169_private *);
 907         const char *msg;
 908 };
 909
 910 static void rtl_udelay(unsigned int d)
 911 {
 912         udelay(d);
 913 }
 914
 915 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 916                           void (*delay)(unsigned int), unsigned int d, int n,
 917                           bool high)
 918 {
 919         int i;
 920
 921         for (i = 0; i < n; i++) {
 922                 delay(d);
 923                 if (c->check(tp) == high)
 924                         return true;
 925         }
 926         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 927                   c->msg, !high, n, d);
 928         return false;
 929 }
 930
 931 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 932                                       const struct rtl_cond *c,
 933                                       unsigned int d, int n)
 934 {
 935         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 936 }
 937
 938 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 939                                      const struct rtl_cond *c,
 940                                      unsigned int d, int n)
 941 {
 942         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 943 }
 944
 945 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 946                                       const struct rtl_cond *c,
 947                                       unsigned int d, int n)
 948 {
 949         return rtl_loop_wait(tp, c, msleep, d, n, true);
 950 }
 951
 952 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 953                                      const struct rtl_cond *c,
 954                                      unsigned int d, int n)
 955 {
 956         return rtl_loop_wait(tp, c, msleep, d, n, false);
 957 }
 958
 959 #define DECLARE_RTL_COND(name)                          \
 960 static bool name ## _check(struct rtl8169_private *);   \
 961                                                         \
 962 static const struct rtl_cond name = {                   \
 963         .check  = name ## _check,                       \
 964         .msg    = #name                                 \
 965 };                                                      \
 966                                                         \
 967 static bool name ## _check(struct rtl8169_private *tp)
 968
 969 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 970 {
 971         if (reg & 0xffff0001) {
 972                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 973                 return true;
 974         }
 975         return false;
 976 }
 977
 978 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 979 {
 980         void __iomem *ioaddr = tp->mmio_addr;
 981
 982         return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
 983 }
 984
 985 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 986 {
 987         void __iomem *ioaddr = tp->mmio_addr;
 988
 989         if (rtl_ocp_reg_failure(tp, reg))
 990                 return;
 991
 992         RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 993
 994         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 995 }
 996
 997 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 998 {
 999         void __iomem *ioaddr = tp->mmio_addr;
1000
1001         if (rtl_ocp_reg_failure(tp, reg))
1002                 return 0;
1003
1004         RTL_W32(GPHY_OCP, reg << 15);
1005
1006         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1007                 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1008 }
1009
1010 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1011 {
1012         void __iomem *ioaddr = tp->mmio_addr;
1013
1014         if (rtl_ocp_reg_failure(tp, reg))
1015                 return;
1016
1017         RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1018 }
1019
1020 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1021 {
1022         void __iomem *ioaddr = tp->mmio_addr;
1023
1024         if (rtl_ocp_reg_failure(tp, reg))
1025                 return 0;
1026
1027         RTL_W32(OCPDR, reg << 15);
1028
1029         return RTL_R32(OCPDR);
1030 }
1031
1032 #define OCP_STD_PHY_BASE        0xa400
1033
1034 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1035 {
1036         if (reg == 0x1f) {
1037                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1038                 return;
1039         }
1040
1041         if (tp->ocp_base != OCP_STD_PHY_BASE)
1042                 reg -= 0x10;
1043
1044         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1045 }
1046
1047 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1048 {
1049         if (tp->ocp_base != OCP_STD_PHY_BASE)
1050                 reg -= 0x10;
1051
1052         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1053 }
1054
1055 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1056 {
1057         if (reg == 0x1f) {
1058                 tp->ocp_base = value << 4;
1059                 return;
1060         }
1061
1062         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1063 }
1064
1065 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1066 {
1067         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1068 }
1069
1070 DECLARE_RTL_COND(rtl_phyar_cond)
1071 {
1072         void __iomem *ioaddr = tp->mmio_addr;
1073
1074         return RTL_R32(PHYAR) & 0x80000000;
1075 }
1076
1077 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1078 {
1079         void __iomem *ioaddr = tp->mmio_addr;
1080
1081         RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1082
1083         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1084         /*
1085          * According to hardware specs a 20us delay is required after write
1086          * complete indication, but before sending next command.
1087          */
1088         udelay(20);
1089 }
1090
1091 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1092 {
1093         void __iomem *ioaddr = tp->mmio_addr;
1094         int value;
1095
1096         RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1097
1098         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1099                 RTL_R32(PHYAR) & 0xffff : ~0;
1100
1101         /*
1102          * According to hardware specs a 20us delay is required after read
1103          * complete indication, but before sending next command.
1104          */
1105         udelay(20);
1106
1107         return value;
1108 }
1109
1110 DECLARE_RTL_COND(rtl_ocpar_cond)
1111 {
1112         void __iomem *ioaddr = tp->mmio_addr;
1113
1114         return RTL_R32(OCPAR) & OCPAR_FLAG;
1115 }
1116
1117 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1118 {
1119         void __iomem *ioaddr = tp->mmio_addr;
1120
1121         RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1122         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1123         RTL_W32(EPHY_RXER_NUM, 0);
1124
1125         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1126 }
1127
1128 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1129 {
1130         r8168dp_1_mdio_access(tp, reg,
1131                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1132 }
1133
1134 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1135 {
1136         void __iomem *ioaddr = tp->mmio_addr;
1137
1138         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1139
1140         mdelay(1);
1141         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1142         RTL_W32(EPHY_RXER_NUM, 0);
1143
1144         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1145                 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1146 }
1147
1148 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1149
1150 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1151 {
1152         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1153 }
1154
1155 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1156 {
1157         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1158 }
1159
1160 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1161 {
1162         void __iomem *ioaddr = tp->mmio_addr;
1163
1164         r8168dp_2_mdio_start(ioaddr);
1165
1166         r8169_mdio_write(tp, reg, value);
1167
1168         r8168dp_2_mdio_stop(ioaddr);
1169 }
1170
1171 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1172 {
1173         void __iomem *ioaddr = tp->mmio_addr;
1174         int value;
1175
1176         r8168dp_2_mdio_start(ioaddr);
1177
1178         value = r8169_mdio_read(tp, reg);
1179
1180         r8168dp_2_mdio_stop(ioaddr);
1181
1182         return value;
1183 }
1184
1185 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1186 {
1187         tp->mdio_ops.write(tp, location, val);
1188 }
1189
1190 static int rtl_readphy(struct rtl8169_private *tp, int location)
1191 {
1192         return tp->mdio_ops.read(tp, location);
1193 }
1194
1195 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1196 {
1197         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1198 }
1199
1200 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1201 {
1202         int val;
1203
1204         val = rtl_readphy(tp, reg_addr);
1205         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1206 }
1207
1208 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1209                            int val)
1210 {
1211         struct rtl8169_private *tp = netdev_priv(dev);
1212
1213         rtl_writephy(tp, location, val);
1214 }
1215
1216 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1217 {
1218         struct rtl8169_private *tp = netdev_priv(dev);
1219
1220         return rtl_readphy(tp, location);
1221 }
1222
1223 DECLARE_RTL_COND(rtl_ephyar_cond)
1224 {
1225         void __iomem *ioaddr = tp->mmio_addr;
1226
1227         return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1228 }
1229
1230 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1231 {
1232         void __iomem *ioaddr = tp->mmio_addr;
1233
1234         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1235                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1236
1237         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1238
1239         udelay(10);
1240 }
1241
1242 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1243 {
1244         void __iomem *ioaddr = tp->mmio_addr;
1245
1246         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1247
1248         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1249                 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1250 }
1251
1252 DECLARE_RTL_COND(rtl_eriar_cond)
1253 {
1254         void __iomem *ioaddr = tp->mmio_addr;
1255
1256         return RTL_R32(ERIAR) & ERIAR_FLAG;
1257 }
1258
1259 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1260                           u32 val, int type)
1261 {
1262         void __iomem *ioaddr = tp->mmio_addr;
1263
1264         BUG_ON((addr & 3) || (mask == 0));
1265         RTL_W32(ERIDR, val);
1266         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1267
1268         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1269 }
1270
1271 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1272 {
1273         void __iomem *ioaddr = tp->mmio_addr;
1274
1275         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1276
1277         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1278                 RTL_R32(ERIDR) : ~0;
1279 }
1280
1281 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1282                          u32 m, int type)
1283 {
1284         u32 val;
1285
1286         val = rtl_eri_read(tp, addr, type);
1287         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1288 }
1289
1290 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1291 {
1292         void __iomem *ioaddr = tp->mmio_addr;
1293
1294         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1295         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1296                 RTL_R32(OCPDR) : ~0;
1297 }
1298
1299 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1300 {
1301         return rtl_eri_read(tp, reg, ERIAR_OOB);
1302 }
1303
1304 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1305 {
1306         switch (tp->mac_version) {
1307         case RTL_GIGA_MAC_VER_27:
1308         case RTL_GIGA_MAC_VER_28:
1309         case RTL_GIGA_MAC_VER_31:
1310                 return r8168dp_ocp_read(tp, mask, reg);
1311         case RTL_GIGA_MAC_VER_49:
1312         case RTL_GIGA_MAC_VER_50:
1313         case RTL_GIGA_MAC_VER_51:
1314                 return r8168ep_ocp_read(tp, mask, reg);
1315         default:
1316                 BUG();
1317                 return ~0;
1318         }
1319 }
1320
1321 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1322                               u32 data)
1323 {
1324         void __iomem *ioaddr = tp->mmio_addr;
1325
1326         RTL_W32(OCPDR, data);
1327         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1328         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1329 }
1330
1331 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1332                               u32 data)
1333 {
1334         rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1335                       data, ERIAR_OOB);
1336 }
1337
1338 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1339 {
1340         switch (tp->mac_version) {
1341         case RTL_GIGA_MAC_VER_27:
1342         case RTL_GIGA_MAC_VER_28:
1343         case RTL_GIGA_MAC_VER_31:
1344                 r8168dp_ocp_write(tp, mask, reg, data);
1345                 break;
1346         case RTL_GIGA_MAC_VER_49:
1347         case RTL_GIGA_MAC_VER_50:
1348         case RTL_GIGA_MAC_VER_51:
1349                 r8168ep_ocp_write(tp, mask, reg, data);
1350                 break;
1351         default:
1352                 BUG();
1353                 break;
1354         }
1355 }
1356
1357 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1358 {
1359         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1360
1361         ocp_write(tp, 0x1, 0x30, 0x00000001);
1362 }
1363
1364 #define OOB_CMD_RESET           0x00
1365 #define OOB_CMD_DRIVER_START    0x05
1366 #define OOB_CMD_DRIVER_STOP     0x06
1367
1368 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1369 {
1370         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1371 }
1372
1373 DECLARE_RTL_COND(rtl_ocp_read_cond)
1374 {
1375         u16 reg;
1376
1377         reg = rtl8168_get_ocp_reg(tp);
1378
1379         return ocp_read(tp, 0x0f, reg) & 0x00000800;
1380 }
1381
1382 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1383 {
1384         return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1385 }
1386
1387 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1388 {
1389         void __iomem *ioaddr = tp->mmio_addr;
1390
1391         return RTL_R8(IBISR0) & 0x02;
1392 }
1393
1394 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1395 {
1396         void __iomem *ioaddr = tp->mmio_addr;
1397
1398         RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
1399         rtl_msleep_loop_wait_low(tp, &rtl_ocp_tx_cond, 50, 2000);
1400         RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1401         RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1402 }
1403
1404 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1405 {
1406         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1407         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1408 }
1409
1410 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1411 {
1412         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1413         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1414         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1415 }
1416
1417 static void rtl8168_driver_start(struct rtl8169_private *tp)
1418 {
1419         switch (tp->mac_version) {
1420         case RTL_GIGA_MAC_VER_27:
1421         case RTL_GIGA_MAC_VER_28:
1422         case RTL_GIGA_MAC_VER_31:
1423                 rtl8168dp_driver_start(tp);
1424                 break;
1425         case RTL_GIGA_MAC_VER_49:
1426         case RTL_GIGA_MAC_VER_50:
1427         case RTL_GIGA_MAC_VER_51:
1428                 rtl8168ep_driver_start(tp);
1429                 break;
1430         default:
1431                 BUG();
1432                 break;
1433         }
1434 }
1435
1436 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1437 {
1438         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1439         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1440 }
1441
1442 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1443 {
1444         rtl8168ep_stop_cmac(tp);
1445         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1446         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1447         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1448 }
1449
1450 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1451 {
1452         switch (tp->mac_version) {
1453         case RTL_GIGA_MAC_VER_27:
1454         case RTL_GIGA_MAC_VER_28:
1455         case RTL_GIGA_MAC_VER_31:
1456                 rtl8168dp_driver_stop(tp);
1457                 break;
1458         case RTL_GIGA_MAC_VER_49:
1459         case RTL_GIGA_MAC_VER_50:
1460         case RTL_GIGA_MAC_VER_51:
1461                 rtl8168ep_driver_stop(tp);
1462                 break;
1463         default:
1464                 BUG();
1465                 break;
1466         }
1467 }
1468
1469 static int r8168dp_check_dash(struct rtl8169_private *tp)
1470 {
1471         u16 reg = rtl8168_get_ocp_reg(tp);
1472
1473         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1474 }
1475
1476 static int r8168ep_check_dash(struct rtl8169_private *tp)
1477 {
1478         return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1479 }
1480
1481 static int r8168_check_dash(struct rtl8169_private *tp)
1482 {
1483         switch (tp->mac_version) {
1484         case RTL_GIGA_MAC_VER_27:
1485         case RTL_GIGA_MAC_VER_28:
1486         case RTL_GIGA_MAC_VER_31:
1487                 return r8168dp_check_dash(tp);
1488         case RTL_GIGA_MAC_VER_49:
1489         case RTL_GIGA_MAC_VER_50:
1490         case RTL_GIGA_MAC_VER_51:
1491                 return r8168ep_check_dash(tp);
1492         default:
1493                 return 0;
1494         }
1495 }
1496
1497 struct exgmac_reg {
1498         u16 addr;
1499         u16 mask;
1500         u32 val;
1501 };
1502
1503 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1504                                    const struct exgmac_reg *r, int len)
1505 {
1506         while (len-- > 0) {
1507                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1508                 r++;
1509         }
1510 }
1511
1512 DECLARE_RTL_COND(rtl_efusear_cond)
1513 {
1514         void __iomem *ioaddr = tp->mmio_addr;
1515
1516         return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1517 }
1518
1519 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1520 {
1521         void __iomem *ioaddr = tp->mmio_addr;
1522
1523         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1524
1525         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1526                 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1527 }
1528
1529 static u16 rtl_get_events(struct rtl8169_private *tp)
1530 {
1531         void __iomem *ioaddr = tp->mmio_addr;
1532
1533         return RTL_R16(IntrStatus);
1534 }
1535
1536 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1537 {
1538         void __iomem *ioaddr = tp->mmio_addr;
1539
1540         RTL_W16(IntrStatus, bits);
1541         mmiowb();
1542 }
1543
1544 static void rtl_irq_disable(struct rtl8169_private *tp)
1545 {
1546         void __iomem *ioaddr = tp->mmio_addr;
1547
1548         RTL_W16(IntrMask, 0);
1549         mmiowb();
1550 }
1551
1552 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1553 {
1554         void __iomem *ioaddr = tp->mmio_addr;
1555
1556         RTL_W16(IntrMask, bits);
1557 }
1558
1559 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1560 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1561 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1562
1563 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1564 {
1565         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1566 }
1567
1568 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1569 {
1570         void __iomem *ioaddr = tp->mmio_addr;
1571
1572         rtl_irq_disable(tp);
1573         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1574         RTL_R8(ChipCmd);
1575 }
1576
1577 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1578 {
1579         void __iomem *ioaddr = tp->mmio_addr;
1580
1581         return RTL_R32(TBICSR) & TBIReset;
1582 }
1583
1584 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1585 {
1586         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1587 }
1588
1589 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1590 {
1591         return RTL_R32(TBICSR) & TBILinkOk;
1592 }
1593
1594 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1595 {
1596         return RTL_R8(PHYstatus) & LinkStatus;
1597 }
1598
1599 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1600 {
1601         void __iomem *ioaddr = tp->mmio_addr;
1602
1603         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1604 }
1605
1606 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1607 {
1608         unsigned int val;
1609
1610         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1611         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1612 }
1613
1614 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1615 {
1616         void __iomem *ioaddr = tp->mmio_addr;
1617         struct net_device *dev = tp->dev;
1618
1619         if (!netif_running(dev))
1620                 return;
1621
1622         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1623             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1624                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1625                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1626                                       ERIAR_EXGMAC);
1627                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1628                                       ERIAR_EXGMAC);
1629                 } else if (RTL_R8(PHYstatus) & _100bps) {
1630                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1631                                       ERIAR_EXGMAC);
1632                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1633                                       ERIAR_EXGMAC);
1634                 } else {
1635                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1636                                       ERIAR_EXGMAC);
1637                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1638                                       ERIAR_EXGMAC);
1639                 }
1640                 /* Reset packet filter */
1641                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1642                              ERIAR_EXGMAC);
1643                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1644                              ERIAR_EXGMAC);
1645         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1646                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1647                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1648                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1649                                       ERIAR_EXGMAC);
1650                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1651                                       ERIAR_EXGMAC);
1652                 } else {
1653                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1654                                       ERIAR_EXGMAC);
1655                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1656                                       ERIAR_EXGMAC);
1657                 }
1658         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1659                 if (RTL_R8(PHYstatus) & _10bps) {
1660                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1661                                       ERIAR_EXGMAC);
1662                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1663                                       ERIAR_EXGMAC);
1664                 } else {
1665                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1666                                       ERIAR_EXGMAC);
1667                 }
1668         }
1669 }
1670
1671 static void __rtl8169_check_link_status(struct net_device *dev,
1672                                         struct rtl8169_private *tp,
1673                                         void __iomem *ioaddr, bool pm)
1674 {
1675         if (tp->link_ok(ioaddr)) {
1676                 rtl_link_chg_patch(tp);
1677                 /* This is to cancel a scheduled suspend if there's one. */
1678                 if (pm)
1679                         pm_request_resume(&tp->pci_dev->dev);
1680                 netif_carrier_on(dev);
1681                 if (net_ratelimit())
1682                         netif_info(tp, ifup, dev, "link up\n");
1683         } else {
1684                 netif_carrier_off(dev);
1685                 netif_info(tp, ifdown, dev, "link down\n");
1686                 if (pm)
1687                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1688         }
1689 }
1690
1691 static void rtl8169_check_link_status(struct net_device *dev,
1692                                       struct rtl8169_private *tp,
1693                                       void __iomem *ioaddr)
1694 {
1695         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1696 }
1697
1698 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1699
1700 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1701 {
1702         void __iomem *ioaddr = tp->mmio_addr;
1703         u8 options;
1704         u32 wolopts = 0;
1705
1706         options = RTL_R8(Config1);
1707         if (!(options & PMEnable))
1708                 return 0;
1709
1710         options = RTL_R8(Config3);
1711         if (options & LinkUp)
1712                 wolopts |= WAKE_PHY;
1713         switch (tp->mac_version) {
1714         case RTL_GIGA_MAC_VER_34:
1715         case RTL_GIGA_MAC_VER_35:
1716         case RTL_GIGA_MAC_VER_36:
1717         case RTL_GIGA_MAC_VER_37:
1718         case RTL_GIGA_MAC_VER_38:
1719         case RTL_GIGA_MAC_VER_40:
1720         case RTL_GIGA_MAC_VER_41:
1721         case RTL_GIGA_MAC_VER_42:
1722         case RTL_GIGA_MAC_VER_43:
1723         case RTL_GIGA_MAC_VER_44:
1724         case RTL_GIGA_MAC_VER_45:
1725         case RTL_GIGA_MAC_VER_46:
1726         case RTL_GIGA_MAC_VER_47:
1727         case RTL_GIGA_MAC_VER_48:
1728         case RTL_GIGA_MAC_VER_49:
1729         case RTL_GIGA_MAC_VER_50:
1730         case RTL_GIGA_MAC_VER_51:
1731                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1732                         wolopts |= WAKE_MAGIC;
1733                 break;
1734         default:
1735                 if (options & MagicPacket)
1736                         wolopts |= WAKE_MAGIC;
1737                 break;
1738         }
1739
1740         options = RTL_R8(Config5);
1741         if (options & UWF)
1742                 wolopts |= WAKE_UCAST;
1743         if (options & BWF)
1744                 wolopts |= WAKE_BCAST;
1745         if (options & MWF)
1746                 wolopts |= WAKE_MCAST;
1747
1748         return wolopts;
1749 }
1750
1751 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1752 {
1753         struct rtl8169_private *tp = netdev_priv(dev);
1754         struct device *d = &tp->pci_dev->dev;
1755
1756         pm_runtime_get_noresume(d);
1757
1758         rtl_lock_work(tp);
1759
1760         wol->supported = WAKE_ANY;
1761         if (pm_runtime_active(d))
1762                 wol->wolopts = __rtl8169_get_wol(tp);
1763         else
1764                 wol->wolopts = tp->saved_wolopts;
1765
1766         rtl_unlock_work(tp);
1767
1768         pm_runtime_put_noidle(d);
1769 }
1770
1771 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1772 {
1773         void __iomem *ioaddr = tp->mmio_addr;
1774         unsigned int i, tmp;
1775         static const struct {
1776                 u32 opt;
1777                 u16 reg;
1778                 u8  mask;
1779         } cfg[] = {
1780                 { WAKE_PHY,   Config3, LinkUp },
1781                 { WAKE_UCAST, Config5, UWF },
1782                 { WAKE_BCAST, Config5, BWF },
1783                 { WAKE_MCAST, Config5, MWF },
1784                 { WAKE_ANY,   Config5, LanWake },
1785                 { WAKE_MAGIC, Config3, MagicPacket }
1786         };
1787         u8 options;
1788
1789         RTL_W8(Cfg9346, Cfg9346_Unlock);
1790
1791         switch (tp->mac_version) {
1792         case RTL_GIGA_MAC_VER_34:
1793         case RTL_GIGA_MAC_VER_35:
1794         case RTL_GIGA_MAC_VER_36:
1795         case RTL_GIGA_MAC_VER_37:
1796         case RTL_GIGA_MAC_VER_38:
1797         case RTL_GIGA_MAC_VER_40:
1798         case RTL_GIGA_MAC_VER_41:
1799         case RTL_GIGA_MAC_VER_42:
1800         case RTL_GIGA_MAC_VER_43:
1801         case RTL_GIGA_MAC_VER_44:
1802         case RTL_GIGA_MAC_VER_45:
1803         case RTL_GIGA_MAC_VER_46:
1804         case RTL_GIGA_MAC_VER_47:
1805         case RTL_GIGA_MAC_VER_48:
1806         case RTL_GIGA_MAC_VER_49:
1807         case RTL_GIGA_MAC_VER_50:
1808         case RTL_GIGA_MAC_VER_51:
1809                 tmp = ARRAY_SIZE(cfg) - 1;
1810                 if (wolopts & WAKE_MAGIC)
1811                         rtl_w0w1_eri(tp,
1812                                      0x0dc,
1813                                      ERIAR_MASK_0100,
1814                                      MagicPacket_v2,
1815                                      0x0000,
1816                                      ERIAR_EXGMAC);
1817                 else
1818                         rtl_w0w1_eri(tp,
1819                                      0x0dc,
1820                                      ERIAR_MASK_0100,
1821                                      0x0000,
1822                                      MagicPacket_v2,
1823                                      ERIAR_EXGMAC);
1824                 break;
1825         default:
1826                 tmp = ARRAY_SIZE(cfg);
1827                 break;
1828         }
1829
1830         for (i = 0; i < tmp; i++) {
1831                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1832                 if (wolopts & cfg[i].opt)
1833                         options |= cfg[i].mask;
1834                 RTL_W8(cfg[i].reg, options);
1835         }
1836
1837         switch (tp->mac_version) {
1838         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1839                 options = RTL_R8(Config1) & ~PMEnable;
1840                 if (wolopts)
1841                         options |= PMEnable;
1842                 RTL_W8(Config1, options);
1843                 break;
1844         default:
1845                 options = RTL_R8(Config2) & ~PME_SIGNAL;
1846                 if (wolopts)
1847                         options |= PME_SIGNAL;
1848                 RTL_W8(Config2, options);
1849                 break;
1850         }
1851
1852         RTL_W8(Cfg9346, Cfg9346_Lock);
1853 }
1854
1855 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1856 {
1857         struct rtl8169_private *tp = netdev_priv(dev);
1858         struct device *d = &tp->pci_dev->dev;
1859
1860         pm_runtime_get_noresume(d);
1861
1862         rtl_lock_work(tp);
1863
1864         if (wol->wolopts)
1865                 tp->features |= RTL_FEATURE_WOL;
1866         else
1867                 tp->features &= ~RTL_FEATURE_WOL;
1868         if (pm_runtime_active(d))
1869                 __rtl8169_set_wol(tp, wol->wolopts);
1870         else
1871                 tp->saved_wolopts = wol->wolopts;
1872
1873         rtl_unlock_work(tp);
1874
1875         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1876
1877         pm_runtime_put_noidle(d);
1878
1879         return 0;
1880 }
1881
1882 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1883 {
1884         return rtl_chip_infos[tp->mac_version].fw_name;
1885 }
1886
1887 static void rtl8169_get_drvinfo(struct net_device *dev,
1888                                 struct ethtool_drvinfo *info)
1889 {
1890         struct rtl8169_private *tp = netdev_priv(dev);
1891         struct rtl_fw *rtl_fw = tp->rtl_fw;
1892
1893         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1894         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1895         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1896         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1897         if (!IS_ERR_OR_NULL(rtl_fw))
1898                 strlcpy(info->fw_version, rtl_fw->version,
1899                         sizeof(info->fw_version));
1900 }
1901
1902 static int rtl8169_get_regs_len(struct net_device *dev)
1903 {
1904         return R8169_REGS_SIZE;
1905 }
1906
1907 static int rtl8169_set_speed_tbi(struct net_device *dev,
1908                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1909 {
1910         struct rtl8169_private *tp = netdev_priv(dev);
1911         void __iomem *ioaddr = tp->mmio_addr;
1912         int ret = 0;
1913         u32 reg;
1914
1915         reg = RTL_R32(TBICSR);
1916         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1917             (duplex == DUPLEX_FULL)) {
1918                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1919         } else if (autoneg == AUTONEG_ENABLE)
1920                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1921         else {
1922                 netif_warn(tp, link, dev,
1923                            "incorrect speed setting refused in TBI mode\n");
1924                 ret = -EOPNOTSUPP;
1925         }
1926
1927         return ret;
1928 }
1929
1930 static int rtl8169_set_speed_xmii(struct net_device *dev,
1931                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1932 {
1933         struct rtl8169_private *tp = netdev_priv(dev);
1934         int giga_ctrl, bmcr;
1935         int rc = -EINVAL;
1936
1937         rtl_writephy(tp, 0x1f, 0x0000);
1938
1939         if (autoneg == AUTONEG_ENABLE) {
1940                 int auto_nego;
1941
1942                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1943                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1944                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1945
1946                 if (adv & ADVERTISED_10baseT_Half)
1947                         auto_nego |= ADVERTISE_10HALF;
1948                 if (adv & ADVERTISED_10baseT_Full)
1949                         auto_nego |= ADVERTISE_10FULL;
1950                 if (adv & ADVERTISED_100baseT_Half)
1951                         auto_nego |= ADVERTISE_100HALF;
1952                 if (adv & ADVERTISED_100baseT_Full)
1953                         auto_nego |= ADVERTISE_100FULL;
1954
1955                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1956
1957                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1958                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1959
1960                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1961                 if (tp->mii.supports_gmii) {
1962                         if (adv & ADVERTISED_1000baseT_Half)
1963                                 giga_ctrl |= ADVERTISE_1000HALF;
1964                         if (adv & ADVERTISED_1000baseT_Full)
1965                                 giga_ctrl |= ADVERTISE_1000FULL;
1966                 } else if (adv & (ADVERTISED_1000baseT_Half |
1967                                   ADVERTISED_1000baseT_Full)) {
1968                         netif_info(tp, link, dev,
1969                                    "PHY does not support 1000Mbps\n");
1970                         goto out;
1971                 }
1972
1973                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1974
1975                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1976                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1977         } else {
1978                 giga_ctrl = 0;
1979
1980                 if (speed == SPEED_10)
1981                         bmcr = 0;
1982                 else if (speed == SPEED_100)
1983                         bmcr = BMCR_SPEED100;
1984                 else
1985                         goto out;
1986
1987                 if (duplex == DUPLEX_FULL)
1988                         bmcr |= BMCR_FULLDPLX;
1989         }
1990
1991         rtl_writephy(tp, MII_BMCR, bmcr);
1992
1993         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1994             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1995                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1996                         rtl_writephy(tp, 0x17, 0x2138);
1997                         rtl_writephy(tp, 0x0e, 0x0260);
1998                 } else {
1999                         rtl_writephy(tp, 0x17, 0x2108);
2000                         rtl_writephy(tp, 0x0e, 0x0000);
2001                 }
2002         }
2003
2004         rc = 0;
2005 out:
2006         return rc;
2007 }
2008
2009 static int rtl8169_set_speed(struct net_device *dev,
2010                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
2011 {
2012         struct rtl8169_private *tp = netdev_priv(dev);
2013         int ret;
2014
2015         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
2016         if (ret < 0)
2017                 goto out;
2018
2019         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
2020             (advertising & ADVERTISED_1000baseT_Full) &&
2021             !pci_is_pcie(tp->pci_dev)) {
2022                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
2023         }
2024 out:
2025         return ret;
2026 }
2027
2028 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2029 {
2030         struct rtl8169_private *tp = netdev_priv(dev);
2031         int ret;
2032
2033         del_timer_sync(&tp->timer);
2034
2035         rtl_lock_work(tp);
2036         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
2037                                 cmd->duplex, cmd->advertising);
2038         rtl_unlock_work(tp);
2039
2040         return ret;
2041 }
2042
2043 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
2044         netdev_features_t features)
2045 {
2046         struct rtl8169_private *tp = netdev_priv(dev);
2047
2048         if (dev->mtu > TD_MSS_MAX)
2049                 features &= ~NETIF_F_ALL_TSO;
2050
2051         if (dev->mtu > JUMBO_1K &&
2052             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
2053                 features &= ~NETIF_F_IP_CSUM;
2054
2055         return features;
2056 }
2057
2058 static void __rtl8169_set_features(struct net_device *dev,
2059                                    netdev_features_t features)
2060 {
2061         struct rtl8169_private *tp = netdev_priv(dev);
2062         void __iomem *ioaddr = tp->mmio_addr;
2063         u32 rx_config;
2064
2065         rx_config = RTL_R32(RxConfig);
2066         if (features & NETIF_F_RXALL)
2067                 rx_config |= (AcceptErr | AcceptRunt);
2068         else
2069                 rx_config &= ~(AcceptErr | AcceptRunt);
2070
2071         RTL_W32(RxConfig, rx_config);
2072
2073         if (features & NETIF_F_RXCSUM)
2074                 tp->cp_cmd |= RxChkSum;
2075         else
2076                 tp->cp_cmd &= ~RxChkSum;
2077
2078         if (features & NETIF_F_HW_VLAN_CTAG_RX)
2079                 tp->cp_cmd |= RxVlan;
2080         else
2081                 tp->cp_cmd &= ~RxVlan;
2082
2083         tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
2084
2085         RTL_W16(CPlusCmd, tp->cp_cmd);
2086         RTL_R16(CPlusCmd);
2087 }
2088
2089 static int rtl8169_set_features(struct net_device *dev,
2090                                 netdev_features_t features)
2091 {
2092         struct rtl8169_private *tp = netdev_priv(dev);
2093
2094         features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2095
2096         rtl_lock_work(tp);
2097         if (features ^ dev->features)
2098                 __rtl8169_set_features(dev, features);
2099         rtl_unlock_work(tp);
2100
2101         return 0;
2102 }
2103
2104
2105 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
2106 {
2107         return (skb_vlan_tag_present(skb)) ?
2108                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
2109 }
2110
2111 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
2112 {
2113         u32 opts2 = le32_to_cpu(desc->opts2);
2114
2115         if (opts2 & RxVlanTag)
2116                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
2117 }
2118
2119 static int rtl8169_get_link_ksettings_tbi(struct net_device *dev,
2120                                           struct ethtool_link_ksettings *cmd)
2121 {
2122         struct rtl8169_private *tp = netdev_priv(dev);
2123         void __iomem *ioaddr = tp->mmio_addr;
2124         u32 status;
2125         u32 supported, advertising;
2126
2127         supported =
2128                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
2129         cmd->base.port = PORT_FIBRE;
2130
2131         status = RTL_R32(TBICSR);
2132         advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
2133         cmd->base.autoneg = !!(status & TBINwEnable);
2134
2135         cmd->base.speed = SPEED_1000;
2136         cmd->base.duplex = DUPLEX_FULL; /* Always set */
2137
2138         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
2139                                                 supported);
2140         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
2141                                                 advertising);
2142
2143         return 0;
2144 }
2145
2146 static int rtl8169_get_link_ksettings_xmii(struct net_device *dev,
2147                                            struct ethtool_link_ksettings *cmd)
2148 {
2149         struct rtl8169_private *tp = netdev_priv(dev);
2150
2151         return mii_ethtool_get_link_ksettings(&tp->mii, cmd);
2152 }
2153
2154 static int rtl8169_get_link_ksettings(struct net_device *dev,
2155                                       struct ethtool_link_ksettings *cmd)
2156 {
2157         struct rtl8169_private *tp = netdev_priv(dev);
2158         int rc;
2159
2160         rtl_lock_work(tp);
2161         rc = tp->get_link_ksettings(dev, cmd);
2162         rtl_unlock_work(tp);
2163
2164         return rc;
2165 }
2166
2167 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2168                              void *p)
2169 {
2170         struct rtl8169_private *tp = netdev_priv(dev);
2171         u32 __iomem *data = tp->mmio_addr;
2172         u32 *dw = p;
2173         int i;
2174
2175         rtl_lock_work(tp);
2176         for (i = 0; i < R8169_REGS_SIZE; i += 4)
2177                 memcpy_fromio(dw++, data++, 4);
2178         rtl_unlock_work(tp);
2179 }
2180
2181 static u32 rtl8169_get_msglevel(struct net_device *dev)
2182 {
2183         struct rtl8169_private *tp = netdev_priv(dev);
2184
2185         return tp->msg_enable;
2186 }
2187
2188 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2189 {
2190         struct rtl8169_private *tp = netdev_priv(dev);
2191
2192         tp->msg_enable = value;
2193 }
2194
2195 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2196         "tx_packets",
2197         "rx_packets",
2198         "tx_errors",
2199         "rx_errors",
2200         "rx_missed",
2201         "align_errors",
2202         "tx_single_collisions",
2203         "tx_multi_collisions",
2204         "unicast",
2205         "broadcast",
2206         "multicast",
2207         "tx_aborted",
2208         "tx_underrun",
2209 };
2210
2211 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
2212 {
2213         switch (sset) {
2214         case ETH_SS_STATS:
2215                 return ARRAY_SIZE(rtl8169_gstrings);
2216         default:
2217                 return -EOPNOTSUPP;
2218         }
2219 }
2220
2221 DECLARE_RTL_COND(rtl_counters_cond)
2222 {
2223         void __iomem *ioaddr = tp->mmio_addr;
2224
2225         return RTL_R32(CounterAddrLow) & (CounterReset | CounterDump);
2226 }
2227
2228 static bool rtl8169_do_counters(struct net_device *dev, u32 counter_cmd)
2229 {
2230         struct rtl8169_private *tp = netdev_priv(dev);
2231         void __iomem *ioaddr = tp->mmio_addr;
2232         dma_addr_t paddr = tp->counters_phys_addr;
2233         u32 cmd;
2234         bool ret;
2235
2236         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
2237         cmd = (u64)paddr & DMA_BIT_MASK(32);
2238         RTL_W32(CounterAddrLow, cmd);
2239         RTL_W32(CounterAddrLow, cmd | counter_cmd);
2240
2241         ret = rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
2242
2243         RTL_W32(CounterAddrLow, 0);
2244         RTL_W32(CounterAddrHigh, 0);
2245
2246         return ret;
2247 }
2248
2249 static bool rtl8169_reset_counters(struct net_device *dev)
2250 {
2251         struct rtl8169_private *tp = netdev_priv(dev);
2252
2253         /*
2254          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2255          * tally counters.
2256          */
2257         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2258                 return true;
2259
2260         return rtl8169_do_counters(dev, CounterReset);
2261 }
2262
2263 static bool rtl8169_update_counters(struct net_device *dev)
2264 {
2265         struct rtl8169_private *tp = netdev_priv(dev);
2266         void __iomem *ioaddr = tp->mmio_addr;
2267
2268         /*
2269          * Some chips are unable to dump tally counters when the receiver
2270          * is disabled.
2271          */
2272         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
2273                 return true;
2274
2275         return rtl8169_do_counters(dev, CounterDump);
2276 }
2277
2278 static bool rtl8169_init_counter_offsets(struct net_device *dev)
2279 {
2280         struct rtl8169_private *tp = netdev_priv(dev);
2281         struct rtl8169_counters *counters = tp->counters;
2282         bool ret = false;
2283
2284         /*
2285          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
2286          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2287          * reset by a power cycle, while the counter values collected by the
2288          * driver are reset at every driver unload/load cycle.
2289          *
2290          * To make sure the HW values returned by @get_stats64 match the SW
2291          * values, we collect the initial values at first open(*) and use them
2292          * as offsets to normalize the values returned by @get_stats64.
2293          *
2294          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2295          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2296          * set at open time by rtl_hw_start.
2297          */
2298
2299         if (tp->tc_offset.inited)
2300                 return true;
2301
2302         /* If both, reset and update fail, propagate to caller. */
2303         if (rtl8169_reset_counters(dev))
2304                 ret = true;
2305
2306         if (rtl8169_update_counters(dev))
2307                 ret = true;
2308
2309         tp->tc_offset.tx_errors = counters->tx_errors;
2310         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
2311         tp->tc_offset.tx_aborted = counters->tx_aborted;
2312         tp->tc_offset.inited = true;
2313
2314         return ret;
2315 }
2316
2317 static void rtl8169_get_ethtool_stats(struct net_device *dev,
2318                                       struct ethtool_stats *stats, u64 *data)
2319 {
2320         struct rtl8169_private *tp = netdev_priv(dev);
2321         struct device *d = &tp->pci_dev->dev;
2322         struct rtl8169_counters *counters = tp->counters;
2323
2324         ASSERT_RTNL();
2325
2326         pm_runtime_get_noresume(d);
2327
2328         if (pm_runtime_active(d))
2329                 rtl8169_update_counters(dev);
2330
2331         pm_runtime_put_noidle(d);
2332
2333         data[0] = le64_to_cpu(counters->tx_packets);
2334         data[1] = le64_to_cpu(counters->rx_packets);
2335         data[2] = le64_to_cpu(counters->tx_errors);
2336         data[3] = le32_to_cpu(counters->rx_errors);
2337         data[4] = le16_to_cpu(counters->rx_missed);
2338         data[5] = le16_to_cpu(counters->align_errors);
2339         data[6] = le32_to_cpu(counters->tx_one_collision);
2340         data[7] = le32_to_cpu(counters->tx_multi_collision);
2341         data[8] = le64_to_cpu(counters->rx_unicast);
2342         data[9] = le64_to_cpu(counters->rx_broadcast);
2343         data[10] = le32_to_cpu(counters->rx_multicast);
2344         data[11] = le16_to_cpu(counters->tx_aborted);
2345         data[12] = le16_to_cpu(counters->tx_underun);
2346 }
2347
2348 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2349 {
2350         switch(stringset) {
2351         case ETH_SS_STATS:
2352                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2353                 break;
2354         }
2355 }
2356
2357 static int rtl8169_nway_reset(struct net_device *dev)
2358 {
2359         struct rtl8169_private *tp = netdev_priv(dev);
2360
2361         return mii_nway_restart(&tp->mii);
2362 }
2363
2364 static const struct ethtool_ops rtl8169_ethtool_ops = {
2365         .get_drvinfo            = rtl8169_get_drvinfo,
2366         .get_regs_len           = rtl8169_get_regs_len,
2367         .get_link               = ethtool_op_get_link,
2368         .set_settings           = rtl8169_set_settings,
2369         .get_msglevel           = rtl8169_get_msglevel,
2370         .set_msglevel           = rtl8169_set_msglevel,
2371         .get_regs               = rtl8169_get_regs,
2372         .get_wol                = rtl8169_get_wol,
2373         .set_wol                = rtl8169_set_wol,
2374         .get_strings            = rtl8169_get_strings,
2375         .get_sset_count         = rtl8169_get_sset_count,
2376         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2377         .get_ts_info            = ethtool_op_get_ts_info,
2378         .nway_reset             = rtl8169_nway_reset,
2379         .get_link_ksettings     = rtl8169_get_link_ksettings,
2380 };
2381
2382 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2383                                     struct net_device *dev, u8 default_version)
2384 {
2385         void __iomem *ioaddr = tp->mmio_addr;
2386         /*
2387          * The driver currently handles the 8168Bf and the 8168Be identically
2388          * but they can be identified more specifically through the test below
2389          * if needed:
2390          *
2391          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2392          *
2393          * Same thing for the 8101Eb and the 8101Ec:
2394          *
2395          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2396          */
2397         static const struct rtl_mac_info {
2398                 u32 mask;
2399                 u32 val;
2400                 int mac_version;
2401         } mac_info[] = {
2402                 /* 8168EP family. */
2403                 { 0x7cf00000, 0x50200000,       RTL_GIGA_MAC_VER_51 },
2404                 { 0x7cf00000, 0x50100000,       RTL_GIGA_MAC_VER_50 },
2405                 { 0x7cf00000, 0x50000000,       RTL_GIGA_MAC_VER_49 },
2406
2407                 /* 8168H family. */
2408                 { 0x7cf00000, 0x54100000,       RTL_GIGA_MAC_VER_46 },
2409                 { 0x7cf00000, 0x54000000,       RTL_GIGA_MAC_VER_45 },
2410
2411                 /* 8168G family. */
2412                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
2413                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2414                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2415                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2416
2417                 /* 8168F family. */
2418                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2419                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2420                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2421
2422                 /* 8168E family. */
2423                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2424                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
2425                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2426                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2427
2428                 /* 8168D family. */
2429                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
2430                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2431                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2432
2433                 /* 8168DP family. */
2434                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2435                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2436                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2437
2438                 /* 8168C family. */
2439                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
2440                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2441                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2442                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2443                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2444                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2445                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2446                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
2447                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2448
2449                 /* 8168B family. */
2450                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2451                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
2452                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2453                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2454
2455                 /* 8101 family. */
2456                 { 0x7cf00000, 0x44900000,       RTL_GIGA_MAC_VER_39 },
2457                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2458                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2459                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
2460                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
2461                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2462                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2463                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
2464                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
2465                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2466                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2467                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2468                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2469                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2470                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2471                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2472                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2473                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2474                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2475                 /* FIXME: where did these entries come from ? -- FR */
2476                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2477                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2478
2479                 /* 8110 family. */
2480                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2481                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2482                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2483                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2484                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2485                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2486
2487                 /* Catch-all */
2488                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2489         };
2490         const struct rtl_mac_info *p = mac_info;
2491         u32 reg;
2492
2493         reg = RTL_R32(TxConfig);
2494         while ((reg & p->mask) != p->val)
2495                 p++;
2496         tp->mac_version = p->mac_version;
2497
2498         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2499                 netif_notice(tp, probe, dev,
2500                              "unknown MAC, using family default\n");
2501                 tp->mac_version = default_version;
2502         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2503                 tp->mac_version = tp->mii.supports_gmii ?
2504                                   RTL_GIGA_MAC_VER_42 :
2505                                   RTL_GIGA_MAC_VER_43;
2506         } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2507                 tp->mac_version = tp->mii.supports_gmii ?
2508                                   RTL_GIGA_MAC_VER_45 :
2509                                   RTL_GIGA_MAC_VER_47;
2510         } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2511                 tp->mac_version = tp->mii.supports_gmii ?
2512                                   RTL_GIGA_MAC_VER_46 :
2513                                   RTL_GIGA_MAC_VER_48;
2514         }
2515 }
2516
2517 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2518 {
2519         dprintk("mac_version = 0x%02x\n", tp->mac_version);
2520 }
2521
2522 struct phy_reg {
2523         u16 reg;
2524         u16 val;
2525 };
2526
2527 static void rtl_writephy_batch(struct rtl8169_private *tp,
2528                                const struct phy_reg *regs, int len)
2529 {
2530         while (len-- > 0) {
2531                 rtl_writephy(tp, regs->reg, regs->val);
2532                 regs++;
2533         }
2534 }
2535
2536 #define PHY_READ                0x00000000
2537 #define PHY_DATA_OR             0x10000000
2538 #define PHY_DATA_AND            0x20000000
2539 #define PHY_BJMPN               0x30000000
2540 #define PHY_MDIO_CHG            0x40000000
2541 #define PHY_CLEAR_READCOUNT     0x70000000
2542 #define PHY_WRITE               0x80000000
2543 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2544 #define PHY_COMP_EQ_SKIPN       0xa0000000
2545 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2546 #define PHY_WRITE_PREVIOUS      0xc0000000
2547 #define PHY_SKIPN               0xd0000000
2548 #define PHY_DELAY_MS            0xe0000000
2549
2550 struct fw_info {
2551         u32     magic;
2552         char    version[RTL_VER_SIZE];
2553         __le32  fw_start;
2554         __le32  fw_len;
2555         u8      chksum;
2556 } __packed;
2557
2558 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2559
2560 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2561 {
2562         const struct firmware *fw = rtl_fw->fw;
2563         struct fw_info *fw_info = (struct fw_info *)fw->data;
2564         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2565         char *version = rtl_fw->version;
2566         bool rc = false;
2567
2568         if (fw->size < FW_OPCODE_SIZE)
2569                 goto out;
2570
2571         if (!fw_info->magic) {
2572                 size_t i, size, start;
2573                 u8 checksum = 0;
2574
2575                 if (fw->size < sizeof(*fw_info))
2576                         goto out;
2577
2578                 for (i = 0; i < fw->size; i++)
2579                         checksum += fw->data[i];
2580                 if (checksum != 0)
2581                         goto out;
2582
2583                 start = le32_to_cpu(fw_info->fw_start);
2584                 if (start > fw->size)
2585                         goto out;
2586
2587                 size = le32_to_cpu(fw_info->fw_len);
2588                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2589                         goto out;
2590
2591                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2592
2593                 pa->code = (__le32 *)(fw->data + start);
2594                 pa->size = size;
2595         } else {
2596                 if (fw->size % FW_OPCODE_SIZE)
2597                         goto out;
2598
2599                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2600
2601                 pa->code = (__le32 *)fw->data;
2602                 pa->size = fw->size / FW_OPCODE_SIZE;
2603         }
2604         version[RTL_VER_SIZE - 1] = 0;
2605
2606         rc = true;
2607 out:
2608         return rc;
2609 }
2610
2611 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2612                            struct rtl_fw_phy_action *pa)
2613 {
2614         bool rc = false;
2615         size_t index;
2616
2617         for (index = 0; index < pa->size; index++) {
2618                 u32 action = le32_to_cpu(pa->code[index]);
2619                 u32 regno = (action & 0x0fff0000) >> 16;
2620
2621                 switch(action & 0xf0000000) {
2622                 case PHY_READ:
2623                 case PHY_DATA_OR:
2624                 case PHY_DATA_AND:
2625                 case PHY_MDIO_CHG:
2626                 case PHY_CLEAR_READCOUNT:
2627                 case PHY_WRITE:
2628                 case PHY_WRITE_PREVIOUS:
2629                 case PHY_DELAY_MS:
2630                         break;
2631
2632                 case PHY_BJMPN:
2633                         if (regno > index) {
2634                                 netif_err(tp, ifup, tp->dev,
2635                                           "Out of range of firmware\n");
2636                                 goto out;
2637                         }
2638                         break;
2639                 case PHY_READCOUNT_EQ_SKIP:
2640                         if (index + 2 >= pa->size) {
2641                                 netif_err(tp, ifup, tp->dev,
2642                                           "Out of range of firmware\n");
2643                                 goto out;
2644                         }
2645                         break;
2646                 case PHY_COMP_EQ_SKIPN:
2647                 case PHY_COMP_NEQ_SKIPN:
2648                 case PHY_SKIPN:
2649                         if (index + 1 + regno >= pa->size) {
2650                                 netif_err(tp, ifup, tp->dev,
2651                                           "Out of range of firmware\n");
2652                                 goto out;
2653                         }
2654                         break;
2655
2656                 default:
2657                         netif_err(tp, ifup, tp->dev,
2658                                   "Invalid action 0x%08x\n", action);
2659                         goto out;
2660                 }
2661         }
2662         rc = true;
2663 out:
2664         return rc;
2665 }
2666
2667 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2668 {
2669         struct net_device *dev = tp->dev;
2670         int rc = -EINVAL;
2671
2672         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2673                 netif_err(tp, ifup, dev, "invalid firmware\n");
2674                 goto out;
2675         }
2676
2677         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2678                 rc = 0;
2679 out:
2680         return rc;
2681 }
2682
2683 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2684 {
2685         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2686         struct mdio_ops org, *ops = &tp->mdio_ops;
2687         u32 predata, count;
2688         size_t index;
2689
2690         predata = count = 0;
2691         org.write = ops->write;
2692         org.read = ops->read;
2693
2694         for (index = 0; index < pa->size; ) {
2695                 u32 action = le32_to_cpu(pa->code[index]);
2696                 u32 data = action & 0x0000ffff;
2697                 u32 regno = (action & 0x0fff0000) >> 16;
2698
2699                 if (!action)
2700                         break;
2701
2702                 switch(action & 0xf0000000) {
2703                 case PHY_READ:
2704                         predata = rtl_readphy(tp, regno);
2705                         count++;
2706                         index++;
2707                         break;
2708                 case PHY_DATA_OR:
2709                         predata |= data;
2710                         index++;
2711                         break;
2712                 case PHY_DATA_AND:
2713                         predata &= data;
2714                         index++;
2715                         break;
2716                 case PHY_BJMPN:
2717                         index -= regno;
2718                         break;
2719                 case PHY_MDIO_CHG:
2720                         if (data == 0) {
2721                                 ops->write = org.write;
2722                                 ops->read = org.read;
2723                         } else if (data == 1) {
2724                                 ops->write = mac_mcu_write;
2725                                 ops->read = mac_mcu_read;
2726                         }
2727
2728                         index++;
2729                         break;
2730                 case PHY_CLEAR_READCOUNT:
2731                         count = 0;
2732                         index++;
2733                         break;
2734                 case PHY_WRITE:
2735                         rtl_writephy(tp, regno, data);
2736                         index++;
2737                         break;
2738                 case PHY_READCOUNT_EQ_SKIP:
2739                         index += (count == data) ? 2 : 1;
2740                         break;
2741                 case PHY_COMP_EQ_SKIPN:
2742                         if (predata == data)
2743                                 index += regno;
2744                         index++;
2745                         break;
2746                 case PHY_COMP_NEQ_SKIPN:
2747                         if (predata != data)
2748                                 index += regno;
2749                         index++;
2750                         break;
2751                 case PHY_WRITE_PREVIOUS:
2752                         rtl_writephy(tp, regno, predata);
2753                         index++;
2754                         break;
2755                 case PHY_SKIPN:
2756                         index += regno + 1;
2757                         break;
2758                 case PHY_DELAY_MS:
2759                         mdelay(data);
2760                         index++;
2761                         break;
2762
2763                 default:
2764                         BUG();
2765                 }
2766         }
2767
2768         ops->write = org.write;
2769         ops->read = org.read;
2770 }
2771
2772 static void rtl_release_firmware(struct rtl8169_private *tp)
2773 {
2774         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2775                 release_firmware(tp->rtl_fw->fw);
2776                 kfree(tp->rtl_fw);
2777         }
2778         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2779 }
2780
2781 static void rtl_apply_firmware(struct rtl8169_private *tp)
2782 {
2783         struct rtl_fw *rtl_fw = tp->rtl_fw;
2784
2785         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2786         if (!IS_ERR_OR_NULL(rtl_fw))
2787                 rtl_phy_write_fw(tp, rtl_fw);
2788 }
2789
2790 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2791 {
2792         if (rtl_readphy(tp, reg) != val)
2793                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2794         else
2795                 rtl_apply_firmware(tp);
2796 }
2797
2798 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2799 {
2800         static const struct phy_reg phy_reg_init[] = {
2801                 { 0x1f, 0x0001 },
2802                 { 0x06, 0x006e },
2803                 { 0x08, 0x0708 },
2804                 { 0x15, 0x4000 },
2805                 { 0x18, 0x65c7 },
2806
2807                 { 0x1f, 0x0001 },
2808                 { 0x03, 0x00a1 },
2809                 { 0x02, 0x0008 },
2810                 { 0x01, 0x0120 },
2811                 { 0x00, 0x1000 },
2812                 { 0x04, 0x0800 },
2813                 { 0x04, 0x0000 },
2814
2815                 { 0x03, 0xff41 },
2816                 { 0x02, 0xdf60 },
2817                 { 0x01, 0x0140 },
2818                 { 0x00, 0x0077 },
2819                 { 0x04, 0x7800 },
2820                 { 0x04, 0x7000 },
2821
2822                 { 0x03, 0x802f },
2823                 { 0x02, 0x4f02 },
2824                 { 0x01, 0x0409 },
2825                 { 0x00, 0xf0f9 },
2826                 { 0x04, 0x9800 },
2827                 { 0x04, 0x9000 },
2828
2829                 { 0x03, 0xdf01 },
2830                 { 0x02, 0xdf20 },
2831                 { 0x01, 0xff95 },
2832                 { 0x00, 0xba00 },
2833                 { 0x04, 0xa800 },
2834                 { 0x04, 0xa000 },
2835
2836                 { 0x03, 0xff41 },
2837                 { 0x02, 0xdf20 },
2838                 { 0x01, 0x0140 },
2839                 { 0x00, 0x00bb },
2840                 { 0x04, 0xb800 },
2841                 { 0x04, 0xb000 },
2842
2843                 { 0x03, 0xdf41 },
2844                 { 0x02, 0xdc60 },
2845                 { 0x01, 0x6340 },
2846                 { 0x00, 0x007d },
2847                 { 0x04, 0xd800 },
2848                 { 0x04, 0xd000 },
2849
2850                 { 0x03, 0xdf01 },
2851                 { 0x02, 0xdf20 },
2852                 { 0x01, 0x100a },
2853                 { 0x00, 0xa0ff },
2854                 { 0x04, 0xf800 },
2855                 { 0x04, 0xf000 },
2856
2857                 { 0x1f, 0x0000 },
2858                 { 0x0b, 0x0000 },
2859                 { 0x00, 0x9200 }
2860         };
2861
2862         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2863 }
2864
2865 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2866 {
2867         static const struct phy_reg phy_reg_init[] = {
2868                 { 0x1f, 0x0002 },
2869                 { 0x01, 0x90d0 },
2870                 { 0x1f, 0x0000 }
2871         };
2872
2873         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2874 }
2875
2876 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2877 {
2878         struct pci_dev *pdev = tp->pci_dev;
2879
2880         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2881             (pdev->subsystem_device != 0xe000))
2882                 return;
2883
2884         rtl_writephy(tp, 0x1f, 0x0001);
2885         rtl_writephy(tp, 0x10, 0xf01b);
2886         rtl_writephy(tp, 0x1f, 0x0000);
2887 }
2888
2889 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2890 {
2891         static const struct phy_reg phy_reg_init[] = {
2892                 { 0x1f, 0x0001 },
2893                 { 0x04, 0x0000 },
2894                 { 0x03, 0x00a1 },
2895                 { 0x02, 0x0008 },
2896                 { 0x01, 0x0120 },
2897                 { 0x00, 0x1000 },
2898                 { 0x04, 0x0800 },
2899                 { 0x04, 0x9000 },
2900                 { 0x03, 0x802f },
2901                 { 0x02, 0x4f02 },
2902                 { 0x01, 0x0409 },
2903                 { 0x00, 0xf099 },
2904                 { 0x04, 0x9800 },
2905                 { 0x04, 0xa000 },
2906                 { 0x03, 0xdf01 },
2907                 { 0x02, 0xdf20 },
2908                 { 0x01, 0xff95 },
2909                 { 0x00, 0xba00 },
2910                 { 0x04, 0xa800 },
2911                 { 0x04, 0xf000 },
2912                 { 0x03, 0xdf01 },
2913                 { 0x02, 0xdf20 },
2914                 { 0x01, 0x101a },
2915                 { 0x00, 0xa0ff },
2916                 { 0x04, 0xf800 },
2917                 { 0x04, 0x0000 },
2918                 { 0x1f, 0x0000 },
2919
2920                 { 0x1f, 0x0001 },
2921                 { 0x10, 0xf41b },
2922                 { 0x14, 0xfb54 },
2923                 { 0x18, 0xf5c7 },
2924                 { 0x1f, 0x0000 },
2925
2926                 { 0x1f, 0x0001 },
2927                 { 0x17, 0x0cc0 },
2928                 { 0x1f, 0x0000 }
2929         };
2930
2931         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2932
2933         rtl8169scd_hw_phy_config_quirk(tp);
2934 }
2935
2936 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2937 {
2938         static const struct phy_reg phy_reg_init[] = {
2939                 { 0x1f, 0x0001 },
2940                 { 0x04, 0x0000 },
2941                 { 0x03, 0x00a1 },
2942                 { 0x02, 0x0008 },
2943                 { 0x01, 0x0120 },
2944                 { 0x00, 0x1000 },
2945                 { 0x04, 0x0800 },
2946                 { 0x04, 0x9000 },
2947                 { 0x03, 0x802f },
2948                 { 0x02, 0x4f02 },
2949                 { 0x01, 0x0409 },
2950                 { 0x00, 0xf099 },
2951                 { 0x04, 0x9800 },
2952                 { 0x04, 0xa000 },
2953                 { 0x03, 0xdf01 },
2954                 { 0x02, 0xdf20 },
2955                 { 0x01, 0xff95 },
2956                 { 0x00, 0xba00 },
2957                 { 0x04, 0xa800 },
2958                 { 0x04, 0xf000 },
2959                 { 0x03, 0xdf01 },
2960                 { 0x02, 0xdf20 },
2961                 { 0x01, 0x101a },
2962                 { 0x00, 0xa0ff },
2963                 { 0x04, 0xf800 },
2964                 { 0x04, 0x0000 },
2965                 { 0x1f, 0x0000 },
2966
2967                 { 0x1f, 0x0001 },
2968                 { 0x0b, 0x8480 },
2969                 { 0x1f, 0x0000 },
2970
2971                 { 0x1f, 0x0001 },
2972                 { 0x18, 0x67c7 },
2973                 { 0x04, 0x2000 },
2974                 { 0x03, 0x002f },
2975                 { 0x02, 0x4360 },
2976                 { 0x01, 0x0109 },
2977                 { 0x00, 0x3022 },
2978                 { 0x04, 0x2800 },
2979                 { 0x1f, 0x0000 },
2980
2981                 { 0x1f, 0x0001 },
2982                 { 0x17, 0x0cc0 },
2983                 { 0x1f, 0x0000 }
2984         };
2985
2986         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2987 }
2988
2989 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2990 {
2991         static const struct phy_reg phy_reg_init[] = {
2992                 { 0x10, 0xf41b },
2993                 { 0x1f, 0x0000 }
2994         };
2995
2996         rtl_writephy(tp, 0x1f, 0x0001);
2997         rtl_patchphy(tp, 0x16, 1 << 0);
2998
2999         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3000 }
3001
3002 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
3003 {
3004         static const struct phy_reg phy_reg_init[] = {
3005                 { 0x1f, 0x0001 },
3006                 { 0x10, 0xf41b },
3007                 { 0x1f, 0x0000 }
3008         };
3009
3010         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3011 }
3012
3013 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
3014 {
3015         static const struct phy_reg phy_reg_init[] = {
3016                 { 0x1f, 0x0000 },
3017                 { 0x1d, 0x0f00 },
3018                 { 0x1f, 0x0002 },
3019                 { 0x0c, 0x1ec8 },
3020                 { 0x1f, 0x0000 }
3021         };
3022
3023         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3024 }
3025
3026 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
3027 {
3028         static const struct phy_reg phy_reg_init[] = {
3029                 { 0x1f, 0x0001 },
3030                 { 0x1d, 0x3d98 },
3031                 { 0x1f, 0x0000 }
3032         };
3033
3034         rtl_writephy(tp, 0x1f, 0x0000);
3035         rtl_patchphy(tp, 0x14, 1 << 5);
3036         rtl_patchphy(tp, 0x0d, 1 << 5);
3037
3038         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3039 }
3040
3041 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
3042 {
3043         static const struct phy_reg phy_reg_init[] = {
3044                 { 0x1f, 0x0001 },
3045                 { 0x12, 0x2300 },
3046                 { 0x1f, 0x0002 },
3047                 { 0x00, 0x88d4 },
3048                 { 0x01, 0x82b1 },
3049                 { 0x03, 0x7002 },
3050                 { 0x08, 0x9e30 },
3051                 { 0x09, 0x01f0 },
3052                 { 0x0a, 0x5500 },
3053                 { 0x0c, 0x00c8 },
3054                 { 0x1f, 0x0003 },
3055                 { 0x12, 0xc096 },
3056                 { 0x16, 0x000a },
3057                 { 0x1f, 0x0000 },
3058                 { 0x1f, 0x0000 },
3059                 { 0x09, 0x2000 },
3060                 { 0x09, 0x0000 }
3061         };
3062
3063         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3064
3065         rtl_patchphy(tp, 0x14, 1 << 5);
3066         rtl_patchphy(tp, 0x0d, 1 << 5);
3067         rtl_writephy(tp, 0x1f, 0x0000);
3068 }
3069
3070 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
3071 {
3072         static const struct phy_reg phy_reg_init[] = {
3073                 { 0x1f, 0x0001 },
3074                 { 0x12, 0x2300 },
3075                 { 0x03, 0x802f },
3076                 { 0x02, 0x4f02 },
3077                 { 0x01, 0x0409 },
3078                 { 0x00, 0xf099 },
3079                 { 0x04, 0x9800 },
3080                 { 0x04, 0x9000 },
3081                 { 0x1d, 0x3d98 },
3082                 { 0x1f, 0x0002 },
3083                 { 0x0c, 0x7eb8 },
3084                 { 0x06, 0x0761 },
3085                 { 0x1f, 0x0003 },
3086                 { 0x16, 0x0f0a },
3087                 { 0x1f, 0x0000 }
3088         };
3089
3090         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3091
3092         rtl_patchphy(tp, 0x16, 1 << 0);
3093         rtl_patchphy(tp, 0x14, 1 << 5);
3094         rtl_patchphy(tp, 0x0d, 1 << 5);
3095         rtl_writephy(tp, 0x1f, 0x0000);
3096 }
3097
3098 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
3099 {
3100         static const struct phy_reg phy_reg_init[] = {
3101                 { 0x1f, 0x0001 },
3102                 { 0x12, 0x2300 },
3103                 { 0x1d, 0x3d98 },
3104                 { 0x1f, 0x0002 },
3105                 { 0x0c, 0x7eb8 },
3106                 { 0x06, 0x5461 },
3107                 { 0x1f, 0x0003 },
3108                 { 0x16, 0x0f0a },
3109                 { 0x1f, 0x0000 }
3110         };
3111
3112         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3113
3114         rtl_patchphy(tp, 0x16, 1 << 0);
3115         rtl_patchphy(tp, 0x14, 1 << 5);
3116         rtl_patchphy(tp, 0x0d, 1 << 5);
3117         rtl_writephy(tp, 0x1f, 0x0000);
3118 }
3119
3120 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
3121 {
3122         rtl8168c_3_hw_phy_config(tp);
3123 }
3124
3125 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
3126 {
3127         static const struct phy_reg phy_reg_init_0[] = {
3128                 /* Channel Estimation */
3129                 { 0x1f, 0x0001 },
3130                 { 0x06, 0x4064 },
3131                 { 0x07, 0x2863 },
3132                 { 0x08, 0x059c },
3133                 { 0x09, 0x26b4 },
3134                 { 0x0a, 0x6a19 },
3135                 { 0x0b, 0xdcc8 },
3136                 { 0x10, 0xf06d },
3137                 { 0x14, 0x7f68 },
3138                 { 0x18, 0x7fd9 },
3139                 { 0x1c, 0xf0ff },
3140                 { 0x1d, 0x3d9c },
3141                 { 0x1f, 0x0003 },
3142                 { 0x12, 0xf49f },
3143                 { 0x13, 0x070b },
3144                 { 0x1a, 0x05ad },
3145                 { 0x14, 0x94c0 },
3146
3147                 /*
3148                  * Tx Error Issue
3149                  * Enhance line driver power
3150                  */
3151                 { 0x1f, 0x0002 },
3152                 { 0x06, 0x5561 },
3153                 { 0x1f, 0x0005 },
3154                 { 0x05, 0x8332 },
3155                 { 0x06, 0x5561 },
3156
3157                 /*
3158                  * Can not link to 1Gbps with bad cable
3159                  * Decrease SNR threshold form 21.07dB to 19.04dB
3160                  */
3161                 { 0x1f, 0x0001 },
3162                 { 0x17, 0x0cc0 },
3163
3164                 { 0x1f, 0x0000 },
3165                 { 0x0d, 0xf880 }
3166         };
3167
3168         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3169
3170         /*
3171          * Rx Error Issue
3172          * Fine Tune Switching regulator parameter
3173          */
3174         rtl_writephy(tp, 0x1f, 0x0002);
3175         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3176         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
3177
3178         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3179                 static const struct phy_reg phy_reg_init[] = {
3180                         { 0x1f, 0x0002 },
3181                         { 0x05, 0x669a },
3182                         { 0x1f, 0x0005 },
3183                         { 0x05, 0x8330 },
3184                         { 0x06, 0x669a },
3185                         { 0x1f, 0x0002 }
3186                 };
3187                 int val;
3188
3189                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3190
3191                 val = rtl_readphy(tp, 0x0d);
3192
3193                 if ((val & 0x00ff) != 0x006c) {
3194                         static const u32 set[] = {
3195                                 0x0065, 0x0066, 0x0067, 0x0068,
3196                                 0x0069, 0x006a, 0x006b, 0x006c
3197                         };
3198                         int i;
3199
3200                         rtl_writephy(tp, 0x1f, 0x0002);
3201
3202                         val &= 0xff00;
3203                         for (i = 0; i < ARRAY_SIZE(set); i++)
3204                                 rtl_writephy(tp, 0x0d, val | set[i]);
3205                 }
3206         } else {
3207                 static const struct phy_reg phy_reg_init[] = {
3208                         { 0x1f, 0x0002 },
3209                         { 0x05, 0x6662 },
3210                         { 0x1f, 0x0005 },
3211                         { 0x05, 0x8330 },
3212                         { 0x06, 0x6662 }
3213                 };
3214
3215                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3216         }
3217
3218         /* RSET couple improve */
3219         rtl_writephy(tp, 0x1f, 0x0002);
3220         rtl_patchphy(tp, 0x0d, 0x0300);
3221         rtl_patchphy(tp, 0x0f, 0x0010);
3222
3223         /* Fine tune PLL performance */
3224         rtl_writephy(tp, 0x1f, 0x0002);
3225         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3226         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3227
3228         rtl_writephy(tp, 0x1f, 0x0005);
3229         rtl_writephy(tp, 0x05, 0x001b);
3230
3231         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3232
3233         rtl_writephy(tp, 0x1f, 0x0000);
3234 }
3235
3236 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3237 {
3238         static const struct phy_reg phy_reg_init_0[] = {
3239                 /* Channel Estimation */
3240                 { 0x1f, 0x0001 },
3241                 { 0x06, 0x4064 },
3242                 { 0x07, 0x2863 },
3243                 { 0x08, 0x059c },
3244                 { 0x09, 0x26b4 },
3245                 { 0x0a, 0x6a19 },
3246                 { 0x0b, 0xdcc8 },
3247                 { 0x10, 0xf06d },
3248                 { 0x14, 0x7f68 },
3249                 { 0x18, 0x7fd9 },
3250                 { 0x1c, 0xf0ff },
3251                 { 0x1d, 0x3d9c },
3252                 { 0x1f, 0x0003 },
3253                 { 0x12, 0xf49f },
3254                 { 0x13, 0x070b },
3255                 { 0x1a, 0x05ad },
3256                 { 0x14, 0x94c0 },
3257
3258                 /*
3259                  * Tx Error Issue
3260                  * Enhance line driver power
3261                  */
3262                 { 0x1f, 0x0002 },
3263                 { 0x06, 0x5561 },
3264                 { 0x1f, 0x0005 },
3265                 { 0x05, 0x8332 },
3266                 { 0x06, 0x5561 },
3267
3268                 /*
3269                  * Can not link to 1Gbps with bad cable
3270                  * Decrease SNR threshold form 21.07dB to 19.04dB
3271                  */
3272                 { 0x1f, 0x0001 },
3273                 { 0x17, 0x0cc0 },
3274
3275                 { 0x1f, 0x0000 },
3276                 { 0x0d, 0xf880 }
3277         };
3278
3279         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3280
3281         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3282                 static const struct phy_reg phy_reg_init[] = {
3283                         { 0x1f, 0x0002 },
3284                         { 0x05, 0x669a },
3285                         { 0x1f, 0x0005 },
3286                         { 0x05, 0x8330 },
3287                         { 0x06, 0x669a },
3288
3289                         { 0x1f, 0x0002 }
3290                 };
3291                 int val;
3292
3293                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3294
3295                 val = rtl_readphy(tp, 0x0d);
3296                 if ((val & 0x00ff) != 0x006c) {
3297                         static const u32 set[] = {
3298                                 0x0065, 0x0066, 0x0067, 0x0068,
3299                                 0x0069, 0x006a, 0x006b, 0x006c
3300                         };
3301                         int i;
3302
3303                         rtl_writephy(tp, 0x1f, 0x0002);
3304
3305                         val &= 0xff00;
3306                         for (i = 0; i < ARRAY_SIZE(set); i++)
3307                                 rtl_writephy(tp, 0x0d, val | set[i]);
3308                 }
3309         } else {
3310                 static const struct phy_reg phy_reg_init[] = {
3311                         { 0x1f, 0x0002 },
3312                         { 0x05, 0x2642 },
3313                         { 0x1f, 0x0005 },
3314                         { 0x05, 0x8330 },
3315                         { 0x06, 0x2642 }
3316                 };
3317
3318                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3319         }
3320
3321         /* Fine tune PLL performance */
3322         rtl_writephy(tp, 0x1f, 0x0002);
3323         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3324         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3325
3326         /* Switching regulator Slew rate */
3327         rtl_writephy(tp, 0x1f, 0x0002);
3328         rtl_patchphy(tp, 0x0f, 0x0017);
3329
3330         rtl_writephy(tp, 0x1f, 0x0005);
3331         rtl_writephy(tp, 0x05, 0x001b);
3332
3333         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3334
3335         rtl_writephy(tp, 0x1f, 0x0000);
3336 }
3337
3338 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3339 {
3340         static const struct phy_reg phy_reg_init[] = {
3341                 { 0x1f, 0x0002 },
3342                 { 0x10, 0x0008 },
3343                 { 0x0d, 0x006c },
3344
3345                 { 0x1f, 0x0000 },
3346                 { 0x0d, 0xf880 },
3347
3348                 { 0x1f, 0x0001 },
3349                 { 0x17, 0x0cc0 },
3350
3351                 { 0x1f, 0x0001 },
3352                 { 0x0b, 0xa4d8 },
3353                 { 0x09, 0x281c },
3354                 { 0x07, 0x2883 },
3355                 { 0x0a, 0x6b35 },
3356                 { 0x1d, 0x3da4 },
3357                 { 0x1c, 0xeffd },
3358                 { 0x14, 0x7f52 },
3359                 { 0x18, 0x7fc6 },
3360                 { 0x08, 0x0601 },
3361                 { 0x06, 0x4063 },
3362                 { 0x10, 0xf074 },
3363                 { 0x1f, 0x0003 },
3364                 { 0x13, 0x0789 },
3365                 { 0x12, 0xf4bd },
3366                 { 0x1a, 0x04fd },
3367                 { 0x14, 0x84b0 },
3368                 { 0x1f, 0x0000 },
3369                 { 0x00, 0x9200 },
3370
3371                 { 0x1f, 0x0005 },
3372                 { 0x01, 0x0340 },
3373                 { 0x1f, 0x0001 },
3374                 { 0x04, 0x4000 },
3375                 { 0x03, 0x1d21 },
3376                 { 0x02, 0x0c32 },
3377                 { 0x01, 0x0200 },
3378                 { 0x00, 0x5554 },
3379                 { 0x04, 0x4800 },
3380                 { 0x04, 0x4000 },
3381                 { 0x04, 0xf000 },
3382                 { 0x03, 0xdf01 },
3383                 { 0x02, 0xdf20 },
3384                 { 0x01, 0x101a },
3385                 { 0x00, 0xa0ff },
3386                 { 0x04, 0xf800 },
3387                 { 0x04, 0xf000 },
3388                 { 0x1f, 0x0000 },
3389
3390                 { 0x1f, 0x0007 },
3391                 { 0x1e, 0x0023 },
3392                 { 0x16, 0x0000 },
3393                 { 0x1f, 0x0000 }
3394         };
3395
3396         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3397 }
3398
3399 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3400 {
3401         static const struct phy_reg phy_reg_init[] = {
3402                 { 0x1f, 0x0001 },
3403                 { 0x17, 0x0cc0 },
3404
3405                 { 0x1f, 0x0007 },
3406                 { 0x1e, 0x002d },
3407                 { 0x18, 0x0040 },
3408                 { 0x1f, 0x0000 }
3409         };
3410
3411         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3412         rtl_patchphy(tp, 0x0d, 1 << 5);
3413 }
3414
3415 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3416 {
3417         static const struct phy_reg phy_reg_init[] = {
3418                 /* Enable Delay cap */
3419                 { 0x1f, 0x0005 },
3420                 { 0x05, 0x8b80 },
3421                 { 0x06, 0xc896 },
3422                 { 0x1f, 0x0000 },
3423
3424                 /* Channel estimation fine tune */
3425                 { 0x1f, 0x0001 },
3426                 { 0x0b, 0x6c20 },
3427                 { 0x07, 0x2872 },
3428                 { 0x1c, 0xefff },
3429                 { 0x1f, 0x0003 },
3430                 { 0x14, 0x6420 },
3431                 { 0x1f, 0x0000 },
3432
3433                 /* Update PFM & 10M TX idle timer */
3434                 { 0x1f, 0x0007 },
3435                 { 0x1e, 0x002f },
3436                 { 0x15, 0x1919 },
3437                 { 0x1f, 0x0000 },
3438
3439                 { 0x1f, 0x0007 },
3440                 { 0x1e, 0x00ac },
3441                 { 0x18, 0x0006 },
3442                 { 0x1f, 0x0000 }
3443         };
3444
3445         rtl_apply_firmware(tp);
3446
3447         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3448
3449         /* DCO enable for 10M IDLE Power */
3450         rtl_writephy(tp, 0x1f, 0x0007);
3451         rtl_writephy(tp, 0x1e, 0x0023);
3452         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3453         rtl_writephy(tp, 0x1f, 0x0000);
3454
3455         /* For impedance matching */
3456         rtl_writephy(tp, 0x1f, 0x0002);
3457         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3458         rtl_writephy(tp, 0x1f, 0x0000);
3459
3460         /* PHY auto speed down */
3461         rtl_writephy(tp, 0x1f, 0x0007);
3462         rtl_writephy(tp, 0x1e, 0x002d);
3463         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3464         rtl_writephy(tp, 0x1f, 0x0000);
3465         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3466
3467         rtl_writephy(tp, 0x1f, 0x0005);
3468         rtl_writephy(tp, 0x05, 0x8b86);
3469         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3470         rtl_writephy(tp, 0x1f, 0x0000);
3471
3472         rtl_writephy(tp, 0x1f, 0x0005);
3473         rtl_writephy(tp, 0x05, 0x8b85);
3474         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3475         rtl_writephy(tp, 0x1f, 0x0007);
3476         rtl_writephy(tp, 0x1e, 0x0020);
3477         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3478         rtl_writephy(tp, 0x1f, 0x0006);
3479         rtl_writephy(tp, 0x00, 0x5a00);
3480         rtl_writephy(tp, 0x1f, 0x0000);
3481         rtl_writephy(tp, 0x0d, 0x0007);
3482         rtl_writephy(tp, 0x0e, 0x003c);
3483         rtl_writephy(tp, 0x0d, 0x4007);
3484         rtl_writephy(tp, 0x0e, 0x0000);
3485         rtl_writephy(tp, 0x0d, 0x0000);
3486 }
3487
3488 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3489 {
3490         const u16 w[] = {
3491                 addr[0] | (addr[1] << 8),
3492                 addr[2] | (addr[3] << 8),
3493                 addr[4] | (addr[5] << 8)
3494         };
3495         const struct exgmac_reg e[] = {
3496                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3497                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3498                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3499                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3500         };
3501
3502         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3503 }
3504
3505 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3506 {
3507         static const struct phy_reg phy_reg_init[] = {
3508                 /* Enable Delay cap */
3509                 { 0x1f, 0x0004 },
3510                 { 0x1f, 0x0007 },
3511                 { 0x1e, 0x00ac },
3512                 { 0x18, 0x0006 },
3513                 { 0x1f, 0x0002 },
3514                 { 0x1f, 0x0000 },
3515                 { 0x1f, 0x0000 },
3516
3517                 /* Channel estimation fine tune */
3518                 { 0x1f, 0x0003 },
3519                 { 0x09, 0xa20f },
3520                 { 0x1f, 0x0000 },
3521                 { 0x1f, 0x0000 },
3522
3523                 /* Green Setting */
3524                 { 0x1f, 0x0005 },
3525                 { 0x05, 0x8b5b },
3526                 { 0x06, 0x9222 },
3527                 { 0x05, 0x8b6d },
3528                 { 0x06, 0x8000 },
3529                 { 0x05, 0x8b76 },
3530                 { 0x06, 0x8000 },
3531                 { 0x1f, 0x0000 }
3532         };
3533
3534         rtl_apply_firmware(tp);
3535
3536         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3537
3538         /* For 4-corner performance improve */
3539         rtl_writephy(tp, 0x1f, 0x0005);
3540         rtl_writephy(tp, 0x05, 0x8b80);
3541         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3542         rtl_writephy(tp, 0x1f, 0x0000);
3543
3544         /* PHY auto speed down */
3545         rtl_writephy(tp, 0x1f, 0x0004);
3546         rtl_writephy(tp, 0x1f, 0x0007);
3547         rtl_writephy(tp, 0x1e, 0x002d);
3548         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3549         rtl_writephy(tp, 0x1f, 0x0002);
3550         rtl_writephy(tp, 0x1f, 0x0000);
3551         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3552
3553         /* improve 10M EEE waveform */
3554         rtl_writephy(tp, 0x1f, 0x0005);
3555         rtl_writephy(tp, 0x05, 0x8b86);
3556         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3557         rtl_writephy(tp, 0x1f, 0x0000);
3558
3559         /* Improve 2-pair detection performance */
3560         rtl_writephy(tp, 0x1f, 0x0005);
3561         rtl_writephy(tp, 0x05, 0x8b85);
3562         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3563         rtl_writephy(tp, 0x1f, 0x0000);
3564
3565         /* EEE setting */
3566         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3567         rtl_writephy(tp, 0x1f, 0x0005);
3568         rtl_writephy(tp, 0x05, 0x8b85);
3569         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3570         rtl_writephy(tp, 0x1f, 0x0004);
3571         rtl_writephy(tp, 0x1f, 0x0007);
3572         rtl_writephy(tp, 0x1e, 0x0020);
3573         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3574         rtl_writephy(tp, 0x1f, 0x0002);
3575         rtl_writephy(tp, 0x1f, 0x0000);
3576         rtl_writephy(tp, 0x0d, 0x0007);
3577         rtl_writephy(tp, 0x0e, 0x003c);
3578         rtl_writephy(tp, 0x0d, 0x4007);
3579         rtl_writephy(tp, 0x0e, 0x0000);
3580         rtl_writephy(tp, 0x0d, 0x0000);
3581
3582         /* Green feature */
3583         rtl_writephy(tp, 0x1f, 0x0003);
3584         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3585         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3586         rtl_writephy(tp, 0x1f, 0x0000);
3587
3588         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3589         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3590 }
3591
3592 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3593 {
3594         /* For 4-corner performance improve */
3595         rtl_writephy(tp, 0x1f, 0x0005);
3596         rtl_writephy(tp, 0x05, 0x8b80);
3597         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3598         rtl_writephy(tp, 0x1f, 0x0000);
3599
3600         /* PHY auto speed down */
3601         rtl_writephy(tp, 0x1f, 0x0007);
3602         rtl_writephy(tp, 0x1e, 0x002d);
3603         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3604         rtl_writephy(tp, 0x1f, 0x0000);
3605         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3606
3607         /* Improve 10M EEE waveform */
3608         rtl_writephy(tp, 0x1f, 0x0005);
3609         rtl_writephy(tp, 0x05, 0x8b86);
3610         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3611         rtl_writephy(tp, 0x1f, 0x0000);
3612 }
3613
3614 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3615 {
3616         static const struct phy_reg phy_reg_init[] = {
3617                 /* Channel estimation fine tune */
3618                 { 0x1f, 0x0003 },
3619                 { 0x09, 0xa20f },
3620                 { 0x1f, 0x0000 },
3621
3622                 /* Modify green table for giga & fnet */
3623                 { 0x1f, 0x0005 },
3624                 { 0x05, 0x8b55 },
3625                 { 0x06, 0x0000 },
3626                 { 0x05, 0x8b5e },
3627                 { 0x06, 0x0000 },
3628                 { 0x05, 0x8b67 },
3629                 { 0x06, 0x0000 },
3630                 { 0x05, 0x8b70 },
3631                 { 0x06, 0x0000 },
3632                 { 0x1f, 0x0000 },
3633                 { 0x1f, 0x0007 },
3634                 { 0x1e, 0x0078 },
3635                 { 0x17, 0x0000 },
3636                 { 0x19, 0x00fb },
3637                 { 0x1f, 0x0000 },
3638
3639                 /* Modify green table for 10M */
3640                 { 0x1f, 0x0005 },
3641                 { 0x05, 0x8b79 },
3642                 { 0x06, 0xaa00 },
3643                 { 0x1f, 0x0000 },
3644
3645                 /* Disable hiimpedance detection (RTCT) */
3646                 { 0x1f, 0x0003 },
3647                 { 0x01, 0x328a },
3648                 { 0x1f, 0x0000 }
3649         };
3650
3651         rtl_apply_firmware(tp);
3652
3653         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3654
3655         rtl8168f_hw_phy_config(tp);
3656
3657         /* Improve 2-pair detection performance */
3658         rtl_writephy(tp, 0x1f, 0x0005);
3659         rtl_writephy(tp, 0x05, 0x8b85);
3660         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3661         rtl_writephy(tp, 0x1f, 0x0000);
3662 }
3663
3664 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3665 {
3666         rtl_apply_firmware(tp);
3667
3668         rtl8168f_hw_phy_config(tp);
3669 }
3670
3671 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3672 {
3673         static const struct phy_reg phy_reg_init[] = {
3674                 /* Channel estimation fine tune */
3675                 { 0x1f, 0x0003 },
3676                 { 0x09, 0xa20f },
3677                 { 0x1f, 0x0000 },
3678
3679                 /* Modify green table for giga & fnet */
3680                 { 0x1f, 0x0005 },
3681                 { 0x05, 0x8b55 },
3682                 { 0x06, 0x0000 },
3683                 { 0x05, 0x8b5e },
3684                 { 0x06, 0x0000 },
3685                 { 0x05, 0x8b67 },
3686                 { 0x06, 0x0000 },
3687                 { 0x05, 0x8b70 },
3688                 { 0x06, 0x0000 },
3689                 { 0x1f, 0x0000 },
3690                 { 0x1f, 0x0007 },
3691                 { 0x1e, 0x0078 },
3692                 { 0x17, 0x0000 },
3693                 { 0x19, 0x00aa },
3694                 { 0x1f, 0x0000 },
3695
3696                 /* Modify green table for 10M */
3697                 { 0x1f, 0x0005 },
3698                 { 0x05, 0x8b79 },
3699                 { 0x06, 0xaa00 },
3700                 { 0x1f, 0x0000 },
3701
3702                 /* Disable hiimpedance detection (RTCT) */
3703                 { 0x1f, 0x0003 },
3704                 { 0x01, 0x328a },
3705                 { 0x1f, 0x0000 }
3706         };
3707
3708
3709         rtl_apply_firmware(tp);
3710
3711         rtl8168f_hw_phy_config(tp);
3712
3713         /* Improve 2-pair detection performance */
3714         rtl_writephy(tp, 0x1f, 0x0005);
3715         rtl_writephy(tp, 0x05, 0x8b85);
3716         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3717         rtl_writephy(tp, 0x1f, 0x0000);
3718
3719         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3720
3721         /* Modify green table for giga */
3722         rtl_writephy(tp, 0x1f, 0x0005);
3723         rtl_writephy(tp, 0x05, 0x8b54);
3724         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3725         rtl_writephy(tp, 0x05, 0x8b5d);
3726         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3727         rtl_writephy(tp, 0x05, 0x8a7c);
3728         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3729         rtl_writephy(tp, 0x05, 0x8a7f);
3730         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3731         rtl_writephy(tp, 0x05, 0x8a82);
3732         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3733         rtl_writephy(tp, 0x05, 0x8a85);
3734         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3735         rtl_writephy(tp, 0x05, 0x8a88);
3736         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3737         rtl_writephy(tp, 0x1f, 0x0000);
3738
3739         /* uc same-seed solution */
3740         rtl_writephy(tp, 0x1f, 0x0005);
3741         rtl_writephy(tp, 0x05, 0x8b85);
3742         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3743         rtl_writephy(tp, 0x1f, 0x0000);
3744
3745         /* eee setting */
3746         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3747         rtl_writephy(tp, 0x1f, 0x0005);
3748         rtl_writephy(tp, 0x05, 0x8b85);
3749         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3750         rtl_writephy(tp, 0x1f, 0x0004);
3751         rtl_writephy(tp, 0x1f, 0x0007);
3752         rtl_writephy(tp, 0x1e, 0x0020);
3753         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3754         rtl_writephy(tp, 0x1f, 0x0000);
3755         rtl_writephy(tp, 0x0d, 0x0007);
3756         rtl_writephy(tp, 0x0e, 0x003c);
3757         rtl_writephy(tp, 0x0d, 0x4007);
3758         rtl_writephy(tp, 0x0e, 0x0000);
3759         rtl_writephy(tp, 0x0d, 0x0000);
3760
3761         /* Green feature */
3762         rtl_writephy(tp, 0x1f, 0x0003);
3763         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3764         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3765         rtl_writephy(tp, 0x1f, 0x0000);
3766 }
3767
3768 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3769 {
3770         rtl_apply_firmware(tp);
3771
3772         rtl_writephy(tp, 0x1f, 0x0a46);
3773         if (rtl_readphy(tp, 0x10) & 0x0100) {
3774                 rtl_writephy(tp, 0x1f, 0x0bcc);
3775                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3776         } else {
3777                 rtl_writephy(tp, 0x1f, 0x0bcc);
3778                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3779         }
3780
3781         rtl_writephy(tp, 0x1f, 0x0a46);
3782         if (rtl_readphy(tp, 0x13) & 0x0100) {
3783                 rtl_writephy(tp, 0x1f, 0x0c41);
3784                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3785         } else {
3786                 rtl_writephy(tp, 0x1f, 0x0c41);
3787                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3788         }
3789
3790         /* Enable PHY auto speed down */
3791         rtl_writephy(tp, 0x1f, 0x0a44);
3792         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3793
3794         rtl_writephy(tp, 0x1f, 0x0bcc);
3795         rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3796         rtl_writephy(tp, 0x1f, 0x0a44);
3797         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3798         rtl_writephy(tp, 0x1f, 0x0a43);
3799         rtl_writephy(tp, 0x13, 0x8084);
3800         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3801         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3802
3803         /* EEE auto-fallback function */
3804         rtl_writephy(tp, 0x1f, 0x0a4b);
3805         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3806
3807         /* Enable UC LPF tune function */
3808         rtl_writephy(tp, 0x1f, 0x0a43);
3809         rtl_writephy(tp, 0x13, 0x8012);
3810         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3811
3812         rtl_writephy(tp, 0x1f, 0x0c42);
3813         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3814
3815         /* Improve SWR Efficiency */
3816         rtl_writephy(tp, 0x1f, 0x0bcd);
3817         rtl_writephy(tp, 0x14, 0x5065);
3818         rtl_writephy(tp, 0x14, 0xd065);
3819         rtl_writephy(tp, 0x1f, 0x0bc8);
3820         rtl_writephy(tp, 0x11, 0x5655);
3821         rtl_writephy(tp, 0x1f, 0x0bcd);
3822         rtl_writephy(tp, 0x14, 0x1065);
3823         rtl_writephy(tp, 0x14, 0x9065);
3824         rtl_writephy(tp, 0x14, 0x1065);
3825
3826         /* Check ALDPS bit, disable it if enabled */
3827         rtl_writephy(tp, 0x1f, 0x0a43);
3828         if (rtl_readphy(tp, 0x10) & 0x0004)
3829                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3830
3831         rtl_writephy(tp, 0x1f, 0x0000);
3832 }
3833
3834 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3835 {
3836         rtl_apply_firmware(tp);
3837 }
3838
3839 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3840 {
3841         u16 dout_tapbin;
3842         u32 data;
3843
3844         rtl_apply_firmware(tp);
3845
3846         /* CHN EST parameters adjust - giga master */
3847         rtl_writephy(tp, 0x1f, 0x0a43);
3848         rtl_writephy(tp, 0x13, 0x809b);
3849         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3850         rtl_writephy(tp, 0x13, 0x80a2);
3851         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3852         rtl_writephy(tp, 0x13, 0x80a4);
3853         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3854         rtl_writephy(tp, 0x13, 0x809c);
3855         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3856         rtl_writephy(tp, 0x1f, 0x0000);
3857
3858         /* CHN EST parameters adjust - giga slave */
3859         rtl_writephy(tp, 0x1f, 0x0a43);
3860         rtl_writephy(tp, 0x13, 0x80ad);
3861         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3862         rtl_writephy(tp, 0x13, 0x80b4);
3863         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3864         rtl_writephy(tp, 0x13, 0x80ac);
3865         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3866         rtl_writephy(tp, 0x1f, 0x0000);
3867
3868         /* CHN EST parameters adjust - fnet */
3869         rtl_writephy(tp, 0x1f, 0x0a43);
3870         rtl_writephy(tp, 0x13, 0x808e);
3871         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3872         rtl_writephy(tp, 0x13, 0x8090);
3873         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3874         rtl_writephy(tp, 0x13, 0x8092);
3875         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3876         rtl_writephy(tp, 0x1f, 0x0000);
3877
3878         /* enable R-tune & PGA-retune function */
3879         dout_tapbin = 0;
3880         rtl_writephy(tp, 0x1f, 0x0a46);
3881         data = rtl_readphy(tp, 0x13);
3882         data &= 3;
3883         data <<= 2;
3884         dout_tapbin |= data;
3885         data = rtl_readphy(tp, 0x12);
3886         data &= 0xc000;
3887         data >>= 14;
3888         dout_tapbin |= data;
3889         dout_tapbin = ~(dout_tapbin^0x08);
3890         dout_tapbin <<= 12;
3891         dout_tapbin &= 0xf000;
3892         rtl_writephy(tp, 0x1f, 0x0a43);
3893         rtl_writephy(tp, 0x13, 0x827a);
3894         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3895         rtl_writephy(tp, 0x13, 0x827b);
3896         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3897         rtl_writephy(tp, 0x13, 0x827c);
3898         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3899         rtl_writephy(tp, 0x13, 0x827d);
3900         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3901
3902         rtl_writephy(tp, 0x1f, 0x0a43);
3903         rtl_writephy(tp, 0x13, 0x0811);
3904         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3905         rtl_writephy(tp, 0x1f, 0x0a42);
3906         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3907         rtl_writephy(tp, 0x1f, 0x0000);
3908
3909         /* enable GPHY 10M */
3910         rtl_writephy(tp, 0x1f, 0x0a44);
3911         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3912         rtl_writephy(tp, 0x1f, 0x0000);
3913
3914         /* SAR ADC performance */
3915         rtl_writephy(tp, 0x1f, 0x0bca);
3916         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3917         rtl_writephy(tp, 0x1f, 0x0000);
3918
3919         rtl_writephy(tp, 0x1f, 0x0a43);
3920         rtl_writephy(tp, 0x13, 0x803f);
3921         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3922         rtl_writephy(tp, 0x13, 0x8047);
3923         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3924         rtl_writephy(tp, 0x13, 0x804f);
3925         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3926         rtl_writephy(tp, 0x13, 0x8057);
3927         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3928         rtl_writephy(tp, 0x13, 0x805f);
3929         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3930         rtl_writephy(tp, 0x13, 0x8067);
3931         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3932         rtl_writephy(tp, 0x13, 0x806f);
3933         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3934         rtl_writephy(tp, 0x1f, 0x0000);
3935
3936         /* disable phy pfm mode */
3937         rtl_writephy(tp, 0x1f, 0x0a44);
3938         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3939         rtl_writephy(tp, 0x1f, 0x0000);
3940
3941         /* Check ALDPS bit, disable it if enabled */
3942         rtl_writephy(tp, 0x1f, 0x0a43);
3943         if (rtl_readphy(tp, 0x10) & 0x0004)
3944                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3945
3946         rtl_writephy(tp, 0x1f, 0x0000);
3947 }
3948
3949 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3950 {
3951         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3952         u16 rlen;
3953         u32 data;
3954
3955         rtl_apply_firmware(tp);
3956
3957         /* CHIN EST parameter update */
3958         rtl_writephy(tp, 0x1f, 0x0a43);
3959         rtl_writephy(tp, 0x13, 0x808a);
3960         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3961         rtl_writephy(tp, 0x1f, 0x0000);
3962
3963         /* enable R-tune & PGA-retune function */
3964         rtl_writephy(tp, 0x1f, 0x0a43);
3965         rtl_writephy(tp, 0x13, 0x0811);
3966         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3967         rtl_writephy(tp, 0x1f, 0x0a42);
3968         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3969         rtl_writephy(tp, 0x1f, 0x0000);
3970
3971         /* enable GPHY 10M */
3972         rtl_writephy(tp, 0x1f, 0x0a44);
3973         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3974         rtl_writephy(tp, 0x1f, 0x0000);
3975
3976         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3977         data = r8168_mac_ocp_read(tp, 0xdd02);
3978         ioffset_p3 = ((data & 0x80)>>7);
3979         ioffset_p3 <<= 3;
3980
3981         data = r8168_mac_ocp_read(tp, 0xdd00);
3982         ioffset_p3 |= ((data & (0xe000))>>13);
3983         ioffset_p2 = ((data & (0x1e00))>>9);
3984         ioffset_p1 = ((data & (0x01e0))>>5);
3985         ioffset_p0 = ((data & 0x0010)>>4);
3986         ioffset_p0 <<= 3;
3987         ioffset_p0 |= (data & (0x07));
3988         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3989
3990         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3991             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3992                 rtl_writephy(tp, 0x1f, 0x0bcf);
3993                 rtl_writephy(tp, 0x16, data);
3994                 rtl_writephy(tp, 0x1f, 0x0000);
3995         }
3996
3997         /* Modify rlen (TX LPF corner frequency) level */
3998         rtl_writephy(tp, 0x1f, 0x0bcd);
3999         data = rtl_readphy(tp, 0x16);
4000         data &= 0x000f;
4001         rlen = 0;
4002         if (data > 3)
4003                 rlen = data - 3;
4004         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
4005         rtl_writephy(tp, 0x17, data);
4006         rtl_writephy(tp, 0x1f, 0x0bcd);
4007         rtl_writephy(tp, 0x1f, 0x0000);
4008
4009         /* disable phy pfm mode */
4010         rtl_writephy(tp, 0x1f, 0x0a44);
4011         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
4012         rtl_writephy(tp, 0x1f, 0x0000);
4013
4014         /* Check ALDPS bit, disable it if enabled */
4015         rtl_writephy(tp, 0x1f, 0x0a43);
4016         if (rtl_readphy(tp, 0x10) & 0x0004)
4017                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4018
4019         rtl_writephy(tp, 0x1f, 0x0000);
4020 }
4021
4022 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
4023 {
4024         /* Enable PHY auto speed down */
4025         rtl_writephy(tp, 0x1f, 0x0a44);
4026         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
4027         rtl_writephy(tp, 0x1f, 0x0000);
4028
4029         /* patch 10M & ALDPS */
4030         rtl_writephy(tp, 0x1f, 0x0bcc);
4031         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4032         rtl_writephy(tp, 0x1f, 0x0a44);
4033         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4034         rtl_writephy(tp, 0x1f, 0x0a43);
4035         rtl_writephy(tp, 0x13, 0x8084);
4036         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4037         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4038         rtl_writephy(tp, 0x1f, 0x0000);
4039
4040         /* Enable EEE auto-fallback function */
4041         rtl_writephy(tp, 0x1f, 0x0a4b);
4042         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4043         rtl_writephy(tp, 0x1f, 0x0000);
4044
4045         /* Enable UC LPF tune function */
4046         rtl_writephy(tp, 0x1f, 0x0a43);
4047         rtl_writephy(tp, 0x13, 0x8012);
4048         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4049         rtl_writephy(tp, 0x1f, 0x0000);
4050
4051         /* set rg_sel_sdm_rate */
4052         rtl_writephy(tp, 0x1f, 0x0c42);
4053         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4054         rtl_writephy(tp, 0x1f, 0x0000);
4055
4056         /* Check ALDPS bit, disable it if enabled */
4057         rtl_writephy(tp, 0x1f, 0x0a43);
4058         if (rtl_readphy(tp, 0x10) & 0x0004)
4059                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4060
4061         rtl_writephy(tp, 0x1f, 0x0000);
4062 }
4063
4064 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
4065 {
4066         /* patch 10M & ALDPS */
4067         rtl_writephy(tp, 0x1f, 0x0bcc);
4068         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4069         rtl_writephy(tp, 0x1f, 0x0a44);
4070         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4071         rtl_writephy(tp, 0x1f, 0x0a43);
4072         rtl_writephy(tp, 0x13, 0x8084);
4073         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4074         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4075         rtl_writephy(tp, 0x1f, 0x0000);
4076
4077         /* Enable UC LPF tune function */
4078         rtl_writephy(tp, 0x1f, 0x0a43);
4079         rtl_writephy(tp, 0x13, 0x8012);
4080         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4081         rtl_writephy(tp, 0x1f, 0x0000);
4082
4083         /* Set rg_sel_sdm_rate */
4084         rtl_writephy(tp, 0x1f, 0x0c42);
4085         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4086         rtl_writephy(tp, 0x1f, 0x0000);
4087
4088         /* Channel estimation parameters */
4089         rtl_writephy(tp, 0x1f, 0x0a43);
4090         rtl_writephy(tp, 0x13, 0x80f3);
4091         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
4092         rtl_writephy(tp, 0x13, 0x80f0);
4093         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
4094         rtl_writephy(tp, 0x13, 0x80ef);
4095         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
4096         rtl_writephy(tp, 0x13, 0x80f6);
4097         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
4098         rtl_writephy(tp, 0x13, 0x80ec);
4099         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
4100         rtl_writephy(tp, 0x13, 0x80ed);
4101         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4102         rtl_writephy(tp, 0x13, 0x80f2);
4103         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
4104         rtl_writephy(tp, 0x13, 0x80f4);
4105         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
4106         rtl_writephy(tp, 0x1f, 0x0a43);
4107         rtl_writephy(tp, 0x13, 0x8110);
4108         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4109         rtl_writephy(tp, 0x13, 0x810f);
4110         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4111         rtl_writephy(tp, 0x13, 0x8111);
4112         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4113         rtl_writephy(tp, 0x13, 0x8113);
4114         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4115         rtl_writephy(tp, 0x13, 0x8115);
4116         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4117         rtl_writephy(tp, 0x13, 0x810e);
4118         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4119         rtl_writephy(tp, 0x13, 0x810c);
4120         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4121         rtl_writephy(tp, 0x13, 0x810b);
4122         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4123         rtl_writephy(tp, 0x1f, 0x0a43);
4124         rtl_writephy(tp, 0x13, 0x80d1);
4125         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4126         rtl_writephy(tp, 0x13, 0x80cd);
4127         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4128         rtl_writephy(tp, 0x13, 0x80d3);
4129         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4130         rtl_writephy(tp, 0x13, 0x80d5);
4131         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4132         rtl_writephy(tp, 0x13, 0x80d7);
4133         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4134
4135         /* Force PWM-mode */
4136         rtl_writephy(tp, 0x1f, 0x0bcd);
4137         rtl_writephy(tp, 0x14, 0x5065);
4138         rtl_writephy(tp, 0x14, 0xd065);
4139         rtl_writephy(tp, 0x1f, 0x0bc8);
4140         rtl_writephy(tp, 0x12, 0x00ed);
4141         rtl_writephy(tp, 0x1f, 0x0bcd);
4142         rtl_writephy(tp, 0x14, 0x1065);
4143         rtl_writephy(tp, 0x14, 0x9065);
4144         rtl_writephy(tp, 0x14, 0x1065);
4145         rtl_writephy(tp, 0x1f, 0x0000);
4146
4147         /* Check ALDPS bit, disable it if enabled */
4148         rtl_writephy(tp, 0x1f, 0x0a43);
4149         if (rtl_readphy(tp, 0x10) & 0x0004)
4150                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4151
4152         rtl_writephy(tp, 0x1f, 0x0000);
4153 }
4154
4155 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
4156 {
4157         static const struct phy_reg phy_reg_init[] = {
4158                 { 0x1f, 0x0003 },
4159                 { 0x08, 0x441d },
4160                 { 0x01, 0x9100 },
4161                 { 0x1f, 0x0000 }
4162         };
4163
4164         rtl_writephy(tp, 0x1f, 0x0000);
4165         rtl_patchphy(tp, 0x11, 1 << 12);
4166         rtl_patchphy(tp, 0x19, 1 << 13);
4167         rtl_patchphy(tp, 0x10, 1 << 15);
4168
4169         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4170 }
4171
4172 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4173 {
4174         static const struct phy_reg phy_reg_init[] = {
4175                 { 0x1f, 0x0005 },
4176                 { 0x1a, 0x0000 },
4177                 { 0x1f, 0x0000 },
4178
4179                 { 0x1f, 0x0004 },
4180                 { 0x1c, 0x0000 },
4181                 { 0x1f, 0x0000 },
4182
4183                 { 0x1f, 0x0001 },
4184                 { 0x15, 0x7701 },
4185                 { 0x1f, 0x0000 }
4186         };
4187
4188         /* Disable ALDPS before ram code */
4189         rtl_writephy(tp, 0x1f, 0x0000);
4190         rtl_writephy(tp, 0x18, 0x0310);
4191         msleep(100);
4192
4193         rtl_apply_firmware(tp);
4194
4195         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4196 }
4197
4198 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4199 {
4200         /* Disable ALDPS before setting firmware */
4201         rtl_writephy(tp, 0x1f, 0x0000);
4202         rtl_writephy(tp, 0x18, 0x0310);
4203         msleep(20);
4204
4205         rtl_apply_firmware(tp);
4206
4207         /* EEE setting */
4208         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4209         rtl_writephy(tp, 0x1f, 0x0004);
4210         rtl_writephy(tp, 0x10, 0x401f);
4211         rtl_writephy(tp, 0x19, 0x7030);
4212         rtl_writephy(tp, 0x1f, 0x0000);
4213 }
4214
4215 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4216 {
4217         static const struct phy_reg phy_reg_init[] = {
4218                 { 0x1f, 0x0004 },
4219                 { 0x10, 0xc07f },
4220                 { 0x19, 0x7030 },
4221                 { 0x1f, 0x0000 }
4222         };
4223
4224         /* Disable ALDPS before ram code */
4225         rtl_writephy(tp, 0x1f, 0x0000);
4226         rtl_writephy(tp, 0x18, 0x0310);
4227         msleep(100);
4228
4229         rtl_apply_firmware(tp);
4230
4231         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4232         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4233
4234         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4235 }
4236
4237 static void rtl_hw_phy_config(struct net_device *dev)
4238 {
4239         struct rtl8169_private *tp = netdev_priv(dev);
4240
4241         rtl8169_print_mac_version(tp);
4242
4243         switch (tp->mac_version) {
4244         case RTL_GIGA_MAC_VER_01:
4245                 break;
4246         case RTL_GIGA_MAC_VER_02:
4247         case RTL_GIGA_MAC_VER_03:
4248                 rtl8169s_hw_phy_config(tp);
4249                 break;
4250         case RTL_GIGA_MAC_VER_04:
4251                 rtl8169sb_hw_phy_config(tp);
4252                 break;
4253         case RTL_GIGA_MAC_VER_05:
4254                 rtl8169scd_hw_phy_config(tp);
4255                 break;
4256         case RTL_GIGA_MAC_VER_06:
4257                 rtl8169sce_hw_phy_config(tp);
4258                 break;
4259         case RTL_GIGA_MAC_VER_07:
4260         case RTL_GIGA_MAC_VER_08:
4261         case RTL_GIGA_MAC_VER_09:
4262                 rtl8102e_hw_phy_config(tp);
4263                 break;
4264         case RTL_GIGA_MAC_VER_11:
4265                 rtl8168bb_hw_phy_config(tp);
4266                 break;
4267         case RTL_GIGA_MAC_VER_12:
4268                 rtl8168bef_hw_phy_config(tp);
4269                 break;
4270         case RTL_GIGA_MAC_VER_17:
4271                 rtl8168bef_hw_phy_config(tp);
4272                 break;
4273         case RTL_GIGA_MAC_VER_18:
4274                 rtl8168cp_1_hw_phy_config(tp);
4275                 break;
4276         case RTL_GIGA_MAC_VER_19:
4277                 rtl8168c_1_hw_phy_config(tp);
4278                 break;
4279         case RTL_GIGA_MAC_VER_20:
4280                 rtl8168c_2_hw_phy_config(tp);
4281                 break;
4282         case RTL_GIGA_MAC_VER_21:
4283                 rtl8168c_3_hw_phy_config(tp);
4284                 break;
4285         case RTL_GIGA_MAC_VER_22:
4286                 rtl8168c_4_hw_phy_config(tp);
4287                 break;
4288         case RTL_GIGA_MAC_VER_23:
4289         case RTL_GIGA_MAC_VER_24:
4290                 rtl8168cp_2_hw_phy_config(tp);
4291                 break;
4292         case RTL_GIGA_MAC_VER_25:
4293                 rtl8168d_1_hw_phy_config(tp);
4294                 break;
4295         case RTL_GIGA_MAC_VER_26:
4296                 rtl8168d_2_hw_phy_config(tp);
4297                 break;
4298         case RTL_GIGA_MAC_VER_27:
4299                 rtl8168d_3_hw_phy_config(tp);
4300                 break;
4301         case RTL_GIGA_MAC_VER_28:
4302                 rtl8168d_4_hw_phy_config(tp);
4303                 break;
4304         case RTL_GIGA_MAC_VER_29:
4305         case RTL_GIGA_MAC_VER_30:
4306                 rtl8105e_hw_phy_config(tp);
4307                 break;
4308         case RTL_GIGA_MAC_VER_31:
4309                 /* None. */
4310                 break;
4311         case RTL_GIGA_MAC_VER_32:
4312         case RTL_GIGA_MAC_VER_33:
4313                 rtl8168e_1_hw_phy_config(tp);
4314                 break;
4315         case RTL_GIGA_MAC_VER_34:
4316                 rtl8168e_2_hw_phy_config(tp);
4317                 break;
4318         case RTL_GIGA_MAC_VER_35:
4319                 rtl8168f_1_hw_phy_config(tp);
4320                 break;
4321         case RTL_GIGA_MAC_VER_36:
4322                 rtl8168f_2_hw_phy_config(tp);
4323                 break;
4324
4325         case RTL_GIGA_MAC_VER_37:
4326                 rtl8402_hw_phy_config(tp);
4327                 break;
4328
4329         case RTL_GIGA_MAC_VER_38:
4330                 rtl8411_hw_phy_config(tp);
4331                 break;
4332
4333         case RTL_GIGA_MAC_VER_39:
4334                 rtl8106e_hw_phy_config(tp);
4335                 break;
4336
4337         case RTL_GIGA_MAC_VER_40:
4338                 rtl8168g_1_hw_phy_config(tp);
4339                 break;
4340         case RTL_GIGA_MAC_VER_42:
4341         case RTL_GIGA_MAC_VER_43:
4342         case RTL_GIGA_MAC_VER_44:
4343                 rtl8168g_2_hw_phy_config(tp);
4344                 break;
4345         case RTL_GIGA_MAC_VER_45:
4346         case RTL_GIGA_MAC_VER_47:
4347                 rtl8168h_1_hw_phy_config(tp);
4348                 break;
4349         case RTL_GIGA_MAC_VER_46:
4350         case RTL_GIGA_MAC_VER_48:
4351                 rtl8168h_2_hw_phy_config(tp);
4352                 break;
4353
4354         case RTL_GIGA_MAC_VER_49:
4355                 rtl8168ep_1_hw_phy_config(tp);
4356                 break;
4357         case RTL_GIGA_MAC_VER_50:
4358         case RTL_GIGA_MAC_VER_51:
4359                 rtl8168ep_2_hw_phy_config(tp);
4360                 break;
4361
4362         case RTL_GIGA_MAC_VER_41:
4363         default:
4364                 break;
4365         }
4366 }
4367
4368 static void rtl_phy_work(struct rtl8169_private *tp)
4369 {
4370         struct timer_list *timer = &tp->timer;
4371         void __iomem *ioaddr = tp->mmio_addr;
4372         unsigned long timeout = RTL8169_PHY_TIMEOUT;
4373
4374         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
4375
4376         if (tp->phy_reset_pending(tp)) {
4377                 /*
4378                  * A busy loop could burn quite a few cycles on nowadays CPU.
4379                  * Let's delay the execution of the timer for a few ticks.
4380                  */
4381                 timeout = HZ/10;
4382                 goto out_mod_timer;
4383         }
4384
4385         if (tp->link_ok(ioaddr))
4386                 return;
4387
4388         netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
4389
4390         tp->phy_reset_enable(tp);
4391
4392 out_mod_timer:
4393         mod_timer(timer, jiffies + timeout);
4394 }
4395
4396 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4397 {
4398         if (!test_and_set_bit(flag, tp->wk.flags))
4399                 schedule_work(&tp->wk.work);
4400 }
4401
4402 static void rtl8169_phy_timer(unsigned long __opaque)
4403 {
4404         struct net_device *dev = (struct net_device *)__opaque;
4405         struct rtl8169_private *tp = netdev_priv(dev);
4406
4407         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
4408 }
4409
4410 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
4411                                   void __iomem *ioaddr)
4412 {
4413         iounmap(ioaddr);
4414         pci_release_regions(pdev);
4415         pci_clear_mwi(pdev);
4416         pci_disable_device(pdev);
4417         free_netdev(dev);
4418 }
4419
4420 DECLARE_RTL_COND(rtl_phy_reset_cond)
4421 {
4422         return tp->phy_reset_pending(tp);
4423 }
4424
4425 static void rtl8169_phy_reset(struct net_device *dev,
4426                               struct rtl8169_private *tp)
4427 {
4428         tp->phy_reset_enable(tp);
4429         rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
4430 }
4431
4432 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4433 {
4434         void __iomem *ioaddr = tp->mmio_addr;
4435
4436         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4437             (RTL_R8(PHYstatus) & TBI_Enable);
4438 }
4439
4440 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4441 {
4442         void __iomem *ioaddr = tp->mmio_addr;
4443
4444         rtl_hw_phy_config(dev);
4445
4446         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4447                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4448                 RTL_W8(0x82, 0x01);
4449         }
4450
4451         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4452
4453         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4454                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4455
4456         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4457                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4458                 RTL_W8(0x82, 0x01);
4459                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4460                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4461         }
4462
4463         rtl8169_phy_reset(dev, tp);
4464
4465         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4466                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4467                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4468                           (tp->mii.supports_gmii ?
4469                            ADVERTISED_1000baseT_Half |
4470                            ADVERTISED_1000baseT_Full : 0));
4471
4472         if (rtl_tbi_enabled(tp))
4473                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4474 }
4475
4476 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4477 {
4478         void __iomem *ioaddr = tp->mmio_addr;
4479
4480         rtl_lock_work(tp);
4481
4482         RTL_W8(Cfg9346, Cfg9346_Unlock);
4483
4484         RTL_W32(MAC4, addr[4] | addr[5] << 8);
4485         RTL_R32(MAC4);
4486
4487         RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4488         RTL_R32(MAC0);
4489
4490         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4491                 rtl_rar_exgmac_set(tp, addr);
4492
4493         RTL_W8(Cfg9346, Cfg9346_Lock);
4494
4495         rtl_unlock_work(tp);
4496 }
4497
4498 static int rtl_set_mac_address(struct net_device *dev, void *p)
4499 {
4500         struct rtl8169_private *tp = netdev_priv(dev);
4501         struct device *d = &tp->pci_dev->dev;
4502         struct sockaddr *addr = p;
4503
4504         if (!is_valid_ether_addr(addr->sa_data))
4505                 return -EADDRNOTAVAIL;
4506
4507         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4508
4509         pm_runtime_get_noresume(d);
4510
4511         if (pm_runtime_active(d))
4512                 rtl_rar_set(tp, dev->dev_addr);
4513
4514         pm_runtime_put_noidle(d);
4515
4516         return 0;
4517 }
4518
4519 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4520 {
4521         struct rtl8169_private *tp = netdev_priv(dev);
4522         struct mii_ioctl_data *data = if_mii(ifr);
4523
4524         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4525 }
4526
4527 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4528                           struct mii_ioctl_data *data, int cmd)
4529 {
4530         switch (cmd) {
4531         case SIOCGMIIPHY:
4532                 data->phy_id = 32; /* Internal PHY */
4533                 return 0;
4534
4535         case SIOCGMIIREG:
4536                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
4537                 return 0;
4538
4539         case SIOCSMIIREG:
4540                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
4541                 return 0;
4542         }
4543         return -EOPNOTSUPP;
4544 }
4545
4546 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4547 {
4548         return -EOPNOTSUPP;
4549 }
4550
4551 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
4552 {
4553         if (tp->features & RTL_FEATURE_MSI) {
4554                 pci_disable_msi(pdev);
4555                 tp->features &= ~RTL_FEATURE_MSI;
4556         }
4557 }
4558
4559 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4560 {
4561         struct mdio_ops *ops = &tp->mdio_ops;
4562
4563         switch (tp->mac_version) {
4564         case RTL_GIGA_MAC_VER_27:
4565                 ops->write      = r8168dp_1_mdio_write;
4566                 ops->read       = r8168dp_1_mdio_read;
4567                 break;
4568         case RTL_GIGA_MAC_VER_28:
4569         case RTL_GIGA_MAC_VER_31:
4570                 ops->write      = r8168dp_2_mdio_write;
4571                 ops->read       = r8168dp_2_mdio_read;
4572                 break;
4573         case RTL_GIGA_MAC_VER_40:
4574         case RTL_GIGA_MAC_VER_41:
4575         case RTL_GIGA_MAC_VER_42:
4576         case RTL_GIGA_MAC_VER_43:
4577         case RTL_GIGA_MAC_VER_44:
4578         case RTL_GIGA_MAC_VER_45:
4579         case RTL_GIGA_MAC_VER_46:
4580         case RTL_GIGA_MAC_VER_47:
4581         case RTL_GIGA_MAC_VER_48:
4582         case RTL_GIGA_MAC_VER_49:
4583         case RTL_GIGA_MAC_VER_50:
4584         case RTL_GIGA_MAC_VER_51:
4585                 ops->write      = r8168g_mdio_write;
4586                 ops->read       = r8168g_mdio_read;
4587                 break;
4588         default:
4589                 ops->write      = r8169_mdio_write;
4590                 ops->read       = r8169_mdio_read;
4591                 break;
4592         }
4593 }
4594
4595 static void rtl_speed_down(struct rtl8169_private *tp)
4596 {
4597         u32 adv;
4598         int lpa;
4599
4600         rtl_writephy(tp, 0x1f, 0x0000);
4601         lpa = rtl_readphy(tp, MII_LPA);
4602
4603         if (lpa & (LPA_10HALF | LPA_10FULL))
4604                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4605         else if (lpa & (LPA_100HALF | LPA_100FULL))
4606                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4607                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4608         else
4609                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4610                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4611                       (tp->mii.supports_gmii ?
4612                        ADVERTISED_1000baseT_Half |
4613                        ADVERTISED_1000baseT_Full : 0);
4614
4615         rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4616                           adv);
4617 }
4618
4619 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4620 {
4621         void __iomem *ioaddr = tp->mmio_addr;
4622
4623         switch (tp->mac_version) {
4624         case RTL_GIGA_MAC_VER_25:
4625         case RTL_GIGA_MAC_VER_26:
4626         case RTL_GIGA_MAC_VER_29:
4627         case RTL_GIGA_MAC_VER_30:
4628         case RTL_GIGA_MAC_VER_32:
4629         case RTL_GIGA_MAC_VER_33:
4630         case RTL_GIGA_MAC_VER_34:
4631         case RTL_GIGA_MAC_VER_37:
4632         case RTL_GIGA_MAC_VER_38:
4633         case RTL_GIGA_MAC_VER_39:
4634         case RTL_GIGA_MAC_VER_40:
4635         case RTL_GIGA_MAC_VER_41:
4636         case RTL_GIGA_MAC_VER_42:
4637         case RTL_GIGA_MAC_VER_43:
4638         case RTL_GIGA_MAC_VER_44:
4639         case RTL_GIGA_MAC_VER_45:
4640         case RTL_GIGA_MAC_VER_46:
4641         case RTL_GIGA_MAC_VER_47:
4642         case RTL_GIGA_MAC_VER_48:
4643         case RTL_GIGA_MAC_VER_49:
4644         case RTL_GIGA_MAC_VER_50:
4645         case RTL_GIGA_MAC_VER_51:
4646                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4647                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4648                 break;
4649         default:
4650                 break;
4651         }
4652 }
4653
4654 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4655 {
4656         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4657                 return false;
4658
4659         rtl_speed_down(tp);
4660         rtl_wol_suspend_quirk(tp);
4661
4662         return true;
4663 }
4664
4665 static void r810x_phy_power_down(struct rtl8169_private *tp)
4666 {
4667         rtl_writephy(tp, 0x1f, 0x0000);
4668         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4669 }
4670
4671 static void r810x_phy_power_up(struct rtl8169_private *tp)
4672 {
4673         rtl_writephy(tp, 0x1f, 0x0000);
4674         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4675 }
4676
4677 static void r810x_pll_power_down(struct rtl8169_private *tp)
4678 {
4679         void __iomem *ioaddr = tp->mmio_addr;
4680
4681         if (rtl_wol_pll_power_down(tp))
4682                 return;
4683
4684         r810x_phy_power_down(tp);
4685
4686         switch (tp->mac_version) {
4687         case RTL_GIGA_MAC_VER_07:
4688         case RTL_GIGA_MAC_VER_08:
4689         case RTL_GIGA_MAC_VER_09:
4690         case RTL_GIGA_MAC_VER_10:
4691         case RTL_GIGA_MAC_VER_13:
4692         case RTL_GIGA_MAC_VER_16:
4693                 break;
4694         default:
4695                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4696                 break;
4697         }
4698 }
4699
4700 static void r810x_pll_power_up(struct rtl8169_private *tp)
4701 {
4702         void __iomem *ioaddr = tp->mmio_addr;
4703
4704         r810x_phy_power_up(tp);
4705
4706         switch (tp->mac_version) {
4707         case RTL_GIGA_MAC_VER_07:
4708         case RTL_GIGA_MAC_VER_08:
4709         case RTL_GIGA_MAC_VER_09:
4710         case RTL_GIGA_MAC_VER_10:
4711         case RTL_GIGA_MAC_VER_13:
4712         case RTL_GIGA_MAC_VER_16:
4713                 break;
4714         case RTL_GIGA_MAC_VER_47:
4715         case RTL_GIGA_MAC_VER_48:
4716                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4717                 break;
4718         default:
4719                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4720                 break;
4721         }
4722 }
4723
4724 static void r8168_phy_power_up(struct rtl8169_private *tp)
4725 {
4726         rtl_writephy(tp, 0x1f, 0x0000);
4727         switch (tp->mac_version) {
4728         case RTL_GIGA_MAC_VER_11:
4729         case RTL_GIGA_MAC_VER_12:
4730         case RTL_GIGA_MAC_VER_17:
4731         case RTL_GIGA_MAC_VER_18:
4732         case RTL_GIGA_MAC_VER_19:
4733         case RTL_GIGA_MAC_VER_20:
4734         case RTL_GIGA_MAC_VER_21:
4735         case RTL_GIGA_MAC_VER_22:
4736         case RTL_GIGA_MAC_VER_23:
4737         case RTL_GIGA_MAC_VER_24:
4738         case RTL_GIGA_MAC_VER_25:
4739         case RTL_GIGA_MAC_VER_26:
4740         case RTL_GIGA_MAC_VER_27:
4741         case RTL_GIGA_MAC_VER_28:
4742         case RTL_GIGA_MAC_VER_31:
4743                 rtl_writephy(tp, 0x0e, 0x0000);
4744                 break;
4745         default:
4746                 break;
4747         }
4748         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4749 }
4750
4751 static void r8168_phy_power_down(struct rtl8169_private *tp)
4752 {
4753         rtl_writephy(tp, 0x1f, 0x0000);
4754         switch (tp->mac_version) {
4755         case RTL_GIGA_MAC_VER_32:
4756         case RTL_GIGA_MAC_VER_33:
4757         case RTL_GIGA_MAC_VER_40:
4758         case RTL_GIGA_MAC_VER_41:
4759                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4760                 break;
4761
4762         case RTL_GIGA_MAC_VER_11:
4763         case RTL_GIGA_MAC_VER_12:
4764         case RTL_GIGA_MAC_VER_17:
4765         case RTL_GIGA_MAC_VER_18:
4766         case RTL_GIGA_MAC_VER_19:
4767         case RTL_GIGA_MAC_VER_20:
4768         case RTL_GIGA_MAC_VER_21:
4769         case RTL_GIGA_MAC_VER_22:
4770         case RTL_GIGA_MAC_VER_23:
4771         case RTL_GIGA_MAC_VER_24:
4772         case RTL_GIGA_MAC_VER_25:
4773         case RTL_GIGA_MAC_VER_26:
4774         case RTL_GIGA_MAC_VER_27:
4775         case RTL_GIGA_MAC_VER_28:
4776         case RTL_GIGA_MAC_VER_31:
4777                 rtl_writephy(tp, 0x0e, 0x0200);
4778         default:
4779                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4780                 break;
4781         }
4782 }
4783
4784 static void r8168_pll_power_down(struct rtl8169_private *tp)
4785 {
4786         void __iomem *ioaddr = tp->mmio_addr;
4787
4788         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4789              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4790              tp->mac_version == RTL_GIGA_MAC_VER_31 ||
4791              tp->mac_version == RTL_GIGA_MAC_VER_49 ||
4792              tp->mac_version == RTL_GIGA_MAC_VER_50 ||
4793              tp->mac_version == RTL_GIGA_MAC_VER_51) &&
4794             r8168_check_dash(tp)) {
4795                 return;
4796         }
4797
4798         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4799              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4800             (RTL_R16(CPlusCmd) & ASF)) {
4801                 return;
4802         }
4803
4804         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4805             tp->mac_version == RTL_GIGA_MAC_VER_33)
4806                 rtl_ephy_write(tp, 0x19, 0xff64);
4807
4808         if (rtl_wol_pll_power_down(tp))
4809                 return;
4810
4811         r8168_phy_power_down(tp);
4812
4813         switch (tp->mac_version) {
4814         case RTL_GIGA_MAC_VER_25:
4815         case RTL_GIGA_MAC_VER_26:
4816         case RTL_GIGA_MAC_VER_27:
4817         case RTL_GIGA_MAC_VER_28:
4818         case RTL_GIGA_MAC_VER_31:
4819         case RTL_GIGA_MAC_VER_32:
4820         case RTL_GIGA_MAC_VER_33:
4821         case RTL_GIGA_MAC_VER_44:
4822         case RTL_GIGA_MAC_VER_45:
4823         case RTL_GIGA_MAC_VER_46:
4824         case RTL_GIGA_MAC_VER_50:
4825         case RTL_GIGA_MAC_VER_51:
4826                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4827                 break;
4828         case RTL_GIGA_MAC_VER_40:
4829         case RTL_GIGA_MAC_VER_41:
4830         case RTL_GIGA_MAC_VER_49:
4831                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4832                              0xfc000000, ERIAR_EXGMAC);
4833                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4834                 break;
4835         }
4836 }
4837
4838 static void r8168_pll_power_up(struct rtl8169_private *tp)
4839 {
4840         void __iomem *ioaddr = tp->mmio_addr;
4841
4842         switch (tp->mac_version) {
4843         case RTL_GIGA_MAC_VER_25:
4844         case RTL_GIGA_MAC_VER_26:
4845         case RTL_GIGA_MAC_VER_27:
4846         case RTL_GIGA_MAC_VER_28:
4847         case RTL_GIGA_MAC_VER_31:
4848         case RTL_GIGA_MAC_VER_32:
4849         case RTL_GIGA_MAC_VER_33:
4850                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4851                 break;
4852         case RTL_GIGA_MAC_VER_44:
4853         case RTL_GIGA_MAC_VER_45:
4854         case RTL_GIGA_MAC_VER_46:
4855         case RTL_GIGA_MAC_VER_50:
4856         case RTL_GIGA_MAC_VER_51:
4857                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4858                 break;
4859         case RTL_GIGA_MAC_VER_40:
4860         case RTL_GIGA_MAC_VER_41:
4861         case RTL_GIGA_MAC_VER_49:
4862                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4863                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4864                              0x00000000, ERIAR_EXGMAC);
4865                 break;
4866         }
4867
4868         r8168_phy_power_up(tp);
4869 }
4870
4871 static void rtl_generic_op(struct rtl8169_private *tp,
4872                            void (*op)(struct rtl8169_private *))
4873 {
4874         if (op)
4875                 op(tp);
4876 }
4877
4878 static void rtl_pll_power_down(struct rtl8169_private *tp)
4879 {
4880         rtl_generic_op(tp, tp->pll_power_ops.down);
4881 }
4882
4883 static void rtl_pll_power_up(struct rtl8169_private *tp)
4884 {
4885         rtl_generic_op(tp, tp->pll_power_ops.up);
4886 }
4887
4888 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4889 {
4890         struct pll_power_ops *ops = &tp->pll_power_ops;
4891
4892         switch (tp->mac_version) {
4893         case RTL_GIGA_MAC_VER_07:
4894         case RTL_GIGA_MAC_VER_08:
4895         case RTL_GIGA_MAC_VER_09:
4896         case RTL_GIGA_MAC_VER_10:
4897         case RTL_GIGA_MAC_VER_16:
4898         case RTL_GIGA_MAC_VER_29:
4899         case RTL_GIGA_MAC_VER_30:
4900         case RTL_GIGA_MAC_VER_37:
4901         case RTL_GIGA_MAC_VER_39:
4902         case RTL_GIGA_MAC_VER_43:
4903         case RTL_GIGA_MAC_VER_47:
4904         case RTL_GIGA_MAC_VER_48:
4905                 ops->down       = r810x_pll_power_down;
4906                 ops->up         = r810x_pll_power_up;
4907                 break;
4908
4909         case RTL_GIGA_MAC_VER_11:
4910         case RTL_GIGA_MAC_VER_12:
4911         case RTL_GIGA_MAC_VER_17:
4912         case RTL_GIGA_MAC_VER_18:
4913         case RTL_GIGA_MAC_VER_19:
4914         case RTL_GIGA_MAC_VER_20:
4915         case RTL_GIGA_MAC_VER_21:
4916         case RTL_GIGA_MAC_VER_22:
4917         case RTL_GIGA_MAC_VER_23:
4918         case RTL_GIGA_MAC_VER_24:
4919         case RTL_GIGA_MAC_VER_25:
4920         case RTL_GIGA_MAC_VER_26:
4921         case RTL_GIGA_MAC_VER_27:
4922         case RTL_GIGA_MAC_VER_28:
4923         case RTL_GIGA_MAC_VER_31:
4924         case RTL_GIGA_MAC_VER_32:
4925         case RTL_GIGA_MAC_VER_33:
4926         case RTL_GIGA_MAC_VER_34:
4927         case RTL_GIGA_MAC_VER_35:
4928         case RTL_GIGA_MAC_VER_36:
4929         case RTL_GIGA_MAC_VER_38:
4930         case RTL_GIGA_MAC_VER_40:
4931         case RTL_GIGA_MAC_VER_41:
4932         case RTL_GIGA_MAC_VER_42:
4933         case RTL_GIGA_MAC_VER_44:
4934         case RTL_GIGA_MAC_VER_45:
4935         case RTL_GIGA_MAC_VER_46:
4936         case RTL_GIGA_MAC_VER_49:
4937         case RTL_GIGA_MAC_VER_50:
4938         case RTL_GIGA_MAC_VER_51:
4939                 ops->down       = r8168_pll_power_down;
4940                 ops->up         = r8168_pll_power_up;
4941                 break;
4942
4943         default:
4944                 ops->down       = NULL;
4945                 ops->up         = NULL;
4946                 break;
4947         }
4948 }
4949
4950 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4951 {
4952         void __iomem *ioaddr = tp->mmio_addr;
4953
4954         switch (tp->mac_version) {
4955         case RTL_GIGA_MAC_VER_01:
4956         case RTL_GIGA_MAC_VER_02:
4957         case RTL_GIGA_MAC_VER_03:
4958         case RTL_GIGA_MAC_VER_04:
4959         case RTL_GIGA_MAC_VER_05:
4960         case RTL_GIGA_MAC_VER_06:
4961         case RTL_GIGA_MAC_VER_10:
4962         case RTL_GIGA_MAC_VER_11:
4963         case RTL_GIGA_MAC_VER_12:
4964         case RTL_GIGA_MAC_VER_13:
4965         case RTL_GIGA_MAC_VER_14:
4966         case RTL_GIGA_MAC_VER_15:
4967         case RTL_GIGA_MAC_VER_16:
4968         case RTL_GIGA_MAC_VER_17:
4969                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4970                 break;
4971         case RTL_GIGA_MAC_VER_18:
4972         case RTL_GIGA_MAC_VER_19:
4973         case RTL_GIGA_MAC_VER_20:
4974         case RTL_GIGA_MAC_VER_21:
4975         case RTL_GIGA_MAC_VER_22:
4976         case RTL_GIGA_MAC_VER_23:
4977         case RTL_GIGA_MAC_VER_24:
4978         case RTL_GIGA_MAC_VER_34:
4979         case RTL_GIGA_MAC_VER_35:
4980                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4981                 break;
4982         case RTL_GIGA_MAC_VER_40:
4983         case RTL_GIGA_MAC_VER_41:
4984         case RTL_GIGA_MAC_VER_42:
4985         case RTL_GIGA_MAC_VER_43:
4986         case RTL_GIGA_MAC_VER_44:
4987         case RTL_GIGA_MAC_VER_45:
4988         case RTL_GIGA_MAC_VER_46:
4989         case RTL_GIGA_MAC_VER_47:
4990         case RTL_GIGA_MAC_VER_48:
4991         case RTL_GIGA_MAC_VER_49:
4992         case RTL_GIGA_MAC_VER_50:
4993         case RTL_GIGA_MAC_VER_51:
4994                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4995                 break;
4996         default:
4997                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4998                 break;
4999         }
5000 }
5001
5002 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
5003 {
5004         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
5005 }
5006
5007 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
5008 {
5009         void __iomem *ioaddr = tp->mmio_addr;
5010
5011         RTL_W8(Cfg9346, Cfg9346_Unlock);
5012         rtl_generic_op(tp, tp->jumbo_ops.enable);
5013         RTL_W8(Cfg9346, Cfg9346_Lock);
5014 }
5015
5016 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
5017 {
5018         void __iomem *ioaddr = tp->mmio_addr;
5019
5020         RTL_W8(Cfg9346, Cfg9346_Unlock);
5021         rtl_generic_op(tp, tp->jumbo_ops.disable);
5022         RTL_W8(Cfg9346, Cfg9346_Lock);
5023 }
5024
5025 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
5026 {
5027         void __iomem *ioaddr = tp->mmio_addr;
5028
5029         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5030         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
5031         rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
5032 }
5033
5034 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
5035 {
5036         void __iomem *ioaddr = tp->mmio_addr;
5037
5038         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5039         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
5040         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5041 }
5042
5043 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
5044 {
5045         void __iomem *ioaddr = tp->mmio_addr;
5046
5047         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5048 }
5049
5050 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
5051 {
5052         void __iomem *ioaddr = tp->mmio_addr;
5053
5054         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5055 }
5056
5057 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
5058 {
5059         void __iomem *ioaddr = tp->mmio_addr;
5060
5061         RTL_W8(MaxTxPacketSize, 0x3f);
5062         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5063         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
5064         rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
5065 }
5066
5067 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
5068 {
5069         void __iomem *ioaddr = tp->mmio_addr;
5070
5071         RTL_W8(MaxTxPacketSize, 0x0c);
5072         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5073         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
5074         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5075 }
5076
5077 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
5078 {
5079         rtl_tx_performance_tweak(tp->pci_dev,
5080                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
5081 }
5082
5083 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
5084 {
5085         rtl_tx_performance_tweak(tp->pci_dev,
5086                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
5087 }
5088
5089 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
5090 {
5091         void __iomem *ioaddr = tp->mmio_addr;
5092
5093         r8168b_0_hw_jumbo_enable(tp);
5094
5095         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
5096 }
5097
5098 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
5099 {
5100         void __iomem *ioaddr = tp->mmio_addr;
5101
5102         r8168b_0_hw_jumbo_disable(tp);
5103
5104         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5105 }
5106
5107 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
5108 {
5109         struct jumbo_ops *ops = &tp->jumbo_ops;
5110
5111         switch (tp->mac_version) {
5112         case RTL_GIGA_MAC_VER_11:
5113                 ops->disable    = r8168b_0_hw_jumbo_disable;
5114                 ops->enable     = r8168b_0_hw_jumbo_enable;
5115                 break;
5116         case RTL_GIGA_MAC_VER_12:
5117         case RTL_GIGA_MAC_VER_17:
5118                 ops->disable    = r8168b_1_hw_jumbo_disable;
5119                 ops->enable     = r8168b_1_hw_jumbo_enable;
5120                 break;
5121         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5122         case RTL_GIGA_MAC_VER_19:
5123         case RTL_GIGA_MAC_VER_20:
5124         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5125         case RTL_GIGA_MAC_VER_22:
5126         case RTL_GIGA_MAC_VER_23:
5127         case RTL_GIGA_MAC_VER_24:
5128         case RTL_GIGA_MAC_VER_25:
5129         case RTL_GIGA_MAC_VER_26:
5130                 ops->disable    = r8168c_hw_jumbo_disable;
5131                 ops->enable     = r8168c_hw_jumbo_enable;
5132                 break;
5133         case RTL_GIGA_MAC_VER_27:
5134         case RTL_GIGA_MAC_VER_28:
5135                 ops->disable    = r8168dp_hw_jumbo_disable;
5136                 ops->enable     = r8168dp_hw_jumbo_enable;
5137                 break;
5138         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5139         case RTL_GIGA_MAC_VER_32:
5140         case RTL_GIGA_MAC_VER_33:
5141         case RTL_GIGA_MAC_VER_34:
5142                 ops->disable    = r8168e_hw_jumbo_disable;
5143                 ops->enable     = r8168e_hw_jumbo_enable;
5144                 break;
5145
5146         /*
5147          * No action needed for jumbo frames with 8169.
5148          * No jumbo for 810x at all.
5149          */
5150         case RTL_GIGA_MAC_VER_40:
5151         case RTL_GIGA_MAC_VER_41:
5152         case RTL_GIGA_MAC_VER_42:
5153         case RTL_GIGA_MAC_VER_43:
5154         case RTL_GIGA_MAC_VER_44:
5155         case RTL_GIGA_MAC_VER_45:
5156         case RTL_GIGA_MAC_VER_46:
5157         case RTL_GIGA_MAC_VER_47:
5158         case RTL_GIGA_MAC_VER_48:
5159         case RTL_GIGA_MAC_VER_49:
5160         case RTL_GIGA_MAC_VER_50:
5161         case RTL_GIGA_MAC_VER_51:
5162         default:
5163                 ops->disable    = NULL;
5164                 ops->enable     = NULL;
5165                 break;
5166         }
5167 }
5168
5169 DECLARE_RTL_COND(rtl_chipcmd_cond)
5170 {
5171         void __iomem *ioaddr = tp->mmio_addr;
5172
5173         return RTL_R8(ChipCmd) & CmdReset;
5174 }
5175
5176 static void rtl_hw_reset(struct rtl8169_private *tp)
5177 {
5178         void __iomem *ioaddr = tp->mmio_addr;
5179
5180         RTL_W8(ChipCmd, CmdReset);
5181
5182         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
5183 }
5184
5185 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
5186 {
5187         struct rtl_fw *rtl_fw;
5188         const char *name;
5189         int rc = -ENOMEM;
5190
5191         name = rtl_lookup_firmware_name(tp);
5192         if (!name)
5193                 goto out_no_firmware;
5194
5195         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5196         if (!rtl_fw)
5197                 goto err_warn;
5198
5199         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
5200         if (rc < 0)
5201                 goto err_free;
5202
5203         rc = rtl_check_firmware(tp, rtl_fw);
5204         if (rc < 0)
5205                 goto err_release_firmware;
5206
5207         tp->rtl_fw = rtl_fw;
5208 out:
5209         return;
5210
5211 err_release_firmware:
5212         release_firmware(rtl_fw->fw);
5213 err_free:
5214         kfree(rtl_fw);
5215 err_warn:
5216         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5217                    name, rc);
5218 out_no_firmware:
5219         tp->rtl_fw = NULL;
5220         goto out;
5221 }
5222
5223 static void rtl_request_firmware(struct rtl8169_private *tp)
5224 {
5225         if (IS_ERR(tp->rtl_fw))
5226                 rtl_request_uncached_firmware(tp);
5227 }
5228
5229 static void rtl_rx_close(struct rtl8169_private *tp)
5230 {
5231         void __iomem *ioaddr = tp->mmio_addr;
5232
5233         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
5234 }
5235
5236 DECLARE_RTL_COND(rtl_npq_cond)
5237 {
5238         void __iomem *ioaddr = tp->mmio_addr;
5239
5240         return RTL_R8(TxPoll) & NPQ;
5241 }
5242
5243 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5244 {
5245         void __iomem *ioaddr = tp->mmio_addr;
5246
5247         return RTL_R32(TxConfig) & TXCFG_EMPTY;
5248 }
5249
5250 static void rtl8169_hw_reset(struct rtl8169_private *tp)
5251 {
5252         void __iomem *ioaddr = tp->mmio_addr;
5253
5254         /* Disable interrupts */
5255         rtl8169_irq_mask_and_ack(tp);
5256
5257         rtl_rx_close(tp);
5258
5259         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5260             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5261             tp->mac_version == RTL_GIGA_MAC_VER_31) {
5262                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
5263         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
5264                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5265                    tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5266                    tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5267                    tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5268                    tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5269                    tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5270                    tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5271                    tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5272                    tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5273                    tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5274                    tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5275                    tp->mac_version == RTL_GIGA_MAC_VER_47 ||
5276                    tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5277                    tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5278                    tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5279                    tp->mac_version == RTL_GIGA_MAC_VER_51) {
5280                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5281                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
5282         } else {
5283                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5284                 udelay(100);
5285         }
5286
5287         rtl_hw_reset(tp);
5288 }
5289
5290 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
5291 {
5292         void __iomem *ioaddr = tp->mmio_addr;
5293
5294         /* Set DMA burst size and Interframe Gap Time */
5295         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5296                 (InterFrameGap << TxInterFrameGapShift));
5297 }
5298
5299 static void rtl_hw_start(struct net_device *dev)
5300 {
5301         struct rtl8169_private *tp = netdev_priv(dev);
5302
5303         tp->hw_start(dev);
5304
5305         rtl_irq_enable_all(tp);
5306 }
5307
5308 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
5309                                          void __iomem *ioaddr)
5310 {
5311         /*
5312          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5313          * register to be written before TxDescAddrLow to work.
5314          * Switching from MMIO to I/O access fixes the issue as well.
5315          */
5316         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
5317         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
5318         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
5319         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
5320 }
5321
5322 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
5323 {
5324         u16 cmd;
5325
5326         cmd = RTL_R16(CPlusCmd);
5327         RTL_W16(CPlusCmd, cmd);
5328         return cmd;
5329 }
5330
5331 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
5332 {
5333         /* Low hurts. Let's disable the filtering. */
5334         RTL_W16(RxMaxSize, rx_buf_sz + 1);
5335 }
5336
5337 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
5338 {
5339         static const struct rtl_cfg2_info {
5340                 u32 mac_version;
5341                 u32 clk;
5342                 u32 val;
5343         } cfg2_info [] = {
5344                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5345                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5346                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5347                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
5348         };
5349         const struct rtl_cfg2_info *p = cfg2_info;
5350         unsigned int i;
5351         u32 clk;
5352
5353         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
5354         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
5355                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5356                         RTL_W32(0x7c, p->val);
5357                         break;
5358                 }
5359         }
5360 }
5361
5362 static void rtl_set_rx_mode(struct net_device *dev)
5363 {
5364         struct rtl8169_private *tp = netdev_priv(dev);
5365         void __iomem *ioaddr = tp->mmio_addr;
5366         u32 mc_filter[2];       /* Multicast hash filter */
5367         int rx_mode;
5368         u32 tmp = 0;
5369
5370         if (dev->flags & IFF_PROMISC) {
5371                 /* Unconditionally log net taps. */
5372                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5373                 rx_mode =
5374                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5375                     AcceptAllPhys;
5376                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5377         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5378                    (dev->flags & IFF_ALLMULTI)) {
5379                 /* Too many to filter perfectly -- accept all multicasts. */
5380                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5381                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5382         } else {
5383                 struct netdev_hw_addr *ha;
5384
5385                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5386                 mc_filter[1] = mc_filter[0] = 0;
5387                 netdev_for_each_mc_addr(ha, dev) {
5388                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5389                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5390                         rx_mode |= AcceptMulticast;
5391                 }
5392         }
5393
5394         if (dev->features & NETIF_F_RXALL)
5395                 rx_mode |= (AcceptErr | AcceptRunt);
5396
5397         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5398
5399         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5400                 u32 data = mc_filter[0];
5401
5402                 mc_filter[0] = swab32(mc_filter[1]);
5403                 mc_filter[1] = swab32(data);
5404         }
5405
5406         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5407                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5408
5409         RTL_W32(MAR0 + 4, mc_filter[1]);
5410         RTL_W32(MAR0 + 0, mc_filter[0]);
5411
5412         RTL_W32(RxConfig, tmp);
5413 }
5414
5415 static void rtl_hw_start_8169(struct net_device *dev)
5416 {
5417         struct rtl8169_private *tp = netdev_priv(dev);
5418         void __iomem *ioaddr = tp->mmio_addr;
5419         struct pci_dev *pdev = tp->pci_dev;
5420
5421         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5422                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
5423                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
5424         }
5425
5426         RTL_W8(Cfg9346, Cfg9346_Unlock);
5427         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5428             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5429             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5430             tp->mac_version == RTL_GIGA_MAC_VER_04)
5431                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5432
5433         rtl_init_rxcfg(tp);
5434
5435         RTL_W8(EarlyTxThres, NoEarlyTx);
5436
5437         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5438
5439         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5440             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5441             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5442             tp->mac_version == RTL_GIGA_MAC_VER_04)
5443                 rtl_set_rx_tx_config_registers(tp);
5444
5445         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
5446
5447         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5448             tp->mac_version == RTL_GIGA_MAC_VER_03) {
5449                 dprintk("Set MAC Reg C+CR Offset 0xe0. "
5450                         "Bit-3 and bit-14 MUST be 1\n");
5451                 tp->cp_cmd |= (1 << 14);
5452         }
5453
5454         RTL_W16(CPlusCmd, tp->cp_cmd);
5455
5456         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5457
5458         /*
5459          * Undocumented corner. Supposedly:
5460          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5461          */
5462         RTL_W16(IntrMitigate, 0x0000);
5463
5464         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5465
5466         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5467             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5468             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5469             tp->mac_version != RTL_GIGA_MAC_VER_04) {
5470                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5471                 rtl_set_rx_tx_config_registers(tp);
5472         }
5473
5474         RTL_W8(Cfg9346, Cfg9346_Lock);
5475
5476         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5477         RTL_R8(IntrMask);
5478
5479         RTL_W32(RxMissed, 0);
5480
5481         rtl_set_rx_mode(dev);
5482
5483         /* no early-rx interrupts */
5484         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5485 }
5486
5487 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5488 {
5489         if (tp->csi_ops.write)
5490                 tp->csi_ops.write(tp, addr, value);
5491 }
5492
5493 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5494 {
5495         return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
5496 }
5497
5498 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
5499 {
5500         u32 csi;
5501
5502         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5503         rtl_csi_write(tp, 0x070c, csi | bits);
5504 }
5505
5506 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5507 {
5508         rtl_csi_access_enable(tp, 0x17000000);
5509 }
5510
5511 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
5512 {
5513         rtl_csi_access_enable(tp, 0x27000000);
5514 }
5515
5516 DECLARE_RTL_COND(rtl_csiar_cond)
5517 {
5518         void __iomem *ioaddr = tp->mmio_addr;
5519
5520         return RTL_R32(CSIAR) & CSIAR_FLAG;
5521 }
5522
5523 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
5524 {
5525         void __iomem *ioaddr = tp->mmio_addr;
5526
5527         RTL_W32(CSIDR, value);
5528         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5529                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5530
5531         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5532 }
5533
5534 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
5535 {
5536         void __iomem *ioaddr = tp->mmio_addr;
5537
5538         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5539                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5540
5541         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5542                 RTL_R32(CSIDR) : ~0;
5543 }
5544
5545 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
5546 {
5547         void __iomem *ioaddr = tp->mmio_addr;
5548
5549         RTL_W32(CSIDR, value);
5550         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5551                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5552                 CSIAR_FUNC_NIC);
5553
5554         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5555 }
5556
5557 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
5558 {
5559         void __iomem *ioaddr = tp->mmio_addr;
5560
5561         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5562                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5563
5564         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5565                 RTL_R32(CSIDR) : ~0;
5566 }
5567
5568 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5569 {
5570         void __iomem *ioaddr = tp->mmio_addr;
5571
5572         RTL_W32(CSIDR, value);
5573         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5574                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5575                 CSIAR_FUNC_NIC2);
5576
5577         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5578 }
5579
5580 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5581 {
5582         void __iomem *ioaddr = tp->mmio_addr;
5583
5584         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5585                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5586
5587         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5588                 RTL_R32(CSIDR) : ~0;
5589 }
5590
5591 static void rtl_init_csi_ops(struct rtl8169_private *tp)
5592 {
5593         struct csi_ops *ops = &tp->csi_ops;
5594
5595         switch (tp->mac_version) {
5596         case RTL_GIGA_MAC_VER_01:
5597         case RTL_GIGA_MAC_VER_02:
5598         case RTL_GIGA_MAC_VER_03:
5599         case RTL_GIGA_MAC_VER_04:
5600         case RTL_GIGA_MAC_VER_05:
5601         case RTL_GIGA_MAC_VER_06:
5602         case RTL_GIGA_MAC_VER_10:
5603         case RTL_GIGA_MAC_VER_11:
5604         case RTL_GIGA_MAC_VER_12:
5605         case RTL_GIGA_MAC_VER_13:
5606         case RTL_GIGA_MAC_VER_14:
5607         case RTL_GIGA_MAC_VER_15:
5608         case RTL_GIGA_MAC_VER_16:
5609         case RTL_GIGA_MAC_VER_17:
5610                 ops->write      = NULL;
5611                 ops->read       = NULL;
5612                 break;
5613
5614         case RTL_GIGA_MAC_VER_37:
5615         case RTL_GIGA_MAC_VER_38:
5616                 ops->write      = r8402_csi_write;
5617                 ops->read       = r8402_csi_read;
5618                 break;
5619
5620         case RTL_GIGA_MAC_VER_44:
5621                 ops->write      = r8411_csi_write;
5622                 ops->read       = r8411_csi_read;
5623                 break;
5624
5625         default:
5626                 ops->write      = r8169_csi_write;
5627                 ops->read       = r8169_csi_read;
5628                 break;
5629         }
5630 }
5631
5632 struct ephy_info {
5633         unsigned int offset;
5634         u16 mask;
5635         u16 bits;
5636 };
5637
5638 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5639                           int len)
5640 {
5641         u16 w;
5642
5643         while (len-- > 0) {
5644                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5645                 rtl_ephy_write(tp, e->offset, w);
5646                 e++;
5647         }
5648 }
5649
5650 static void rtl_disable_clock_request(struct pci_dev *pdev)
5651 {
5652         pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5653                                    PCI_EXP_LNKCTL_CLKREQ_EN);
5654 }
5655
5656 static void rtl_enable_clock_request(struct pci_dev *pdev)
5657 {
5658         pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5659                                  PCI_EXP_LNKCTL_CLKREQ_EN);
5660 }
5661
5662 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5663 {
5664         void __iomem *ioaddr = tp->mmio_addr;
5665         u8 data;
5666
5667         data = RTL_R8(Config3);
5668
5669         if (enable)
5670                 data |= Rdy_to_L23;
5671         else
5672                 data &= ~Rdy_to_L23;
5673
5674         RTL_W8(Config3, data);
5675 }
5676
5677 #define R8168_CPCMD_QUIRK_MASK (\
5678         EnableBist | \
5679         Mac_dbgo_oe | \
5680         Force_half_dup | \
5681         Force_rxflow_en | \
5682         Force_txflow_en | \
5683         Cxpl_dbg_sel | \
5684         ASF | \
5685         PktCntrDisable | \
5686         Mac_dbgo_sel)
5687
5688 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
5689 {
5690         void __iomem *ioaddr = tp->mmio_addr;
5691         struct pci_dev *pdev = tp->pci_dev;
5692
5693         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5694
5695         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5696
5697         if (tp->dev->mtu <= ETH_DATA_LEN) {
5698                 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5699                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5700         }
5701 }
5702
5703 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
5704 {
5705         void __iomem *ioaddr = tp->mmio_addr;
5706
5707         rtl_hw_start_8168bb(tp);
5708
5709         RTL_W8(MaxTxPacketSize, TxPacketMax);
5710
5711         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5712 }
5713
5714 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
5715 {
5716         void __iomem *ioaddr = tp->mmio_addr;
5717         struct pci_dev *pdev = tp->pci_dev;
5718
5719         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5720
5721         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5722
5723         if (tp->dev->mtu <= ETH_DATA_LEN)
5724                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5725
5726         rtl_disable_clock_request(pdev);
5727
5728         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5729 }
5730
5731 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
5732 {
5733         static const struct ephy_info e_info_8168cp[] = {
5734                 { 0x01, 0,      0x0001 },
5735                 { 0x02, 0x0800, 0x1000 },
5736                 { 0x03, 0,      0x0042 },
5737                 { 0x06, 0x0080, 0x0000 },
5738                 { 0x07, 0,      0x2000 }
5739         };
5740
5741         rtl_csi_access_enable_2(tp);
5742
5743         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
5744
5745         __rtl_hw_start_8168cp(tp);
5746 }
5747
5748 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
5749 {
5750         void __iomem *ioaddr = tp->mmio_addr;
5751         struct pci_dev *pdev = tp->pci_dev;
5752
5753         rtl_csi_access_enable_2(tp);
5754
5755         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5756
5757         if (tp->dev->mtu <= ETH_DATA_LEN)
5758                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5759
5760         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5761 }
5762
5763 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
5764 {
5765         void __iomem *ioaddr = tp->mmio_addr;
5766         struct pci_dev *pdev = tp->pci_dev;
5767
5768         rtl_csi_access_enable_2(tp);
5769
5770         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5771
5772         /* Magic. */
5773         RTL_W8(DBG_REG, 0x20);
5774
5775         RTL_W8(MaxTxPacketSize, TxPacketMax);
5776
5777         if (tp->dev->mtu <= ETH_DATA_LEN)
5778                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5779
5780         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5781 }
5782
5783 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5784 {
5785         void __iomem *ioaddr = tp->mmio_addr;
5786         static const struct ephy_info e_info_8168c_1[] = {
5787                 { 0x02, 0x0800, 0x1000 },
5788                 { 0x03, 0,      0x0002 },
5789                 { 0x06, 0x0080, 0x0000 }
5790         };
5791
5792         rtl_csi_access_enable_2(tp);
5793
5794         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5795
5796         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5797
5798         __rtl_hw_start_8168cp(tp);
5799 }
5800
5801 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5802 {
5803         static const struct ephy_info e_info_8168c_2[] = {
5804                 { 0x01, 0,      0x0001 },
5805                 { 0x03, 0x0400, 0x0220 }
5806         };
5807
5808         rtl_csi_access_enable_2(tp);
5809
5810         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5811
5812         __rtl_hw_start_8168cp(tp);
5813 }
5814
5815 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5816 {
5817         rtl_hw_start_8168c_2(tp);
5818 }
5819
5820 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5821 {
5822         rtl_csi_access_enable_2(tp);
5823
5824         __rtl_hw_start_8168cp(tp);
5825 }
5826
5827 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5828 {
5829         void __iomem *ioaddr = tp->mmio_addr;
5830         struct pci_dev *pdev = tp->pci_dev;
5831
5832         rtl_csi_access_enable_2(tp);
5833
5834         rtl_disable_clock_request(pdev);
5835
5836         RTL_W8(MaxTxPacketSize, TxPacketMax);
5837
5838         if (tp->dev->mtu <= ETH_DATA_LEN)
5839                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5840
5841         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5842 }
5843
5844 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5845 {
5846         void __iomem *ioaddr = tp->mmio_addr;
5847         struct pci_dev *pdev = tp->pci_dev;
5848
5849         rtl_csi_access_enable_1(tp);
5850
5851         if (tp->dev->mtu <= ETH_DATA_LEN)
5852                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5853
5854         RTL_W8(MaxTxPacketSize, TxPacketMax);
5855
5856         rtl_disable_clock_request(pdev);
5857 }
5858
5859 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5860 {
5861         void __iomem *ioaddr = tp->mmio_addr;
5862         struct pci_dev *pdev = tp->pci_dev;
5863         static const struct ephy_info e_info_8168d_4[] = {
5864                 { 0x0b, 0x0000, 0x0048 },
5865                 { 0x19, 0x0020, 0x0050 },
5866                 { 0x0c, 0x0100, 0x0020 }
5867         };
5868
5869         rtl_csi_access_enable_1(tp);
5870
5871         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5872
5873         RTL_W8(MaxTxPacketSize, TxPacketMax);
5874
5875         rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
5876
5877         rtl_enable_clock_request(pdev);
5878 }
5879
5880 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5881 {
5882         void __iomem *ioaddr = tp->mmio_addr;
5883         struct pci_dev *pdev = tp->pci_dev;
5884         static const struct ephy_info e_info_8168e_1[] = {
5885                 { 0x00, 0x0200, 0x0100 },
5886                 { 0x00, 0x0000, 0x0004 },
5887                 { 0x06, 0x0002, 0x0001 },
5888                 { 0x06, 0x0000, 0x0030 },
5889                 { 0x07, 0x0000, 0x2000 },
5890                 { 0x00, 0x0000, 0x0020 },
5891                 { 0x03, 0x5800, 0x2000 },
5892                 { 0x03, 0x0000, 0x0001 },
5893                 { 0x01, 0x0800, 0x1000 },
5894                 { 0x07, 0x0000, 0x4000 },
5895                 { 0x1e, 0x0000, 0x2000 },
5896                 { 0x19, 0xffff, 0xfe6c },
5897                 { 0x0a, 0x0000, 0x0040 }
5898         };
5899
5900         rtl_csi_access_enable_2(tp);
5901
5902         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5903
5904         if (tp->dev->mtu <= ETH_DATA_LEN)
5905                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5906
5907         RTL_W8(MaxTxPacketSize, TxPacketMax);
5908
5909         rtl_disable_clock_request(pdev);
5910
5911         /* Reset tx FIFO pointer */
5912         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5913         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5914
5915         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5916 }
5917
5918 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5919 {
5920         void __iomem *ioaddr = tp->mmio_addr;
5921         struct pci_dev *pdev = tp->pci_dev;
5922         static const struct ephy_info e_info_8168e_2[] = {
5923                 { 0x09, 0x0000, 0x0080 },
5924                 { 0x19, 0x0000, 0x0224 }
5925         };
5926
5927         rtl_csi_access_enable_1(tp);
5928
5929         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5930
5931         if (tp->dev->mtu <= ETH_DATA_LEN)
5932                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5933
5934         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5935         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5936         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5937         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5938         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5939         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5940         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5941         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5942
5943         RTL_W8(MaxTxPacketSize, EarlySize);
5944
5945         rtl_disable_clock_request(pdev);
5946
5947         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5948         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5949
5950         /* Adjust EEE LED frequency */
5951         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5952
5953         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5954         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5955         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5956 }
5957
5958 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5959 {
5960         void __iomem *ioaddr = tp->mmio_addr;
5961         struct pci_dev *pdev = tp->pci_dev;
5962
5963         rtl_csi_access_enable_2(tp);
5964
5965         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5966
5967         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5968         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5969         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5970         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5971         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5972         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5973         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5974         rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5975         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5976         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5977
5978         RTL_W8(MaxTxPacketSize, EarlySize);
5979
5980         rtl_disable_clock_request(pdev);
5981
5982         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5983         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5984         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5985         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5986         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5987 }
5988
5989 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5990 {
5991         void __iomem *ioaddr = tp->mmio_addr;
5992         static const struct ephy_info e_info_8168f_1[] = {
5993                 { 0x06, 0x00c0, 0x0020 },
5994                 { 0x08, 0x0001, 0x0002 },
5995                 { 0x09, 0x0000, 0x0080 },
5996                 { 0x19, 0x0000, 0x0224 }
5997         };
5998
5999         rtl_hw_start_8168f(tp);
6000
6001         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
6002
6003         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
6004
6005         /* Adjust EEE LED frequency */
6006         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6007 }
6008
6009 static void rtl_hw_start_8411(struct rtl8169_private *tp)
6010 {
6011         static const struct ephy_info e_info_8168f_1[] = {
6012                 { 0x06, 0x00c0, 0x0020 },
6013                 { 0x0f, 0xffff, 0x5200 },
6014                 { 0x1e, 0x0000, 0x4000 },
6015                 { 0x19, 0x0000, 0x0224 }
6016         };
6017
6018         rtl_hw_start_8168f(tp);
6019         rtl_pcie_state_l2l3_enable(tp, false);
6020
6021         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
6022
6023         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
6024 }
6025
6026 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
6027 {
6028         void __iomem *ioaddr = tp->mmio_addr;
6029         struct pci_dev *pdev = tp->pci_dev;
6030
6031         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6032
6033         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
6034         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6035         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6036         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6037
6038         rtl_csi_access_enable_1(tp);
6039
6040         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6041
6042         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6043         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6044         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
6045
6046         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6047         RTL_W8(MaxTxPacketSize, EarlySize);
6048
6049         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6050         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6051
6052         /* Adjust EEE LED frequency */
6053         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6054
6055         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6056         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6057
6058         rtl_pcie_state_l2l3_enable(tp, false);
6059 }
6060
6061 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
6062 {
6063         void __iomem *ioaddr = tp->mmio_addr;
6064         static const struct ephy_info e_info_8168g_1[] = {
6065                 { 0x00, 0x0000, 0x0008 },
6066                 { 0x0c, 0x37d0, 0x0820 },
6067                 { 0x1e, 0x0000, 0x0001 },
6068                 { 0x19, 0x8000, 0x0000 }
6069         };
6070
6071         rtl_hw_start_8168g(tp);
6072
6073         /* disable aspm and clock request before access ephy */
6074         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6075         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6076         rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
6077 }
6078
6079 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
6080 {
6081         void __iomem *ioaddr = tp->mmio_addr;
6082         static const struct ephy_info e_info_8168g_2[] = {
6083                 { 0x00, 0x0000, 0x0008 },
6084                 { 0x0c, 0x3df0, 0x0200 },
6085                 { 0x19, 0xffff, 0xfc00 },
6086                 { 0x1e, 0xffff, 0x20eb }
6087         };
6088
6089         rtl_hw_start_8168g(tp);
6090
6091         /* disable aspm and clock request before access ephy */
6092         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6093         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6094         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
6095 }
6096
6097 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
6098 {
6099         void __iomem *ioaddr = tp->mmio_addr;
6100         static const struct ephy_info e_info_8411_2[] = {
6101                 { 0x00, 0x0000, 0x0008 },
6102                 { 0x0c, 0x3df0, 0x0200 },
6103                 { 0x0f, 0xffff, 0x5200 },
6104                 { 0x19, 0x0020, 0x0000 },
6105                 { 0x1e, 0x0000, 0x2000 }
6106         };
6107
6108         rtl_hw_start_8168g(tp);
6109
6110         /* disable aspm and clock request before access ephy */
6111         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6112         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6113         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
6114 }
6115
6116 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
6117 {
6118         void __iomem *ioaddr = tp->mmio_addr;
6119         struct pci_dev *pdev = tp->pci_dev;
6120         int rg_saw_cnt;
6121         u32 data;
6122         static const struct ephy_info e_info_8168h_1[] = {
6123                 { 0x1e, 0x0800, 0x0001 },
6124                 { 0x1d, 0x0000, 0x0800 },
6125                 { 0x05, 0xffff, 0x2089 },
6126                 { 0x06, 0xffff, 0x5881 },
6127                 { 0x04, 0xffff, 0x154a },
6128                 { 0x01, 0xffff, 0x068b }
6129         };
6130
6131         /* disable aspm and clock request before access ephy */
6132         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6133         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6134         rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6135
6136         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6137
6138         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6139         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6140         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6141         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6142
6143         rtl_csi_access_enable_1(tp);
6144
6145         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6146
6147         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6148         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6149
6150         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6151
6152         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6153
6154         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6155
6156         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6157         RTL_W8(MaxTxPacketSize, EarlySize);
6158
6159         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6160         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6161
6162         /* Adjust EEE LED frequency */
6163         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6164
6165         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6166         RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6167
6168         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6169
6170         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6171
6172         rtl_pcie_state_l2l3_enable(tp, false);
6173
6174         rtl_writephy(tp, 0x1f, 0x0c42);
6175         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6176         rtl_writephy(tp, 0x1f, 0x0000);
6177         if (rg_saw_cnt > 0) {
6178                 u16 sw_cnt_1ms_ini;
6179
6180                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6181                 sw_cnt_1ms_ini &= 0x0fff;
6182                 data = r8168_mac_ocp_read(tp, 0xd412);
6183                 data &= ~0x0fff;
6184                 data |= sw_cnt_1ms_ini;
6185                 r8168_mac_ocp_write(tp, 0xd412, data);
6186         }
6187
6188         data = r8168_mac_ocp_read(tp, 0xe056);
6189         data &= ~0xf0;
6190         data |= 0x70;
6191         r8168_mac_ocp_write(tp, 0xe056, data);
6192
6193         data = r8168_mac_ocp_read(tp, 0xe052);
6194         data &= ~0x6000;
6195         data |= 0x8008;
6196         r8168_mac_ocp_write(tp, 0xe052, data);
6197
6198         data = r8168_mac_ocp_read(tp, 0xe0d6);
6199         data &= ~0x01ff;
6200         data |= 0x017f;
6201         r8168_mac_ocp_write(tp, 0xe0d6, data);
6202
6203         data = r8168_mac_ocp_read(tp, 0xd420);
6204         data &= ~0x0fff;
6205         data |= 0x047f;
6206         r8168_mac_ocp_write(tp, 0xd420, data);
6207
6208         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6209         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6210         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6211         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6212 }
6213
6214 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6215 {
6216         void __iomem *ioaddr = tp->mmio_addr;
6217         struct pci_dev *pdev = tp->pci_dev;
6218
6219         rtl8168ep_stop_cmac(tp);
6220
6221         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6222
6223         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6224         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6225         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6226         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6227
6228         rtl_csi_access_enable_1(tp);
6229
6230         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6231
6232         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6233         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6234
6235         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6236
6237         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6238
6239         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6240         RTL_W8(MaxTxPacketSize, EarlySize);
6241
6242         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6243         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6244
6245         /* Adjust EEE LED frequency */
6246         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6247
6248         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6249
6250         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6251
6252         rtl_pcie_state_l2l3_enable(tp, false);
6253 }
6254
6255 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6256 {
6257         void __iomem *ioaddr = tp->mmio_addr;
6258         static const struct ephy_info e_info_8168ep_1[] = {
6259                 { 0x00, 0xffff, 0x10ab },
6260                 { 0x06, 0xffff, 0xf030 },
6261                 { 0x08, 0xffff, 0x2006 },
6262                 { 0x0d, 0xffff, 0x1666 },
6263                 { 0x0c, 0x3ff0, 0x0000 }
6264         };
6265
6266         /* disable aspm and clock request before access ephy */
6267         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6268         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6269         rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6270
6271         rtl_hw_start_8168ep(tp);
6272 }
6273
6274 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6275 {
6276         void __iomem *ioaddr = tp->mmio_addr;
6277         static const struct ephy_info e_info_8168ep_2[] = {
6278                 { 0x00, 0xffff, 0x10a3 },
6279                 { 0x19, 0xffff, 0xfc00 },
6280                 { 0x1e, 0xffff, 0x20ea }
6281         };
6282
6283         /* disable aspm and clock request before access ephy */
6284         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6285         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6286         rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6287
6288         rtl_hw_start_8168ep(tp);
6289
6290         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6291         RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6292 }
6293
6294 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6295 {
6296         void __iomem *ioaddr = tp->mmio_addr;
6297         u32 data;
6298         static const struct ephy_info e_info_8168ep_3[] = {
6299                 { 0x00, 0xffff, 0x10a3 },
6300                 { 0x19, 0xffff, 0x7c00 },
6301                 { 0x1e, 0xffff, 0x20eb },
6302                 { 0x0d, 0xffff, 0x1666 }
6303         };
6304
6305         /* disable aspm and clock request before access ephy */
6306         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6307         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6308         rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6309
6310         rtl_hw_start_8168ep(tp);
6311
6312         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6313         RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6314
6315         data = r8168_mac_ocp_read(tp, 0xd3e2);
6316         data &= 0xf000;
6317         data |= 0x0271;
6318         r8168_mac_ocp_write(tp, 0xd3e2, data);
6319
6320         data = r8168_mac_ocp_read(tp, 0xd3e4);
6321         data &= 0xff00;
6322         r8168_mac_ocp_write(tp, 0xd3e4, data);
6323
6324         data = r8168_mac_ocp_read(tp, 0xe860);
6325         data |= 0x0080;
6326         r8168_mac_ocp_write(tp, 0xe860, data);
6327 }
6328
6329 static void rtl_hw_start_8168(struct net_device *dev)
6330 {
6331         struct rtl8169_private *tp = netdev_priv(dev);
6332         void __iomem *ioaddr = tp->mmio_addr;
6333
6334         RTL_W8(Cfg9346, Cfg9346_Unlock);
6335
6336         RTL_W8(MaxTxPacketSize, TxPacketMax);
6337
6338         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6339
6340         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
6341
6342         RTL_W16(CPlusCmd, tp->cp_cmd);
6343
6344         RTL_W16(IntrMitigate, 0x5151);
6345
6346         /* Work around for RxFIFO overflow. */
6347         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
6348                 tp->event_slow |= RxFIFOOver | PCSTimeout;
6349                 tp->event_slow &= ~RxOverflow;
6350         }
6351
6352         rtl_set_rx_tx_desc_registers(tp, ioaddr);
6353
6354         rtl_set_rx_tx_config_registers(tp);
6355
6356         RTL_R8(IntrMask);
6357
6358         switch (tp->mac_version) {
6359         case RTL_GIGA_MAC_VER_11:
6360                 rtl_hw_start_8168bb(tp);
6361                 break;
6362
6363         case RTL_GIGA_MAC_VER_12:
6364         case RTL_GIGA_MAC_VER_17:
6365                 rtl_hw_start_8168bef(tp);
6366                 break;
6367
6368         case RTL_GIGA_MAC_VER_18:
6369                 rtl_hw_start_8168cp_1(tp);
6370                 break;
6371
6372         case RTL_GIGA_MAC_VER_19:
6373                 rtl_hw_start_8168c_1(tp);
6374                 break;
6375
6376         case RTL_GIGA_MAC_VER_20:
6377                 rtl_hw_start_8168c_2(tp);
6378                 break;
6379
6380         case RTL_GIGA_MAC_VER_21:
6381                 rtl_hw_start_8168c_3(tp);
6382                 break;
6383
6384         case RTL_GIGA_MAC_VER_22:
6385                 rtl_hw_start_8168c_4(tp);
6386                 break;
6387
6388         case RTL_GIGA_MAC_VER_23:
6389                 rtl_hw_start_8168cp_2(tp);
6390                 break;
6391
6392         case RTL_GIGA_MAC_VER_24:
6393                 rtl_hw_start_8168cp_3(tp);
6394                 break;
6395
6396         case RTL_GIGA_MAC_VER_25:
6397         case RTL_GIGA_MAC_VER_26:
6398         case RTL_GIGA_MAC_VER_27:
6399                 rtl_hw_start_8168d(tp);
6400                 break;
6401
6402         case RTL_GIGA_MAC_VER_28:
6403                 rtl_hw_start_8168d_4(tp);
6404                 break;
6405
6406         case RTL_GIGA_MAC_VER_31:
6407                 rtl_hw_start_8168dp(tp);
6408                 break;
6409
6410         case RTL_GIGA_MAC_VER_32:
6411         case RTL_GIGA_MAC_VER_33:
6412                 rtl_hw_start_8168e_1(tp);
6413                 break;
6414         case RTL_GIGA_MAC_VER_34:
6415                 rtl_hw_start_8168e_2(tp);
6416                 break;
6417
6418         case RTL_GIGA_MAC_VER_35:
6419         case RTL_GIGA_MAC_VER_36:
6420                 rtl_hw_start_8168f_1(tp);
6421                 break;
6422
6423         case RTL_GIGA_MAC_VER_38:
6424                 rtl_hw_start_8411(tp);
6425                 break;
6426
6427         case RTL_GIGA_MAC_VER_40:
6428         case RTL_GIGA_MAC_VER_41:
6429                 rtl_hw_start_8168g_1(tp);
6430                 break;
6431         case RTL_GIGA_MAC_VER_42:
6432                 rtl_hw_start_8168g_2(tp);
6433                 break;
6434
6435         case RTL_GIGA_MAC_VER_44:
6436                 rtl_hw_start_8411_2(tp);
6437                 break;
6438
6439         case RTL_GIGA_MAC_VER_45:
6440         case RTL_GIGA_MAC_VER_46:
6441                 rtl_hw_start_8168h_1(tp);
6442                 break;
6443
6444         case RTL_GIGA_MAC_VER_49:
6445                 rtl_hw_start_8168ep_1(tp);
6446                 break;
6447
6448         case RTL_GIGA_MAC_VER_50:
6449                 rtl_hw_start_8168ep_2(tp);
6450                 break;
6451
6452         case RTL_GIGA_MAC_VER_51:
6453                 rtl_hw_start_8168ep_3(tp);
6454                 break;
6455
6456         default:
6457                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6458                         dev->name, tp->mac_version);
6459                 break;
6460         }
6461
6462         RTL_W8(Cfg9346, Cfg9346_Lock);
6463
6464         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6465
6466         rtl_set_rx_mode(dev);
6467
6468         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6469 }
6470
6471 #define R810X_CPCMD_QUIRK_MASK (\
6472         EnableBist | \
6473         Mac_dbgo_oe | \
6474         Force_half_dup | \
6475         Force_rxflow_en | \
6476         Force_txflow_en | \
6477         Cxpl_dbg_sel | \
6478         ASF | \
6479         PktCntrDisable | \
6480         Mac_dbgo_sel)
6481
6482 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
6483 {
6484         void __iomem *ioaddr = tp->mmio_addr;
6485         struct pci_dev *pdev = tp->pci_dev;
6486         static const struct ephy_info e_info_8102e_1[] = {
6487                 { 0x01, 0, 0x6e65 },
6488                 { 0x02, 0, 0x091f },
6489                 { 0x03, 0, 0xc2f9 },
6490                 { 0x06, 0, 0xafb5 },
6491                 { 0x07, 0, 0x0e00 },
6492                 { 0x19, 0, 0xec80 },
6493                 { 0x01, 0, 0x2e65 },
6494                 { 0x01, 0, 0x6e65 }
6495         };
6496         u8 cfg1;
6497
6498         rtl_csi_access_enable_2(tp);
6499
6500         RTL_W8(DBG_REG, FIX_NAK_1);
6501
6502         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6503
6504         RTL_W8(Config1,
6505                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6506         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6507
6508         cfg1 = RTL_R8(Config1);
6509         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6510                 RTL_W8(Config1, cfg1 & ~LEDS0);
6511
6512         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
6513 }
6514
6515 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
6516 {
6517         void __iomem *ioaddr = tp->mmio_addr;
6518         struct pci_dev *pdev = tp->pci_dev;
6519
6520         rtl_csi_access_enable_2(tp);
6521
6522         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6523
6524         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
6525         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6526 }
6527
6528 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
6529 {
6530         rtl_hw_start_8102e_2(tp);
6531
6532         rtl_ephy_write(tp, 0x03, 0xc2f9);
6533 }
6534
6535 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
6536 {
6537         void __iomem *ioaddr = tp->mmio_addr;
6538         static const struct ephy_info e_info_8105e_1[] = {
6539                 { 0x07, 0, 0x4000 },
6540                 { 0x19, 0, 0x0200 },
6541                 { 0x19, 0, 0x0020 },
6542                 { 0x1e, 0, 0x2000 },
6543                 { 0x03, 0, 0x0001 },
6544                 { 0x19, 0, 0x0100 },
6545                 { 0x19, 0, 0x0004 },
6546                 { 0x0a, 0, 0x0020 }
6547         };
6548
6549         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6550         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6551
6552         /* Disable Early Tally Counter */
6553         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
6554
6555         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6556         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
6557
6558         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
6559
6560         rtl_pcie_state_l2l3_enable(tp, false);
6561 }
6562
6563 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
6564 {
6565         rtl_hw_start_8105e_1(tp);
6566         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
6567 }
6568
6569 static void rtl_hw_start_8402(struct rtl8169_private *tp)
6570 {
6571         void __iomem *ioaddr = tp->mmio_addr;
6572         static const struct ephy_info e_info_8402[] = {
6573                 { 0x19, 0xffff, 0xff64 },
6574                 { 0x1e, 0, 0x4000 }
6575         };
6576
6577         rtl_csi_access_enable_2(tp);
6578
6579         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6580         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6581
6582         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6583         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6584
6585         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
6586
6587         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6588
6589         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6590         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
6591         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6592         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6593         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6594         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6595         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
6596
6597         rtl_pcie_state_l2l3_enable(tp, false);
6598 }
6599
6600 static void rtl_hw_start_8106(struct rtl8169_private *tp)
6601 {
6602         void __iomem *ioaddr = tp->mmio_addr;
6603
6604         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6605         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6606
6607         RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
6608         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6609         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6610
6611         rtl_pcie_state_l2l3_enable(tp, false);
6612 }
6613
6614 static void rtl_hw_start_8101(struct net_device *dev)
6615 {
6616         struct rtl8169_private *tp = netdev_priv(dev);
6617         void __iomem *ioaddr = tp->mmio_addr;
6618         struct pci_dev *pdev = tp->pci_dev;
6619
6620         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6621                 tp->event_slow &= ~RxFIFOOver;
6622
6623         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
6624             tp->mac_version == RTL_GIGA_MAC_VER_16)
6625                 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6626                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
6627
6628         RTL_W8(Cfg9346, Cfg9346_Unlock);
6629
6630         RTL_W8(MaxTxPacketSize, TxPacketMax);
6631
6632         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6633
6634         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6635         RTL_W16(CPlusCmd, tp->cp_cmd);
6636
6637         rtl_set_rx_tx_desc_registers(tp, ioaddr);
6638
6639         rtl_set_rx_tx_config_registers(tp);
6640
6641         switch (tp->mac_version) {
6642         case RTL_GIGA_MAC_VER_07:
6643                 rtl_hw_start_8102e_1(tp);
6644                 break;
6645
6646         case RTL_GIGA_MAC_VER_08:
6647                 rtl_hw_start_8102e_3(tp);
6648                 break;
6649
6650         case RTL_GIGA_MAC_VER_09:
6651                 rtl_hw_start_8102e_2(tp);
6652                 break;
6653
6654         case RTL_GIGA_MAC_VER_29:
6655                 rtl_hw_start_8105e_1(tp);
6656                 break;
6657         case RTL_GIGA_MAC_VER_30:
6658                 rtl_hw_start_8105e_2(tp);
6659                 break;
6660
6661         case RTL_GIGA_MAC_VER_37:
6662                 rtl_hw_start_8402(tp);
6663                 break;
6664
6665         case RTL_GIGA_MAC_VER_39:
6666                 rtl_hw_start_8106(tp);
6667                 break;
6668         case RTL_GIGA_MAC_VER_43:
6669                 rtl_hw_start_8168g_2(tp);
6670                 break;
6671         case RTL_GIGA_MAC_VER_47:
6672         case RTL_GIGA_MAC_VER_48:
6673                 rtl_hw_start_8168h_1(tp);
6674                 break;
6675         }
6676
6677         RTL_W8(Cfg9346, Cfg9346_Lock);
6678
6679         RTL_W16(IntrMitigate, 0x0000);
6680
6681         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6682
6683         rtl_set_rx_mode(dev);
6684
6685         RTL_R8(IntrMask);
6686
6687         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6688 }
6689
6690 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6691 {
6692         struct rtl8169_private *tp = netdev_priv(dev);
6693
6694         if (new_mtu > ETH_DATA_LEN)
6695                 rtl_hw_jumbo_enable(tp);
6696         else
6697                 rtl_hw_jumbo_disable(tp);
6698
6699         dev->mtu = new_mtu;
6700         netdev_update_features(dev);
6701
6702         return 0;
6703 }
6704
6705 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6706 {
6707         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
6708         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6709 }
6710
6711 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6712                                      void **data_buff, struct RxDesc *desc)
6713 {
6714         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
6715                          DMA_FROM_DEVICE);
6716
6717         kfree(*data_buff);
6718         *data_buff = NULL;
6719         rtl8169_make_unusable_by_asic(desc);
6720 }
6721
6722 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6723 {
6724         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6725
6726         /* Force memory writes to complete before releasing descriptor */
6727         dma_wmb();
6728
6729         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6730 }
6731
6732 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6733                                        u32 rx_buf_sz)
6734 {
6735         desc->addr = cpu_to_le64(mapping);
6736         rtl8169_mark_to_asic(desc, rx_buf_sz);
6737 }
6738
6739 static inline void *rtl8169_align(void *data)
6740 {
6741         return (void *)ALIGN((long)data, 16);
6742 }
6743
6744 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6745                                              struct RxDesc *desc)
6746 {
6747         void *data;
6748         dma_addr_t mapping;
6749         struct device *d = &tp->pci_dev->dev;
6750         struct net_device *dev = tp->dev;
6751         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
6752
6753         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6754         if (!data)
6755                 return NULL;
6756
6757         if (rtl8169_align(data) != data) {
6758                 kfree(data);
6759                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6760                 if (!data)
6761                         return NULL;
6762         }
6763
6764         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
6765                                  DMA_FROM_DEVICE);
6766         if (unlikely(dma_mapping_error(d, mapping))) {
6767                 if (net_ratelimit())
6768                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
6769                 goto err_out;
6770         }
6771
6772         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6773         return data;
6774
6775 err_out:
6776         kfree(data);
6777         return NULL;
6778 }
6779
6780 static void rtl8169_rx_clear(struct rtl8169_private *tp)
6781 {
6782         unsigned int i;
6783
6784         for (i = 0; i < NUM_RX_DESC; i++) {
6785                 if (tp->Rx_databuff[i]) {
6786                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
6787                                             tp->RxDescArray + i);
6788                 }
6789         }
6790 }
6791
6792 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
6793 {
6794         desc->opts1 |= cpu_to_le32(RingEnd);
6795 }
6796
6797 static int rtl8169_rx_fill(struct rtl8169_private *tp)
6798 {
6799         unsigned int i;
6800
6801         for (i = 0; i < NUM_RX_DESC; i++) {
6802                 void *data;
6803
6804                 if (tp->Rx_databuff[i])
6805                         continue;
6806
6807                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6808                 if (!data) {
6809                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
6810                         goto err_out;
6811                 }
6812                 tp->Rx_databuff[i] = data;
6813         }
6814
6815         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6816         return 0;
6817
6818 err_out:
6819         rtl8169_rx_clear(tp);
6820         return -ENOMEM;
6821 }
6822
6823 static int rtl8169_init_ring(struct net_device *dev)
6824 {
6825         struct rtl8169_private *tp = netdev_priv(dev);
6826
6827         rtl8169_init_ring_indexes(tp);
6828
6829         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6830         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
6831
6832         return rtl8169_rx_fill(tp);
6833 }
6834
6835 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
6836                                  struct TxDesc *desc)
6837 {
6838         unsigned int len = tx_skb->len;
6839
6840         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6841
6842         desc->opts1 = 0x00;
6843         desc->opts2 = 0x00;
6844         desc->addr = 0x00;
6845         tx_skb->len = 0;
6846 }
6847
6848 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6849                                    unsigned int n)
6850 {
6851         unsigned int i;
6852
6853         for (i = 0; i < n; i++) {
6854                 unsigned int entry = (start + i) % NUM_TX_DESC;
6855                 struct ring_info *tx_skb = tp->tx_skb + entry;
6856                 unsigned int len = tx_skb->len;
6857
6858                 if (len) {
6859                         struct sk_buff *skb = tx_skb->skb;
6860
6861                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6862                                              tp->TxDescArray + entry);
6863                         if (skb) {
6864                                 tp->dev->stats.tx_dropped++;
6865                                 dev_kfree_skb_any(skb);
6866                                 tx_skb->skb = NULL;
6867                         }
6868                 }
6869         }
6870 }
6871
6872 static void rtl8169_tx_clear(struct rtl8169_private *tp)
6873 {
6874         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
6875         tp->cur_tx = tp->dirty_tx = 0;
6876 }
6877
6878 static void rtl_reset_work(struct rtl8169_private *tp)
6879 {
6880         struct net_device *dev = tp->dev;
6881         int i;
6882
6883         napi_disable(&tp->napi);
6884         netif_stop_queue(dev);
6885         synchronize_sched();
6886
6887         rtl8169_hw_reset(tp);
6888
6889         for (i = 0; i < NUM_RX_DESC; i++)
6890                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
6891
6892         rtl8169_tx_clear(tp);
6893         rtl8169_init_ring_indexes(tp);
6894
6895         napi_enable(&tp->napi);
6896         rtl_hw_start(dev);
6897         netif_wake_queue(dev);
6898         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
6899 }
6900
6901 static void rtl8169_tx_timeout(struct net_device *dev)
6902 {
6903         struct rtl8169_private *tp = netdev_priv(dev);
6904
6905         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6906 }
6907
6908 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
6909                               u32 *opts)
6910 {
6911         struct skb_shared_info *info = skb_shinfo(skb);
6912         unsigned int cur_frag, entry;
6913         struct TxDesc *uninitialized_var(txd);
6914         struct device *d = &tp->pci_dev->dev;
6915
6916         entry = tp->cur_tx;
6917         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
6918                 const skb_frag_t *frag = info->frags + cur_frag;
6919                 dma_addr_t mapping;
6920                 u32 status, len;
6921                 void *addr;
6922
6923                 entry = (entry + 1) % NUM_TX_DESC;
6924
6925                 txd = tp->TxDescArray + entry;
6926                 len = skb_frag_size(frag);
6927                 addr = skb_frag_address(frag);
6928                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
6929                 if (unlikely(dma_mapping_error(d, mapping))) {
6930                         if (net_ratelimit())
6931                                 netif_err(tp, drv, tp->dev,
6932                                           "Failed to map TX fragments DMA!\n");
6933                         goto err_out;
6934                 }
6935
6936                 /* Anti gcc 2.95.3 bugware (sic) */
6937                 status = opts[0] | len |
6938                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
6939
6940                 txd->opts1 = cpu_to_le32(status);
6941                 txd->opts2 = cpu_to_le32(opts[1]);
6942                 txd->addr = cpu_to_le64(mapping);
6943
6944                 tp->tx_skb[entry].len = len;
6945         }
6946
6947         if (cur_frag) {
6948                 tp->tx_skb[entry].skb = skb;
6949                 txd->opts1 |= cpu_to_le32(LastFrag);
6950         }
6951
6952         return cur_frag;
6953
6954 err_out:
6955         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6956         return -EIO;
6957 }
6958
6959 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6960 {
6961         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6962 }
6963
6964 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6965                                       struct net_device *dev);
6966 /* r8169_csum_workaround()
6967  * The hw limites the value the transport offset. When the offset is out of the
6968  * range, calculate the checksum by sw.
6969  */
6970 static void r8169_csum_workaround(struct rtl8169_private *tp,
6971                                   struct sk_buff *skb)
6972 {
6973         if (skb_shinfo(skb)->gso_size) {
6974                 netdev_features_t features = tp->dev->features;
6975                 struct sk_buff *segs, *nskb;
6976
6977                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6978                 segs = skb_gso_segment(skb, features);
6979                 if (IS_ERR(segs) || !segs)
6980                         goto drop;
6981
6982                 do {
6983                         nskb = segs;
6984                         segs = segs->next;
6985                         nskb->next = NULL;
6986                         rtl8169_start_xmit(nskb, tp->dev);
6987                 } while (segs);
6988
6989                 dev_consume_skb_any(skb);
6990         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6991                 if (skb_checksum_help(skb) < 0)
6992                         goto drop;
6993
6994                 rtl8169_start_xmit(skb, tp->dev);
6995         } else {
6996                 struct net_device_stats *stats;
6997
6998 drop:
6999                 stats = &tp->dev->stats;
7000                 stats->tx_dropped++;
7001                 dev_kfree_skb_any(skb);
7002         }
7003 }
7004
7005 /* msdn_giant_send_check()
7006  * According to the document of microsoft, the TCP Pseudo Header excludes the
7007  * packet length for IPv6 TCP large packets.
7008  */
7009 static int msdn_giant_send_check(struct sk_buff *skb)
7010 {
7011         const struct ipv6hdr *ipv6h;
7012         struct tcphdr *th;
7013         int ret;
7014
7015         ret = skb_cow_head(skb, 0);
7016         if (ret)
7017                 return ret;
7018
7019         ipv6h = ipv6_hdr(skb);
7020         th = tcp_hdr(skb);
7021
7022         th->check = 0;
7023         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
7024
7025         return ret;
7026 }
7027
7028 static inline __be16 get_protocol(struct sk_buff *skb)
7029 {
7030         __be16 protocol;
7031
7032         if (skb->protocol == htons(ETH_P_8021Q))
7033                 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
7034         else
7035                 protocol = skb->protocol;
7036
7037         return protocol;
7038 }
7039
7040 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
7041                                 struct sk_buff *skb, u32 *opts)
7042 {
7043         u32 mss = skb_shinfo(skb)->gso_size;
7044
7045         if (mss) {
7046                 opts[0] |= TD_LSO;
7047                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
7048         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7049                 const struct iphdr *ip = ip_hdr(skb);
7050
7051                 if (ip->protocol == IPPROTO_TCP)
7052                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
7053                 else if (ip->protocol == IPPROTO_UDP)
7054                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
7055                 else
7056                         WARN_ON_ONCE(1);
7057         }
7058
7059         return true;
7060 }
7061
7062 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
7063                                 struct sk_buff *skb, u32 *opts)
7064 {
7065         u32 transport_offset = (u32)skb_transport_offset(skb);
7066         u32 mss = skb_shinfo(skb)->gso_size;
7067
7068         if (mss) {
7069                 if (transport_offset > GTTCPHO_MAX) {
7070                         netif_warn(tp, tx_err, tp->dev,
7071                                    "Invalid transport offset 0x%x for TSO\n",
7072                                    transport_offset);
7073                         return false;
7074                 }
7075
7076                 switch (get_protocol(skb)) {
7077                 case htons(ETH_P_IP):
7078                         opts[0] |= TD1_GTSENV4;
7079                         break;
7080
7081                 case htons(ETH_P_IPV6):
7082                         if (msdn_giant_send_check(skb))
7083                                 return false;
7084
7085                         opts[0] |= TD1_GTSENV6;
7086                         break;
7087
7088                 default:
7089                         WARN_ON_ONCE(1);
7090                         break;
7091                 }
7092
7093                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
7094                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
7095         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7096                 u8 ip_protocol;
7097
7098                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7099                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
7100
7101                 if (transport_offset > TCPHO_MAX) {
7102                         netif_warn(tp, tx_err, tp->dev,
7103                                    "Invalid transport offset 0x%x\n",
7104                                    transport_offset);
7105                         return false;
7106                 }
7107
7108                 switch (get_protocol(skb)) {
7109                 case htons(ETH_P_IP):
7110                         opts[1] |= TD1_IPv4_CS;
7111                         ip_protocol = ip_hdr(skb)->protocol;
7112                         break;
7113
7114                 case htons(ETH_P_IPV6):
7115                         opts[1] |= TD1_IPv6_CS;
7116                         ip_protocol = ipv6_hdr(skb)->nexthdr;
7117                         break;
7118
7119                 default:
7120                         ip_protocol = IPPROTO_RAW;
7121                         break;
7122                 }
7123
7124                 if (ip_protocol == IPPROTO_TCP)
7125                         opts[1] |= TD1_TCP_CS;
7126                 else if (ip_protocol == IPPROTO_UDP)
7127                         opts[1] |= TD1_UDP_CS;
7128                 else
7129                         WARN_ON_ONCE(1);
7130
7131                 opts[1] |= transport_offset << TCPHO_SHIFT;
7132         } else {
7133                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7134                         return !eth_skb_pad(skb);
7135         }
7136
7137         return true;
7138 }
7139
7140 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7141                                       struct net_device *dev)
7142 {
7143         struct rtl8169_private *tp = netdev_priv(dev);
7144         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
7145         struct TxDesc *txd = tp->TxDescArray + entry;
7146         void __iomem *ioaddr = tp->mmio_addr;
7147         struct device *d = &tp->pci_dev->dev;
7148         dma_addr_t mapping;
7149         u32 status, len;
7150         u32 opts[2];
7151         int frags;
7152
7153         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
7154                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
7155                 goto err_stop_0;
7156         }
7157
7158         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
7159                 goto err_stop_0;
7160
7161         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7162         opts[0] = DescOwn;
7163
7164         if (!tp->tso_csum(tp, skb, opts)) {
7165                 r8169_csum_workaround(tp, skb);
7166                 return NETDEV_TX_OK;
7167         }
7168
7169         len = skb_headlen(skb);
7170         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
7171         if (unlikely(dma_mapping_error(d, mapping))) {
7172                 if (net_ratelimit())
7173                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
7174                 goto err_dma_0;
7175         }
7176
7177         tp->tx_skb[entry].len = len;
7178         txd->addr = cpu_to_le64(mapping);
7179
7180         frags = rtl8169_xmit_frags(tp, skb, opts);
7181         if (frags < 0)
7182                 goto err_dma_1;
7183         else if (frags)
7184                 opts[0] |= FirstFrag;
7185         else {
7186                 opts[0] |= FirstFrag | LastFrag;
7187                 tp->tx_skb[entry].skb = skb;
7188         }
7189
7190         txd->opts2 = cpu_to_le32(opts[1]);
7191
7192         skb_tx_timestamp(skb);
7193
7194         /* Force memory writes to complete before releasing descriptor */
7195         dma_wmb();
7196
7197         /* Anti gcc 2.95.3 bugware (sic) */
7198         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
7199         txd->opts1 = cpu_to_le32(status);
7200
7201         /* Force all memory writes to complete before notifying device */
7202         wmb();
7203
7204         tp->cur_tx += frags + 1;
7205
7206         RTL_W8(TxPoll, NPQ);
7207
7208         mmiowb();
7209
7210         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7211                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7212                  * not miss a ring update when it notices a stopped queue.
7213                  */
7214                 smp_wmb();
7215                 netif_stop_queue(dev);
7216                 /* Sync with rtl_tx:
7217                  * - publish queue status and cur_tx ring index (write barrier)
7218                  * - refresh dirty_tx ring index (read barrier).
7219                  * May the current thread have a pessimistic view of the ring
7220                  * status and forget to wake up queue, a racing rtl_tx thread
7221                  * can't.
7222                  */
7223                 smp_mb();
7224                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
7225                         netif_wake_queue(dev);
7226         }
7227
7228         return NETDEV_TX_OK;
7229
7230 err_dma_1:
7231         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
7232 err_dma_0:
7233         dev_kfree_skb_any(skb);
7234         dev->stats.tx_dropped++;
7235         return NETDEV_TX_OK;
7236
7237 err_stop_0:
7238         netif_stop_queue(dev);
7239         dev->stats.tx_dropped++;
7240         return NETDEV_TX_BUSY;
7241 }
7242
7243 static void rtl8169_pcierr_interrupt(struct net_device *dev)
7244 {
7245         struct rtl8169_private *tp = netdev_priv(dev);
7246         struct pci_dev *pdev = tp->pci_dev;
7247         u16 pci_status, pci_cmd;
7248
7249         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7250         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7251
7252         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7253                   pci_cmd, pci_status);
7254
7255         /*
7256          * The recovery sequence below admits a very elaborated explanation:
7257          * - it seems to work;
7258          * - I did not see what else could be done;
7259          * - it makes iop3xx happy.
7260          *
7261          * Feel free to adjust to your needs.
7262          */
7263         if (pdev->broken_parity_status)
7264                 pci_cmd &= ~PCI_COMMAND_PARITY;
7265         else
7266                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7267
7268         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
7269
7270         pci_write_config_word(pdev, PCI_STATUS,
7271                 pci_status & (PCI_STATUS_DETECTED_PARITY |
7272                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7273                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7274
7275         /* The infamous DAC f*ckup only happens at boot time */
7276         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
7277                 void __iomem *ioaddr = tp->mmio_addr;
7278
7279                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
7280                 tp->cp_cmd &= ~PCIDAC;
7281                 RTL_W16(CPlusCmd, tp->cp_cmd);
7282                 dev->features &= ~NETIF_F_HIGHDMA;
7283         }
7284
7285         rtl8169_hw_reset(tp);
7286
7287         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7288 }
7289
7290 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
7291 {
7292         unsigned int dirty_tx, tx_left;
7293
7294         dirty_tx = tp->dirty_tx;
7295         smp_rmb();
7296         tx_left = tp->cur_tx - dirty_tx;
7297
7298         while (tx_left > 0) {
7299                 unsigned int entry = dirty_tx % NUM_TX_DESC;
7300                 struct ring_info *tx_skb = tp->tx_skb + entry;
7301                 u32 status;
7302
7303                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7304                 if (status & DescOwn)
7305                         break;
7306
7307                 /* This barrier is needed to keep us from reading
7308                  * any other fields out of the Tx descriptor until
7309                  * we know the status of DescOwn
7310                  */
7311                 dma_rmb();
7312
7313                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7314                                      tp->TxDescArray + entry);
7315                 if (status & LastFrag) {
7316                         u64_stats_update_begin(&tp->tx_stats.syncp);
7317                         tp->tx_stats.packets++;
7318                         tp->tx_stats.bytes += tx_skb->skb->len;
7319                         u64_stats_update_end(&tp->tx_stats.syncp);
7320                         dev_kfree_skb_any(tx_skb->skb);
7321                         tx_skb->skb = NULL;
7322                 }
7323                 dirty_tx++;
7324                 tx_left--;
7325         }
7326
7327         if (tp->dirty_tx != dirty_tx) {
7328                 tp->dirty_tx = dirty_tx;
7329                 /* Sync with rtl8169_start_xmit:
7330                  * - publish dirty_tx ring index (write barrier)
7331                  * - refresh cur_tx ring index and queue status (read barrier)
7332                  * May the current thread miss the stopped queue condition,
7333                  * a racing xmit thread can only have a right view of the
7334                  * ring status.
7335                  */
7336                 smp_mb();
7337                 if (netif_queue_stopped(dev) &&
7338                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7339                         netif_wake_queue(dev);
7340                 }
7341                 /*
7342                  * 8168 hack: TxPoll requests are lost when the Tx packets are
7343                  * too close. Let's kick an extra TxPoll request when a burst
7344                  * of start_xmit activity is detected (if it is not detected,
7345                  * it is slow enough). -- FR
7346                  */
7347                 if (tp->cur_tx != dirty_tx) {
7348                         void __iomem *ioaddr = tp->mmio_addr;
7349
7350                         RTL_W8(TxPoll, NPQ);
7351                 }
7352         }
7353 }
7354
7355 static inline int rtl8169_fragmented_frame(u32 status)
7356 {
7357         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7358 }
7359
7360 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
7361 {
7362         u32 status = opts1 & RxProtoMask;
7363
7364         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
7365             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
7366                 skb->ip_summed = CHECKSUM_UNNECESSARY;
7367         else
7368                 skb_checksum_none_assert(skb);
7369 }
7370
7371 static struct sk_buff *rtl8169_try_rx_copy(void *data,
7372                                            struct rtl8169_private *tp,
7373                                            int pkt_size,
7374                                            dma_addr_t addr)
7375 {
7376         struct sk_buff *skb;
7377         struct device *d = &tp->pci_dev->dev;
7378
7379         data = rtl8169_align(data);
7380         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
7381         prefetch(data);
7382         skb = napi_alloc_skb(&tp->napi, pkt_size);
7383         if (skb)
7384                 memcpy(skb->data, data, pkt_size);
7385         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7386
7387         return skb;
7388 }
7389
7390 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
7391 {
7392         unsigned int cur_rx, rx_left;
7393         unsigned int count;
7394
7395         cur_rx = tp->cur_rx;
7396
7397         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
7398                 unsigned int entry = cur_rx % NUM_RX_DESC;
7399                 struct RxDesc *desc = tp->RxDescArray + entry;
7400                 u32 status;
7401
7402                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
7403                 if (status & DescOwn)
7404                         break;
7405
7406                 /* This barrier is needed to keep us from reading
7407                  * any other fields out of the Rx descriptor until
7408                  * we know the status of DescOwn
7409                  */
7410                 dma_rmb();
7411
7412                 if (unlikely(status & RxRES)) {
7413                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7414                                    status);
7415                         dev->stats.rx_errors++;
7416                         if (status & (RxRWT | RxRUNT))
7417                                 dev->stats.rx_length_errors++;
7418                         if (status & RxCRC)
7419                                 dev->stats.rx_crc_errors++;
7420                         if (status & RxFOVF) {
7421                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7422                                 dev->stats.rx_fifo_errors++;
7423                         }
7424                         if ((status & (RxRUNT | RxCRC)) &&
7425                             !(status & (RxRWT | RxFOVF)) &&
7426                             (dev->features & NETIF_F_RXALL))
7427                                 goto process_pkt;
7428                 } else {
7429                         struct sk_buff *skb;
7430                         dma_addr_t addr;
7431                         int pkt_size;
7432
7433 process_pkt:
7434                         addr = le64_to_cpu(desc->addr);
7435                         if (likely(!(dev->features & NETIF_F_RXFCS)))
7436                                 pkt_size = (status & 0x00003fff) - 4;
7437                         else
7438                                 pkt_size = status & 0x00003fff;
7439
7440                         /*
7441                          * The driver does not support incoming fragmented
7442                          * frames. They are seen as a symptom of over-mtu
7443                          * sized frames.
7444                          */
7445                         if (unlikely(rtl8169_fragmented_frame(status))) {
7446                                 dev->stats.rx_dropped++;
7447                                 dev->stats.rx_length_errors++;
7448                                 goto release_descriptor;
7449                         }
7450
7451                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7452                                                   tp, pkt_size, addr);
7453                         if (!skb) {
7454                                 dev->stats.rx_dropped++;
7455                                 goto release_descriptor;
7456                         }
7457
7458                         rtl8169_rx_csum(skb, status);
7459                         skb_put(skb, pkt_size);
7460                         skb->protocol = eth_type_trans(skb, dev);
7461
7462                         rtl8169_rx_vlan_tag(desc, skb);
7463
7464                         if (skb->pkt_type == PACKET_MULTICAST)
7465                                 dev->stats.multicast++;
7466
7467                         napi_gro_receive(&tp->napi, skb);
7468
7469                         u64_stats_update_begin(&tp->rx_stats.syncp);
7470                         tp->rx_stats.packets++;
7471                         tp->rx_stats.bytes += pkt_size;
7472                         u64_stats_update_end(&tp->rx_stats.syncp);
7473                 }
7474 release_descriptor:
7475                 desc->opts2 = 0;
7476                 rtl8169_mark_to_asic(desc, rx_buf_sz);
7477         }
7478
7479         count = cur_rx - tp->cur_rx;
7480         tp->cur_rx = cur_rx;
7481
7482         return count;
7483 }
7484
7485 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
7486 {
7487         struct net_device *dev = dev_instance;
7488         struct rtl8169_private *tp = netdev_priv(dev);
7489         int handled = 0;
7490         u16 status;
7491
7492         status = rtl_get_events(tp);
7493         if (status && status != 0xffff) {
7494                 status &= RTL_EVENT_NAPI | tp->event_slow;
7495                 if (status) {
7496                         handled = 1;
7497
7498                         rtl_irq_disable(tp);
7499                         napi_schedule(&tp->napi);
7500                 }
7501         }
7502         return IRQ_RETVAL(handled);
7503 }
7504
7505 /*
7506  * Workqueue context.
7507  */
7508 static void rtl_slow_event_work(struct rtl8169_private *tp)
7509 {
7510         struct net_device *dev = tp->dev;
7511         u16 status;
7512
7513         status = rtl_get_events(tp) & tp->event_slow;
7514         rtl_ack_events(tp, status);
7515
7516         if (unlikely(status & RxFIFOOver)) {
7517                 switch (tp->mac_version) {
7518                 /* Work around for rx fifo overflow */
7519                 case RTL_GIGA_MAC_VER_11:
7520                         netif_stop_queue(dev);
7521                         /* XXX - Hack alert. See rtl_task(). */
7522                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
7523                 default:
7524                         break;
7525                 }
7526         }
7527
7528         if (unlikely(status & SYSErr))
7529                 rtl8169_pcierr_interrupt(dev);
7530
7531         if (status & LinkChg)
7532                 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
7533
7534         rtl_irq_enable_all(tp);
7535 }
7536
7537 static void rtl_task(struct work_struct *work)
7538 {
7539         static const struct {
7540                 int bitnr;
7541                 void (*action)(struct rtl8169_private *);
7542         } rtl_work[] = {
7543                 /* XXX - keep rtl_slow_event_work() as first element. */
7544                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
7545                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
7546                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
7547         };
7548         struct rtl8169_private *tp =
7549                 container_of(work, struct rtl8169_private, wk.work);
7550         struct net_device *dev = tp->dev;
7551         int i;
7552
7553         rtl_lock_work(tp);
7554
7555         if (!netif_running(dev) ||
7556             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
7557                 goto out_unlock;
7558
7559         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7560                 bool pending;
7561
7562                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
7563                 if (pending)
7564                         rtl_work[i].action(tp);
7565         }
7566
7567 out_unlock:
7568         rtl_unlock_work(tp);
7569 }
7570
7571 static int rtl8169_poll(struct napi_struct *napi, int budget)
7572 {
7573         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7574         struct net_device *dev = tp->dev;
7575         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7576         int work_done= 0;
7577         u16 status;
7578
7579         status = rtl_get_events(tp);
7580         rtl_ack_events(tp, status & ~tp->event_slow);
7581
7582         if (status & RTL_EVENT_NAPI_RX)
7583                 work_done = rtl_rx(dev, tp, (u32) budget);
7584
7585         if (status & RTL_EVENT_NAPI_TX)
7586                 rtl_tx(dev, tp);
7587
7588         if (status & tp->event_slow) {
7589                 enable_mask &= ~tp->event_slow;
7590
7591                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7592         }
7593
7594         if (work_done < budget) {
7595                 napi_complete_done(napi, work_done);
7596
7597                 rtl_irq_enable(tp, enable_mask);
7598                 mmiowb();
7599         }
7600
7601         return work_done;
7602 }
7603
7604 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7605 {
7606         struct rtl8169_private *tp = netdev_priv(dev);
7607
7608         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7609                 return;
7610
7611         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7612         RTL_W32(RxMissed, 0);
7613 }
7614
7615 static void rtl8169_down(struct net_device *dev)
7616 {
7617         struct rtl8169_private *tp = netdev_priv(dev);
7618         void __iomem *ioaddr = tp->mmio_addr;
7619
7620         del_timer_sync(&tp->timer);
7621
7622         napi_disable(&tp->napi);
7623         netif_stop_queue(dev);
7624
7625         rtl8169_hw_reset(tp);
7626         /*
7627          * At this point device interrupts can not be enabled in any function,
7628          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7629          * and napi is disabled (rtl8169_poll).
7630          */
7631         rtl8169_rx_missed(dev, ioaddr);
7632
7633         /* Give a racing hard_start_xmit a few cycles to complete. */
7634         synchronize_sched();
7635
7636         rtl8169_tx_clear(tp);
7637
7638         rtl8169_rx_clear(tp);
7639
7640         rtl_pll_power_down(tp);
7641 }
7642
7643 static int rtl8169_close(struct net_device *dev)
7644 {
7645         struct rtl8169_private *tp = netdev_priv(dev);
7646         struct pci_dev *pdev = tp->pci_dev;
7647
7648         pm_runtime_get_sync(&pdev->dev);
7649
7650         /* Update counters before going down */
7651         rtl8169_update_counters(dev);
7652
7653         rtl_lock_work(tp);
7654         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7655
7656         rtl8169_down(dev);
7657         rtl_unlock_work(tp);
7658
7659         cancel_work_sync(&tp->wk.work);
7660
7661         free_irq(pdev->irq, dev);
7662
7663         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7664                           tp->RxPhyAddr);
7665         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7666                           tp->TxPhyAddr);
7667         tp->TxDescArray = NULL;
7668         tp->RxDescArray = NULL;
7669
7670         pm_runtime_put_sync(&pdev->dev);
7671
7672         return 0;
7673 }
7674
7675 #ifdef CONFIG_NET_POLL_CONTROLLER
7676 static void rtl8169_netpoll(struct net_device *dev)
7677 {
7678         struct rtl8169_private *tp = netdev_priv(dev);
7679
7680         rtl8169_interrupt(tp->pci_dev->irq, dev);
7681 }
7682 #endif
7683
7684 static int rtl_open(struct net_device *dev)
7685 {
7686         struct rtl8169_private *tp = netdev_priv(dev);
7687         void __iomem *ioaddr = tp->mmio_addr;
7688         struct pci_dev *pdev = tp->pci_dev;
7689         int retval = -ENOMEM;
7690
7691         pm_runtime_get_sync(&pdev->dev);
7692
7693         /*
7694          * Rx and Tx descriptors needs 256 bytes alignment.
7695          * dma_alloc_coherent provides more.
7696          */
7697         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7698                                              &tp->TxPhyAddr, GFP_KERNEL);
7699         if (!tp->TxDescArray)
7700                 goto err_pm_runtime_put;
7701
7702         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7703                                              &tp->RxPhyAddr, GFP_KERNEL);
7704         if (!tp->RxDescArray)
7705                 goto err_free_tx_0;
7706
7707         retval = rtl8169_init_ring(dev);
7708         if (retval < 0)
7709                 goto err_free_rx_1;
7710
7711         INIT_WORK(&tp->wk.work, rtl_task);
7712
7713         smp_mb();
7714
7715         rtl_request_firmware(tp);
7716
7717         retval = request_irq(pdev->irq, rtl8169_interrupt,
7718                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7719                              dev->name, dev);
7720         if (retval < 0)
7721                 goto err_release_fw_2;
7722
7723         rtl_lock_work(tp);
7724
7725         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7726
7727         napi_enable(&tp->napi);
7728
7729         rtl8169_init_phy(dev, tp);
7730
7731         __rtl8169_set_features(dev, dev->features);
7732
7733         rtl_pll_power_up(tp);
7734
7735         rtl_hw_start(dev);
7736
7737         if (!rtl8169_init_counter_offsets(dev))
7738                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7739
7740         netif_start_queue(dev);
7741
7742         rtl_unlock_work(tp);
7743
7744         tp->saved_wolopts = 0;
7745         pm_runtime_put_noidle(&pdev->dev);
7746
7747         rtl8169_check_link_status(dev, tp, ioaddr);
7748 out:
7749         return retval;
7750
7751 err_release_fw_2:
7752         rtl_release_firmware(tp);
7753         rtl8169_rx_clear(tp);
7754 err_free_rx_1:
7755         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7756                           tp->RxPhyAddr);
7757         tp->RxDescArray = NULL;
7758 err_free_tx_0:
7759         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7760                           tp->TxPhyAddr);
7761         tp->TxDescArray = NULL;
7762 err_pm_runtime_put:
7763         pm_runtime_put_noidle(&pdev->dev);
7764         goto out;
7765 }
7766
7767 static void
7768 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7769 {
7770         struct rtl8169_private *tp = netdev_priv(dev);
7771         void __iomem *ioaddr = tp->mmio_addr;
7772         struct pci_dev *pdev = tp->pci_dev;
7773         struct rtl8169_counters *counters = tp->counters;
7774         unsigned int start;
7775
7776         pm_runtime_get_noresume(&pdev->dev);
7777
7778         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
7779                 rtl8169_rx_missed(dev, ioaddr);
7780
7781         do {
7782                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
7783                 stats->rx_packets = tp->rx_stats.packets;
7784                 stats->rx_bytes = tp->rx_stats.bytes;
7785         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
7786
7787         do {
7788                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
7789                 stats->tx_packets = tp->tx_stats.packets;
7790                 stats->tx_bytes = tp->tx_stats.bytes;
7791         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
7792
7793         stats->rx_dropped       = dev->stats.rx_dropped;
7794         stats->tx_dropped       = dev->stats.tx_dropped;
7795         stats->rx_length_errors = dev->stats.rx_length_errors;
7796         stats->rx_errors        = dev->stats.rx_errors;
7797         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
7798         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
7799         stats->rx_missed_errors = dev->stats.rx_missed_errors;
7800         stats->multicast        = dev->stats.multicast;
7801
7802         /*
7803          * Fetch additonal counter values missing in stats collected by driver
7804          * from tally counters.
7805          */
7806         if (pm_runtime_active(&pdev->dev))
7807                 rtl8169_update_counters(dev);
7808
7809         /*
7810          * Subtract values fetched during initalization.
7811          * See rtl8169_init_counter_offsets for a description why we do that.
7812          */
7813         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
7814                 le64_to_cpu(tp->tc_offset.tx_errors);
7815         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
7816                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
7817         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
7818                 le16_to_cpu(tp->tc_offset.tx_aborted);
7819
7820         pm_runtime_put_noidle(&pdev->dev);
7821 }
7822
7823 static void rtl8169_net_suspend(struct net_device *dev)
7824 {
7825         struct rtl8169_private *tp = netdev_priv(dev);
7826
7827         if (!netif_running(dev))
7828                 return;
7829
7830         netif_device_detach(dev);
7831         netif_stop_queue(dev);
7832
7833         rtl_lock_work(tp);
7834         napi_disable(&tp->napi);
7835         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7836         rtl_unlock_work(tp);
7837
7838         rtl_pll_power_down(tp);
7839 }
7840
7841 #ifdef CONFIG_PM
7842
7843 static int rtl8169_suspend(struct device *device)
7844 {
7845         struct pci_dev *pdev = to_pci_dev(device);
7846         struct net_device *dev = pci_get_drvdata(pdev);
7847
7848         rtl8169_net_suspend(dev);
7849
7850         return 0;
7851 }
7852
7853 static void __rtl8169_resume(struct net_device *dev)
7854 {
7855         struct rtl8169_private *tp = netdev_priv(dev);
7856
7857         netif_device_attach(dev);
7858
7859         rtl_pll_power_up(tp);
7860
7861         rtl_lock_work(tp);
7862         napi_enable(&tp->napi);
7863         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7864         rtl_unlock_work(tp);
7865
7866         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7867 }
7868
7869 static int rtl8169_resume(struct device *device)
7870 {
7871         struct pci_dev *pdev = to_pci_dev(device);
7872         struct net_device *dev = pci_get_drvdata(pdev);
7873         struct rtl8169_private *tp = netdev_priv(dev);
7874
7875         rtl8169_init_phy(dev, tp);
7876
7877         if (netif_running(dev))
7878                 __rtl8169_resume(dev);
7879
7880         return 0;
7881 }
7882
7883 static int rtl8169_runtime_suspend(struct device *device)
7884 {
7885         struct pci_dev *pdev = to_pci_dev(device);
7886         struct net_device *dev = pci_get_drvdata(pdev);
7887         struct rtl8169_private *tp = netdev_priv(dev);
7888
7889         if (!tp->TxDescArray)
7890                 return 0;
7891
7892         rtl_lock_work(tp);
7893         tp->saved_wolopts = __rtl8169_get_wol(tp);
7894         __rtl8169_set_wol(tp, WAKE_ANY);
7895         rtl_unlock_work(tp);
7896
7897         rtl8169_net_suspend(dev);
7898
7899         /* Update counters before going runtime suspend */
7900         rtl8169_rx_missed(dev, tp->mmio_addr);
7901         rtl8169_update_counters(dev);
7902
7903         return 0;
7904 }
7905
7906 static int rtl8169_runtime_resume(struct device *device)
7907 {
7908         struct pci_dev *pdev = to_pci_dev(device);
7909         struct net_device *dev = pci_get_drvdata(pdev);
7910         struct rtl8169_private *tp = netdev_priv(dev);
7911         rtl_rar_set(tp, dev->dev_addr);
7912
7913         if (!tp->TxDescArray)
7914                 return 0;
7915
7916         rtl_lock_work(tp);
7917         __rtl8169_set_wol(tp, tp->saved_wolopts);
7918         tp->saved_wolopts = 0;
7919         rtl_unlock_work(tp);
7920
7921         rtl8169_init_phy(dev, tp);
7922
7923         __rtl8169_resume(dev);
7924
7925         return 0;
7926 }
7927
7928 static int rtl8169_runtime_idle(struct device *device)
7929 {
7930         struct pci_dev *pdev = to_pci_dev(device);
7931         struct net_device *dev = pci_get_drvdata(pdev);
7932         struct rtl8169_private *tp = netdev_priv(dev);
7933
7934         return tp->TxDescArray ? -EBUSY : 0;
7935 }
7936
7937 static const struct dev_pm_ops rtl8169_pm_ops = {
7938         .suspend                = rtl8169_suspend,
7939         .resume                 = rtl8169_resume,
7940         .freeze                 = rtl8169_suspend,
7941         .thaw                   = rtl8169_resume,
7942         .poweroff               = rtl8169_suspend,
7943         .restore                = rtl8169_resume,
7944         .runtime_suspend        = rtl8169_runtime_suspend,
7945         .runtime_resume         = rtl8169_runtime_resume,
7946         .runtime_idle           = rtl8169_runtime_idle,
7947 };
7948
7949 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
7950
7951 #else /* !CONFIG_PM */
7952
7953 #define RTL8169_PM_OPS  NULL
7954
7955 #endif /* !CONFIG_PM */
7956
7957 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7958 {
7959         void __iomem *ioaddr = tp->mmio_addr;
7960
7961         /* WoL fails with 8168b when the receiver is disabled. */
7962         switch (tp->mac_version) {
7963         case RTL_GIGA_MAC_VER_11:
7964         case RTL_GIGA_MAC_VER_12:
7965         case RTL_GIGA_MAC_VER_17:
7966                 pci_clear_master(tp->pci_dev);
7967
7968                 RTL_W8(ChipCmd, CmdRxEnb);
7969                 /* PCI commit */
7970                 RTL_R8(ChipCmd);
7971                 break;
7972         default:
7973                 break;
7974         }
7975 }
7976
7977 static void rtl_shutdown(struct pci_dev *pdev)
7978 {
7979         struct net_device *dev = pci_get_drvdata(pdev);
7980         struct rtl8169_private *tp = netdev_priv(dev);
7981         struct device *d = &pdev->dev;
7982
7983         pm_runtime_get_sync(d);
7984
7985         rtl8169_net_suspend(dev);
7986
7987         /* Restore original MAC address */
7988         rtl_rar_set(tp, dev->perm_addr);
7989
7990         rtl8169_hw_reset(tp);
7991
7992         if (system_state == SYSTEM_POWER_OFF) {
7993                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7994                         rtl_wol_suspend_quirk(tp);
7995                         rtl_wol_shutdown_quirk(tp);
7996                 }
7997
7998                 pci_wake_from_d3(pdev, true);
7999                 pci_set_power_state(pdev, PCI_D3hot);
8000         }
8001
8002         pm_runtime_put_noidle(d);
8003 }
8004
8005 static void rtl_remove_one(struct pci_dev *pdev)
8006 {
8007         struct net_device *dev = pci_get_drvdata(pdev);
8008         struct rtl8169_private *tp = netdev_priv(dev);
8009
8010         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8011              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8012              tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8013              tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8014              tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8015              tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8016             r8168_check_dash(tp)) {
8017                 rtl8168_driver_stop(tp);
8018         }
8019
8020         netif_napi_del(&tp->napi);
8021
8022         unregister_netdev(dev);
8023
8024         dma_free_coherent(&tp->pci_dev->dev, sizeof(*tp->counters),
8025                           tp->counters, tp->counters_phys_addr);
8026
8027         rtl_release_firmware(tp);
8028
8029         if (pci_dev_run_wake(pdev))
8030                 pm_runtime_get_noresume(&pdev->dev);
8031
8032         /* restore original MAC address */
8033         rtl_rar_set(tp, dev->perm_addr);
8034
8035         rtl_disable_msi(pdev, tp);
8036         rtl8169_release_board(pdev, dev, tp->mmio_addr);
8037 }
8038
8039 static const struct net_device_ops rtl_netdev_ops = {
8040         .ndo_open               = rtl_open,
8041         .ndo_stop               = rtl8169_close,
8042         .ndo_get_stats64        = rtl8169_get_stats64,
8043         .ndo_start_xmit         = rtl8169_start_xmit,
8044         .ndo_tx_timeout         = rtl8169_tx_timeout,
8045         .ndo_validate_addr      = eth_validate_addr,
8046         .ndo_change_mtu         = rtl8169_change_mtu,
8047         .ndo_fix_features       = rtl8169_fix_features,
8048         .ndo_set_features       = rtl8169_set_features,
8049         .ndo_set_mac_address    = rtl_set_mac_address,
8050         .ndo_do_ioctl           = rtl8169_ioctl,
8051         .ndo_set_rx_mode        = rtl_set_rx_mode,
8052 #ifdef CONFIG_NET_POLL_CONTROLLER
8053         .ndo_poll_controller    = rtl8169_netpoll,
8054 #endif
8055
8056 };
8057
8058 static const struct rtl_cfg_info {
8059         void (*hw_start)(struct net_device *);
8060         unsigned int region;
8061         unsigned int align;
8062         u16 event_slow;
8063         unsigned features;
8064         u8 default_ver;
8065 } rtl_cfg_infos [] = {
8066         [RTL_CFG_0] = {
8067                 .hw_start       = rtl_hw_start_8169,
8068                 .region         = 1,
8069                 .align          = 0,
8070                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
8071                 .features       = RTL_FEATURE_GMII,
8072                 .default_ver    = RTL_GIGA_MAC_VER_01,
8073         },
8074         [RTL_CFG_1] = {
8075                 .hw_start       = rtl_hw_start_8168,
8076                 .region         = 2,
8077                 .align          = 8,
8078                 .event_slow     = SYSErr | LinkChg | RxOverflow,
8079                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
8080                 .default_ver    = RTL_GIGA_MAC_VER_11,
8081         },
8082         [RTL_CFG_2] = {
8083                 .hw_start       = rtl_hw_start_8101,
8084                 .region         = 2,
8085                 .align          = 8,
8086                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
8087                                   PCSTimeout,
8088                 .features       = RTL_FEATURE_MSI,
8089                 .default_ver    = RTL_GIGA_MAC_VER_13,
8090         }
8091 };
8092
8093 /* Cfg9346_Unlock assumed. */
8094 static unsigned rtl_try_msi(struct rtl8169_private *tp,
8095                             const struct rtl_cfg_info *cfg)
8096 {
8097         void __iomem *ioaddr = tp->mmio_addr;
8098         unsigned msi = 0;
8099         u8 cfg2;
8100
8101         cfg2 = RTL_R8(Config2) & ~MSIEnable;
8102         if (cfg->features & RTL_FEATURE_MSI) {
8103                 if (pci_enable_msi(tp->pci_dev)) {
8104                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
8105                 } else {
8106                         cfg2 |= MSIEnable;
8107                         msi = RTL_FEATURE_MSI;
8108                 }
8109         }
8110         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
8111                 RTL_W8(Config2, cfg2);
8112         return msi;
8113 }
8114
8115 DECLARE_RTL_COND(rtl_link_list_ready_cond)
8116 {
8117         void __iomem *ioaddr = tp->mmio_addr;
8118
8119         return RTL_R8(MCU) & LINK_LIST_RDY;
8120 }
8121
8122 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
8123 {
8124         void __iomem *ioaddr = tp->mmio_addr;
8125
8126         return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
8127 }
8128
8129 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
8130 {
8131         void __iomem *ioaddr = tp->mmio_addr;
8132         u32 data;
8133
8134         tp->ocp_base = OCP_STD_PHY_BASE;
8135
8136         RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
8137
8138         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
8139                 return;
8140
8141         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
8142                 return;
8143
8144         RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
8145         msleep(1);
8146         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
8147
8148         data = r8168_mac_ocp_read(tp, 0xe8de);
8149         data &= ~(1 << 14);
8150         r8168_mac_ocp_write(tp, 0xe8de, data);
8151
8152         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8153                 return;
8154
8155         data = r8168_mac_ocp_read(tp, 0xe8de);
8156         data |= (1 << 15);
8157         r8168_mac_ocp_write(tp, 0xe8de, data);
8158
8159         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8160                 return;
8161 }
8162
8163 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
8164 {
8165         rtl8168ep_stop_cmac(tp);
8166         rtl_hw_init_8168g(tp);
8167 }
8168
8169 static void rtl_hw_initialize(struct rtl8169_private *tp)
8170 {
8171         switch (tp->mac_version) {
8172         case RTL_GIGA_MAC_VER_40:
8173         case RTL_GIGA_MAC_VER_41:
8174         case RTL_GIGA_MAC_VER_42:
8175         case RTL_GIGA_MAC_VER_43:
8176         case RTL_GIGA_MAC_VER_44:
8177         case RTL_GIGA_MAC_VER_45:
8178         case RTL_GIGA_MAC_VER_46:
8179         case RTL_GIGA_MAC_VER_47:
8180         case RTL_GIGA_MAC_VER_48:
8181                 rtl_hw_init_8168g(tp);
8182                 break;
8183         case RTL_GIGA_MAC_VER_49:
8184         case RTL_GIGA_MAC_VER_50:
8185         case RTL_GIGA_MAC_VER_51:
8186                 rtl_hw_init_8168ep(tp);
8187                 break;
8188         default:
8189                 break;
8190         }
8191 }
8192
8193 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8194 {
8195         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8196         const unsigned int region = cfg->region;
8197         struct rtl8169_private *tp;
8198         struct mii_if_info *mii;
8199         struct net_device *dev;
8200         void __iomem *ioaddr;
8201         int chipset, i;
8202         int rc;
8203
8204         if (netif_msg_drv(&debug)) {
8205                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8206                        MODULENAME, RTL8169_VERSION);
8207         }
8208
8209         dev = alloc_etherdev(sizeof (*tp));
8210         if (!dev) {
8211                 rc = -ENOMEM;
8212                 goto out;
8213         }
8214
8215         SET_NETDEV_DEV(dev, &pdev->dev);
8216         dev->netdev_ops = &rtl_netdev_ops;
8217         tp = netdev_priv(dev);
8218         tp->dev = dev;
8219         tp->pci_dev = pdev;
8220         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8221
8222         mii = &tp->mii;
8223         mii->dev = dev;
8224         mii->mdio_read = rtl_mdio_read;
8225         mii->mdio_write = rtl_mdio_write;
8226         mii->phy_id_mask = 0x1f;
8227         mii->reg_num_mask = 0x1f;
8228         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
8229
8230         /* disable ASPM completely as that cause random device stop working
8231          * problems as well as full system hangs for some PCIe devices users */
8232         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8233                                      PCIE_LINK_STATE_CLKPM);
8234
8235         /* enable device (incl. PCI PM wakeup and hotplug setup) */
8236         rc = pci_enable_device(pdev);
8237         if (rc < 0) {
8238                 netif_err(tp, probe, dev, "enable failure\n");
8239                 goto err_out_free_dev_1;
8240         }
8241
8242         if (pci_set_mwi(pdev) < 0)
8243                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8244
8245         /* make sure PCI base addr 1 is MMIO */
8246         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8247                 netif_err(tp, probe, dev,
8248                           "region #%d not an MMIO resource, aborting\n",
8249                           region);
8250                 rc = -ENODEV;
8251                 goto err_out_mwi_2;
8252         }
8253
8254         /* check for weird/broken PCI region reporting */
8255         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8256                 netif_err(tp, probe, dev,
8257                           "Invalid PCI region size(s), aborting\n");
8258                 rc = -ENODEV;
8259                 goto err_out_mwi_2;
8260         }
8261
8262         rc = pci_request_regions(pdev, MODULENAME);
8263         if (rc < 0) {
8264                 netif_err(tp, probe, dev, "could not request regions\n");
8265                 goto err_out_mwi_2;
8266         }
8267
8268         /* ioremap MMIO region */
8269         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
8270         if (!ioaddr) {
8271                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
8272                 rc = -EIO;
8273                 goto err_out_free_res_3;
8274         }
8275         tp->mmio_addr = ioaddr;
8276
8277         if (!pci_is_pcie(pdev))
8278                 netif_info(tp, probe, dev, "not PCI Express\n");
8279
8280         /* Identify chip attached to board */
8281         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8282
8283         tp->cp_cmd = 0;
8284
8285         if ((sizeof(dma_addr_t) > 4) &&
8286             (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
8287                               tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
8288             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
8289             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
8290
8291                 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
8292                 if (!pci_is_pcie(pdev))
8293                         tp->cp_cmd |= PCIDAC;
8294                 dev->features |= NETIF_F_HIGHDMA;
8295         } else {
8296                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8297                 if (rc < 0) {
8298                         netif_err(tp, probe, dev, "DMA configuration failed\n");
8299                         goto err_out_unmap_4;
8300                 }
8301         }
8302
8303         rtl_init_rxcfg(tp);
8304
8305         rtl_irq_disable(tp);
8306
8307         rtl_hw_initialize(tp);
8308
8309         rtl_hw_reset(tp);
8310
8311         rtl_ack_events(tp, 0xffff);
8312
8313         pci_set_master(pdev);
8314
8315         rtl_init_mdio_ops(tp);
8316         rtl_init_pll_power_ops(tp);
8317         rtl_init_jumbo_ops(tp);
8318         rtl_init_csi_ops(tp);
8319
8320         rtl8169_print_mac_version(tp);
8321
8322         chipset = tp->mac_version;
8323         tp->txd_version = rtl_chip_infos[chipset].txd_version;
8324
8325         RTL_W8(Cfg9346, Cfg9346_Unlock);
8326         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
8327         RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
8328         switch (tp->mac_version) {
8329         case RTL_GIGA_MAC_VER_34:
8330         case RTL_GIGA_MAC_VER_35:
8331         case RTL_GIGA_MAC_VER_36:
8332         case RTL_GIGA_MAC_VER_37:
8333         case RTL_GIGA_MAC_VER_38:
8334         case RTL_GIGA_MAC_VER_40:
8335         case RTL_GIGA_MAC_VER_41:
8336         case RTL_GIGA_MAC_VER_42:
8337         case RTL_GIGA_MAC_VER_43:
8338         case RTL_GIGA_MAC_VER_44:
8339         case RTL_GIGA_MAC_VER_45:
8340         case RTL_GIGA_MAC_VER_46:
8341         case RTL_GIGA_MAC_VER_47:
8342         case RTL_GIGA_MAC_VER_48:
8343         case RTL_GIGA_MAC_VER_49:
8344         case RTL_GIGA_MAC_VER_50:
8345         case RTL_GIGA_MAC_VER_51:
8346                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
8347                         tp->features |= RTL_FEATURE_WOL;
8348                 if ((RTL_R8(Config3) & LinkUp) != 0)
8349                         tp->features |= RTL_FEATURE_WOL;
8350                 break;
8351         default:
8352                 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
8353                         tp->features |= RTL_FEATURE_WOL;
8354                 break;
8355         }
8356         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
8357                 tp->features |= RTL_FEATURE_WOL;
8358         tp->features |= rtl_try_msi(tp, cfg);
8359         RTL_W8(Cfg9346, Cfg9346_Lock);
8360
8361         if (rtl_tbi_enabled(tp)) {
8362                 tp->set_speed = rtl8169_set_speed_tbi;
8363                 tp->get_link_ksettings = rtl8169_get_link_ksettings_tbi;
8364                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8365                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8366                 tp->link_ok = rtl8169_tbi_link_ok;
8367                 tp->do_ioctl = rtl_tbi_ioctl;
8368         } else {
8369                 tp->set_speed = rtl8169_set_speed_xmii;
8370                 tp->get_link_ksettings = rtl8169_get_link_ksettings_xmii;
8371                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8372                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8373                 tp->link_ok = rtl8169_xmii_link_ok;
8374                 tp->do_ioctl = rtl_xmii_ioctl;
8375         }
8376
8377         mutex_init(&tp->wk.mutex);
8378         u64_stats_init(&tp->rx_stats.syncp);
8379         u64_stats_init(&tp->tx_stats.syncp);
8380
8381         /* Get MAC address */
8382         if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8383             tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8384             tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8385             tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8386             tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8387             tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8388             tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8389             tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8390             tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8391             tp->mac_version == RTL_GIGA_MAC_VER_45 ||
8392             tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8393             tp->mac_version == RTL_GIGA_MAC_VER_47 ||
8394             tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8395             tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8396             tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8397             tp->mac_version == RTL_GIGA_MAC_VER_51) {
8398                 u16 mac_addr[3];
8399
8400                 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8401                 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
8402
8403                 if (is_valid_ether_addr((u8 *)mac_addr))
8404                         rtl_rar_set(tp, (u8 *)mac_addr);
8405         }
8406         for (i = 0; i < ETH_ALEN; i++)
8407                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
8408
8409         dev->ethtool_ops = &rtl8169_ethtool_ops;
8410         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
8411
8412         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
8413
8414         /* don't enable SG, IP_CSUM and TSO by default - it might not work
8415          * properly for all devices */
8416         dev->features |= NETIF_F_RXCSUM |
8417                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
8418
8419         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8420                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8421                 NETIF_F_HW_VLAN_CTAG_RX;
8422         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8423                 NETIF_F_HIGHDMA;
8424
8425         tp->cp_cmd |= RxChkSum | RxVlan;
8426
8427         /*
8428          * Pretend we are using VLANs; This bypasses a nasty bug where
8429          * Interrupts stop flowing on high load on 8110SCd controllers.
8430          */
8431         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
8432                 /* Disallow toggling */
8433                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
8434
8435         if (tp->txd_version == RTL_TD_0)
8436                 tp->tso_csum = rtl8169_tso_csum_v1;
8437         else if (tp->txd_version == RTL_TD_1) {
8438                 tp->tso_csum = rtl8169_tso_csum_v2;
8439                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8440         } else
8441                 WARN_ON_ONCE(1);
8442
8443         dev->hw_features |= NETIF_F_RXALL;
8444         dev->hw_features |= NETIF_F_RXFCS;
8445
8446         /* MTU range: 60 - hw-specific max */
8447         dev->min_mtu = ETH_ZLEN;
8448         dev->max_mtu = rtl_chip_infos[chipset].jumbo_max;
8449
8450         tp->hw_start = cfg->hw_start;
8451         tp->event_slow = cfg->event_slow;
8452
8453         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8454                 ~(RxBOVF | RxFOVF) : ~0;
8455
8456         setup_timer(&tp->timer, rtl8169_phy_timer, (unsigned long)dev);
8457
8458         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8459
8460         tp->counters = dma_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
8461                                            &tp->counters_phys_addr, GFP_KERNEL);
8462         if (!tp->counters) {
8463                 rc = -ENOMEM;
8464                 goto err_out_msi_5;
8465         }
8466
8467         rc = register_netdev(dev);
8468         if (rc < 0)
8469                 goto err_out_cnt_6;
8470
8471         pci_set_drvdata(pdev, dev);
8472
8473         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8474                    rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
8475                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
8476         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8477                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8478                            "tx checksumming: %s]\n",
8479                            rtl_chip_infos[chipset].jumbo_max,
8480                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8481         }
8482
8483         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8484              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8485              tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8486              tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8487              tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8488              tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8489             r8168_check_dash(tp)) {
8490                 rtl8168_driver_start(tp);
8491         }
8492
8493         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
8494
8495         if (pci_dev_run_wake(pdev))
8496                 pm_runtime_put_noidle(&pdev->dev);
8497
8498         netif_carrier_off(dev);
8499
8500 out:
8501         return rc;
8502
8503 err_out_cnt_6:
8504         dma_free_coherent(&pdev->dev, sizeof(*tp->counters), tp->counters,
8505                           tp->counters_phys_addr);
8506 err_out_msi_5:
8507         netif_napi_del(&tp->napi);
8508         rtl_disable_msi(pdev, tp);
8509 err_out_unmap_4:
8510         iounmap(ioaddr);
8511 err_out_free_res_3:
8512         pci_release_regions(pdev);
8513 err_out_mwi_2:
8514         pci_clear_mwi(pdev);
8515         pci_disable_device(pdev);
8516 err_out_free_dev_1:
8517         free_netdev(dev);
8518         goto out;
8519 }
8520
8521 static struct pci_driver rtl8169_pci_driver = {
8522         .name           = MODULENAME,
8523         .id_table       = rtl8169_pci_tbl,
8524         .probe          = rtl_init_one,
8525         .remove         = rtl_remove_one,
8526         .shutdown       = rtl_shutdown,
8527         .driver.pm      = RTL8169_PM_OPS,
8528 };
8529
8530 module_pci_driver(rtl8169_pci_driver);