1 /* 10G controller driver for Samsung SoCs
3 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Author: Siva Reddy Kallam <siva.kallam@samsung.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #ifndef __SXGBE_DESC_H__
13 #define __SXGBE_DESC_H__
15 #define SXGBE_DESC_SIZE_BYTES 16
17 /* forward declaration */
18 struct sxgbe_extra_stats;
20 /* Transmit checksum insertion control */
21 enum tdes_csum_insertion {
22 cic_disabled = 0, /* Checksum Insertion Control */
23 cic_only_ip = 1, /* Only IP header */
24 /* IP header but pseudoheader is not calculated */
25 cic_no_pseudoheader = 2,
26 cic_full = 3, /* IP header and pseudoheader */
29 struct sxgbe_tx_norm_desc {
30 u64 tdes01; /* buf1 address */
32 /* TX Read-Format Desc 2,3 */
38 u32 timestmp_enable:1;
42 u32 tcp_payload_len:18;
60 /* tx write back Desc 2,3 */
71 struct sxgbe_rx_norm_desc {
73 u32 rdes0; /* buf1 address */
81 u32 rdes1; /* buf2 address or buf1[63:32] */
82 u32 rss_hash; /* Write-back RX */
86 /* RX Read format Desc 2,3 */
100 u32 rdes2_reserved:2;
104 u32 vlan_filter_match:1;
105 u32 sa_filter_fail:1;
106 u32 da_filter_fail:1;
107 u32 hash_filter_pass:1;
108 u32 macaddr_filter_match:8;
109 u32 l3_filter_match:1;
110 u32 l4_filter_match:1;
111 u32 l34_filter_num:3;
115 u32 rdes3_reserved:1;
118 u32 layer34_pkt_type:4;
119 u32 no_coagulation_pkt:1;
122 u32 context_des_avail:1;
125 u32 recv_context_desc:1;
131 /* Context descriptor structure */
132 struct sxgbe_tx_ctxt_desc {
140 u32 ivlan_tag_valid:1;
152 struct sxgbe_rx_ctxt_desc {
157 u32 tstamp_available:1;
159 u32 tstamp_dropped:1;
165 struct sxgbe_desc_ops {
166 /* DMA TX descriptor ring initialization */
167 void (*init_tx_desc)(struct sxgbe_tx_norm_desc *p);
169 /* Invoked by the xmit function to prepare the tx descriptor */
170 void (*tx_desc_enable_tse)(struct sxgbe_tx_norm_desc *p, u8 is_tse,
171 u32 total_hdr_len, u32 tcp_hdr_len,
172 u32 tcp_payload_len);
174 /* Assign buffer lengths for descriptor */
175 void (*prepare_tx_desc)(struct sxgbe_tx_norm_desc *p, u8 is_fd,
176 int buf1_len, int pkt_len, int cksum);
178 /* Set VLAN control information */
179 void (*tx_vlanctl_desc)(struct sxgbe_tx_norm_desc *p, int vlan_ctl);
181 /* Set the owner of the descriptor */
182 void (*set_tx_owner)(struct sxgbe_tx_norm_desc *p);
184 /* Get the owner of the descriptor */
185 int (*get_tx_owner)(struct sxgbe_tx_norm_desc *p);
187 /* Invoked by the xmit function to close the tx descriptor */
188 void (*close_tx_desc)(struct sxgbe_tx_norm_desc *p);
190 /* Clean the tx descriptor as soon as the tx irq is received */
191 void (*release_tx_desc)(struct sxgbe_tx_norm_desc *p);
193 /* Clear interrupt on tx frame completion. When this bit is
194 * set an interrupt happens as soon as the frame is transmitted
196 void (*clear_tx_ic)(struct sxgbe_tx_norm_desc *p);
198 /* Last tx segment reports the transmit status */
199 int (*get_tx_ls)(struct sxgbe_tx_norm_desc *p);
201 /* Get the buffer size from the descriptor */
202 int (*get_tx_len)(struct sxgbe_tx_norm_desc *p);
204 /* Set tx timestamp enable bit */
205 void (*tx_enable_tstamp)(struct sxgbe_tx_norm_desc *p);
207 /* get tx timestamp status */
208 int (*get_tx_timestamp_status)(struct sxgbe_tx_norm_desc *p);
210 /* TX Context Descripto Specific */
211 void (*tx_ctxt_desc_set_ctxt)(struct sxgbe_tx_ctxt_desc *p);
213 /* Set the owner of the TX context descriptor */
214 void (*tx_ctxt_desc_set_owner)(struct sxgbe_tx_ctxt_desc *p);
216 /* Get the owner of the TX context descriptor */
217 int (*get_tx_ctxt_owner)(struct sxgbe_tx_ctxt_desc *p);
220 void (*tx_ctxt_desc_set_mss)(struct sxgbe_tx_ctxt_desc *p, u16 mss);
223 int (*tx_ctxt_desc_get_mss)(struct sxgbe_tx_ctxt_desc *p);
226 void (*tx_ctxt_desc_set_tcmssv)(struct sxgbe_tx_ctxt_desc *p);
229 void (*tx_ctxt_desc_reset_ostc)(struct sxgbe_tx_ctxt_desc *p);
231 /* Set IVLAN information */
232 void (*tx_ctxt_desc_set_ivlantag)(struct sxgbe_tx_ctxt_desc *p,
233 int is_ivlanvalid, int ivlan_tag,
236 /* Return IVLAN Tag */
237 int (*tx_ctxt_desc_get_ivlantag)(struct sxgbe_tx_ctxt_desc *p);
240 void (*tx_ctxt_desc_set_vlantag)(struct sxgbe_tx_ctxt_desc *p,
241 int is_vlanvalid, int vlan_tag);
243 /* Return VLAN Tag */
244 int (*tx_ctxt_desc_get_vlantag)(struct sxgbe_tx_ctxt_desc *p);
247 void (*tx_ctxt_set_tstamp)(struct sxgbe_tx_ctxt_desc *p,
248 u8 ostc_enable, u64 tstamp);
250 /* Close TX context descriptor */
251 void (*close_tx_ctxt_desc)(struct sxgbe_tx_ctxt_desc *p);
253 /* WB status of context descriptor */
254 int (*get_tx_ctxt_cde)(struct sxgbe_tx_ctxt_desc *p);
256 /* DMA RX descriptor ring initialization */
257 void (*init_rx_desc)(struct sxgbe_rx_norm_desc *p, int disable_rx_ic,
261 int (*get_rx_owner)(struct sxgbe_rx_norm_desc *p);
264 void (*set_rx_owner)(struct sxgbe_rx_norm_desc *p);
266 /* Get the receive frame size */
267 int (*get_rx_frame_len)(struct sxgbe_rx_norm_desc *p);
269 /* Return first Descriptor status */
270 int (*get_rx_fd_status)(struct sxgbe_rx_norm_desc *p);
272 /* Return first Descriptor status */
273 int (*get_rx_ld_status)(struct sxgbe_rx_norm_desc *p);
275 /* Return the reception status looking at the RDES1 */
276 int (*rx_wbstatus)(struct sxgbe_rx_norm_desc *p,
277 struct sxgbe_extra_stats *x, int *checksum);
280 int (*get_rx_ctxt_owner)(struct sxgbe_rx_ctxt_desc *p);
283 void (*set_rx_ctxt_owner)(struct sxgbe_rx_ctxt_desc *p);
285 /* Return the reception status looking at Context control information */
286 void (*rx_ctxt_wbstatus)(struct sxgbe_rx_ctxt_desc *p,
287 struct sxgbe_extra_stats *x);
289 /* Get rx timestamp status */
290 int (*get_rx_ctxt_tstamp_status)(struct sxgbe_rx_ctxt_desc *p);
292 /* Get timestamp value for rx, need to check this */
293 u64 (*get_timestamp)(struct sxgbe_rx_ctxt_desc *p);
296 const struct sxgbe_desc_ops *sxgbe_get_desc_ops(void);
298 #endif /* __SXGBE_DESC_H__ */