3 * This is a driver for SMSC's 91C9x/91C1xx single-chip Ethernet devices.
5 * Copyright (C) 1996 by Erik Stahlman
6 * Copyright (C) 2001 Standard Microsystems Corporation
7 * Developed by Simple Network Magic Corporation
8 * Copyright (C) 2003 Monta Vista Software, Inc.
9 * Unified SMC91x driver by Nicolas Pitre
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
25 * io = for the base address
27 * nowait = 0 for normal wait states, 1 eliminates additional wait states
30 * Erik Stahlman <erik@vt.edu>
32 * hardware multicast code:
33 * Peter Cammaert <pc@denkart.be>
36 * Daris A Nevil <dnevil@snmc.com>
37 * Nicolas Pitre <nico@fluxnic.net>
38 * Russell King <rmk@arm.linux.org.uk>
41 * 08/20/00 Arnaldo Melo fix kfree(skb) in smc_hardware_send_packet
42 * 12/15/00 Christian Jullien fix "Warning: kfree_skb on hard IRQ"
43 * 03/16/01 Daris A Nevil modified smc9194.c for use with LAN91C111
44 * 08/22/01 Scott Anderson merge changes from smc9194 to smc91111
45 * 08/21/01 Pramod B Bhardwaj added support for RevB of LAN91C111
46 * 12/20/01 Jeff Sutherland initial port to Xscale PXA with DMA support
47 * 04/07/03 Nicolas Pitre unified SMC91x driver, killed irq races,
48 * more bus abstraction, big cleanup, etc.
49 * 29/09/03 Russell King - add driver model support
51 * - convert to use generic MII interface
52 * - add link up/down notification
53 * - don't try to handle full negotiation in
55 * - clean up (and fix stack overrun) in PHY
56 * MII read/write functions
57 * 22/09/04 Nicolas Pitre big update (see commit log for details)
59 static const char version[] =
60 "smc91x.c: v1.1, sep 22 2004 by Nicolas Pitre <nico@fluxnic.net>";
68 #include <linux/module.h>
69 #include <linux/kernel.h>
70 #include <linux/sched.h>
71 #include <linux/delay.h>
72 #include <linux/interrupt.h>
73 #include <linux/irq.h>
74 #include <linux/errno.h>
75 #include <linux/ioport.h>
76 #include <linux/crc32.h>
77 #include <linux/platform_device.h>
78 #include <linux/spinlock.h>
79 #include <linux/ethtool.h>
80 #include <linux/mii.h>
81 #include <linux/workqueue.h>
83 #include <linux/of_device.h>
84 #include <linux/of_gpio.h>
86 #include <linux/netdevice.h>
87 #include <linux/etherdevice.h>
88 #include <linux/skbuff.h>
94 #if defined(CONFIG_ASSABET_NEPONSET)
95 #include <mach/assabet.h>
96 #include <mach/neponset.h>
100 # define SMC_NOWAIT 0
102 static int nowait = SMC_NOWAIT;
103 module_param(nowait, int, 0400);
104 MODULE_PARM_DESC(nowait, "set to 1 for no wait state");
107 * Transmit timeout, default 5 seconds.
109 static int watchdog = 1000;
110 module_param(watchdog, int, 0400);
111 MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
113 MODULE_LICENSE("GPL");
114 MODULE_ALIAS("platform:smc91x");
117 * The internal workings of the driver. If you are changing anything
118 * here with the SMC stuff, you should have the datasheet and know
119 * what you are doing.
121 #define CARDNAME "smc91x"
124 * Use power-down feature of the chip
129 * Wait time for memory to be free. This probably shouldn't be
130 * tuned that much, as waiting for this means nothing else happens
133 #define MEMORY_WAIT_TIME 16
136 * The maximum number of processing loops allowed for each call to the
139 #define MAX_IRQ_LOOPS 8
142 * This selects whether TX packets are sent one by one to the SMC91x internal
143 * memory and throttled until transmission completes. This may prevent
144 * RX overruns a litle by keeping much of the memory free for RX packets
145 * but to the expense of reduced TX throughput and increased IRQ overhead.
146 * Note this is not a cure for a too slow data bus or too high IRQ latency.
148 #define THROTTLE_TX_PKTS 0
151 * The MII clock high/low times. 2x this number gives the MII clock period
152 * in microseconds. (was 50, but this gives 6.4ms for each MII transaction!)
156 #define DBG(n, dev, fmt, ...) \
158 if (SMC_DEBUG >= (n)) \
159 netdev_dbg(dev, fmt, ##__VA_ARGS__); \
162 #define PRINTK(dev, fmt, ...) \
165 netdev_info(dev, fmt, ##__VA_ARGS__); \
167 netdev_dbg(dev, fmt, ##__VA_ARGS__); \
171 static void PRINT_PKT(u_char *buf, int length)
178 remainder = length % 16;
180 for (i = 0; i < lines ; i ++) {
183 for (cur = 0; cur < 8; cur++) {
187 pr_cont("%02x%02x ", a, b);
192 for (i = 0; i < remainder/2 ; i++) {
196 pr_cont("%02x%02x ", a, b);
201 static inline void PRINT_PKT(u_char *buf, int length) { }
205 /* this enables an interrupt in the interrupt mask register */
206 #define SMC_ENABLE_INT(lp, x) do { \
207 unsigned char mask; \
208 unsigned long smc_enable_flags; \
209 spin_lock_irqsave(&lp->lock, smc_enable_flags); \
210 mask = SMC_GET_INT_MASK(lp); \
212 SMC_SET_INT_MASK(lp, mask); \
213 spin_unlock_irqrestore(&lp->lock, smc_enable_flags); \
216 /* this disables an interrupt from the interrupt mask register */
217 #define SMC_DISABLE_INT(lp, x) do { \
218 unsigned char mask; \
219 unsigned long smc_disable_flags; \
220 spin_lock_irqsave(&lp->lock, smc_disable_flags); \
221 mask = SMC_GET_INT_MASK(lp); \
223 SMC_SET_INT_MASK(lp, mask); \
224 spin_unlock_irqrestore(&lp->lock, smc_disable_flags); \
228 * Wait while MMU is busy. This is usually in the order of a few nanosecs
229 * if at all, but let's avoid deadlocking the system if the hardware
230 * decides to go south.
232 #define SMC_WAIT_MMU_BUSY(lp) do { \
233 if (unlikely(SMC_GET_MMU_CMD(lp) & MC_BUSY)) { \
234 unsigned long timeout = jiffies + 2; \
235 while (SMC_GET_MMU_CMD(lp) & MC_BUSY) { \
236 if (time_after(jiffies, timeout)) { \
237 netdev_dbg(dev, "timeout %s line %d\n", \
238 __FILE__, __LINE__); \
248 * this does a soft reset on the device
250 static void smc_reset(struct net_device *dev)
252 struct smc_local *lp = netdev_priv(dev);
253 void __iomem *ioaddr = lp->base;
254 unsigned int ctl, cfg;
255 struct sk_buff *pending_skb;
257 DBG(2, dev, "%s\n", __func__);
259 /* Disable all interrupts, block TX tasklet */
260 spin_lock_irq(&lp->lock);
261 SMC_SELECT_BANK(lp, 2);
262 SMC_SET_INT_MASK(lp, 0);
263 pending_skb = lp->pending_tx_skb;
264 lp->pending_tx_skb = NULL;
265 spin_unlock_irq(&lp->lock);
267 /* free any pending tx skb */
269 dev_kfree_skb(pending_skb);
270 dev->stats.tx_errors++;
271 dev->stats.tx_aborted_errors++;
275 * This resets the registers mostly to defaults, but doesn't
276 * affect EEPROM. That seems unnecessary
278 SMC_SELECT_BANK(lp, 0);
279 SMC_SET_RCR(lp, RCR_SOFTRST);
282 * Setup the Configuration Register
283 * This is necessary because the CONFIG_REG is not affected
286 SMC_SELECT_BANK(lp, 1);
288 cfg = CONFIG_DEFAULT;
291 * Setup for fast accesses if requested. If the card/system
292 * can't handle it then there will be no recovery except for
293 * a hard reset or power cycle
295 if (lp->cfg.flags & SMC91X_NOWAIT)
296 cfg |= CONFIG_NO_WAIT;
299 * Release from possible power-down state
300 * Configuration register is not affected by Soft Reset
302 cfg |= CONFIG_EPH_POWER_EN;
304 SMC_SET_CONFIG(lp, cfg);
306 /* this should pause enough for the chip to be happy */
308 * elaborate? What does the chip _need_? --jgarzik
310 * This seems to be undocumented, but something the original
311 * driver(s) have always done. Suspect undocumented timing
312 * info/determined empirically. --rmk
316 /* Disable transmit and receive functionality */
317 SMC_SELECT_BANK(lp, 0);
318 SMC_SET_RCR(lp, RCR_CLEAR);
319 SMC_SET_TCR(lp, TCR_CLEAR);
321 SMC_SELECT_BANK(lp, 1);
322 ctl = SMC_GET_CTL(lp) | CTL_LE_ENABLE;
325 * Set the control register to automatically release successfully
326 * transmitted packets, to make the best use out of our limited
329 if(!THROTTLE_TX_PKTS)
330 ctl |= CTL_AUTO_RELEASE;
332 ctl &= ~CTL_AUTO_RELEASE;
333 SMC_SET_CTL(lp, ctl);
336 SMC_SELECT_BANK(lp, 2);
337 SMC_SET_MMU_CMD(lp, MC_RESET);
338 SMC_WAIT_MMU_BUSY(lp);
342 * Enable Interrupts, Receive, and Transmit
344 static void smc_enable(struct net_device *dev)
346 struct smc_local *lp = netdev_priv(dev);
347 void __iomem *ioaddr = lp->base;
350 DBG(2, dev, "%s\n", __func__);
352 /* see the header file for options in TCR/RCR DEFAULT */
353 SMC_SELECT_BANK(lp, 0);
354 SMC_SET_TCR(lp, lp->tcr_cur_mode);
355 SMC_SET_RCR(lp, lp->rcr_cur_mode);
357 SMC_SELECT_BANK(lp, 1);
358 SMC_SET_MAC_ADDR(lp, dev->dev_addr);
360 /* now, enable interrupts */
361 mask = IM_EPH_INT|IM_RX_OVRN_INT|IM_RCV_INT;
362 if (lp->version >= (CHIP_91100 << 4))
364 SMC_SELECT_BANK(lp, 2);
365 SMC_SET_INT_MASK(lp, mask);
368 * From this point the register bank must _NOT_ be switched away
369 * to something else than bank 2 without proper locking against
370 * races with any tasklet or interrupt handlers until smc_shutdown()
371 * or smc_reset() is called.
376 * this puts the device in an inactive state
378 static void smc_shutdown(struct net_device *dev)
380 struct smc_local *lp = netdev_priv(dev);
381 void __iomem *ioaddr = lp->base;
382 struct sk_buff *pending_skb;
384 DBG(2, dev, "%s: %s\n", CARDNAME, __func__);
386 /* no more interrupts for me */
387 spin_lock_irq(&lp->lock);
388 SMC_SELECT_BANK(lp, 2);
389 SMC_SET_INT_MASK(lp, 0);
390 pending_skb = lp->pending_tx_skb;
391 lp->pending_tx_skb = NULL;
392 spin_unlock_irq(&lp->lock);
394 dev_kfree_skb(pending_skb);
396 /* and tell the card to stay away from that nasty outside world */
397 SMC_SELECT_BANK(lp, 0);
398 SMC_SET_RCR(lp, RCR_CLEAR);
399 SMC_SET_TCR(lp, TCR_CLEAR);
402 /* finally, shut the chip down */
403 SMC_SELECT_BANK(lp, 1);
404 SMC_SET_CONFIG(lp, SMC_GET_CONFIG(lp) & ~CONFIG_EPH_POWER_EN);
409 * This is the procedure to handle the receipt of a packet.
411 static inline void smc_rcv(struct net_device *dev)
413 struct smc_local *lp = netdev_priv(dev);
414 void __iomem *ioaddr = lp->base;
415 unsigned int packet_number, status, packet_len;
417 DBG(3, dev, "%s\n", __func__);
419 packet_number = SMC_GET_RXFIFO(lp);
420 if (unlikely(packet_number & RXFIFO_REMPTY)) {
421 PRINTK(dev, "smc_rcv with nothing on FIFO.\n");
425 /* read from start of packet */
426 SMC_SET_PTR(lp, PTR_READ | PTR_RCV | PTR_AUTOINC);
428 /* First two words are status and packet length */
429 SMC_GET_PKT_HDR(lp, status, packet_len);
430 packet_len &= 0x07ff; /* mask off top bits */
431 DBG(2, dev, "RX PNR 0x%x STATUS 0x%04x LENGTH 0x%04x (%d)\n",
432 packet_number, status, packet_len, packet_len);
435 if (unlikely(packet_len < 6 || status & RS_ERRORS)) {
436 if (status & RS_TOOLONG && packet_len <= (1514 + 4 + 6)) {
437 /* accept VLAN packets */
438 status &= ~RS_TOOLONG;
441 if (packet_len < 6) {
442 /* bloody hardware */
443 netdev_err(dev, "fubar (rxlen %u status %x\n",
445 status |= RS_TOOSHORT;
447 SMC_WAIT_MMU_BUSY(lp);
448 SMC_SET_MMU_CMD(lp, MC_RELEASE);
449 dev->stats.rx_errors++;
450 if (status & RS_ALGNERR)
451 dev->stats.rx_frame_errors++;
452 if (status & (RS_TOOSHORT | RS_TOOLONG))
453 dev->stats.rx_length_errors++;
454 if (status & RS_BADCRC)
455 dev->stats.rx_crc_errors++;
459 unsigned int data_len;
461 /* set multicast stats */
462 if (status & RS_MULTICAST)
463 dev->stats.multicast++;
466 * Actual payload is packet_len - 6 (or 5 if odd byte).
467 * We want skb_reserve(2) and the final ctrl word
468 * (2 bytes, possibly containing the payload odd byte).
469 * Furthermore, we add 2 bytes to allow rounding up to
470 * multiple of 4 bytes on 32 bit buses.
471 * Hence packet_len - 6 + 2 + 2 + 2.
473 skb = netdev_alloc_skb(dev, packet_len);
474 if (unlikely(skb == NULL)) {
475 SMC_WAIT_MMU_BUSY(lp);
476 SMC_SET_MMU_CMD(lp, MC_RELEASE);
477 dev->stats.rx_dropped++;
481 /* Align IP header to 32 bits */
484 /* BUG: the LAN91C111 rev A never sets this bit. Force it. */
485 if (lp->version == 0x90)
486 status |= RS_ODDFRAME;
489 * If odd length: packet_len - 5,
490 * otherwise packet_len - 6.
491 * With the trailing ctrl byte it's packet_len - 4.
493 data_len = packet_len - ((status & RS_ODDFRAME) ? 5 : 6);
494 data = skb_put(skb, data_len);
495 SMC_PULL_DATA(lp, data, packet_len - 4);
497 SMC_WAIT_MMU_BUSY(lp);
498 SMC_SET_MMU_CMD(lp, MC_RELEASE);
500 PRINT_PKT(data, packet_len - 4);
502 skb->protocol = eth_type_trans(skb, dev);
504 dev->stats.rx_packets++;
505 dev->stats.rx_bytes += data_len;
511 * On SMP we have the following problem:
513 * A = smc_hardware_send_pkt()
514 * B = smc_hard_start_xmit()
515 * C = smc_interrupt()
517 * A and B can never be executed simultaneously. However, at least on UP,
518 * it is possible (and even desirable) for C to interrupt execution of
519 * A or B in order to have better RX reliability and avoid overruns.
520 * C, just like A and B, must have exclusive access to the chip and
521 * each of them must lock against any other concurrent access.
522 * Unfortunately this is not possible to have C suspend execution of A or
523 * B taking place on another CPU. On UP this is no an issue since A and B
524 * are run from softirq context and C from hard IRQ context, and there is
525 * no other CPU where concurrent access can happen.
526 * If ever there is a way to force at least B and C to always be executed
527 * on the same CPU then we could use read/write locks to protect against
528 * any other concurrent access and C would always interrupt B. But life
529 * isn't that easy in a SMP world...
531 #define smc_special_trylock(lock, flags) \
534 local_irq_save(flags); \
535 __ret = spin_trylock(lock); \
537 local_irq_restore(flags); \
540 #define smc_special_lock(lock, flags) spin_lock_irqsave(lock, flags)
541 #define smc_special_unlock(lock, flags) spin_unlock_irqrestore(lock, flags)
543 #define smc_special_trylock(lock, flags) ((void)flags, true)
544 #define smc_special_lock(lock, flags) do { flags = 0; } while (0)
545 #define smc_special_unlock(lock, flags) do { flags = 0; } while (0)
549 * This is called to actually send a packet to the chip.
551 static void smc_hardware_send_pkt(unsigned long data)
553 struct net_device *dev = (struct net_device *)data;
554 struct smc_local *lp = netdev_priv(dev);
555 void __iomem *ioaddr = lp->base;
557 unsigned int packet_no, len;
561 DBG(3, dev, "%s\n", __func__);
563 if (!smc_special_trylock(&lp->lock, flags)) {
564 netif_stop_queue(dev);
565 tasklet_schedule(&lp->tx_task);
569 skb = lp->pending_tx_skb;
570 if (unlikely(!skb)) {
571 smc_special_unlock(&lp->lock, flags);
574 lp->pending_tx_skb = NULL;
576 packet_no = SMC_GET_AR(lp);
577 if (unlikely(packet_no & AR_FAILED)) {
578 netdev_err(dev, "Memory allocation failed.\n");
579 dev->stats.tx_errors++;
580 dev->stats.tx_fifo_errors++;
581 smc_special_unlock(&lp->lock, flags);
585 /* point to the beginning of the packet */
586 SMC_SET_PN(lp, packet_no);
587 SMC_SET_PTR(lp, PTR_AUTOINC);
591 DBG(2, dev, "TX PNR 0x%x LENGTH 0x%04x (%d) BUF 0x%p\n",
592 packet_no, len, len, buf);
596 * Send the packet length (+6 for status words, length, and ctl.
597 * The card will pad to 64 bytes with zeroes if packet is too small.
599 SMC_PUT_PKT_HDR(lp, 0, len + 6);
601 /* send the actual data */
602 SMC_PUSH_DATA(lp, buf, len & ~1);
604 /* Send final ctl word with the last byte if there is one */
605 SMC_outw(lp, ((len & 1) ? (0x2000 | buf[len - 1]) : 0), ioaddr,
609 * If THROTTLE_TX_PKTS is set, we stop the queue here. This will
610 * have the effect of having at most one packet queued for TX
611 * in the chip's memory at all time.
613 * If THROTTLE_TX_PKTS is not set then the queue is stopped only
614 * when memory allocation (MC_ALLOC) does not succeed right away.
616 if (THROTTLE_TX_PKTS)
617 netif_stop_queue(dev);
619 /* queue the packet for TX */
620 SMC_SET_MMU_CMD(lp, MC_ENQUEUE);
621 smc_special_unlock(&lp->lock, flags);
623 netif_trans_update(dev);
624 dev->stats.tx_packets++;
625 dev->stats.tx_bytes += len;
627 SMC_ENABLE_INT(lp, IM_TX_INT | IM_TX_EMPTY_INT);
629 done: if (!THROTTLE_TX_PKTS)
630 netif_wake_queue(dev);
632 dev_consume_skb_any(skb);
636 * Since I am not sure if I will have enough room in the chip's ram
637 * to store the packet, I call this routine which either sends it
638 * now, or set the card to generates an interrupt when ready
641 static int smc_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
643 struct smc_local *lp = netdev_priv(dev);
644 void __iomem *ioaddr = lp->base;
645 unsigned int numPages, poll_count, status;
648 DBG(3, dev, "%s\n", __func__);
650 BUG_ON(lp->pending_tx_skb != NULL);
653 * The MMU wants the number of pages to be the number of 256 bytes
654 * 'pages', minus 1 (since a packet can't ever have 0 pages :))
656 * The 91C111 ignores the size bits, but earlier models don't.
658 * Pkt size for allocating is data length +6 (for additional status
659 * words, length and ctl)
661 * If odd size then last byte is included in ctl word.
663 numPages = ((skb->len & ~1) + (6 - 1)) >> 8;
664 if (unlikely(numPages > 7)) {
665 netdev_warn(dev, "Far too big packet error.\n");
666 dev->stats.tx_errors++;
667 dev->stats.tx_dropped++;
668 dev_kfree_skb_any(skb);
672 smc_special_lock(&lp->lock, flags);
674 /* now, try to allocate the memory */
675 SMC_SET_MMU_CMD(lp, MC_ALLOC | numPages);
678 * Poll the chip for a short amount of time in case the
679 * allocation succeeds quickly.
681 poll_count = MEMORY_WAIT_TIME;
683 status = SMC_GET_INT(lp);
684 if (status & IM_ALLOC_INT) {
685 SMC_ACK_INT(lp, IM_ALLOC_INT);
688 } while (--poll_count);
690 smc_special_unlock(&lp->lock, flags);
692 lp->pending_tx_skb = skb;
694 /* oh well, wait until the chip finds memory later */
695 netif_stop_queue(dev);
696 DBG(2, dev, "TX memory allocation deferred.\n");
697 SMC_ENABLE_INT(lp, IM_ALLOC_INT);
700 * Allocation succeeded: push packet to the chip's own memory
703 smc_hardware_send_pkt((unsigned long)dev);
710 * This handles a TX interrupt, which is only called when:
711 * - a TX error occurred, or
712 * - CTL_AUTO_RELEASE is not set and TX of a packet completed.
714 static void smc_tx(struct net_device *dev)
716 struct smc_local *lp = netdev_priv(dev);
717 void __iomem *ioaddr = lp->base;
718 unsigned int saved_packet, packet_no, tx_status, pkt_len;
720 DBG(3, dev, "%s\n", __func__);
722 /* If the TX FIFO is empty then nothing to do */
723 packet_no = SMC_GET_TXFIFO(lp);
724 if (unlikely(packet_no & TXFIFO_TEMPTY)) {
725 PRINTK(dev, "smc_tx with nothing on FIFO.\n");
729 /* select packet to read from */
730 saved_packet = SMC_GET_PN(lp);
731 SMC_SET_PN(lp, packet_no);
733 /* read the first word (status word) from this packet */
734 SMC_SET_PTR(lp, PTR_AUTOINC | PTR_READ);
735 SMC_GET_PKT_HDR(lp, tx_status, pkt_len);
736 DBG(2, dev, "TX STATUS 0x%04x PNR 0x%02x\n",
737 tx_status, packet_no);
739 if (!(tx_status & ES_TX_SUC))
740 dev->stats.tx_errors++;
742 if (tx_status & ES_LOSTCARR)
743 dev->stats.tx_carrier_errors++;
745 if (tx_status & (ES_LATCOL | ES_16COL)) {
746 PRINTK(dev, "%s occurred on last xmit\n",
747 (tx_status & ES_LATCOL) ?
748 "late collision" : "too many collisions");
749 dev->stats.tx_window_errors++;
750 if (!(dev->stats.tx_window_errors & 63) && net_ratelimit()) {
751 netdev_info(dev, "unexpectedly large number of bad collisions. Please check duplex setting.\n");
755 /* kill the packet */
756 SMC_WAIT_MMU_BUSY(lp);
757 SMC_SET_MMU_CMD(lp, MC_FREEPKT);
759 /* Don't restore Packet Number Reg until busy bit is cleared */
760 SMC_WAIT_MMU_BUSY(lp);
761 SMC_SET_PN(lp, saved_packet);
763 /* re-enable transmit */
764 SMC_SELECT_BANK(lp, 0);
765 SMC_SET_TCR(lp, lp->tcr_cur_mode);
766 SMC_SELECT_BANK(lp, 2);
770 /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
772 static void smc_mii_out(struct net_device *dev, unsigned int val, int bits)
774 struct smc_local *lp = netdev_priv(dev);
775 void __iomem *ioaddr = lp->base;
776 unsigned int mii_reg, mask;
778 mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO);
781 for (mask = 1 << (bits - 1); mask; mask >>= 1) {
787 SMC_SET_MII(lp, mii_reg);
789 SMC_SET_MII(lp, mii_reg | MII_MCLK);
794 static unsigned int smc_mii_in(struct net_device *dev, int bits)
796 struct smc_local *lp = netdev_priv(dev);
797 void __iomem *ioaddr = lp->base;
798 unsigned int mii_reg, mask, val;
800 mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO);
801 SMC_SET_MII(lp, mii_reg);
803 for (mask = 1 << (bits - 1), val = 0; mask; mask >>= 1) {
804 if (SMC_GET_MII(lp) & MII_MDI)
807 SMC_SET_MII(lp, mii_reg);
809 SMC_SET_MII(lp, mii_reg | MII_MCLK);
817 * Reads a register from the MII Management serial interface
819 static int smc_phy_read(struct net_device *dev, int phyaddr, int phyreg)
821 struct smc_local *lp = netdev_priv(dev);
822 void __iomem *ioaddr = lp->base;
823 unsigned int phydata;
825 SMC_SELECT_BANK(lp, 3);
828 smc_mii_out(dev, 0xffffffff, 32);
830 /* Start code (01) + read (10) + phyaddr + phyreg */
831 smc_mii_out(dev, 6 << 10 | phyaddr << 5 | phyreg, 14);
833 /* Turnaround (2bits) + phydata */
834 phydata = smc_mii_in(dev, 18);
836 /* Return to idle state */
837 SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO));
839 DBG(3, dev, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
840 __func__, phyaddr, phyreg, phydata);
842 SMC_SELECT_BANK(lp, 2);
847 * Writes a register to the MII Management serial interface
849 static void smc_phy_write(struct net_device *dev, int phyaddr, int phyreg,
852 struct smc_local *lp = netdev_priv(dev);
853 void __iomem *ioaddr = lp->base;
855 SMC_SELECT_BANK(lp, 3);
858 smc_mii_out(dev, 0xffffffff, 32);
860 /* Start code (01) + write (01) + phyaddr + phyreg + turnaround + phydata */
861 smc_mii_out(dev, 5 << 28 | phyaddr << 23 | phyreg << 18 | 2 << 16 | phydata, 32);
863 /* Return to idle state */
864 SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO));
866 DBG(3, dev, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
867 __func__, phyaddr, phyreg, phydata);
869 SMC_SELECT_BANK(lp, 2);
873 * Finds and reports the PHY address
875 static void smc_phy_detect(struct net_device *dev)
877 struct smc_local *lp = netdev_priv(dev);
880 DBG(2, dev, "%s\n", __func__);
885 * Scan all 32 PHY addresses if necessary, starting at
886 * PHY#1 to PHY#31, and then PHY#0 last.
888 for (phyaddr = 1; phyaddr < 33; ++phyaddr) {
889 unsigned int id1, id2;
891 /* Read the PHY identifiers */
892 id1 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID1);
893 id2 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID2);
895 DBG(3, dev, "phy_id1=0x%x, phy_id2=0x%x\n",
898 /* Make sure it is a valid identifier */
899 if (id1 != 0x0000 && id1 != 0xffff && id1 != 0x8000 &&
900 id2 != 0x0000 && id2 != 0xffff && id2 != 0x8000) {
901 /* Save the PHY's address */
902 lp->mii.phy_id = phyaddr & 31;
903 lp->phy_type = id1 << 16 | id2;
910 * Sets the PHY to a configuration as determined by the user
912 static int smc_phy_fixed(struct net_device *dev)
914 struct smc_local *lp = netdev_priv(dev);
915 void __iomem *ioaddr = lp->base;
916 int phyaddr = lp->mii.phy_id;
919 DBG(3, dev, "%s\n", __func__);
921 /* Enter Link Disable state */
922 cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG);
923 cfg1 |= PHY_CFG1_LNKDIS;
924 smc_phy_write(dev, phyaddr, PHY_CFG1_REG, cfg1);
927 * Set our fixed capabilities
928 * Disable auto-negotiation
933 bmcr |= BMCR_FULLDPLX;
935 if (lp->ctl_rspeed == 100)
936 bmcr |= BMCR_SPEED100;
938 /* Write our capabilities to the phy control register */
939 smc_phy_write(dev, phyaddr, MII_BMCR, bmcr);
941 /* Re-Configure the Receive/Phy Control register */
942 SMC_SELECT_BANK(lp, 0);
943 SMC_SET_RPC(lp, lp->rpc_cur_mode);
944 SMC_SELECT_BANK(lp, 2);
950 * smc_phy_reset - reset the phy
954 * Issue a software reset for the specified PHY and
955 * wait up to 100ms for the reset to complete. We should
956 * not access the PHY for 50ms after issuing the reset.
958 * The time to wait appears to be dependent on the PHY.
960 * Must be called with lp->lock locked.
962 static int smc_phy_reset(struct net_device *dev, int phy)
964 struct smc_local *lp = netdev_priv(dev);
968 smc_phy_write(dev, phy, MII_BMCR, BMCR_RESET);
970 for (timeout = 2; timeout; timeout--) {
971 spin_unlock_irq(&lp->lock);
973 spin_lock_irq(&lp->lock);
975 bmcr = smc_phy_read(dev, phy, MII_BMCR);
976 if (!(bmcr & BMCR_RESET))
980 return bmcr & BMCR_RESET;
984 * smc_phy_powerdown - powerdown phy
987 * Power down the specified PHY
989 static void smc_phy_powerdown(struct net_device *dev)
991 struct smc_local *lp = netdev_priv(dev);
993 int phy = lp->mii.phy_id;
995 if (lp->phy_type == 0)
998 /* We need to ensure that no calls to smc_phy_configure are
1001 cancel_work_sync(&lp->phy_configure);
1003 bmcr = smc_phy_read(dev, phy, MII_BMCR);
1004 smc_phy_write(dev, phy, MII_BMCR, bmcr | BMCR_PDOWN);
1008 * smc_phy_check_media - check the media status and adjust TCR
1010 * @init: set true for initialisation
1012 * Select duplex mode depending on negotiation state. This
1013 * also updates our carrier state.
1015 static void smc_phy_check_media(struct net_device *dev, int init)
1017 struct smc_local *lp = netdev_priv(dev);
1018 void __iomem *ioaddr = lp->base;
1020 if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) {
1021 /* duplex state has changed */
1022 if (lp->mii.full_duplex) {
1023 lp->tcr_cur_mode |= TCR_SWFDUP;
1025 lp->tcr_cur_mode &= ~TCR_SWFDUP;
1028 SMC_SELECT_BANK(lp, 0);
1029 SMC_SET_TCR(lp, lp->tcr_cur_mode);
1034 * Configures the specified PHY through the MII management interface
1035 * using Autonegotiation.
1036 * Calls smc_phy_fixed() if the user has requested a certain config.
1037 * If RPC ANEG bit is set, the media selection is dependent purely on
1038 * the selection by the MII (either in the MII BMCR reg or the result
1039 * of autonegotiation.) If the RPC ANEG bit is cleared, the selection
1040 * is controlled by the RPC SPEED and RPC DPLX bits.
1042 static void smc_phy_configure(struct work_struct *work)
1044 struct smc_local *lp =
1045 container_of(work, struct smc_local, phy_configure);
1046 struct net_device *dev = lp->dev;
1047 void __iomem *ioaddr = lp->base;
1048 int phyaddr = lp->mii.phy_id;
1049 int my_phy_caps; /* My PHY capabilities */
1050 int my_ad_caps; /* My Advertised capabilities */
1053 DBG(3, dev, "smc_program_phy()\n");
1055 spin_lock_irq(&lp->lock);
1058 * We should not be called if phy_type is zero.
1060 if (lp->phy_type == 0)
1061 goto smc_phy_configure_exit;
1063 if (smc_phy_reset(dev, phyaddr)) {
1064 netdev_info(dev, "PHY reset timed out\n");
1065 goto smc_phy_configure_exit;
1069 * Enable PHY Interrupts (for register 18)
1070 * Interrupts listed here are disabled
1072 smc_phy_write(dev, phyaddr, PHY_MASK_REG,
1073 PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD |
1074 PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB |
1075 PHY_INT_SPDDET | PHY_INT_DPLXDET);
1077 /* Configure the Receive/Phy Control register */
1078 SMC_SELECT_BANK(lp, 0);
1079 SMC_SET_RPC(lp, lp->rpc_cur_mode);
1081 /* If the user requested no auto neg, then go set his request */
1082 if (lp->mii.force_media) {
1084 goto smc_phy_configure_exit;
1087 /* Copy our capabilities from MII_BMSR to MII_ADVERTISE */
1088 my_phy_caps = smc_phy_read(dev, phyaddr, MII_BMSR);
1090 if (!(my_phy_caps & BMSR_ANEGCAPABLE)) {
1091 netdev_info(dev, "Auto negotiation NOT supported\n");
1093 goto smc_phy_configure_exit;
1096 my_ad_caps = ADVERTISE_CSMA; /* I am CSMA capable */
1098 if (my_phy_caps & BMSR_100BASE4)
1099 my_ad_caps |= ADVERTISE_100BASE4;
1100 if (my_phy_caps & BMSR_100FULL)
1101 my_ad_caps |= ADVERTISE_100FULL;
1102 if (my_phy_caps & BMSR_100HALF)
1103 my_ad_caps |= ADVERTISE_100HALF;
1104 if (my_phy_caps & BMSR_10FULL)
1105 my_ad_caps |= ADVERTISE_10FULL;
1106 if (my_phy_caps & BMSR_10HALF)
1107 my_ad_caps |= ADVERTISE_10HALF;
1109 /* Disable capabilities not selected by our user */
1110 if (lp->ctl_rspeed != 100)
1111 my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF);
1113 if (!lp->ctl_rfduplx)
1114 my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL);
1116 /* Update our Auto-Neg Advertisement Register */
1117 smc_phy_write(dev, phyaddr, MII_ADVERTISE, my_ad_caps);
1118 lp->mii.advertising = my_ad_caps;
1121 * Read the register back. Without this, it appears that when
1122 * auto-negotiation is restarted, sometimes it isn't ready and
1123 * the link does not come up.
1125 status = smc_phy_read(dev, phyaddr, MII_ADVERTISE);
1127 DBG(2, dev, "phy caps=%x\n", my_phy_caps);
1128 DBG(2, dev, "phy advertised caps=%x\n", my_ad_caps);
1130 /* Restart auto-negotiation process in order to advertise my caps */
1131 smc_phy_write(dev, phyaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1133 smc_phy_check_media(dev, 1);
1135 smc_phy_configure_exit:
1136 SMC_SELECT_BANK(lp, 2);
1137 spin_unlock_irq(&lp->lock);
1143 * Purpose: Handle interrupts relating to PHY register 18. This is
1144 * called from the "hard" interrupt handler under our private spinlock.
1146 static void smc_phy_interrupt(struct net_device *dev)
1148 struct smc_local *lp = netdev_priv(dev);
1149 int phyaddr = lp->mii.phy_id;
1152 DBG(2, dev, "%s\n", __func__);
1154 if (lp->phy_type == 0)
1158 smc_phy_check_media(dev, 0);
1160 /* Read PHY Register 18, Status Output */
1161 phy18 = smc_phy_read(dev, phyaddr, PHY_INT_REG);
1162 if ((phy18 & PHY_INT_INT) == 0)
1167 /*--- END PHY CONTROL AND CONFIGURATION-------------------------------------*/
1169 static void smc_10bt_check_media(struct net_device *dev, int init)
1171 struct smc_local *lp = netdev_priv(dev);
1172 void __iomem *ioaddr = lp->base;
1173 unsigned int old_carrier, new_carrier;
1175 old_carrier = netif_carrier_ok(dev) ? 1 : 0;
1177 SMC_SELECT_BANK(lp, 0);
1178 new_carrier = (SMC_GET_EPH_STATUS(lp) & ES_LINK_OK) ? 1 : 0;
1179 SMC_SELECT_BANK(lp, 2);
1181 if (init || (old_carrier != new_carrier)) {
1183 netif_carrier_off(dev);
1185 netif_carrier_on(dev);
1187 if (netif_msg_link(lp))
1188 netdev_info(dev, "link %s\n",
1189 new_carrier ? "up" : "down");
1193 static void smc_eph_interrupt(struct net_device *dev)
1195 struct smc_local *lp = netdev_priv(dev);
1196 void __iomem *ioaddr = lp->base;
1199 smc_10bt_check_media(dev, 0);
1201 SMC_SELECT_BANK(lp, 1);
1202 ctl = SMC_GET_CTL(lp);
1203 SMC_SET_CTL(lp, ctl & ~CTL_LE_ENABLE);
1204 SMC_SET_CTL(lp, ctl);
1205 SMC_SELECT_BANK(lp, 2);
1209 * This is the main routine of the driver, to handle the device when
1210 * it needs some attention.
1212 static irqreturn_t smc_interrupt(int irq, void *dev_id)
1214 struct net_device *dev = dev_id;
1215 struct smc_local *lp = netdev_priv(dev);
1216 void __iomem *ioaddr = lp->base;
1217 int status, mask, timeout, card_stats;
1220 DBG(3, dev, "%s\n", __func__);
1222 spin_lock(&lp->lock);
1224 /* A preamble may be used when there is a potential race
1225 * between the interruptible transmit functions and this
1227 SMC_INTERRUPT_PREAMBLE;
1229 saved_pointer = SMC_GET_PTR(lp);
1230 mask = SMC_GET_INT_MASK(lp);
1231 SMC_SET_INT_MASK(lp, 0);
1233 /* set a timeout value, so I don't stay here forever */
1234 timeout = MAX_IRQ_LOOPS;
1237 status = SMC_GET_INT(lp);
1239 DBG(2, dev, "INT 0x%02x MASK 0x%02x MEM 0x%04x FIFO 0x%04x\n",
1241 ({ int meminfo; SMC_SELECT_BANK(lp, 0);
1242 meminfo = SMC_GET_MIR(lp);
1243 SMC_SELECT_BANK(lp, 2); meminfo; }),
1250 if (status & IM_TX_INT) {
1251 /* do this before RX as it will free memory quickly */
1252 DBG(3, dev, "TX int\n");
1254 SMC_ACK_INT(lp, IM_TX_INT);
1255 if (THROTTLE_TX_PKTS)
1256 netif_wake_queue(dev);
1257 } else if (status & IM_RCV_INT) {
1258 DBG(3, dev, "RX irq\n");
1260 } else if (status & IM_ALLOC_INT) {
1261 DBG(3, dev, "Allocation irq\n");
1262 tasklet_hi_schedule(&lp->tx_task);
1263 mask &= ~IM_ALLOC_INT;
1264 } else if (status & IM_TX_EMPTY_INT) {
1265 DBG(3, dev, "TX empty\n");
1266 mask &= ~IM_TX_EMPTY_INT;
1269 SMC_SELECT_BANK(lp, 0);
1270 card_stats = SMC_GET_COUNTER(lp);
1271 SMC_SELECT_BANK(lp, 2);
1273 /* single collisions */
1274 dev->stats.collisions += card_stats & 0xF;
1277 /* multiple collisions */
1278 dev->stats.collisions += card_stats & 0xF;
1279 } else if (status & IM_RX_OVRN_INT) {
1280 DBG(1, dev, "RX overrun (EPH_ST 0x%04x)\n",
1281 ({ int eph_st; SMC_SELECT_BANK(lp, 0);
1282 eph_st = SMC_GET_EPH_STATUS(lp);
1283 SMC_SELECT_BANK(lp, 2); eph_st; }));
1284 SMC_ACK_INT(lp, IM_RX_OVRN_INT);
1285 dev->stats.rx_errors++;
1286 dev->stats.rx_fifo_errors++;
1287 } else if (status & IM_EPH_INT) {
1288 smc_eph_interrupt(dev);
1289 } else if (status & IM_MDINT) {
1290 SMC_ACK_INT(lp, IM_MDINT);
1291 smc_phy_interrupt(dev);
1292 } else if (status & IM_ERCV_INT) {
1293 SMC_ACK_INT(lp, IM_ERCV_INT);
1294 PRINTK(dev, "UNSUPPORTED: ERCV INTERRUPT\n");
1296 } while (--timeout);
1298 /* restore register states */
1299 SMC_SET_PTR(lp, saved_pointer);
1300 SMC_SET_INT_MASK(lp, mask);
1301 spin_unlock(&lp->lock);
1303 #ifndef CONFIG_NET_POLL_CONTROLLER
1304 if (timeout == MAX_IRQ_LOOPS)
1305 PRINTK(dev, "spurious interrupt (mask = 0x%02x)\n",
1308 DBG(3, dev, "Interrupt done (%d loops)\n",
1309 MAX_IRQ_LOOPS - timeout);
1312 * We return IRQ_HANDLED unconditionally here even if there was
1313 * nothing to do. There is a possibility that a packet might
1314 * get enqueued into the chip right after TX_EMPTY_INT is raised
1315 * but just before the CPU acknowledges the IRQ.
1316 * Better take an unneeded IRQ in some occasions than complexifying
1317 * the code for all cases.
1322 #ifdef CONFIG_NET_POLL_CONTROLLER
1324 * Polling receive - used by netconsole and other diagnostic tools
1325 * to allow network i/o with interrupts disabled.
1327 static void smc_poll_controller(struct net_device *dev)
1329 disable_irq(dev->irq);
1330 smc_interrupt(dev->irq, dev);
1331 enable_irq(dev->irq);
1335 /* Our watchdog timed out. Called by the networking layer */
1336 static void smc_timeout(struct net_device *dev)
1338 struct smc_local *lp = netdev_priv(dev);
1339 void __iomem *ioaddr = lp->base;
1340 int status, mask, eph_st, meminfo, fifo;
1342 DBG(2, dev, "%s\n", __func__);
1344 spin_lock_irq(&lp->lock);
1345 status = SMC_GET_INT(lp);
1346 mask = SMC_GET_INT_MASK(lp);
1347 fifo = SMC_GET_FIFO(lp);
1348 SMC_SELECT_BANK(lp, 0);
1349 eph_st = SMC_GET_EPH_STATUS(lp);
1350 meminfo = SMC_GET_MIR(lp);
1351 SMC_SELECT_BANK(lp, 2);
1352 spin_unlock_irq(&lp->lock);
1353 PRINTK(dev, "TX timeout (INT 0x%02x INTMASK 0x%02x MEM 0x%04x FIFO 0x%04x EPH_ST 0x%04x)\n",
1354 status, mask, meminfo, fifo, eph_st);
1360 * Reconfiguring the PHY doesn't seem like a bad idea here, but
1361 * smc_phy_configure() calls msleep() which calls schedule_timeout()
1362 * which calls schedule(). Hence we use a work queue.
1364 if (lp->phy_type != 0)
1365 schedule_work(&lp->phy_configure);
1367 /* We can accept TX packets again */
1368 netif_trans_update(dev); /* prevent tx timeout */
1369 netif_wake_queue(dev);
1373 * This routine will, depending on the values passed to it,
1374 * either make it accept multicast packets, go into
1375 * promiscuous mode (for TCPDUMP and cousins) or accept
1376 * a select set of multicast packets
1378 static void smc_set_multicast_list(struct net_device *dev)
1380 struct smc_local *lp = netdev_priv(dev);
1381 void __iomem *ioaddr = lp->base;
1382 unsigned char multicast_table[8];
1383 int update_multicast = 0;
1385 DBG(2, dev, "%s\n", __func__);
1387 if (dev->flags & IFF_PROMISC) {
1388 DBG(2, dev, "RCR_PRMS\n");
1389 lp->rcr_cur_mode |= RCR_PRMS;
1392 /* BUG? I never disable promiscuous mode if multicasting was turned on.
1393 Now, I turn off promiscuous mode, but I don't do anything to multicasting
1394 when promiscuous mode is turned on.
1398 * Here, I am setting this to accept all multicast packets.
1399 * I don't need to zero the multicast table, because the flag is
1400 * checked before the table is
1402 else if (dev->flags & IFF_ALLMULTI || netdev_mc_count(dev) > 16) {
1403 DBG(2, dev, "RCR_ALMUL\n");
1404 lp->rcr_cur_mode |= RCR_ALMUL;
1408 * This sets the internal hardware table to filter out unwanted
1409 * multicast packets before they take up memory.
1411 * The SMC chip uses a hash table where the high 6 bits of the CRC of
1412 * address are the offset into the table. If that bit is 1, then the
1413 * multicast packet is accepted. Otherwise, it's dropped silently.
1415 * To use the 6 bits as an offset into the table, the high 3 bits are
1416 * the number of the 8 bit register, while the low 3 bits are the bit
1417 * within that register.
1419 else if (!netdev_mc_empty(dev)) {
1420 struct netdev_hw_addr *ha;
1422 /* table for flipping the order of 3 bits */
1423 static const unsigned char invert3[] = {0, 4, 2, 6, 1, 5, 3, 7};
1425 /* start with a table of all zeros: reject all */
1426 memset(multicast_table, 0, sizeof(multicast_table));
1428 netdev_for_each_mc_addr(ha, dev) {
1431 /* only use the low order bits */
1432 position = crc32_le(~0, ha->addr, 6) & 0x3f;
1434 /* do some messy swapping to put the bit in the right spot */
1435 multicast_table[invert3[position&7]] |=
1436 (1<<invert3[(position>>3)&7]);
1439 /* be sure I get rid of flags I might have set */
1440 lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL);
1442 /* now, the table can be loaded into the chipset */
1443 update_multicast = 1;
1445 DBG(2, dev, "~(RCR_PRMS|RCR_ALMUL)\n");
1446 lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL);
1449 * since I'm disabling all multicast entirely, I need to
1450 * clear the multicast list
1452 memset(multicast_table, 0, sizeof(multicast_table));
1453 update_multicast = 1;
1456 spin_lock_irq(&lp->lock);
1457 SMC_SELECT_BANK(lp, 0);
1458 SMC_SET_RCR(lp, lp->rcr_cur_mode);
1459 if (update_multicast) {
1460 SMC_SELECT_BANK(lp, 3);
1461 SMC_SET_MCAST(lp, multicast_table);
1463 SMC_SELECT_BANK(lp, 2);
1464 spin_unlock_irq(&lp->lock);
1469 * Open and Initialize the board
1471 * Set up everything, reset the card, etc..
1474 smc_open(struct net_device *dev)
1476 struct smc_local *lp = netdev_priv(dev);
1478 DBG(2, dev, "%s\n", __func__);
1480 /* Setup the default Register Modes */
1481 lp->tcr_cur_mode = TCR_DEFAULT;
1482 lp->rcr_cur_mode = RCR_DEFAULT;
1483 lp->rpc_cur_mode = RPC_DEFAULT |
1484 lp->cfg.leda << RPC_LSXA_SHFT |
1485 lp->cfg.ledb << RPC_LSXB_SHFT;
1488 * If we are not using a MII interface, we need to
1489 * monitor our own carrier signal to detect faults.
1491 if (lp->phy_type == 0)
1492 lp->tcr_cur_mode |= TCR_MON_CSN;
1494 /* reset the hardware */
1498 /* Configure the PHY, initialize the link state */
1499 if (lp->phy_type != 0)
1500 smc_phy_configure(&lp->phy_configure);
1502 spin_lock_irq(&lp->lock);
1503 smc_10bt_check_media(dev, 1);
1504 spin_unlock_irq(&lp->lock);
1507 netif_start_queue(dev);
1514 * this makes the board clean up everything that it can
1515 * and not talk to the outside world. Caused by
1516 * an 'ifconfig ethX down'
1518 static int smc_close(struct net_device *dev)
1520 struct smc_local *lp = netdev_priv(dev);
1522 DBG(2, dev, "%s\n", __func__);
1524 netif_stop_queue(dev);
1525 netif_carrier_off(dev);
1527 /* clear everything */
1529 tasklet_kill(&lp->tx_task);
1530 smc_phy_powerdown(dev);
1538 smc_ethtool_get_link_ksettings(struct net_device *dev,
1539 struct ethtool_link_ksettings *cmd)
1541 struct smc_local *lp = netdev_priv(dev);
1544 if (lp->phy_type != 0) {
1545 spin_lock_irq(&lp->lock);
1546 ret = mii_ethtool_get_link_ksettings(&lp->mii, cmd);
1547 spin_unlock_irq(&lp->lock);
1549 u32 supported = SUPPORTED_10baseT_Half |
1550 SUPPORTED_10baseT_Full |
1551 SUPPORTED_TP | SUPPORTED_AUI;
1553 if (lp->ctl_rspeed == 10)
1554 cmd->base.speed = SPEED_10;
1555 else if (lp->ctl_rspeed == 100)
1556 cmd->base.speed = SPEED_100;
1558 cmd->base.autoneg = AUTONEG_DISABLE;
1560 cmd->base.duplex = lp->tcr_cur_mode & TCR_SWFDUP ?
1561 DUPLEX_FULL : DUPLEX_HALF;
1563 ethtool_convert_legacy_u32_to_link_mode(
1564 cmd->link_modes.supported, supported);
1573 smc_ethtool_set_link_ksettings(struct net_device *dev,
1574 const struct ethtool_link_ksettings *cmd)
1576 struct smc_local *lp = netdev_priv(dev);
1579 if (lp->phy_type != 0) {
1580 spin_lock_irq(&lp->lock);
1581 ret = mii_ethtool_set_link_ksettings(&lp->mii, cmd);
1582 spin_unlock_irq(&lp->lock);
1584 if (cmd->base.autoneg != AUTONEG_DISABLE ||
1585 cmd->base.speed != SPEED_10 ||
1586 (cmd->base.duplex != DUPLEX_HALF &&
1587 cmd->base.duplex != DUPLEX_FULL) ||
1588 (cmd->base.port != PORT_TP && cmd->base.port != PORT_AUI))
1591 // lp->port = cmd->base.port;
1592 lp->ctl_rfduplx = cmd->base.duplex == DUPLEX_FULL;
1594 // if (netif_running(dev))
1595 // smc_set_port(dev);
1604 smc_ethtool_getdrvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1606 strlcpy(info->driver, CARDNAME, sizeof(info->driver));
1607 strlcpy(info->version, version, sizeof(info->version));
1608 strlcpy(info->bus_info, dev_name(dev->dev.parent),
1609 sizeof(info->bus_info));
1612 static int smc_ethtool_nwayreset(struct net_device *dev)
1614 struct smc_local *lp = netdev_priv(dev);
1617 if (lp->phy_type != 0) {
1618 spin_lock_irq(&lp->lock);
1619 ret = mii_nway_restart(&lp->mii);
1620 spin_unlock_irq(&lp->lock);
1626 static u32 smc_ethtool_getmsglevel(struct net_device *dev)
1628 struct smc_local *lp = netdev_priv(dev);
1629 return lp->msg_enable;
1632 static void smc_ethtool_setmsglevel(struct net_device *dev, u32 level)
1634 struct smc_local *lp = netdev_priv(dev);
1635 lp->msg_enable = level;
1638 static int smc_write_eeprom_word(struct net_device *dev, u16 addr, u16 word)
1641 struct smc_local *lp = netdev_priv(dev);
1642 void __iomem *ioaddr = lp->base;
1644 spin_lock_irq(&lp->lock);
1645 /* load word into GP register */
1646 SMC_SELECT_BANK(lp, 1);
1647 SMC_SET_GP(lp, word);
1648 /* set the address to put the data in EEPROM */
1649 SMC_SELECT_BANK(lp, 2);
1650 SMC_SET_PTR(lp, addr);
1651 /* tell it to write */
1652 SMC_SELECT_BANK(lp, 1);
1653 ctl = SMC_GET_CTL(lp);
1654 SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_STORE));
1655 /* wait for it to finish */
1658 } while (SMC_GET_CTL(lp) & CTL_STORE);
1660 SMC_SET_CTL(lp, ctl);
1661 SMC_SELECT_BANK(lp, 2);
1662 spin_unlock_irq(&lp->lock);
1666 static int smc_read_eeprom_word(struct net_device *dev, u16 addr, u16 *word)
1669 struct smc_local *lp = netdev_priv(dev);
1670 void __iomem *ioaddr = lp->base;
1672 spin_lock_irq(&lp->lock);
1673 /* set the EEPROM address to get the data from */
1674 SMC_SELECT_BANK(lp, 2);
1675 SMC_SET_PTR(lp, addr | PTR_READ);
1676 /* tell it to load */
1677 SMC_SELECT_BANK(lp, 1);
1678 SMC_SET_GP(lp, 0xffff); /* init to known */
1679 ctl = SMC_GET_CTL(lp);
1680 SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_RELOAD));
1681 /* wait for it to finish */
1684 } while (SMC_GET_CTL(lp) & CTL_RELOAD);
1685 /* read word from GP register */
1686 *word = SMC_GET_GP(lp);
1688 SMC_SET_CTL(lp, ctl);
1689 SMC_SELECT_BANK(lp, 2);
1690 spin_unlock_irq(&lp->lock);
1694 static int smc_ethtool_geteeprom_len(struct net_device *dev)
1699 static int smc_ethtool_geteeprom(struct net_device *dev,
1700 struct ethtool_eeprom *eeprom, u8 *data)
1705 DBG(1, dev, "Reading %d bytes at %d(0x%x)\n",
1706 eeprom->len, eeprom->offset, eeprom->offset);
1707 imax = smc_ethtool_geteeprom_len(dev);
1708 for (i = 0; i < eeprom->len; i += 2) {
1711 int offset = i + eeprom->offset;
1714 ret = smc_read_eeprom_word(dev, offset >> 1, &wbuf);
1717 DBG(2, dev, "Read 0x%x from 0x%x\n", wbuf, offset >> 1);
1718 data[i] = (wbuf >> 8) & 0xff;
1719 data[i+1] = wbuf & 0xff;
1724 static int smc_ethtool_seteeprom(struct net_device *dev,
1725 struct ethtool_eeprom *eeprom, u8 *data)
1730 DBG(1, dev, "Writing %d bytes to %d(0x%x)\n",
1731 eeprom->len, eeprom->offset, eeprom->offset);
1732 imax = smc_ethtool_geteeprom_len(dev);
1733 for (i = 0; i < eeprom->len; i += 2) {
1736 int offset = i + eeprom->offset;
1739 wbuf = (data[i] << 8) | data[i + 1];
1740 DBG(2, dev, "Writing 0x%x to 0x%x\n", wbuf, offset >> 1);
1741 ret = smc_write_eeprom_word(dev, offset >> 1, wbuf);
1749 static const struct ethtool_ops smc_ethtool_ops = {
1750 .get_drvinfo = smc_ethtool_getdrvinfo,
1752 .get_msglevel = smc_ethtool_getmsglevel,
1753 .set_msglevel = smc_ethtool_setmsglevel,
1754 .nway_reset = smc_ethtool_nwayreset,
1755 .get_link = ethtool_op_get_link,
1756 .get_eeprom_len = smc_ethtool_geteeprom_len,
1757 .get_eeprom = smc_ethtool_geteeprom,
1758 .set_eeprom = smc_ethtool_seteeprom,
1759 .get_link_ksettings = smc_ethtool_get_link_ksettings,
1760 .set_link_ksettings = smc_ethtool_set_link_ksettings,
1763 static const struct net_device_ops smc_netdev_ops = {
1764 .ndo_open = smc_open,
1765 .ndo_stop = smc_close,
1766 .ndo_start_xmit = smc_hard_start_xmit,
1767 .ndo_tx_timeout = smc_timeout,
1768 .ndo_set_rx_mode = smc_set_multicast_list,
1769 .ndo_validate_addr = eth_validate_addr,
1770 .ndo_set_mac_address = eth_mac_addr,
1771 #ifdef CONFIG_NET_POLL_CONTROLLER
1772 .ndo_poll_controller = smc_poll_controller,
1779 * This routine has a simple purpose -- make the SMC chip generate an
1780 * interrupt, so an auto-detect routine can detect it, and find the IRQ,
1783 * does this still work?
1785 * I just deleted auto_irq.c, since it was never built...
1788 static int smc_findirq(struct smc_local *lp)
1790 void __iomem *ioaddr = lp->base;
1792 unsigned long cookie;
1794 DBG(2, lp->dev, "%s: %s\n", CARDNAME, __func__);
1796 cookie = probe_irq_on();
1799 * What I try to do here is trigger an ALLOC_INT. This is done
1800 * by allocating a small chunk of memory, which will give an interrupt
1803 /* enable ALLOCation interrupts ONLY */
1804 SMC_SELECT_BANK(lp, 2);
1805 SMC_SET_INT_MASK(lp, IM_ALLOC_INT);
1808 * Allocate 512 bytes of memory. Note that the chip was just
1809 * reset so all the memory is available
1811 SMC_SET_MMU_CMD(lp, MC_ALLOC | 1);
1814 * Wait until positive that the interrupt has been generated
1819 int_status = SMC_GET_INT(lp);
1820 if (int_status & IM_ALLOC_INT)
1821 break; /* got the interrupt */
1822 } while (--timeout);
1825 * there is really nothing that I can do here if timeout fails,
1826 * as autoirq_report will return a 0 anyway, which is what I
1827 * want in this case. Plus, the clean up is needed in both
1831 /* and disable all interrupts again */
1832 SMC_SET_INT_MASK(lp, 0);
1834 /* and return what I found */
1835 return probe_irq_off(cookie);
1839 * Function: smc_probe(unsigned long ioaddr)
1842 * Tests to see if a given ioaddr points to an SMC91x chip.
1843 * Returns a 0 on success
1846 * (1) see if the high byte of BANK_SELECT is 0x33
1847 * (2) compare the ioaddr with the base register's address
1848 * (3) see if I recognize the chip ID in the appropriate register
1850 * Here I do typical initialization tasks.
1852 * o Initialize the structure if needed
1853 * o print out my vanity message if not done so already
1854 * o print out what type of hardware is detected
1855 * o print out the ethernet address
1857 * o set up my private data
1858 * o configure the dev structure with my subroutines
1859 * o actually GRAB the irq.
1862 static int smc_probe(struct net_device *dev, void __iomem *ioaddr,
1863 unsigned long irq_flags)
1865 struct smc_local *lp = netdev_priv(dev);
1867 unsigned int val, revision_register;
1868 const char *version_string;
1870 DBG(2, dev, "%s: %s\n", CARDNAME, __func__);
1872 /* First, see if the high byte is 0x33 */
1873 val = SMC_CURRENT_BANK(lp);
1874 DBG(2, dev, "%s: bank signature probe returned 0x%04x\n",
1876 if ((val & 0xFF00) != 0x3300) {
1877 if ((val & 0xFF) == 0x33) {
1879 "%s: Detected possible byte-swapped interface at IOADDR %p\n",
1887 * The above MIGHT indicate a device, but I need to write to
1888 * further test this.
1890 SMC_SELECT_BANK(lp, 0);
1891 val = SMC_CURRENT_BANK(lp);
1892 if ((val & 0xFF00) != 0x3300) {
1898 * well, we've already written once, so hopefully another
1899 * time won't hurt. This time, I need to switch the bank
1900 * register to bank 1, so I can access the base address
1903 SMC_SELECT_BANK(lp, 1);
1904 val = SMC_GET_BASE(lp);
1905 val = ((val & 0x1F00) >> 3) << SMC_IO_SHIFT;
1906 if (((unsigned long)ioaddr & (0x3e0 << SMC_IO_SHIFT)) != val) {
1907 netdev_warn(dev, "%s: IOADDR %p doesn't match configuration (%x).\n",
1908 CARDNAME, ioaddr, val);
1912 * check if the revision register is something that I
1913 * recognize. These might need to be added to later,
1914 * as future revisions could be added.
1916 SMC_SELECT_BANK(lp, 3);
1917 revision_register = SMC_GET_REV(lp);
1918 DBG(2, dev, "%s: revision = 0x%04x\n", CARDNAME, revision_register);
1919 version_string = chip_ids[ (revision_register >> 4) & 0xF];
1920 if (!version_string || (revision_register & 0xff00) != 0x3300) {
1921 /* I don't recognize this chip, so... */
1922 netdev_warn(dev, "%s: IO %p: Unrecognized revision register 0x%04x, Contact author.\n",
1923 CARDNAME, ioaddr, revision_register);
1929 /* At this point I'll assume that the chip is an SMC91x. */
1930 pr_info_once("%s\n", version);
1932 /* fill in some of the fields */
1933 dev->base_addr = (unsigned long)ioaddr;
1935 lp->version = revision_register & 0xff;
1936 spin_lock_init(&lp->lock);
1938 /* Get the MAC address */
1939 SMC_SELECT_BANK(lp, 1);
1940 SMC_GET_MAC_ADDR(lp, dev->dev_addr);
1942 /* now, reset the chip, and put it into a known state */
1946 * If dev->irq is 0, then the device has to be banged on to see
1949 * This banging doesn't always detect the IRQ, for unknown reasons.
1950 * a workaround is to reset the chip and try again.
1952 * Interestingly, the DOS packet driver *SETS* the IRQ on the card to
1953 * be what is requested on the command line. I don't do that, mostly
1954 * because the card that I have uses a non-standard method of accessing
1955 * the IRQs, and because this _should_ work in most configurations.
1957 * Specifying an IRQ is done with the assumption that the user knows
1958 * what (s)he is doing. No checking is done!!!!
1965 dev->irq = smc_findirq(lp);
1968 /* kick the card and try again */
1972 if (dev->irq == 0) {
1973 netdev_warn(dev, "Couldn't autodetect your IRQ. Use irq=xx.\n");
1977 dev->irq = irq_canonicalize(dev->irq);
1979 dev->watchdog_timeo = msecs_to_jiffies(watchdog);
1980 dev->netdev_ops = &smc_netdev_ops;
1981 dev->ethtool_ops = &smc_ethtool_ops;
1983 tasklet_init(&lp->tx_task, smc_hardware_send_pkt, (unsigned long)dev);
1984 INIT_WORK(&lp->phy_configure, smc_phy_configure);
1986 lp->mii.phy_id_mask = 0x1f;
1987 lp->mii.reg_num_mask = 0x1f;
1988 lp->mii.force_media = 0;
1989 lp->mii.full_duplex = 0;
1991 lp->mii.mdio_read = smc_phy_read;
1992 lp->mii.mdio_write = smc_phy_write;
1995 * Locate the phy, if any.
1997 if (lp->version >= (CHIP_91100 << 4))
1998 smc_phy_detect(dev);
2000 /* then shut everything down to save power */
2002 smc_phy_powerdown(dev);
2004 /* Set default parameters */
2005 lp->msg_enable = NETIF_MSG_LINK;
2006 lp->ctl_rfduplx = 0;
2007 lp->ctl_rspeed = 10;
2009 if (lp->version >= (CHIP_91100 << 4)) {
2010 lp->ctl_rfduplx = 1;
2011 lp->ctl_rspeed = 100;
2015 retval = request_irq(dev->irq, smc_interrupt, irq_flags, dev->name, dev);
2019 #ifdef CONFIG_ARCH_PXA
2020 # ifdef SMC_USE_PXA_DMA
2021 lp->cfg.flags |= SMC91X_USE_DMA;
2023 if (lp->cfg.flags & SMC91X_USE_DMA) {
2024 dma_cap_mask_t mask;
2025 struct pxad_param param;
2028 dma_cap_set(DMA_SLAVE, mask);
2029 param.prio = PXAD_PRIO_LOWEST;
2033 dma_request_slave_channel_compat(mask, pxad_filter_fn,
2039 retval = register_netdev(dev);
2041 /* now, print out the card info, in a short format.. */
2042 netdev_info(dev, "%s (rev %d) at %p IRQ %d",
2043 version_string, revision_register & 0x0f,
2044 lp->base, dev->irq);
2047 pr_cont(" DMA %p", lp->dma_chan);
2050 lp->cfg.flags & SMC91X_NOWAIT ? " [nowait]" : "",
2051 THROTTLE_TX_PKTS ? " [throttle_tx]" : "");
2053 if (!is_valid_ether_addr(dev->dev_addr)) {
2054 netdev_warn(dev, "Invalid ethernet MAC address. Please set using ifconfig\n");
2056 /* Print the Ethernet address */
2057 netdev_info(dev, "Ethernet addr: %pM\n",
2061 if (lp->phy_type == 0) {
2062 PRINTK(dev, "No PHY found\n");
2063 } else if ((lp->phy_type & 0xfffffff0) == 0x0016f840) {
2064 PRINTK(dev, "PHY LAN83C183 (LAN91C111 Internal)\n");
2065 } else if ((lp->phy_type & 0xfffffff0) == 0x02821c50) {
2066 PRINTK(dev, "PHY LAN83C180\n");
2071 #ifdef CONFIG_ARCH_PXA
2072 if (retval && lp->dma_chan)
2073 dma_release_channel(lp->dma_chan);
2078 static int smc_enable_device(struct platform_device *pdev)
2080 struct net_device *ndev = platform_get_drvdata(pdev);
2081 struct smc_local *lp = netdev_priv(ndev);
2082 unsigned long flags;
2083 unsigned char ecor, ecsr;
2085 struct resource * res;
2087 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib");
2092 * Map the attribute space. This is overkill, but clean.
2094 addr = ioremap(res->start, ATTRIB_SIZE);
2099 * Reset the device. We must disable IRQs around this
2100 * since a reset causes the IRQ line become active.
2102 local_irq_save(flags);
2103 ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET;
2104 writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT));
2105 readb(addr + (ECOR << SMC_IO_SHIFT));
2108 * Wait 100us for the chip to reset.
2113 * The device will ignore all writes to the enable bit while
2114 * reset is asserted, even if the reset bit is cleared in the
2115 * same write. Must clear reset first, then enable the device.
2117 writeb(ecor, addr + (ECOR << SMC_IO_SHIFT));
2118 writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT));
2121 * Set the appropriate byte/word mode.
2123 ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8;
2126 writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT));
2127 local_irq_restore(flags);
2132 * Wait for the chip to wake up. We could poll the control
2133 * register in the main register space, but that isn't mapped
2134 * yet. We know this is going to take 750us.
2141 static int smc_request_attrib(struct platform_device *pdev,
2142 struct net_device *ndev)
2144 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib");
2145 struct smc_local *lp __maybe_unused = netdev_priv(ndev);
2150 if (!request_mem_region(res->start, ATTRIB_SIZE, CARDNAME))
2156 static void smc_release_attrib(struct platform_device *pdev,
2157 struct net_device *ndev)
2159 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib");
2160 struct smc_local *lp __maybe_unused = netdev_priv(ndev);
2163 release_mem_region(res->start, ATTRIB_SIZE);
2166 static inline void smc_request_datacs(struct platform_device *pdev, struct net_device *ndev)
2168 if (SMC_CAN_USE_DATACS) {
2169 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32");
2170 struct smc_local *lp = netdev_priv(ndev);
2175 if(!request_mem_region(res->start, SMC_DATA_EXTENT, CARDNAME)) {
2176 netdev_info(ndev, "%s: failed to request datacs memory region.\n",
2181 lp->datacs = ioremap(res->start, SMC_DATA_EXTENT);
2185 static void smc_release_datacs(struct platform_device *pdev, struct net_device *ndev)
2187 if (SMC_CAN_USE_DATACS) {
2188 struct smc_local *lp = netdev_priv(ndev);
2189 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32");
2192 iounmap(lp->datacs);
2197 release_mem_region(res->start, SMC_DATA_EXTENT);
2201 static const struct acpi_device_id smc91x_acpi_match[] = {
2205 MODULE_DEVICE_TABLE(acpi, smc91x_acpi_match);
2207 #if IS_BUILTIN(CONFIG_OF)
2208 static const struct of_device_id smc91x_match[] = {
2209 { .compatible = "smsc,lan91c94", },
2210 { .compatible = "smsc,lan91c111", },
2213 MODULE_DEVICE_TABLE(of, smc91x_match);
2216 * of_try_set_control_gpio - configure a gpio if it exists
2218 static int try_toggle_control_gpio(struct device *dev,
2219 struct gpio_desc **desc,
2220 const char *name, int index,
2221 int value, unsigned int nsdelay)
2223 struct gpio_desc *gpio = *desc;
2224 enum gpiod_flags flags = value ? GPIOD_OUT_LOW : GPIOD_OUT_HIGH;
2226 gpio = devm_gpiod_get_index_optional(dev, name, index, flags);
2228 return PTR_ERR(gpio);
2232 usleep_range(nsdelay, 2 * nsdelay);
2233 gpiod_set_value_cansleep(gpio, value);
2244 * dev->base_addr == 0, try to find all possible locations
2245 * dev->base_addr > 0x1ff, this is the address to check
2246 * dev->base_addr == <anything else>, return failure code
2249 * 0 --> there is a device
2250 * anything else, error
2252 static int smc_drv_probe(struct platform_device *pdev)
2254 struct smc91x_platdata *pd = dev_get_platdata(&pdev->dev);
2255 const struct of_device_id *match = NULL;
2256 struct smc_local *lp;
2257 struct net_device *ndev;
2258 struct resource *res;
2259 unsigned int __iomem *addr;
2260 unsigned long irq_flags = SMC_IRQ_FLAGS;
2261 unsigned long irq_resflags;
2264 ndev = alloc_etherdev(sizeof(struct smc_local));
2269 SET_NETDEV_DEV(ndev, &pdev->dev);
2271 /* get configuration from platform data, only allow use of
2272 * bus width if both SMC_CAN_USE_xxx and SMC91X_USE_xxx are set.
2275 lp = netdev_priv(ndev);
2279 memcpy(&lp->cfg, pd, sizeof(lp->cfg));
2280 lp->io_shift = SMC91X_IO_SHIFT(lp->cfg.flags);
2282 if (!SMC_8BIT(lp) && !SMC_16BIT(lp)) {
2284 "at least one of 8-bit or 16-bit access support is required.\n");
2286 goto out_free_netdev;
2290 #if IS_BUILTIN(CONFIG_OF)
2291 match = of_match_device(of_match_ptr(smc91x_match), &pdev->dev);
2295 /* Optional pwrdwn GPIO configured? */
2296 ret = try_toggle_control_gpio(&pdev->dev, &lp->power_gpio,
2297 "power", 0, 0, 100);
2302 * Optional reset GPIO configured? Minimum 100 ns reset needed
2303 * according to LAN91C96 datasheet page 14.
2305 ret = try_toggle_control_gpio(&pdev->dev, &lp->reset_gpio,
2306 "reset", 0, 0, 100);
2311 * Need to wait for optional EEPROM to load, max 750 us according
2312 * to LAN91C96 datasheet page 55.
2315 usleep_range(750, 1000);
2317 /* Combination of IO widths supported, default to 16-bit */
2318 if (!device_property_read_u32(&pdev->dev, "reg-io-width",
2321 lp->cfg.flags |= SMC91X_USE_8BIT;
2322 if ((val == 0) || (val & 2))
2323 lp->cfg.flags |= SMC91X_USE_16BIT;
2325 lp->cfg.flags |= SMC91X_USE_32BIT;
2327 lp->cfg.flags |= SMC91X_USE_16BIT;
2329 if (!device_property_read_u32(&pdev->dev, "reg-shift",
2332 lp->cfg.pxa_u16_align4 =
2333 device_property_read_bool(&pdev->dev, "pxa-u16-align4");
2337 if (!pd && !match) {
2338 lp->cfg.flags |= (SMC_CAN_USE_8BIT) ? SMC91X_USE_8BIT : 0;
2339 lp->cfg.flags |= (SMC_CAN_USE_16BIT) ? SMC91X_USE_16BIT : 0;
2340 lp->cfg.flags |= (SMC_CAN_USE_32BIT) ? SMC91X_USE_32BIT : 0;
2341 lp->cfg.flags |= (nowait) ? SMC91X_NOWAIT : 0;
2344 if (!lp->cfg.leda && !lp->cfg.ledb) {
2345 lp->cfg.leda = RPC_LSA_DEFAULT;
2346 lp->cfg.ledb = RPC_LSB_DEFAULT;
2349 ndev->dma = (unsigned char)-1;
2351 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs");
2353 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2356 goto out_free_netdev;
2360 if (!request_mem_region(res->start, SMC_IO_EXTENT, CARDNAME)) {
2362 goto out_free_netdev;
2365 ndev->irq = platform_get_irq(pdev, 0);
2366 if (ndev->irq < 0) {
2368 goto out_release_io;
2371 * If this platform does not specify any special irqflags, or if
2372 * the resource supplies a trigger, override the irqflags with
2373 * the trigger flags from the resource.
2375 irq_resflags = irqd_get_trigger_type(irq_get_irq_data(ndev->irq));
2376 if (irq_flags == -1 || irq_resflags & IRQF_TRIGGER_MASK)
2377 irq_flags = irq_resflags & IRQF_TRIGGER_MASK;
2379 ret = smc_request_attrib(pdev, ndev);
2381 goto out_release_io;
2382 #if defined(CONFIG_ASSABET_NEPONSET)
2383 if (machine_is_assabet() && machine_has_neponset())
2384 neponset_ncr_set(NCR_ENET_OSC_EN);
2386 platform_set_drvdata(pdev, ndev);
2387 ret = smc_enable_device(pdev);
2389 goto out_release_attrib;
2391 addr = ioremap(res->start, SMC_IO_EXTENT);
2394 goto out_release_attrib;
2397 #ifdef CONFIG_ARCH_PXA
2399 struct smc_local *lp = netdev_priv(ndev);
2400 lp->device = &pdev->dev;
2401 lp->physaddr = res->start;
2406 ret = smc_probe(ndev, addr, irq_flags);
2410 smc_request_datacs(pdev, ndev);
2417 smc_release_attrib(pdev, ndev);
2419 release_mem_region(res->start, SMC_IO_EXTENT);
2423 pr_info("%s: not found (%d).\n", CARDNAME, ret);
2428 static int smc_drv_remove(struct platform_device *pdev)
2430 struct net_device *ndev = platform_get_drvdata(pdev);
2431 struct smc_local *lp = netdev_priv(ndev);
2432 struct resource *res;
2434 unregister_netdev(ndev);
2436 free_irq(ndev->irq, ndev);
2438 #ifdef CONFIG_ARCH_PXA
2440 dma_release_channel(lp->dma_chan);
2444 smc_release_datacs(pdev,ndev);
2445 smc_release_attrib(pdev,ndev);
2447 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs");
2449 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2450 release_mem_region(res->start, SMC_IO_EXTENT);
2457 static int smc_drv_suspend(struct device *dev)
2459 struct platform_device *pdev = to_platform_device(dev);
2460 struct net_device *ndev = platform_get_drvdata(pdev);
2463 if (netif_running(ndev)) {
2464 netif_device_detach(ndev);
2466 smc_phy_powerdown(ndev);
2472 static int smc_drv_resume(struct device *dev)
2474 struct platform_device *pdev = to_platform_device(dev);
2475 struct net_device *ndev = platform_get_drvdata(pdev);
2478 struct smc_local *lp = netdev_priv(ndev);
2479 smc_enable_device(pdev);
2480 if (netif_running(ndev)) {
2483 if (lp->phy_type != 0)
2484 smc_phy_configure(&lp->phy_configure);
2485 netif_device_attach(ndev);
2491 static struct dev_pm_ops smc_drv_pm_ops = {
2492 .suspend = smc_drv_suspend,
2493 .resume = smc_drv_resume,
2496 static struct platform_driver smc_driver = {
2497 .probe = smc_drv_probe,
2498 .remove = smc_drv_remove,
2501 .pm = &smc_drv_pm_ops,
2502 .of_match_table = of_match_ptr(smc91x_match),
2503 .acpi_match_table = smc91x_acpi_match,
2507 module_platform_driver(smc_driver);