drivers/net/ethernet/ti/cpsw.c

   1 /*
   2  * Texas Instruments Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/timer.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/irqreturn.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/net_tstamp.h>
  28 #include <linux/phy.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/of.h>
  33 #include <linux/of_net.h>
  34 #include <linux/of_device.h>
  35 #include <linux/if_vlan.h>
  36
  37 #include <linux/platform_data/cpsw.h>
  38
  39 #include "cpsw_ale.h"
  40 #include "cpts.h"
  41 #include "davinci_cpdma.h"
  42
  43 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  44                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  45                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  46                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  47                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  48                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  49                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  50                          NETIF_MSG_RX_STATUS)
  51
  52 #define cpsw_info(priv, type, format, ...)              \
  53 do {                                                            \
  54         if (netif_msg_##type(priv) && net_ratelimit())          \
  55                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  56 } while (0)
  57
  58 #define cpsw_err(priv, type, format, ...)               \
  59 do {                                                            \
  60         if (netif_msg_##type(priv) && net_ratelimit())          \
  61                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  62 } while (0)
  63
  64 #define cpsw_dbg(priv, type, format, ...)               \
  65 do {                                                            \
  66         if (netif_msg_##type(priv) && net_ratelimit())          \
  67                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  68 } while (0)
  69
  70 #define cpsw_notice(priv, type, format, ...)            \
  71 do {                                                            \
  72         if (netif_msg_##type(priv) && net_ratelimit())          \
  73                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  74 } while (0)
  75
  76 #define ALE_ALL_PORTS           0x7
  77
  78 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  79 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  80 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  81
  82 #define CPSW_VERSION_1          0x19010a
  83 #define CPSW_VERSION_2          0x19010c
  84
  85 #define HOST_PORT_NUM           0
  86 #define SLIVER_SIZE             0x40
  87
  88 #define CPSW1_HOST_PORT_OFFSET  0x028
  89 #define CPSW1_SLAVE_OFFSET      0x050
  90 #define CPSW1_SLAVE_SIZE        0x040
  91 #define CPSW1_CPDMA_OFFSET      0x100
  92 #define CPSW1_STATERAM_OFFSET   0x200
  93 #define CPSW1_CPTS_OFFSET       0x500
  94 #define CPSW1_ALE_OFFSET        0x600
  95 #define CPSW1_SLIVER_OFFSET     0x700
  96
  97 #define CPSW2_HOST_PORT_OFFSET  0x108
  98 #define CPSW2_SLAVE_OFFSET      0x200
  99 #define CPSW2_SLAVE_SIZE        0x100
 100 #define CPSW2_CPDMA_OFFSET      0x800
 101 #define CPSW2_STATERAM_OFFSET   0xa00
 102 #define CPSW2_CPTS_OFFSET       0xc00
 103 #define CPSW2_ALE_OFFSET        0xd00
 104 #define CPSW2_SLIVER_OFFSET     0xd80
 105 #define CPSW2_BD_OFFSET         0x2000
 106
 107 #define CPDMA_RXTHRESH          0x0c0
 108 #define CPDMA_RXFREE            0x0e0
 109 #define CPDMA_TXHDP             0x00
 110 #define CPDMA_RXHDP             0x20
 111 #define CPDMA_TXCP              0x40
 112 #define CPDMA_RXCP              0x60
 113
 114 #define CPSW_POLL_WEIGHT        64
 115 #define CPSW_MIN_PACKET_SIZE    60
 116 #define CPSW_MAX_PACKET_SIZE    (1500 + 14 + 4 + 4)
 117
 118 #define RX_PRIORITY_MAPPING     0x76543210
 119 #define TX_PRIORITY_MAPPING     0x33221100
 120 #define CPDMA_TX_PRIORITY_MAP   0x76543210
 121
 122 #define CPSW_VLAN_AWARE         BIT(1)
 123 #define CPSW_ALE_VLAN_AWARE     1
 124
 125 #define CPSW_FIFO_NORMAL_MODE           (0 << 15)
 126 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 15)
 127 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 15)
 128
 129 #define CPSW_INTPACEEN          (0x3f << 16)
 130 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
 131 #define CPSW_CMINTMAX_CNT       63
 132 #define CPSW_CMINTMIN_CNT       2
 133 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
 134 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
 135
 136 #define cpsw_enable_irq(priv)   \
 137         do {                    \
 138                 u32 i;          \
 139                 for (i = 0; i < priv->num_irqs; i++) \
 140                         enable_irq(priv->irqs_table[i]); \
 141         } while (0);
 142 #define cpsw_disable_irq(priv)  \
 143         do {                    \
 144                 u32 i;          \
 145                 for (i = 0; i < priv->num_irqs; i++) \
 146                         disable_irq_nosync(priv->irqs_table[i]); \
 147         } while (0);
 148
 149 #define cpsw_slave_index(priv)                          \
 150                 ((priv->data.dual_emac) ? priv->emac_port :     \
 151                 priv->data.active_slave)
 152
 153 static int debug_level;
 154 module_param(debug_level, int, 0);
 155 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 156
 157 static int ale_ageout = 10;
 158 module_param(ale_ageout, int, 0);
 159 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 160
 161 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 162 module_param(rx_packet_max, int, 0);
 163 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 164
 165 struct cpsw_wr_regs {
 166         u32     id_ver;
 167         u32     soft_reset;
 168         u32     control;
 169         u32     int_control;
 170         u32     rx_thresh_en;
 171         u32     rx_en;
 172         u32     tx_en;
 173         u32     misc_en;
 174         u32     mem_allign1[8];
 175         u32     rx_thresh_stat;
 176         u32     rx_stat;
 177         u32     tx_stat;
 178         u32     misc_stat;
 179         u32     mem_allign2[8];
 180         u32     rx_imax;
 181         u32     tx_imax;
 182
 183 };
 184
 185 struct cpsw_ss_regs {
 186         u32     id_ver;
 187         u32     control;
 188         u32     soft_reset;
 189         u32     stat_port_en;
 190         u32     ptype;
 191         u32     soft_idle;
 192         u32     thru_rate;
 193         u32     gap_thresh;
 194         u32     tx_start_wds;
 195         u32     flow_control;
 196         u32     vlan_ltype;
 197         u32     ts_ltype;
 198         u32     dlr_ltype;
 199 };
 200
 201 /* CPSW_PORT_V1 */
 202 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 203 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 204 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 205 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 206 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 207 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 208 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 209 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 210
 211 /* CPSW_PORT_V2 */
 212 #define CPSW2_CONTROL       0x00 /* Control Register */
 213 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 214 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 215 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 216 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 217 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 218 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 219
 220 /* CPSW_PORT_V1 and V2 */
 221 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 222 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 223 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 224
 225 /* CPSW_PORT_V2 only */
 226 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 227 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 228 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 229 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 230 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 231 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 232 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 233 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 234
 235 /* Bit definitions for the CPSW2_CONTROL register */
 236 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
 237 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
 238 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
 239 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
 240 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
 241 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
 242 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
 243 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 244 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 245 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
 246 #define TS_BIT8             (1<<8)  /* ts_ttl_nonzero? */
 247 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 248 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 249 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
 250 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
 251 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 252
 253 #define CTRL_TS_BITS \
 254         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \
 255          TS_ANNEX_D_EN | TS_LTYPE1_EN)
 256
 257 #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN)
 258 #define CTRL_TX_TS_BITS  (CTRL_TS_BITS | TS_TX_EN)
 259 #define CTRL_RX_TS_BITS  (CTRL_TS_BITS | TS_RX_EN)
 260
 261 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 262 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 263 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 264 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 265 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 266
 267 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 268 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 269
 270 /* Bit definitions for the CPSW1_TS_CTL register */
 271 #define CPSW_V1_TS_RX_EN                BIT(0)
 272 #define CPSW_V1_TS_TX_EN                BIT(4)
 273 #define CPSW_V1_MSG_TYPE_OFS            16
 274
 275 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 276 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 277
 278 struct cpsw_host_regs {
 279         u32     max_blks;
 280         u32     blk_cnt;
 281         u32     tx_in_ctl;
 282         u32     port_vlan;
 283         u32     tx_pri_map;
 284         u32     cpdma_tx_pri_map;
 285         u32     cpdma_rx_chan_map;
 286 };
 287
 288 struct cpsw_sliver_regs {
 289         u32     id_ver;
 290         u32     mac_control;
 291         u32     mac_status;
 292         u32     soft_reset;
 293         u32     rx_maxlen;
 294         u32     __reserved_0;
 295         u32     rx_pause;
 296         u32     tx_pause;
 297         u32     __reserved_1;
 298         u32     rx_pri_map;
 299 };
 300
 301 struct cpsw_slave {
 302         void __iomem                    *regs;
 303         struct cpsw_sliver_regs __iomem *sliver;
 304         int                             slave_num;
 305         u32                             mac_control;
 306         struct cpsw_slave_data          *data;
 307         struct phy_device               *phy;
 308         struct net_device               *ndev;
 309         u32                             port_vlan;
 310         u32                             open_stat;
 311 };
 312
 313 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 314 {
 315         return __raw_readl(slave->regs + offset);
 316 }
 317
 318 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 319 {
 320         __raw_writel(val, slave->regs + offset);
 321 }
 322
 323 struct cpsw_priv {
 324         spinlock_t                      lock;
 325         struct platform_device          *pdev;
 326         struct net_device               *ndev;
 327         struct resource                 *cpsw_res;
 328         struct resource                 *cpsw_wr_res;
 329         struct napi_struct              napi;
 330         struct device                   *dev;
 331         struct cpsw_platform_data       data;
 332         struct cpsw_ss_regs __iomem     *regs;
 333         struct cpsw_wr_regs __iomem     *wr_regs;
 334         struct cpsw_host_regs __iomem   *host_port_regs;
 335         u32                             msg_enable;
 336         u32                             version;
 337         u32                             coal_intvl;
 338         u32                             bus_freq_mhz;
 339         struct net_device_stats         stats;
 340         int                             rx_packet_max;
 341         int                             host_port;
 342         struct clk                      *clk;
 343         u8                              mac_addr[ETH_ALEN];
 344         struct cpsw_slave               *slaves;
 345         struct cpdma_ctlr               *dma;
 346         struct cpdma_chan               *txch, *rxch;
 347         struct cpsw_ale                 *ale;
 348         /* snapshot of IRQ numbers */
 349         u32 irqs_table[4];
 350         u32 num_irqs;
 351         struct cpts *cpts;
 352         u32 emac_port;
 353 };
 354
 355 #define napi_to_priv(napi)      container_of(napi, struct cpsw_priv, napi)
 356 #define for_each_slave(priv, func, arg...)                              \
 357         do {                                                            \
 358                 int idx;                                                \
 359                 if (priv->data.dual_emac)                               \
 360                         (func)((priv)->slaves + priv->emac_port, ##arg);\
 361                 else                                                    \
 362                         for (idx = 0; idx < (priv)->data.slaves; idx++) \
 363                                 (func)((priv)->slaves + idx, ##arg);    \
 364         } while (0)
 365 #define cpsw_get_slave_ndev(priv, __slave_no__)                         \
 366         (priv->slaves[__slave_no__].ndev)
 367 #define cpsw_get_slave_priv(priv, __slave_no__)                         \
 368         ((priv->slaves[__slave_no__].ndev) ?                            \
 369                 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL)    \
 370
 371 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb)         \
 372         do {                                                            \
 373                 if (!priv->data.dual_emac)                              \
 374                         break;                                          \
 375                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
 376                         ndev = cpsw_get_slave_ndev(priv, 0);            \
 377                         priv = netdev_priv(ndev);                       \
 378                         skb->dev = ndev;                                \
 379                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
 380                         ndev = cpsw_get_slave_ndev(priv, 1);            \
 381                         priv = netdev_priv(ndev);                       \
 382                         skb->dev = ndev;                                \
 383                 }                                                       \
 384         } while (0)
 385 #define cpsw_add_mcast(priv, addr)                                      \
 386         do {                                                            \
 387                 if (priv->data.dual_emac) {                             \
 388                         struct cpsw_slave *slave = priv->slaves +       \
 389                                                 priv->emac_port;        \
 390                         int slave_port = cpsw_get_slave_port(priv,      \
 391                                                 slave->slave_num);      \
 392                         cpsw_ale_add_mcast(priv->ale, addr,             \
 393                                 1 << slave_port | 1 << priv->host_port, \
 394                                 ALE_VLAN, slave->port_vlan, 0);         \
 395                 } else {                                                \
 396                         cpsw_ale_add_mcast(priv->ale, addr,             \
 397                                 ALE_ALL_PORTS << priv->host_port,       \
 398                                 0, 0, 0);                               \
 399                 }                                                       \
 400         } while (0)
 401
 402 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
 403 {
 404         if (priv->host_port == 0)
 405                 return slave_num + 1;
 406         else
 407                 return slave_num;
 408 }
 409
 410 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 411 {
 412         struct cpsw_priv *priv = netdev_priv(ndev);
 413
 414         if (ndev->flags & IFF_PROMISC) {
 415                 /* Enable promiscuous mode */
 416                 dev_err(priv->dev, "Ignoring Promiscuous mode\n");
 417                 return;
 418         }
 419
 420         /* Clear all mcast from ALE */
 421         cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port);
 422
 423         if (!netdev_mc_empty(ndev)) {
 424                 struct netdev_hw_addr *ha;
 425
 426                 /* program multicast address list into ALE register */
 427                 netdev_for_each_mc_addr(ha, ndev) {
 428                         cpsw_add_mcast(priv, (u8 *)ha->addr);
 429                 }
 430         }
 431 }
 432
 433 static void cpsw_intr_enable(struct cpsw_priv *priv)
 434 {
 435         __raw_writel(0xFF, &priv->wr_regs->tx_en);
 436         __raw_writel(0xFF, &priv->wr_regs->rx_en);
 437
 438         cpdma_ctlr_int_ctrl(priv->dma, true);
 439         return;
 440 }
 441
 442 static void cpsw_intr_disable(struct cpsw_priv *priv)
 443 {
 444         __raw_writel(0, &priv->wr_regs->tx_en);
 445         __raw_writel(0, &priv->wr_regs->rx_en);
 446
 447         cpdma_ctlr_int_ctrl(priv->dma, false);
 448         return;
 449 }
 450
 451 void cpsw_tx_handler(void *token, int len, int status)
 452 {
 453         struct sk_buff          *skb = token;
 454         struct net_device       *ndev = skb->dev;
 455         struct cpsw_priv        *priv = netdev_priv(ndev);
 456
 457         /* Check whether the queue is stopped due to stalled tx dma, if the
 458          * queue is stopped then start the queue as we have free desc for tx
 459          */
 460         if (unlikely(netif_queue_stopped(ndev)))
 461                 netif_wake_queue(ndev);
 462         cpts_tx_timestamp(priv->cpts, skb);
 463         priv->stats.tx_packets++;
 464         priv->stats.tx_bytes += len;
 465         dev_kfree_skb_any(skb);
 466 }
 467
 468 void cpsw_rx_handler(void *token, int len, int status)
 469 {
 470         struct sk_buff          *skb = token;
 471         struct sk_buff          *new_skb;
 472         struct net_device       *ndev = skb->dev;
 473         struct cpsw_priv        *priv = netdev_priv(ndev);
 474         int                     ret = 0;
 475
 476         cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
 477
 478         if (unlikely(status < 0)) {
 479                 /* the interface is going down, skbs are purged */
 480                 dev_kfree_skb_any(skb);
 481                 return;
 482         }
 483
 484         new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
 485         if (new_skb) {
 486                 skb_put(skb, len);
 487                 cpts_rx_timestamp(priv->cpts, skb);
 488                 skb->protocol = eth_type_trans(skb, ndev);
 489                 netif_receive_skb(skb);
 490                 priv->stats.rx_bytes += len;
 491                 priv->stats.rx_packets++;
 492         } else {
 493                 priv->stats.rx_dropped++;
 494                 new_skb = skb;
 495         }
 496
 497         ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
 498                         skb_tailroom(new_skb), 0);
 499         if (WARN_ON(ret < 0))
 500                 dev_kfree_skb_any(new_skb);
 501 }
 502
 503 static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
 504 {
 505         struct cpsw_priv *priv = dev_id;
 506         u32 rx, tx, rx_thresh;
 507
 508         rx_thresh = __raw_readl(&priv->wr_regs->rx_thresh_stat);
 509         rx = __raw_readl(&priv->wr_regs->rx_stat);
 510         tx = __raw_readl(&priv->wr_regs->tx_stat);
 511         if (!rx_thresh && !rx && !tx)
 512                 return IRQ_NONE;
 513
 514         cpsw_intr_disable(priv);
 515         cpsw_disable_irq(priv);
 516
 517         if (netif_running(priv->ndev)) {
 518                 napi_schedule(&priv->napi);
 519                 return IRQ_HANDLED;
 520         }
 521
 522         priv = cpsw_get_slave_priv(priv, 1);
 523         if (!priv)
 524                 return IRQ_NONE;
 525
 526         if (netif_running(priv->ndev)) {
 527                 napi_schedule(&priv->napi);
 528                 return IRQ_HANDLED;
 529         }
 530         return IRQ_NONE;
 531 }
 532
 533 static int cpsw_poll(struct napi_struct *napi, int budget)
 534 {
 535         struct cpsw_priv        *priv = napi_to_priv(napi);
 536         int                     num_tx, num_rx;
 537
 538         num_tx = cpdma_chan_process(priv->txch, 128);
 539         if (num_tx)
 540                 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
 541
 542         num_rx = cpdma_chan_process(priv->rxch, budget);
 543         if (num_rx < budget) {
 544                 napi_complete(napi);
 545                 cpsw_intr_enable(priv);
 546                 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
 547                 cpsw_enable_irq(priv);
 548         }
 549
 550         if (num_rx || num_tx)
 551                 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
 552                          num_rx, num_tx);
 553
 554         return num_rx;
 555 }
 556
 557 static inline void soft_reset(const char *module, void __iomem *reg)
 558 {
 559         unsigned long timeout = jiffies + HZ;
 560
 561         __raw_writel(1, reg);
 562         do {
 563                 cpu_relax();
 564         } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
 565
 566         WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
 567 }
 568
 569 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 570                          ((mac)[2] << 16) | ((mac)[3] << 24))
 571 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 572
 573 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 574                                struct cpsw_priv *priv)
 575 {
 576         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
 577         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
 578 }
 579
 580 static void _cpsw_adjust_link(struct cpsw_slave *slave,
 581                               struct cpsw_priv *priv, bool *link)
 582 {
 583         struct phy_device       *phy = slave->phy;
 584         u32                     mac_control = 0;
 585         u32                     slave_port;
 586
 587         if (!phy)
 588                 return;
 589
 590         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 591
 592         if (phy->link) {
 593                 mac_control = priv->data.mac_control;
 594
 595                 /* enable forwarding */
 596                 cpsw_ale_control_set(priv->ale, slave_port,
 597                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 598
 599                 if (phy->speed == 1000)
 600                         mac_control |= BIT(7);  /* GIGABITEN    */
 601                 if (phy->duplex)
 602                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
 603
 604                 /* set speed_in input in case RMII mode is used in 100Mbps */
 605                 if (phy->speed == 100)
 606                         mac_control |= BIT(15);
 607
 608                 *link = true;
 609         } else {
 610                 mac_control = 0;
 611                 /* disable forwarding */
 612                 cpsw_ale_control_set(priv->ale, slave_port,
 613                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
 614         }
 615
 616         if (mac_control != slave->mac_control) {
 617                 phy_print_status(phy);
 618                 __raw_writel(mac_control, &slave->sliver->mac_control);
 619         }
 620
 621         slave->mac_control = mac_control;
 622 }
 623
 624 static void cpsw_adjust_link(struct net_device *ndev)
 625 {
 626         struct cpsw_priv        *priv = netdev_priv(ndev);
 627         bool                    link = false;
 628
 629         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
 630
 631         if (link) {
 632                 netif_carrier_on(ndev);
 633                 if (netif_running(ndev))
 634                         netif_wake_queue(ndev);
 635         } else {
 636                 netif_carrier_off(ndev);
 637                 netif_stop_queue(ndev);
 638         }
 639 }
 640
 641 static int cpsw_get_coalesce(struct net_device *ndev,
 642                                 struct ethtool_coalesce *coal)
 643 {
 644         struct cpsw_priv *priv = netdev_priv(ndev);
 645
 646         coal->rx_coalesce_usecs = priv->coal_intvl;
 647         return 0;
 648 }
 649
 650 static int cpsw_set_coalesce(struct net_device *ndev,
 651                                 struct ethtool_coalesce *coal)
 652 {
 653         struct cpsw_priv *priv = netdev_priv(ndev);
 654         u32 int_ctrl;
 655         u32 num_interrupts = 0;
 656         u32 prescale = 0;
 657         u32 addnl_dvdr = 1;
 658         u32 coal_intvl = 0;
 659
 660         if (!coal->rx_coalesce_usecs)
 661                 return -EINVAL;
 662
 663         coal_intvl = coal->rx_coalesce_usecs;
 664
 665         int_ctrl =  readl(&priv->wr_regs->int_control);
 666         prescale = priv->bus_freq_mhz * 4;
 667
 668         if (coal_intvl < CPSW_CMINTMIN_INTVL)
 669                 coal_intvl = CPSW_CMINTMIN_INTVL;
 670
 671         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
 672                 /* Interrupt pacer works with 4us Pulse, we can
 673                  * throttle further by dilating the 4us pulse.
 674                  */
 675                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
 676
 677                 if (addnl_dvdr > 1) {
 678                         prescale *= addnl_dvdr;
 679                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
 680                                 coal_intvl = (CPSW_CMINTMAX_INTVL
 681                                                 * addnl_dvdr);
 682                 } else {
 683                         addnl_dvdr = 1;
 684                         coal_intvl = CPSW_CMINTMAX_INTVL;
 685                 }
 686         }
 687
 688         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
 689         writel(num_interrupts, &priv->wr_regs->rx_imax);
 690         writel(num_interrupts, &priv->wr_regs->tx_imax);
 691
 692         int_ctrl |= CPSW_INTPACEEN;
 693         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
 694         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
 695         writel(int_ctrl, &priv->wr_regs->int_control);
 696
 697         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
 698         if (priv->data.dual_emac) {
 699                 int i;
 700
 701                 for (i = 0; i < priv->data.slaves; i++) {
 702                         priv = netdev_priv(priv->slaves[i].ndev);
 703                         priv->coal_intvl = coal_intvl;
 704                 }
 705         } else {
 706                 priv->coal_intvl = coal_intvl;
 707         }
 708
 709         return 0;
 710 }
 711
 712 static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val)
 713 {
 714         static char *leader = "........................................";
 715
 716         if (!val)
 717                 return 0;
 718         else
 719                 return snprintf(buf, maxlen, "%s %s %10d\n", name,
 720                                 leader + strlen(name), val);
 721 }
 722
 723 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
 724 {
 725         u32 i;
 726         u32 usage_count = 0;
 727
 728         if (!priv->data.dual_emac)
 729                 return 0;
 730
 731         for (i = 0; i < priv->data.slaves; i++)
 732                 if (priv->slaves[i].open_stat)
 733                         usage_count++;
 734
 735         return usage_count;
 736 }
 737
 738 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
 739                         struct cpsw_priv *priv, struct sk_buff *skb)
 740 {
 741         if (!priv->data.dual_emac)
 742                 return cpdma_chan_submit(priv->txch, skb, skb->data,
 743                                   skb->len, 0);
 744
 745         if (ndev == cpsw_get_slave_ndev(priv, 0))
 746                 return cpdma_chan_submit(priv->txch, skb, skb->data,
 747                                   skb->len, 1);
 748         else
 749                 return cpdma_chan_submit(priv->txch, skb, skb->data,
 750                                   skb->len, 2);
 751 }
 752
 753 static inline void cpsw_add_dual_emac_def_ale_entries(
 754                 struct cpsw_priv *priv, struct cpsw_slave *slave,
 755                 u32 slave_port)
 756 {
 757         u32 port_mask = 1 << slave_port | 1 << priv->host_port;
 758
 759         if (priv->version == CPSW_VERSION_1)
 760                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
 761         else
 762                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
 763         cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
 764                           port_mask, port_mask, 0);
 765         cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
 766                            port_mask, ALE_VLAN, slave->port_vlan, 0);
 767         cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
 768                 priv->host_port, ALE_VLAN, slave->port_vlan);
 769 }
 770
 771 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
 772 {
 773         char name[32];
 774         u32 slave_port;
 775
 776         sprintf(name, "slave-%d", slave->slave_num);
 777
 778         soft_reset(name, &slave->sliver->soft_reset);
 779
 780         /* setup priority mapping */
 781         __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
 782
 783         switch (priv->version) {
 784         case CPSW_VERSION_1:
 785                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
 786                 break;
 787         case CPSW_VERSION_2:
 788                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
 789                 break;
 790         }
 791
 792         /* setup max packet size, and mac address */
 793         __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
 794         cpsw_set_slave_mac(slave, priv);
 795
 796         slave->mac_control = 0; /* no link yet */
 797
 798         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 799
 800         if (priv->data.dual_emac)
 801                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
 802         else
 803                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
 804                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
 805
 806         slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
 807                                  &cpsw_adjust_link, slave->data->phy_if);
 808         if (IS_ERR(slave->phy)) {
 809                 dev_err(priv->dev, "phy %s not found on slave %d\n",
 810                         slave->data->phy_id, slave->slave_num);
 811                 slave->phy = NULL;
 812         } else {
 813                 dev_info(priv->dev, "phy found : id is : 0x%x\n",
 814                          slave->phy->phy_id);
 815                 phy_start(slave->phy);
 816         }
 817 }
 818
 819 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
 820 {
 821         const int vlan = priv->data.default_vlan;
 822         const int port = priv->host_port;
 823         u32 reg;
 824         int i;
 825
 826         reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
 827                CPSW2_PORT_VLAN;
 828
 829         writel(vlan, &priv->host_port_regs->port_vlan);
 830
 831         for (i = 0; i < priv->data.slaves; i++)
 832                 slave_write(priv->slaves + i, vlan, reg);
 833
 834         cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
 835                           ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
 836                           (ALE_PORT_1 | ALE_PORT_2) << port);
 837 }
 838
 839 static void cpsw_init_host_port(struct cpsw_priv *priv)
 840 {
 841         u32 control_reg;
 842         u32 fifo_mode;
 843
 844         /* soft reset the controller and initialize ale */
 845         soft_reset("cpsw", &priv->regs->soft_reset);
 846         cpsw_ale_start(priv->ale);
 847
 848         /* switch to vlan unaware mode */
 849         cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
 850                              CPSW_ALE_VLAN_AWARE);
 851         control_reg = readl(&priv->regs->control);
 852         control_reg |= CPSW_VLAN_AWARE;
 853         writel(control_reg, &priv->regs->control);
 854         fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
 855                      CPSW_FIFO_NORMAL_MODE;
 856         writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
 857
 858         /* setup host port priority mapping */
 859         __raw_writel(CPDMA_TX_PRIORITY_MAP,
 860                      &priv->host_port_regs->cpdma_tx_pri_map);
 861         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
 862
 863         cpsw_ale_control_set(priv->ale, priv->host_port,
 864                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 865
 866         if (!priv->data.dual_emac) {
 867                 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
 868                                    0, 0);
 869                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
 870                                    1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
 871         }
 872 }
 873
 874 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
 875 {
 876         if (!slave->phy)
 877                 return;
 878         phy_stop(slave->phy);
 879         phy_disconnect(slave->phy);
 880         slave->phy = NULL;
 881 }
 882
 883 static int cpsw_ndo_open(struct net_device *ndev)
 884 {
 885         struct cpsw_priv *priv = netdev_priv(ndev);
 886         int i, ret;
 887         u32 reg;
 888
 889         if (!cpsw_common_res_usage_state(priv))
 890                 cpsw_intr_disable(priv);
 891         netif_carrier_off(ndev);
 892
 893         pm_runtime_get_sync(&priv->pdev->dev);
 894
 895         reg = priv->version;
 896
 897         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
 898                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
 899                  CPSW_RTL_VERSION(reg));
 900
 901         /* initialize host and slave ports */
 902         if (!cpsw_common_res_usage_state(priv))
 903                 cpsw_init_host_port(priv);
 904         for_each_slave(priv, cpsw_slave_open, priv);
 905
 906         /* Add default VLAN */
 907         if (!priv->data.dual_emac)
 908                 cpsw_add_default_vlan(priv);
 909
 910         if (!cpsw_common_res_usage_state(priv)) {
 911                 /* setup tx dma to fixed prio and zero offset */
 912                 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
 913                 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
 914
 915                 /* disable priority elevation */
 916                 __raw_writel(0, &priv->regs->ptype);
 917
 918                 /* enable statistics collection only on all ports */
 919                 __raw_writel(0x7, &priv->regs->stat_port_en);
 920
 921                 if (WARN_ON(!priv->data.rx_descs))
 922                         priv->data.rx_descs = 128;
 923
 924                 for (i = 0; i < priv->data.rx_descs; i++) {
 925                         struct sk_buff *skb;
 926
 927                         ret = -ENOMEM;
 928                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
 929                                         priv->rx_packet_max, GFP_KERNEL);
 930                         if (!skb)
 931                                 goto err_cleanup;
 932                         ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
 933                                         skb_tailroom(skb), 0);
 934                         if (ret < 0) {
 935                                 kfree_skb(skb);
 936                                 goto err_cleanup;
 937                         }
 938                 }
 939                 /* continue even if we didn't manage to submit all
 940                  * receive descs
 941                  */
 942                 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
 943         }
 944
 945         /* Enable Interrupt pacing if configured */
 946         if (priv->coal_intvl != 0) {
 947                 struct ethtool_coalesce coal;
 948
 949                 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
 950                 cpsw_set_coalesce(ndev, &coal);
 951         }
 952
 953         cpdma_ctlr_start(priv->dma);
 954         cpsw_intr_enable(priv);
 955         napi_enable(&priv->napi);
 956         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
 957         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
 958
 959         if (priv->data.dual_emac)
 960                 priv->slaves[priv->emac_port].open_stat = true;
 961         return 0;
 962
 963 err_cleanup:
 964         cpdma_ctlr_stop(priv->dma);
 965         for_each_slave(priv, cpsw_slave_stop, priv);
 966         pm_runtime_put_sync(&priv->pdev->dev);
 967         netif_carrier_off(priv->ndev);
 968         return ret;
 969 }
 970
 971 static int cpsw_ndo_stop(struct net_device *ndev)
 972 {
 973         struct cpsw_priv *priv = netdev_priv(ndev);
 974
 975         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
 976         netif_stop_queue(priv->ndev);
 977         napi_disable(&priv->napi);
 978         netif_carrier_off(priv->ndev);
 979
 980         if (cpsw_common_res_usage_state(priv) <= 1) {
 981                 cpsw_intr_disable(priv);
 982                 cpdma_ctlr_int_ctrl(priv->dma, false);
 983                 cpdma_ctlr_stop(priv->dma);
 984                 cpsw_ale_stop(priv->ale);
 985         }
 986         for_each_slave(priv, cpsw_slave_stop, priv);
 987         pm_runtime_put_sync(&priv->pdev->dev);
 988         if (priv->data.dual_emac)
 989                 priv->slaves[priv->emac_port].open_stat = false;
 990         return 0;
 991 }
 992
 993 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
 994                                        struct net_device *ndev)
 995 {
 996         struct cpsw_priv *priv = netdev_priv(ndev);
 997         int ret;
 998
 999         ndev->trans_start = jiffies;
1000
1001         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1002                 cpsw_err(priv, tx_err, "packet pad failed\n");
1003                 priv->stats.tx_dropped++;
1004                 return NETDEV_TX_OK;
1005         }
1006
1007         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1008                                 priv->cpts->tx_enable)
1009                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1010
1011         skb_tx_timestamp(skb);
1012
1013         ret = cpsw_tx_packet_submit(ndev, priv, skb);
1014         if (unlikely(ret != 0)) {
1015                 cpsw_err(priv, tx_err, "desc submit failed\n");
1016                 goto fail;
1017         }
1018
1019         /* If there is no more tx desc left free then we need to
1020          * tell the kernel to stop sending us tx frames.
1021          */
1022         if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1023                 netif_stop_queue(ndev);
1024
1025         return NETDEV_TX_OK;
1026 fail:
1027         priv->stats.tx_dropped++;
1028         netif_stop_queue(ndev);
1029         return NETDEV_TX_BUSY;
1030 }
1031
1032 static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags)
1033 {
1034         /*
1035          * The switch cannot operate in promiscuous mode without substantial
1036          * headache.  For promiscuous mode to work, we would need to put the
1037          * ALE in bypass mode and route all traffic to the host port.
1038          * Subsequently, the host will need to operate as a "bridge", learn,
1039          * and flood as needed.  For now, we simply complain here and
1040          * do nothing about it :-)
1041          */
1042         if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC))
1043                 dev_err(&ndev->dev, "promiscuity ignored!\n");
1044
1045         /*
1046          * The switch cannot filter multicast traffic unless it is configured
1047          * in "VLAN Aware" mode.  Unfortunately, VLAN awareness requires a
1048          * whole bunch of additional logic that this driver does not implement
1049          * at present.
1050          */
1051         if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI))
1052                 dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n");
1053 }
1054
1055 #ifdef CONFIG_TI_CPTS
1056
1057 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1058 {
1059         struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1060         u32 ts_en, seq_id;
1061
1062         if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1063                 slave_write(slave, 0, CPSW1_TS_CTL);
1064                 return;
1065         }
1066
1067         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1068         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1069
1070         if (priv->cpts->tx_enable)
1071                 ts_en |= CPSW_V1_TS_TX_EN;
1072
1073         if (priv->cpts->rx_enable)
1074                 ts_en |= CPSW_V1_TS_RX_EN;
1075
1076         slave_write(slave, ts_en, CPSW1_TS_CTL);
1077         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1078 }
1079
1080 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1081 {
1082         struct cpsw_slave *slave;
1083         u32 ctrl, mtype;
1084
1085         if (priv->data.dual_emac)
1086                 slave = &priv->slaves[priv->emac_port];
1087         else
1088                 slave = &priv->slaves[priv->data.active_slave];
1089
1090         ctrl = slave_read(slave, CPSW2_CONTROL);
1091         ctrl &= ~CTRL_ALL_TS_MASK;
1092
1093         if (priv->cpts->tx_enable)
1094                 ctrl |= CTRL_TX_TS_BITS;
1095
1096         if (priv->cpts->rx_enable)
1097                 ctrl |= CTRL_RX_TS_BITS;
1098
1099         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1100
1101         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1102         slave_write(slave, ctrl, CPSW2_CONTROL);
1103         __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1104 }
1105
1106 static int cpsw_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
1107 {
1108         struct cpsw_priv *priv = netdev_priv(dev);
1109         struct cpts *cpts = priv->cpts;
1110         struct hwtstamp_config cfg;
1111
1112         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1113                 return -EFAULT;
1114
1115         /* reserved for future extensions */
1116         if (cfg.flags)
1117                 return -EINVAL;
1118
1119         switch (cfg.tx_type) {
1120         case HWTSTAMP_TX_OFF:
1121                 cpts->tx_enable = 0;
1122                 break;
1123         case HWTSTAMP_TX_ON:
1124                 cpts->tx_enable = 1;
1125                 break;
1126         default:
1127                 return -ERANGE;
1128         }
1129
1130         switch (cfg.rx_filter) {
1131         case HWTSTAMP_FILTER_NONE:
1132                 cpts->rx_enable = 0;
1133                 break;
1134         case HWTSTAMP_FILTER_ALL:
1135         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1136         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1137         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1138                 return -ERANGE;
1139         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1140         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1141         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1142         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1143         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1144         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1145         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1146         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1147         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1148                 cpts->rx_enable = 1;
1149                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1150                 break;
1151         default:
1152                 return -ERANGE;
1153         }
1154
1155         switch (priv->version) {
1156         case CPSW_VERSION_1:
1157                 cpsw_hwtstamp_v1(priv);
1158                 break;
1159         case CPSW_VERSION_2:
1160                 cpsw_hwtstamp_v2(priv);
1161                 break;
1162         default:
1163                 return -ENOTSUPP;
1164         }
1165
1166         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1167 }
1168
1169 #endif /*CONFIG_TI_CPTS*/
1170
1171 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1172 {
1173         struct cpsw_priv *priv = netdev_priv(dev);
1174         struct mii_ioctl_data *data = if_mii(req);
1175         int slave_no = cpsw_slave_index(priv);
1176
1177         if (!netif_running(dev))
1178                 return -EINVAL;
1179
1180         switch (cmd) {
1181 #ifdef CONFIG_TI_CPTS
1182         case SIOCSHWTSTAMP:
1183                 return cpsw_hwtstamp_ioctl(dev, req);
1184 #endif
1185         case SIOCGMIIPHY:
1186                 data->phy_id = priv->slaves[slave_no].phy->addr;
1187                 break;
1188         default:
1189                 return -ENOTSUPP;
1190         }
1191
1192         return 0;
1193 }
1194
1195 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1196 {
1197         struct cpsw_priv *priv = netdev_priv(ndev);
1198
1199         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1200         priv->stats.tx_errors++;
1201         cpsw_intr_disable(priv);
1202         cpdma_ctlr_int_ctrl(priv->dma, false);
1203         cpdma_chan_stop(priv->txch);
1204         cpdma_chan_start(priv->txch);
1205         cpdma_ctlr_int_ctrl(priv->dma, true);
1206         cpsw_intr_enable(priv);
1207         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1208         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1209
1210 }
1211
1212 static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev)
1213 {
1214         struct cpsw_priv *priv = netdev_priv(ndev);
1215         return &priv->stats;
1216 }
1217
1218 #ifdef CONFIG_NET_POLL_CONTROLLER
1219 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1220 {
1221         struct cpsw_priv *priv = netdev_priv(ndev);
1222
1223         cpsw_intr_disable(priv);
1224         cpdma_ctlr_int_ctrl(priv->dma, false);
1225         cpsw_interrupt(ndev->irq, priv);
1226         cpdma_ctlr_int_ctrl(priv->dma, true);
1227         cpsw_intr_enable(priv);
1228         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1229         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1230
1231 }
1232 #endif
1233
1234 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1235                                 unsigned short vid)
1236 {
1237         int ret;
1238
1239         ret = cpsw_ale_add_vlan(priv->ale, vid,
1240                                 ALE_ALL_PORTS << priv->host_port,
1241                                 0, ALE_ALL_PORTS << priv->host_port,
1242                                 (ALE_PORT_1 | ALE_PORT_2) << priv->host_port);
1243         if (ret != 0)
1244                 return ret;
1245
1246         ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1247                                  priv->host_port, ALE_VLAN, vid);
1248         if (ret != 0)
1249                 goto clean_vid;
1250
1251         ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1252                                  ALE_ALL_PORTS << priv->host_port,
1253                                  ALE_VLAN, vid, 0);
1254         if (ret != 0)
1255                 goto clean_vlan_ucast;
1256         return 0;
1257
1258 clean_vlan_ucast:
1259         cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1260                             priv->host_port, ALE_VLAN, vid);
1261 clean_vid:
1262         cpsw_ale_del_vlan(priv->ale, vid, 0);
1263         return ret;
1264 }
1265
1266 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1267                                     __be16 proto, u16 vid)
1268 {
1269         struct cpsw_priv *priv = netdev_priv(ndev);
1270
1271         if (vid == priv->data.default_vlan)
1272                 return 0;
1273
1274         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1275         return cpsw_add_vlan_ale_entry(priv, vid);
1276 }
1277
1278 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1279                                      __be16 proto, u16 vid)
1280 {
1281         struct cpsw_priv *priv = netdev_priv(ndev);
1282         int ret;
1283
1284         if (vid == priv->data.default_vlan)
1285                 return 0;
1286
1287         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1288         ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1289         if (ret != 0)
1290                 return ret;
1291
1292         ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1293                                  priv->host_port, ALE_VLAN, vid);
1294         if (ret != 0)
1295                 return ret;
1296
1297         return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1298                                   0, ALE_VLAN, vid);
1299 }
1300
1301 static const struct net_device_ops cpsw_netdev_ops = {
1302         .ndo_open               = cpsw_ndo_open,
1303         .ndo_stop               = cpsw_ndo_stop,
1304         .ndo_start_xmit         = cpsw_ndo_start_xmit,
1305         .ndo_change_rx_flags    = cpsw_ndo_change_rx_flags,
1306         .ndo_do_ioctl           = cpsw_ndo_ioctl,
1307         .ndo_validate_addr      = eth_validate_addr,
1308         .ndo_change_mtu         = eth_change_mtu,
1309         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
1310         .ndo_get_stats          = cpsw_ndo_get_stats,
1311         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
1312 #ifdef CONFIG_NET_POLL_CONTROLLER
1313         .ndo_poll_controller    = cpsw_ndo_poll_controller,
1314 #endif
1315         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
1316         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
1317 };
1318
1319 static void cpsw_get_drvinfo(struct net_device *ndev,
1320                              struct ethtool_drvinfo *info)
1321 {
1322         struct cpsw_priv *priv = netdev_priv(ndev);
1323
1324         strlcpy(info->driver, "TI CPSW Driver v1.0", sizeof(info->driver));
1325         strlcpy(info->version, "1.0", sizeof(info->version));
1326         strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1327 }
1328
1329 static u32 cpsw_get_msglevel(struct net_device *ndev)
1330 {
1331         struct cpsw_priv *priv = netdev_priv(ndev);
1332         return priv->msg_enable;
1333 }
1334
1335 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1336 {
1337         struct cpsw_priv *priv = netdev_priv(ndev);
1338         priv->msg_enable = value;
1339 }
1340
1341 static int cpsw_get_ts_info(struct net_device *ndev,
1342                             struct ethtool_ts_info *info)
1343 {
1344 #ifdef CONFIG_TI_CPTS
1345         struct cpsw_priv *priv = netdev_priv(ndev);
1346
1347         info->so_timestamping =
1348                 SOF_TIMESTAMPING_TX_HARDWARE |
1349                 SOF_TIMESTAMPING_TX_SOFTWARE |
1350                 SOF_TIMESTAMPING_RX_HARDWARE |
1351                 SOF_TIMESTAMPING_RX_SOFTWARE |
1352                 SOF_TIMESTAMPING_SOFTWARE |
1353                 SOF_TIMESTAMPING_RAW_HARDWARE;
1354         info->phc_index = priv->cpts->phc_index;
1355         info->tx_types =
1356                 (1 << HWTSTAMP_TX_OFF) |
1357                 (1 << HWTSTAMP_TX_ON);
1358         info->rx_filters =
1359                 (1 << HWTSTAMP_FILTER_NONE) |
1360                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1361 #else
1362         info->so_timestamping =
1363                 SOF_TIMESTAMPING_TX_SOFTWARE |
1364                 SOF_TIMESTAMPING_RX_SOFTWARE |
1365                 SOF_TIMESTAMPING_SOFTWARE;
1366         info->phc_index = -1;
1367         info->tx_types = 0;
1368         info->rx_filters = 0;
1369 #endif
1370         return 0;
1371 }
1372
1373 static int cpsw_get_settings(struct net_device *ndev,
1374                              struct ethtool_cmd *ecmd)
1375 {
1376         struct cpsw_priv *priv = netdev_priv(ndev);
1377         int slave_no = cpsw_slave_index(priv);
1378
1379         if (priv->slaves[slave_no].phy)
1380                 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1381         else
1382                 return -EOPNOTSUPP;
1383 }
1384
1385 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1386 {
1387         struct cpsw_priv *priv = netdev_priv(ndev);
1388         int slave_no = cpsw_slave_index(priv);
1389
1390         if (priv->slaves[slave_no].phy)
1391                 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1392         else
1393                 return -EOPNOTSUPP;
1394 }
1395
1396 static const struct ethtool_ops cpsw_ethtool_ops = {
1397         .get_drvinfo    = cpsw_get_drvinfo,
1398         .get_msglevel   = cpsw_get_msglevel,
1399         .set_msglevel   = cpsw_set_msglevel,
1400         .get_link       = ethtool_op_get_link,
1401         .get_ts_info    = cpsw_get_ts_info,
1402         .get_settings   = cpsw_get_settings,
1403         .set_settings   = cpsw_set_settings,
1404         .get_coalesce   = cpsw_get_coalesce,
1405         .set_coalesce   = cpsw_set_coalesce,
1406 };
1407
1408 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1409                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
1410 {
1411         void __iomem            *regs = priv->regs;
1412         int                     slave_num = slave->slave_num;
1413         struct cpsw_slave_data  *data = priv->data.slave_data + slave_num;
1414
1415         slave->data     = data;
1416         slave->regs     = regs + slave_reg_ofs;
1417         slave->sliver   = regs + sliver_reg_ofs;
1418         slave->port_vlan = data->dual_emac_res_vlan;
1419 }
1420
1421 static int cpsw_probe_dt(struct cpsw_platform_data *data,
1422                          struct platform_device *pdev)
1423 {
1424         struct device_node *node = pdev->dev.of_node;
1425         struct device_node *slave_node;
1426         int i = 0, ret;
1427         u32 prop;
1428
1429         if (!node)
1430                 return -EINVAL;
1431
1432         if (of_property_read_u32(node, "slaves", &prop)) {
1433                 pr_err("Missing slaves property in the DT.\n");
1434                 return -EINVAL;
1435         }
1436         data->slaves = prop;
1437
1438         if (of_property_read_u32(node, "active_slave", &prop)) {
1439                 pr_err("Missing active_slave property in the DT.\n");
1440                 ret = -EINVAL;
1441                 goto error_ret;
1442         }
1443         data->active_slave = prop;
1444
1445         if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1446                 pr_err("Missing cpts_clock_mult property in the DT.\n");
1447                 ret = -EINVAL;
1448                 goto error_ret;
1449         }
1450         data->cpts_clock_mult = prop;
1451
1452         if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1453                 pr_err("Missing cpts_clock_shift property in the DT.\n");
1454                 ret = -EINVAL;
1455                 goto error_ret;
1456         }
1457         data->cpts_clock_shift = prop;
1458
1459         data->slave_data = kcalloc(data->slaves, sizeof(struct cpsw_slave_data),
1460                                    GFP_KERNEL);
1461         if (!data->slave_data)
1462                 return -EINVAL;
1463
1464         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1465                 pr_err("Missing cpdma_channels property in the DT.\n");
1466                 ret = -EINVAL;
1467                 goto error_ret;
1468         }
1469         data->channels = prop;
1470
1471         if (of_property_read_u32(node, "ale_entries", &prop)) {
1472                 pr_err("Missing ale_entries property in the DT.\n");
1473                 ret = -EINVAL;
1474                 goto error_ret;
1475         }
1476         data->ale_entries = prop;
1477
1478         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1479                 pr_err("Missing bd_ram_size property in the DT.\n");
1480                 ret = -EINVAL;
1481                 goto error_ret;
1482         }
1483         data->bd_ram_size = prop;
1484
1485         if (of_property_read_u32(node, "rx_descs", &prop)) {
1486                 pr_err("Missing rx_descs property in the DT.\n");
1487                 ret = -EINVAL;
1488                 goto error_ret;
1489         }
1490         data->rx_descs = prop;
1491
1492         if (of_property_read_u32(node, "mac_control", &prop)) {
1493                 pr_err("Missing mac_control property in the DT.\n");
1494                 ret = -EINVAL;
1495                 goto error_ret;
1496         }
1497         data->mac_control = prop;
1498
1499         if (!of_property_read_u32(node, "dual_emac", &prop))
1500                 data->dual_emac = prop;
1501
1502         /*
1503          * Populate all the child nodes here...
1504          */
1505         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
1506         /* We do not want to force this, as in some cases may not have child */
1507         if (ret)
1508                 pr_warn("Doesn't have any child node\n");
1509
1510         for_each_node_by_name(slave_node, "slave") {
1511                 struct cpsw_slave_data *slave_data = data->slave_data + i;
1512                 const void *mac_addr = NULL;
1513                 u32 phyid;
1514                 int lenp;
1515                 const __be32 *parp;
1516                 struct device_node *mdio_node;
1517                 struct platform_device *mdio;
1518
1519                 parp = of_get_property(slave_node, "phy_id", &lenp);
1520                 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
1521                         pr_err("Missing slave[%d] phy_id property\n", i);
1522                         ret = -EINVAL;
1523                         goto error_ret;
1524                 }
1525                 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
1526                 phyid = be32_to_cpup(parp+1);
1527                 mdio = of_find_device_by_node(mdio_node);
1528                 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
1529                          PHY_ID_FMT, mdio->name, phyid);
1530
1531                 mac_addr = of_get_mac_address(slave_node);
1532                 if (mac_addr)
1533                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
1534
1535                 if (data->dual_emac) {
1536                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
1537                                                  &prop)) {
1538                                 pr_err("Missing dual_emac_res_vlan in DT.\n");
1539                                 slave_data->dual_emac_res_vlan = i+1;
1540                                 pr_err("Using %d as Reserved VLAN for %d slave\n",
1541                                        slave_data->dual_emac_res_vlan, i);
1542                         } else {
1543                                 slave_data->dual_emac_res_vlan = prop;
1544                         }
1545                 }
1546
1547                 i++;
1548         }
1549
1550         return 0;
1551
1552 error_ret:
1553         kfree(data->slave_data);
1554         return ret;
1555 }
1556
1557 static int cpsw_probe_dual_emac(struct platform_device *pdev,
1558                                 struct cpsw_priv *priv)
1559 {
1560         struct cpsw_platform_data       *data = &priv->data;
1561         struct net_device               *ndev;
1562         struct cpsw_priv                *priv_sl2;
1563         int ret = 0, i;
1564
1565         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
1566         if (!ndev) {
1567                 pr_err("cpsw: error allocating net_device\n");
1568                 return -ENOMEM;
1569         }
1570
1571         priv_sl2 = netdev_priv(ndev);
1572         spin_lock_init(&priv_sl2->lock);
1573         priv_sl2->data = *data;
1574         priv_sl2->pdev = pdev;
1575         priv_sl2->ndev = ndev;
1576         priv_sl2->dev  = &ndev->dev;
1577         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
1578         priv_sl2->rx_packet_max = max(rx_packet_max, 128);
1579
1580         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
1581                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
1582                         ETH_ALEN);
1583                 pr_info("cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
1584         } else {
1585                 random_ether_addr(priv_sl2->mac_addr);
1586                 pr_info("cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
1587         }
1588         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
1589
1590         priv_sl2->slaves = priv->slaves;
1591         priv_sl2->clk = priv->clk;
1592
1593         priv_sl2->coal_intvl = 0;
1594         priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
1595
1596         priv_sl2->cpsw_res = priv->cpsw_res;
1597         priv_sl2->regs = priv->regs;
1598         priv_sl2->host_port = priv->host_port;
1599         priv_sl2->host_port_regs = priv->host_port_regs;
1600         priv_sl2->wr_regs = priv->wr_regs;
1601         priv_sl2->dma = priv->dma;
1602         priv_sl2->txch = priv->txch;
1603         priv_sl2->rxch = priv->rxch;
1604         priv_sl2->ale = priv->ale;
1605         priv_sl2->emac_port = 1;
1606         priv->slaves[1].ndev = ndev;
1607         priv_sl2->cpts = priv->cpts;
1608         priv_sl2->version = priv->version;
1609
1610         for (i = 0; i < priv->num_irqs; i++) {
1611                 priv_sl2->irqs_table[i] = priv->irqs_table[i];
1612                 priv_sl2->num_irqs = priv->num_irqs;
1613         }
1614
1615         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1616
1617         ndev->netdev_ops = &cpsw_netdev_ops;
1618         SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
1619         netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);
1620
1621         /* register the network device */
1622         SET_NETDEV_DEV(ndev, &pdev->dev);
1623         ret = register_netdev(ndev);
1624         if (ret) {
1625                 pr_err("cpsw: error registering net device\n");
1626                 free_netdev(ndev);
1627                 ret = -ENODEV;
1628         }
1629
1630         return ret;
1631 }
1632
1633 static int cpsw_probe(struct platform_device *pdev)
1634 {
1635         struct cpsw_platform_data       *data;
1636         struct net_device               *ndev;
1637         struct cpsw_priv                *priv;
1638         struct cpdma_params             dma_params;
1639         struct cpsw_ale_params          ale_params;
1640         void __iomem                    *ss_regs, *wr_regs;
1641         struct resource                 *res;
1642         u32 slave_offset, sliver_offset, slave_size;
1643         int ret = 0, i, k = 0;
1644
1645         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
1646         if (!ndev) {
1647                 pr_err("error allocating net_device\n");
1648                 return -ENOMEM;
1649         }
1650
1651         platform_set_drvdata(pdev, ndev);
1652         priv = netdev_priv(ndev);
1653         spin_lock_init(&priv->lock);
1654         priv->pdev = pdev;
1655         priv->ndev = ndev;
1656         priv->dev  = &ndev->dev;
1657         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
1658         priv->rx_packet_max = max(rx_packet_max, 128);
1659         priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
1660         if (!ndev) {
1661                 pr_err("error allocating cpts\n");
1662                 goto clean_ndev_ret;
1663         }
1664
1665         /*
1666          * This may be required here for child devices.
1667          */
1668         pm_runtime_enable(&pdev->dev);
1669
1670         if (cpsw_probe_dt(&priv->data, pdev)) {
1671                 pr_err("cpsw: platform data missing\n");
1672                 ret = -ENODEV;
1673                 goto clean_ndev_ret;
1674         }
1675         data = &priv->data;
1676
1677         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
1678                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
1679                 pr_info("Detected MACID = %pM", priv->mac_addr);
1680         } else {
1681                 eth_random_addr(priv->mac_addr);
1682                 pr_info("Random MACID = %pM", priv->mac_addr);
1683         }
1684
1685         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1686
1687         priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves,
1688                                GFP_KERNEL);
1689         if (!priv->slaves) {
1690                 ret = -EBUSY;
1691                 goto clean_ndev_ret;
1692         }
1693         for (i = 0; i < data->slaves; i++)
1694                 priv->slaves[i].slave_num = i;
1695
1696         priv->slaves[0].ndev = ndev;
1697         priv->emac_port = 0;
1698
1699         priv->clk = clk_get(&pdev->dev, "fck");
1700         if (IS_ERR(priv->clk)) {
1701                 dev_err(&pdev->dev, "fck is not found\n");
1702                 ret = -ENODEV;
1703                 goto clean_slave_ret;
1704         }
1705         priv->coal_intvl = 0;
1706         priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
1707
1708         priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1709         if (!priv->cpsw_res) {
1710                 dev_err(priv->dev, "error getting i/o resource\n");
1711                 ret = -ENOENT;
1712                 goto clean_clk_ret;
1713         }
1714         if (!request_mem_region(priv->cpsw_res->start,
1715                                 resource_size(priv->cpsw_res), ndev->name)) {
1716                 dev_err(priv->dev, "failed request i/o region\n");
1717                 ret = -ENXIO;
1718                 goto clean_clk_ret;
1719         }
1720         ss_regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res));
1721         if (!ss_regs) {
1722                 dev_err(priv->dev, "unable to map i/o region\n");
1723                 goto clean_cpsw_iores_ret;
1724         }
1725         priv->regs = ss_regs;
1726         priv->version = __raw_readl(&priv->regs->id_ver);
1727         priv->host_port = HOST_PORT_NUM;
1728
1729         priv->cpsw_wr_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1730         if (!priv->cpsw_wr_res) {
1731                 dev_err(priv->dev, "error getting i/o resource\n");
1732                 ret = -ENOENT;
1733                 goto clean_iomap_ret;
1734         }
1735         if (!request_mem_region(priv->cpsw_wr_res->start,
1736                         resource_size(priv->cpsw_wr_res), ndev->name)) {
1737                 dev_err(priv->dev, "failed request i/o region\n");
1738                 ret = -ENXIO;
1739                 goto clean_iomap_ret;
1740         }
1741         wr_regs = ioremap(priv->cpsw_wr_res->start,
1742                                 resource_size(priv->cpsw_wr_res));
1743         if (!wr_regs) {
1744                 dev_err(priv->dev, "unable to map i/o region\n");
1745                 goto clean_cpsw_wr_iores_ret;
1746         }
1747         priv->wr_regs = wr_regs;
1748
1749         memset(&dma_params, 0, sizeof(dma_params));
1750         memset(&ale_params, 0, sizeof(ale_params));
1751
1752         switch (priv->version) {
1753         case CPSW_VERSION_1:
1754                 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
1755                 priv->cpts->reg       = ss_regs + CPSW1_CPTS_OFFSET;
1756                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
1757                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
1758                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
1759                 slave_offset         = CPSW1_SLAVE_OFFSET;
1760                 slave_size           = CPSW1_SLAVE_SIZE;
1761                 sliver_offset        = CPSW1_SLIVER_OFFSET;
1762                 dma_params.desc_mem_phys = 0;
1763                 break;
1764         case CPSW_VERSION_2:
1765                 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
1766                 priv->cpts->reg       = ss_regs + CPSW2_CPTS_OFFSET;
1767                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
1768                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
1769                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
1770                 slave_offset         = CPSW2_SLAVE_OFFSET;
1771                 slave_size           = CPSW2_SLAVE_SIZE;
1772                 sliver_offset        = CPSW2_SLIVER_OFFSET;
1773                 dma_params.desc_mem_phys =
1774                         (u32 __force) priv->cpsw_res->start + CPSW2_BD_OFFSET;
1775                 break;
1776         default:
1777                 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
1778                 ret = -ENODEV;
1779                 goto clean_cpsw_wr_iores_ret;
1780         }
1781         for (i = 0; i < priv->data.slaves; i++) {
1782                 struct cpsw_slave *slave = &priv->slaves[i];
1783                 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
1784                 slave_offset  += slave_size;
1785                 sliver_offset += SLIVER_SIZE;
1786         }
1787
1788         dma_params.dev          = &pdev->dev;
1789         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
1790         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
1791         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
1792         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
1793         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
1794
1795         dma_params.num_chan             = data->channels;
1796         dma_params.has_soft_reset       = true;
1797         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
1798         dma_params.desc_mem_size        = data->bd_ram_size;
1799         dma_params.desc_align           = 16;
1800         dma_params.has_ext_regs         = true;
1801         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
1802
1803         priv->dma = cpdma_ctlr_create(&dma_params);
1804         if (!priv->dma) {
1805                 dev_err(priv->dev, "error initializing dma\n");
1806                 ret = -ENOMEM;
1807                 goto clean_wr_iomap_ret;
1808         }
1809
1810         priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
1811                                        cpsw_tx_handler);
1812         priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
1813                                        cpsw_rx_handler);
1814
1815         if (WARN_ON(!priv->txch || !priv->rxch)) {
1816                 dev_err(priv->dev, "error initializing dma channels\n");
1817                 ret = -ENOMEM;
1818                 goto clean_dma_ret;
1819         }
1820
1821         ale_params.dev                  = &ndev->dev;
1822         ale_params.ale_ageout           = ale_ageout;
1823         ale_params.ale_entries          = data->ale_entries;
1824         ale_params.ale_ports            = data->slaves;
1825
1826         priv->ale = cpsw_ale_create(&ale_params);
1827         if (!priv->ale) {
1828                 dev_err(priv->dev, "error initializing ale engine\n");
1829                 ret = -ENODEV;
1830                 goto clean_dma_ret;
1831         }
1832
1833         ndev->irq = platform_get_irq(pdev, 0);
1834         if (ndev->irq < 0) {
1835                 dev_err(priv->dev, "error getting irq resource\n");
1836                 ret = -ENOENT;
1837                 goto clean_ale_ret;
1838         }
1839
1840         while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
1841                 for (i = res->start; i <= res->end; i++) {
1842                         if (request_irq(i, cpsw_interrupt, IRQF_DISABLED,
1843                                         dev_name(&pdev->dev), priv)) {
1844                                 dev_err(priv->dev, "error attaching irq\n");
1845                                 goto clean_ale_ret;
1846                         }
1847                         priv->irqs_table[k] = i;
1848                         priv->num_irqs = k + 1;
1849                 }
1850                 k++;
1851         }
1852
1853         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1854
1855         ndev->netdev_ops = &cpsw_netdev_ops;
1856         SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
1857         netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
1858
1859         /* register the network device */
1860         SET_NETDEV_DEV(ndev, &pdev->dev);
1861         ret = register_netdev(ndev);
1862         if (ret) {
1863                 dev_err(priv->dev, "error registering net device\n");
1864                 ret = -ENODEV;
1865                 goto clean_irq_ret;
1866         }
1867
1868         if (cpts_register(&pdev->dev, priv->cpts,
1869                           data->cpts_clock_mult, data->cpts_clock_shift))
1870                 dev_err(priv->dev, "error registering cpts device\n");
1871
1872         cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n",
1873                   priv->cpsw_res->start, ndev->irq);
1874
1875         if (priv->data.dual_emac) {
1876                 ret = cpsw_probe_dual_emac(pdev, priv);
1877                 if (ret) {
1878                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
1879                         goto clean_irq_ret;
1880                 }
1881         }
1882
1883         return 0;
1884
1885 clean_irq_ret:
1886         for (i = 0; i < priv->num_irqs; i++)
1887                 free_irq(priv->irqs_table[i], priv);
1888 clean_ale_ret:
1889         cpsw_ale_destroy(priv->ale);
1890 clean_dma_ret:
1891         cpdma_chan_destroy(priv->txch);
1892         cpdma_chan_destroy(priv->rxch);
1893         cpdma_ctlr_destroy(priv->dma);
1894 clean_wr_iomap_ret:
1895         iounmap(priv->wr_regs);
1896 clean_cpsw_wr_iores_ret:
1897         release_mem_region(priv->cpsw_wr_res->start,
1898                            resource_size(priv->cpsw_wr_res));
1899 clean_iomap_ret:
1900         iounmap(priv->regs);
1901 clean_cpsw_iores_ret:
1902         release_mem_region(priv->cpsw_res->start,
1903                            resource_size(priv->cpsw_res));
1904 clean_clk_ret:
1905         clk_put(priv->clk);
1906 clean_slave_ret:
1907         pm_runtime_disable(&pdev->dev);
1908         kfree(priv->slaves);
1909 clean_ndev_ret:
1910         kfree(priv->data.slave_data);
1911         free_netdev(priv->ndev);
1912         return ret;
1913 }
1914
1915 static int cpsw_remove(struct platform_device *pdev)
1916 {
1917         struct net_device *ndev = platform_get_drvdata(pdev);
1918         struct cpsw_priv *priv = netdev_priv(ndev);
1919         int i;
1920
1921         platform_set_drvdata(pdev, NULL);
1922         if (priv->data.dual_emac)
1923                 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
1924         unregister_netdev(ndev);
1925
1926         cpts_unregister(priv->cpts);
1927         for (i = 0; i < priv->num_irqs; i++)
1928                 free_irq(priv->irqs_table[i], priv);
1929
1930         cpsw_ale_destroy(priv->ale);
1931         cpdma_chan_destroy(priv->txch);
1932         cpdma_chan_destroy(priv->rxch);
1933         cpdma_ctlr_destroy(priv->dma);
1934         iounmap(priv->regs);
1935         release_mem_region(priv->cpsw_res->start,
1936                            resource_size(priv->cpsw_res));
1937         iounmap(priv->wr_regs);
1938         release_mem_region(priv->cpsw_wr_res->start,
1939                            resource_size(priv->cpsw_wr_res));
1940         pm_runtime_disable(&pdev->dev);
1941         clk_put(priv->clk);
1942         kfree(priv->slaves);
1943         kfree(priv->data.slave_data);
1944         if (priv->data.dual_emac)
1945                 free_netdev(cpsw_get_slave_ndev(priv, 1));
1946         free_netdev(ndev);
1947         return 0;
1948 }
1949
1950 static int cpsw_suspend(struct device *dev)
1951 {
1952         struct platform_device  *pdev = to_platform_device(dev);
1953         struct net_device       *ndev = platform_get_drvdata(pdev);
1954
1955         if (netif_running(ndev))
1956                 cpsw_ndo_stop(ndev);
1957         pm_runtime_put_sync(&pdev->dev);
1958
1959         return 0;
1960 }
1961
1962 static int cpsw_resume(struct device *dev)
1963 {
1964         struct platform_device  *pdev = to_platform_device(dev);
1965         struct net_device       *ndev = platform_get_drvdata(pdev);
1966
1967         pm_runtime_get_sync(&pdev->dev);
1968         if (netif_running(ndev))
1969                 cpsw_ndo_open(ndev);
1970         return 0;
1971 }
1972
1973 static const struct dev_pm_ops cpsw_pm_ops = {
1974         .suspend        = cpsw_suspend,
1975         .resume         = cpsw_resume,
1976 };
1977
1978 static const struct of_device_id cpsw_of_mtable[] = {
1979         { .compatible = "ti,cpsw", },
1980         { /* sentinel */ },
1981 };
1982 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
1983
1984 static struct platform_driver cpsw_driver = {
1985         .driver = {
1986                 .name    = "cpsw",
1987                 .owner   = THIS_MODULE,
1988                 .pm      = &cpsw_pm_ops,
1989                 .of_match_table = of_match_ptr(cpsw_of_mtable),
1990         },
1991         .probe = cpsw_probe,
1992         .remove = cpsw_remove,
1993 };
1994
1995 static int __init cpsw_init(void)
1996 {
1997         return platform_driver_register(&cpsw_driver);
1998 }
1999 late_initcall(cpsw_init);
2000
2001 static void __exit cpsw_exit(void)
2002 {
2003         platform_driver_unregister(&cpsw_driver);
2004 }
2005 module_exit(cpsw_exit);
2006
2007 MODULE_LICENSE("GPL");
2008 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2009 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2010 MODULE_DESCRIPTION("TI CPSW Ethernet driver");