drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <linux/slab.h>
  40 #include <net/checksum.h>
  41 #include <net/ip6_checksum.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/if_vlan.h>
  44 #include <scsi/fc/fc_fcoe.h>
  45
  46 #include "ixgbe.h"
  47 #include "ixgbe_common.h"
  48 #include "ixgbe_dcb_82599.h"
  49 #include "ixgbe_sriov.h"
  50
  51 char ixgbe_driver_name[] = "ixgbe";
  52 static const char ixgbe_driver_string[] =
  53                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  54
  55 #define DRV_VERSION "2.0.84-k2"
  56 const char ixgbe_driver_version[] = DRV_VERSION;
  57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
  58
  59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  60         [board_82598] = &ixgbe_82598_info,
  61         [board_82599] = &ixgbe_82599_info,
  62 };
  63
  64 /* ixgbe_pci_tbl - PCI Device ID Table
  65  *
  66  * Wildcard entries (PCI_ANY_ID) should come last
  67  * Last entry must be all 0s
  68  *
  69  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  70  *   Class, Class Mask, private data (not used) }
  71  */
  72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  96          board_82598 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 110          board_82599 },
 111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 112          board_82599 },
 113         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 114          board_82599 },
 115
 116         /* required last entry */
 117         {0, }
 118 };
 119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 120
 121 #ifdef CONFIG_IXGBE_DCA
 122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 123                             void *p);
 124 static struct notifier_block dca_notifier = {
 125         .notifier_call = ixgbe_notify_dca,
 126         .next          = NULL,
 127         .priority      = 0
 128 };
 129 #endif
 130
 131 #ifdef CONFIG_PCI_IOV
 132 static unsigned int max_vfs;
 133 module_param(max_vfs, uint, 0);
 134 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
 135                  "per physical function");
 136 #endif /* CONFIG_PCI_IOV */
 137
 138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 140 MODULE_LICENSE("GPL");
 141 MODULE_VERSION(DRV_VERSION);
 142
 143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 144
 145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 146 {
 147         struct ixgbe_hw *hw = &adapter->hw;
 148         u32 gcr;
 149         u32 gpie;
 150         u32 vmdctl;
 151
 152 #ifdef CONFIG_PCI_IOV
 153         /* disable iov and allow time for transactions to clear */
 154         pci_disable_sriov(adapter->pdev);
 155 #endif
 156
 157         /* turn off device IOV mode */
 158         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 159         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 160         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 161         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 162         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 163         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 164
 165         /* set default pool back to 0 */
 166         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 167         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 168         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 169
 170         /* take a breather then clean up driver data */
 171         msleep(100);
 172         if (adapter->vfinfo)
 173                 kfree(adapter->vfinfo);
 174         adapter->vfinfo = NULL;
 175
 176         adapter->num_vfs = 0;
 177         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 178 }
 179
 180 struct ixgbe_reg_info {
 181         u32 ofs;
 182         char *name;
 183 };
 184
 185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 186
 187         /* General Registers */
 188         {IXGBE_CTRL, "CTRL"},
 189         {IXGBE_STATUS, "STATUS"},
 190         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 191
 192         /* Interrupt Registers */
 193         {IXGBE_EICR, "EICR"},
 194
 195         /* RX Registers */
 196         {IXGBE_SRRCTL(0), "SRRCTL"},
 197         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 198         {IXGBE_RDLEN(0), "RDLEN"},
 199         {IXGBE_RDH(0), "RDH"},
 200         {IXGBE_RDT(0), "RDT"},
 201         {IXGBE_RXDCTL(0), "RXDCTL"},
 202         {IXGBE_RDBAL(0), "RDBAL"},
 203         {IXGBE_RDBAH(0), "RDBAH"},
 204
 205         /* TX Registers */
 206         {IXGBE_TDBAL(0), "TDBAL"},
 207         {IXGBE_TDBAH(0), "TDBAH"},
 208         {IXGBE_TDLEN(0), "TDLEN"},
 209         {IXGBE_TDH(0), "TDH"},
 210         {IXGBE_TDT(0), "TDT"},
 211         {IXGBE_TXDCTL(0), "TXDCTL"},
 212
 213         /* List Terminator */
 214         {}
 215 };
 216
 217
 218 /*
 219  * ixgbe_regdump - register printout routine
 220  */
 221 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 222 {
 223         int i = 0, j = 0;
 224         char rname[16];
 225         u32 regs[64];
 226
 227         switch (reginfo->ofs) {
 228         case IXGBE_SRRCTL(0):
 229                 for (i = 0; i < 64; i++)
 230                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 231                 break;
 232         case IXGBE_DCA_RXCTRL(0):
 233                 for (i = 0; i < 64; i++)
 234                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 235                 break;
 236         case IXGBE_RDLEN(0):
 237                 for (i = 0; i < 64; i++)
 238                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 239                 break;
 240         case IXGBE_RDH(0):
 241                 for (i = 0; i < 64; i++)
 242                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 243                 break;
 244         case IXGBE_RDT(0):
 245                 for (i = 0; i < 64; i++)
 246                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 247                 break;
 248         case IXGBE_RXDCTL(0):
 249                 for (i = 0; i < 64; i++)
 250                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 251                 break;
 252         case IXGBE_RDBAL(0):
 253                 for (i = 0; i < 64; i++)
 254                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 255                 break;
 256         case IXGBE_RDBAH(0):
 257                 for (i = 0; i < 64; i++)
 258                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 259                 break;
 260         case IXGBE_TDBAL(0):
 261                 for (i = 0; i < 64; i++)
 262                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 263                 break;
 264         case IXGBE_TDBAH(0):
 265                 for (i = 0; i < 64; i++)
 266                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 267                 break;
 268         case IXGBE_TDLEN(0):
 269                 for (i = 0; i < 64; i++)
 270                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 271                 break;
 272         case IXGBE_TDH(0):
 273                 for (i = 0; i < 64; i++)
 274                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 275                 break;
 276         case IXGBE_TDT(0):
 277                 for (i = 0; i < 64; i++)
 278                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 279                 break;
 280         case IXGBE_TXDCTL(0):
 281                 for (i = 0; i < 64; i++)
 282                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 283                 break;
 284         default:
 285                 printk(KERN_INFO "%-15s %08x\n", reginfo->name,
 286                         IXGBE_READ_REG(hw, reginfo->ofs));
 287                 return;
 288         }
 289
 290         for (i = 0; i < 8; i++) {
 291                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 292                 printk(KERN_ERR "%-15s ", rname);
 293                 for (j = 0; j < 8; j++)
 294                         printk(KERN_CONT "%08x ", regs[i*8+j]);
 295                 printk(KERN_CONT "\n");
 296         }
 297
 298 }
 299
 300 /*
 301  * ixgbe_dump - Print registers, tx-rings and rx-rings
 302  */
 303 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 304 {
 305         struct net_device *netdev = adapter->netdev;
 306         struct ixgbe_hw *hw = &adapter->hw;
 307         struct ixgbe_reg_info *reginfo;
 308         int n = 0;
 309         struct ixgbe_ring *tx_ring;
 310         struct ixgbe_tx_buffer *tx_buffer_info;
 311         union ixgbe_adv_tx_desc *tx_desc;
 312         struct my_u0 { u64 a; u64 b; } *u0;
 313         struct ixgbe_ring *rx_ring;
 314         union ixgbe_adv_rx_desc *rx_desc;
 315         struct ixgbe_rx_buffer *rx_buffer_info;
 316         u32 staterr;
 317         int i = 0;
 318
 319         if (!netif_msg_hw(adapter))
 320                 return;
 321
 322         /* Print netdevice Info */
 323         if (netdev) {
 324                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 325                 printk(KERN_INFO "Device Name     state            "
 326                         "trans_start      last_rx\n");
 327                 printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
 328                 netdev->name,
 329                 netdev->state,
 330                 netdev->trans_start,
 331                 netdev->last_rx);
 332         }
 333
 334         /* Print Registers */
 335         dev_info(&adapter->pdev->dev, "Register Dump\n");
 336         printk(KERN_INFO " Register Name   Value\n");
 337         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 338              reginfo->name; reginfo++) {
 339                 ixgbe_regdump(hw, reginfo);
 340         }
 341
 342         /* Print TX Ring Summary */
 343         if (!netdev || !netif_running(netdev))
 344                 goto exit;
 345
 346         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 347         printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma  ] "
 348                 "leng ntw timestamp\n");
 349         for (n = 0; n < adapter->num_tx_queues; n++) {
 350                 tx_ring = adapter->tx_ring[n];
 351                 tx_buffer_info =
 352                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 353                 printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n",
 354                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 355                            (u64)tx_buffer_info->dma,
 356                            tx_buffer_info->length,
 357                            tx_buffer_info->next_to_watch,
 358                            (u64)tx_buffer_info->time_stamp);
 359         }
 360
 361         /* Print TX Rings */
 362         if (!netif_msg_tx_done(adapter))
 363                 goto rx_ring_summary;
 364
 365         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 366
 367         /* Transmit Descriptor Formats
 368          *
 369          * Advanced Transmit Descriptor
 370          *   +--------------------------------------------------------------+
 371          * 0 |         Buffer Address [63:0]                                |
 372          *   +--------------------------------------------------------------+
 373          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 374          *   +--------------------------------------------------------------+
 375          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 376          */
 377
 378         for (n = 0; n < adapter->num_tx_queues; n++) {
 379                 tx_ring = adapter->tx_ring[n];
 380                 printk(KERN_INFO "------------------------------------\n");
 381                 printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 382                 printk(KERN_INFO "------------------------------------\n");
 383                 printk(KERN_INFO "T [desc]     [address 63:0  ] "
 384                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 385                         "leng  ntw timestamp        bi->skb\n");
 386
 387                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 388                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 389                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 390                         u0 = (struct my_u0 *)tx_desc;
 391                         printk(KERN_INFO "T [0x%03X]    %016llX %016llX %016llX"
 392                                 " %04X  %3X %016llX %p", i,
 393                                 le64_to_cpu(u0->a),
 394                                 le64_to_cpu(u0->b),
 395                                 (u64)tx_buffer_info->dma,
 396                                 tx_buffer_info->length,
 397                                 tx_buffer_info->next_to_watch,
 398                                 (u64)tx_buffer_info->time_stamp,
 399                                 tx_buffer_info->skb);
 400                         if (i == tx_ring->next_to_use &&
 401                                 i == tx_ring->next_to_clean)
 402                                 printk(KERN_CONT " NTC/U\n");
 403                         else if (i == tx_ring->next_to_use)
 404                                 printk(KERN_CONT " NTU\n");
 405                         else if (i == tx_ring->next_to_clean)
 406                                 printk(KERN_CONT " NTC\n");
 407                         else
 408                                 printk(KERN_CONT "\n");
 409
 410                         if (netif_msg_pktdata(adapter) &&
 411                                 tx_buffer_info->dma != 0)
 412                                 print_hex_dump(KERN_INFO, "",
 413                                         DUMP_PREFIX_ADDRESS, 16, 1,
 414                                         phys_to_virt(tx_buffer_info->dma),
 415                                         tx_buffer_info->length, true);
 416                 }
 417         }
 418
 419         /* Print RX Rings Summary */
 420 rx_ring_summary:
 421         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 422         printk(KERN_INFO "Queue [NTU] [NTC]\n");
 423         for (n = 0; n < adapter->num_rx_queues; n++) {
 424                 rx_ring = adapter->rx_ring[n];
 425                 printk(KERN_INFO "%5d %5X %5X\n", n,
 426                            rx_ring->next_to_use, rx_ring->next_to_clean);
 427         }
 428
 429         /* Print RX Rings */
 430         if (!netif_msg_rx_status(adapter))
 431                 goto exit;
 432
 433         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 434
 435         /* Advanced Receive Descriptor (Read) Format
 436          *    63                                           1        0
 437          *    +-----------------------------------------------------+
 438          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 439          *    +----------------------------------------------+------+
 440          *  8 |       Header Buffer Address [63:1]           |  DD  |
 441          *    +-----------------------------------------------------+
 442          *
 443          *
 444          * Advanced Receive Descriptor (Write-Back) Format
 445          *
 446          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 447          *   +------------------------------------------------------+
 448          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 449          *   | Checksum   Ident  |   |           |    | Type | Type |
 450          *   +------------------------------------------------------+
 451          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 452          *   +------------------------------------------------------+
 453          *   63       48 47    32 31            20 19               0
 454          */
 455         for (n = 0; n < adapter->num_rx_queues; n++) {
 456                 rx_ring = adapter->rx_ring[n];
 457                 printk(KERN_INFO "------------------------------------\n");
 458                 printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 459                 printk(KERN_INFO "------------------------------------\n");
 460                 printk(KERN_INFO "R  [desc]      [ PktBuf     A0] "
 461                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 462                         "<-- Adv Rx Read format\n");
 463                 printk(KERN_INFO "RWB[desc]      [PcsmIpSHl PtRs] "
 464                         "[vl er S cks ln] ---------------- [bi->skb] "
 465                         "<-- Adv Rx Write-Back format\n");
 466
 467                 for (i = 0; i < rx_ring->count; i++) {
 468                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 469                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 470                         u0 = (struct my_u0 *)rx_desc;
 471                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 472                         if (staterr & IXGBE_RXD_STAT_DD) {
 473                                 /* Descriptor Done */
 474                                 printk(KERN_INFO "RWB[0x%03X]     %016llX "
 475                                         "%016llX ---------------- %p", i,
 476                                         le64_to_cpu(u0->a),
 477                                         le64_to_cpu(u0->b),
 478                                         rx_buffer_info->skb);
 479                         } else {
 480                                 printk(KERN_INFO "R  [0x%03X]     %016llX "
 481                                         "%016llX %016llX %p", i,
 482                                         le64_to_cpu(u0->a),
 483                                         le64_to_cpu(u0->b),
 484                                         (u64)rx_buffer_info->dma,
 485                                         rx_buffer_info->skb);
 486
 487                                 if (netif_msg_pktdata(adapter)) {
 488                                         print_hex_dump(KERN_INFO, "",
 489                                            DUMP_PREFIX_ADDRESS, 16, 1,
 490                                            phys_to_virt(rx_buffer_info->dma),
 491                                            rx_ring->rx_buf_len, true);
 492
 493                                         if (rx_ring->rx_buf_len
 494                                                 < IXGBE_RXBUFFER_2048)
 495                                                 print_hex_dump(KERN_INFO, "",
 496                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 497                                                   phys_to_virt(
 498                                                     rx_buffer_info->page_dma +
 499                                                     rx_buffer_info->page_offset
 500                                                   ),
 501                                                   PAGE_SIZE/2, true);
 502                                 }
 503                         }
 504
 505                         if (i == rx_ring->next_to_use)
 506                                 printk(KERN_CONT " NTU\n");
 507                         else if (i == rx_ring->next_to_clean)
 508                                 printk(KERN_CONT " NTC\n");
 509                         else
 510                                 printk(KERN_CONT "\n");
 511
 512                 }
 513         }
 514
 515 exit:
 516         return;
 517 }
 518
 519 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 520 {
 521         u32 ctrl_ext;
 522
 523         /* Let firmware take over control of h/w */
 524         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 525         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 526                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 527 }
 528
 529 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 530 {
 531         u32 ctrl_ext;
 532
 533         /* Let firmware know the driver has taken over */
 534         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 535         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 536                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 537 }
 538
 539 /*
 540  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 541  * @adapter: pointer to adapter struct
 542  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 543  * @queue: queue to map the corresponding interrupt to
 544  * @msix_vector: the vector to map to the corresponding queue
 545  *
 546  */
 547 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 548                            u8 queue, u8 msix_vector)
 549 {
 550         u32 ivar, index;
 551         struct ixgbe_hw *hw = &adapter->hw;
 552         switch (hw->mac.type) {
 553         case ixgbe_mac_82598EB:
 554                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 555                 if (direction == -1)
 556                         direction = 0;
 557                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 558                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 559                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 560                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 561                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 562                 break;
 563         case ixgbe_mac_82599EB:
 564                 if (direction == -1) {
 565                         /* other causes */
 566                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 567                         index = ((queue & 1) * 8);
 568                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 569                         ivar &= ~(0xFF << index);
 570                         ivar |= (msix_vector << index);
 571                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 572                         break;
 573                 } else {
 574                         /* tx or rx causes */
 575                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 576                         index = ((16 * (queue & 1)) + (8 * direction));
 577                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 578                         ivar &= ~(0xFF << index);
 579                         ivar |= (msix_vector << index);
 580                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 581                         break;
 582                 }
 583         default:
 584                 break;
 585         }
 586 }
 587
 588 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 589                                           u64 qmask)
 590 {
 591         u32 mask;
 592
 593         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 594                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 595                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 596         } else {
 597                 mask = (qmask & 0xFFFFFFFF);
 598                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 599                 mask = (qmask >> 32);
 600                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 601         }
 602 }
 603
 604 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 605                                              struct ixgbe_tx_buffer
 606                                              *tx_buffer_info)
 607 {
 608         if (tx_buffer_info->dma) {
 609                 if (tx_buffer_info->mapped_as_page)
 610                         dma_unmap_page(&adapter->pdev->dev,
 611                                        tx_buffer_info->dma,
 612                                        tx_buffer_info->length,
 613                                        DMA_TO_DEVICE);
 614                 else
 615                         dma_unmap_single(&adapter->pdev->dev,
 616                                          tx_buffer_info->dma,
 617                                          tx_buffer_info->length,
 618                                          DMA_TO_DEVICE);
 619                 tx_buffer_info->dma = 0;
 620         }
 621         if (tx_buffer_info->skb) {
 622                 dev_kfree_skb_any(tx_buffer_info->skb);
 623                 tx_buffer_info->skb = NULL;
 624         }
 625         tx_buffer_info->time_stamp = 0;
 626         /* tx_buffer_info must be completely set up in the transmit path */
 627 }
 628
 629 /**
 630  * ixgbe_tx_xon_state - check the tx ring xon state
 631  * @adapter: the ixgbe adapter
 632  * @tx_ring: the corresponding tx_ring
 633  *
 634  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 635  * corresponding TC of this tx_ring when checking TFCS.
 636  *
 637  * Returns : true if in xon state (currently not paused)
 638  */
 639 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
 640                                       struct ixgbe_ring *tx_ring)
 641 {
 642         u32 txoff = IXGBE_TFCS_TXOFF;
 643
 644 #ifdef CONFIG_IXGBE_DCB
 645         if (adapter->dcb_cfg.pfc_mode_enable) {
 646                 int tc;
 647                 int reg_idx = tx_ring->reg_idx;
 648                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 649
 650                 switch (adapter->hw.mac.type) {
 651                 case ixgbe_mac_82598EB:
 652                         tc = reg_idx >> 2;
 653                         txoff = IXGBE_TFCS_TXOFF0;
 654                         break;
 655                 case ixgbe_mac_82599EB:
 656                         tc = 0;
 657                         txoff = IXGBE_TFCS_TXOFF;
 658                         if (dcb_i == 8) {
 659                                 /* TC0, TC1 */
 660                                 tc = reg_idx >> 5;
 661                                 if (tc == 2) /* TC2, TC3 */
 662                                         tc += (reg_idx - 64) >> 4;
 663                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 664                                         tc += 1 + ((reg_idx - 96) >> 3);
 665                         } else if (dcb_i == 4) {
 666                                 /* TC0, TC1 */
 667                                 tc = reg_idx >> 6;
 668                                 if (tc == 1) {
 669                                         tc += (reg_idx - 64) >> 5;
 670                                         if (tc == 2) /* TC2, TC3 */
 671                                                 tc += (reg_idx - 96) >> 4;
 672                                 }
 673                         }
 674                         break;
 675                 default:
 676                         tc = 0;
 677                 }
 678                 txoff <<= tc;
 679         }
 680 #endif
 681         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 682 }
 683
 684 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 685                                        struct ixgbe_ring *tx_ring,
 686                                        unsigned int eop)
 687 {
 688         struct ixgbe_hw *hw = &adapter->hw;
 689
 690         /* Detect a transmit hang in hardware, this serializes the
 691          * check with the clearing of time_stamp and movement of eop */
 692         adapter->detect_tx_hung = false;
 693         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 694             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 695             ixgbe_tx_xon_state(adapter, tx_ring)) {
 696                 /* detected Tx unit hang */
 697                 union ixgbe_adv_tx_desc *tx_desc;
 698                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 699                 e_err(drv, "Detected Tx Unit Hang\n"
 700                       "  Tx Queue             <%d>\n"
 701                       "  TDH, TDT             <%x>, <%x>\n"
 702                       "  next_to_use          <%x>\n"
 703                       "  next_to_clean        <%x>\n"
 704                       "tx_buffer_info[next_to_clean]\n"
 705                       "  time_stamp           <%lx>\n"
 706                       "  jiffies              <%lx>\n",
 707                       tx_ring->queue_index,
 708                       IXGBE_READ_REG(hw, tx_ring->head),
 709                       IXGBE_READ_REG(hw, tx_ring->tail),
 710                       tx_ring->next_to_use, eop,
 711                       tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 712                 return true;
 713         }
 714
 715         return false;
 716 }
 717
 718 #define IXGBE_MAX_TXD_PWR       14
 719 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 720
 721 /* Tx Descriptors needed, worst case */
 722 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 723                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 724 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 725         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 726
 727 static void ixgbe_tx_timeout(struct net_device *netdev);
 728
 729 /**
 730  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 731  * @q_vector: structure containing interrupt and ring information
 732  * @tx_ring: tx ring to clean
 733  **/
 734 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 735                                struct ixgbe_ring *tx_ring)
 736 {
 737         struct ixgbe_adapter *adapter = q_vector->adapter;
 738         struct net_device *netdev = adapter->netdev;
 739         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 740         struct ixgbe_tx_buffer *tx_buffer_info;
 741         unsigned int i, eop, count = 0;
 742         unsigned int total_bytes = 0, total_packets = 0;
 743
 744         i = tx_ring->next_to_clean;
 745         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 746         eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 747
 748         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 749                (count < tx_ring->work_limit)) {
 750                 bool cleaned = false;
 751                 rmb(); /* read buffer_info after eop_desc */
 752                 for ( ; !cleaned; count++) {
 753                         struct sk_buff *skb;
 754                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 755                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 756                         cleaned = (i == eop);
 757                         skb = tx_buffer_info->skb;
 758
 759                         if (cleaned && skb) {
 760                                 unsigned int segs, bytecount;
 761                                 unsigned int hlen = skb_headlen(skb);
 762
 763                                 /* gso_segs is currently only valid for tcp */
 764                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 765 #ifdef IXGBE_FCOE
 766                                 /* adjust for FCoE Sequence Offload */
 767                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 768                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 769                                     skb_is_gso(skb)) {
 770                                         hlen = skb_transport_offset(skb) +
 771                                                 sizeof(struct fc_frame_header) +
 772                                                 sizeof(struct fcoe_crc_eof);
 773                                         segs = DIV_ROUND_UP(skb->len - hlen,
 774                                                 skb_shinfo(skb)->gso_size);
 775                                 }
 776 #endif /* IXGBE_FCOE */
 777                                 /* multiply data chunks by size of headers */
 778                                 bytecount = ((segs - 1) * hlen) + skb->len;
 779                                 total_packets += segs;
 780                                 total_bytes += bytecount;
 781                         }
 782
 783                         ixgbe_unmap_and_free_tx_resource(adapter,
 784                                                          tx_buffer_info);
 785
 786                         tx_desc->wb.status = 0;
 787
 788                         i++;
 789                         if (i == tx_ring->count)
 790                                 i = 0;
 791                 }
 792
 793                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 794                 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 795         }
 796
 797         tx_ring->next_to_clean = i;
 798
 799 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 800         if (unlikely(count && netif_carrier_ok(netdev) &&
 801                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 802                 /* Make sure that anybody stopping the queue after this
 803                  * sees the new next_to_clean.
 804                  */
 805                 smp_mb();
 806                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 807                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 808                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 809                         ++tx_ring->restart_queue;
 810                 }
 811         }
 812
 813         if (adapter->detect_tx_hung) {
 814                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 815                         /* schedule immediate reset if we believe we hung */
 816                         e_info(probe, "tx hang %d detected, resetting "
 817                                "adapter\n", adapter->tx_timeout_count + 1);
 818                         ixgbe_tx_timeout(adapter->netdev);
 819                 }
 820         }
 821
 822         /* re-arm the interrupt */
 823         if (count >= tx_ring->work_limit)
 824                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 825
 826         tx_ring->total_bytes += total_bytes;
 827         tx_ring->total_packets += total_packets;
 828         tx_ring->stats.packets += total_packets;
 829         tx_ring->stats.bytes += total_bytes;
 830         return (count < tx_ring->work_limit);
 831 }
 832
 833 #ifdef CONFIG_IXGBE_DCA
 834 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 835                                 struct ixgbe_ring *rx_ring)
 836 {
 837         u32 rxctrl;
 838         int cpu = get_cpu();
 839         int q = rx_ring->reg_idx;
 840
 841         if (rx_ring->cpu != cpu) {
 842                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 843                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 844                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 845                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 846                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 847                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 848                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 849                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 850                 }
 851                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 852                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 853                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 854                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 855                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 856                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 857                 rx_ring->cpu = cpu;
 858         }
 859         put_cpu();
 860 }
 861
 862 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 863                                 struct ixgbe_ring *tx_ring)
 864 {
 865         u32 txctrl;
 866         int cpu = get_cpu();
 867         int q = tx_ring->reg_idx;
 868         struct ixgbe_hw *hw = &adapter->hw;
 869
 870         if (tx_ring->cpu != cpu) {
 871                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 872                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
 873                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 874                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 875                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 876                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
 877                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 878                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
 879                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 880                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 881                                   IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 882                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 883                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
 884                 }
 885                 tx_ring->cpu = cpu;
 886         }
 887         put_cpu();
 888 }
 889
 890 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 891 {
 892         int i;
 893
 894         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 895                 return;
 896
 897         /* always use CB2 mode, difference is masked in the CB driver */
 898         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 899
 900         for (i = 0; i < adapter->num_tx_queues; i++) {
 901                 adapter->tx_ring[i]->cpu = -1;
 902                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
 903         }
 904         for (i = 0; i < adapter->num_rx_queues; i++) {
 905                 adapter->rx_ring[i]->cpu = -1;
 906                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
 907         }
 908 }
 909
 910 static int __ixgbe_notify_dca(struct device *dev, void *data)
 911 {
 912         struct net_device *netdev = dev_get_drvdata(dev);
 913         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 914         unsigned long event = *(unsigned long *)data;
 915
 916         switch (event) {
 917         case DCA_PROVIDER_ADD:
 918                 /* if we're already enabled, don't do it again */
 919                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 920                         break;
 921                 if (dca_add_requester(dev) == 0) {
 922                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 923                         ixgbe_setup_dca(adapter);
 924                         break;
 925                 }
 926                 /* Fall Through since DCA is disabled. */
 927         case DCA_PROVIDER_REMOVE:
 928                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 929                         dca_remove_requester(dev);
 930                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 931                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 932                 }
 933                 break;
 934         }
 935
 936         return 0;
 937 }
 938
 939 #endif /* CONFIG_IXGBE_DCA */
 940 /**
 941  * ixgbe_receive_skb - Send a completed packet up the stack
 942  * @adapter: board private structure
 943  * @skb: packet to send up
 944  * @status: hardware indication of status of receive
 945  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 946  * @rx_desc: rx descriptor
 947  **/
 948 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 949                               struct sk_buff *skb, u8 status,
 950                               struct ixgbe_ring *ring,
 951                               union ixgbe_adv_rx_desc *rx_desc)
 952 {
 953         struct ixgbe_adapter *adapter = q_vector->adapter;
 954         struct napi_struct *napi = &q_vector->napi;
 955         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 956         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 957
 958         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 959                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 960                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 961                 else
 962                         napi_gro_receive(napi, skb);
 963         } else {
 964                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 965                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 966                 else
 967                         netif_rx(skb);
 968         }
 969 }
 970
 971 /**
 972  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 973  * @adapter: address of board private structure
 974  * @status_err: hardware indication of status of receive
 975  * @skb: skb currently being received and modified
 976  **/
 977 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 978                                      union ixgbe_adv_rx_desc *rx_desc,
 979                                      struct sk_buff *skb)
 980 {
 981         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 982
 983         skb->ip_summed = CHECKSUM_NONE;
 984
 985         /* Rx csum disabled */
 986         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 987                 return;
 988
 989         /* if IP and error */
 990         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 991             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 992                 adapter->hw_csum_rx_error++;
 993                 return;
 994         }
 995
 996         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 997                 return;
 998
 999         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1000                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1001
1002                 /*
1003                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1004                  * checksum errors.
1005                  */
1006                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1007                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1008                         return;
1009
1010                 adapter->hw_csum_rx_error++;
1011                 return;
1012         }
1013
1014         /* It must be a TCP or UDP packet with a valid checksum */
1015         skb->ip_summed = CHECKSUM_UNNECESSARY;
1016 }
1017
1018 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
1019                                          struct ixgbe_ring *rx_ring, u32 val)
1020 {
1021         /*
1022          * Force memory writes to complete before letting h/w
1023          * know there are new descriptors to fetch.  (Only
1024          * applicable for weak-ordered memory model archs,
1025          * such as IA-64).
1026          */
1027         wmb();
1028         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1029 }
1030
1031 /**
1032  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1033  * @adapter: address of board private structure
1034  **/
1035 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
1036                                    struct ixgbe_ring *rx_ring,
1037                                    int cleaned_count)
1038 {
1039         struct net_device *netdev = adapter->netdev;
1040         struct pci_dev *pdev = adapter->pdev;
1041         union ixgbe_adv_rx_desc *rx_desc;
1042         struct ixgbe_rx_buffer *bi;
1043         unsigned int i;
1044         unsigned int bufsz = rx_ring->rx_buf_len;
1045
1046         i = rx_ring->next_to_use;
1047         bi = &rx_ring->rx_buffer_info[i];
1048
1049         while (cleaned_count--) {
1050                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1051
1052                 if (!bi->page_dma &&
1053                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
1054                         if (!bi->page) {
1055                                 bi->page = netdev_alloc_page(netdev);
1056                                 if (!bi->page) {
1057                                         adapter->alloc_rx_page_failed++;
1058                                         goto no_buffers;
1059                                 }
1060                                 bi->page_offset = 0;
1061                         } else {
1062                                 /* use a half page if we're re-using */
1063                                 bi->page_offset ^= (PAGE_SIZE / 2);
1064                         }
1065
1066                         bi->page_dma = dma_map_page(&pdev->dev, bi->page,
1067                                                     bi->page_offset,
1068                                                     (PAGE_SIZE / 2),
1069                                                     DMA_FROM_DEVICE);
1070                 }
1071
1072                 if (!bi->skb) {
1073                         struct sk_buff *skb = netdev_alloc_skb_ip_align(netdev,
1074                                                                         bufsz);
1075                         bi->skb = skb;
1076
1077                         if (!skb) {
1078                                 adapter->alloc_rx_buff_failed++;
1079                                 goto no_buffers;
1080                         }
1081                         /* initialize queue mapping */
1082                         skb_record_rx_queue(skb, rx_ring->queue_index);
1083                 }
1084
1085                 if (!bi->dma) {
1086                         bi->dma = dma_map_single(&pdev->dev,
1087                                                  bi->skb->data,
1088                                                  rx_ring->rx_buf_len,
1089                                                  DMA_FROM_DEVICE);
1090                 }
1091                 /* Refresh the desc even if buffer_addrs didn't change because
1092                  * each write-back erases this info. */
1093                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1094                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1095                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1096                 } else {
1097                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1098                 }
1099
1100                 i++;
1101                 if (i == rx_ring->count)
1102                         i = 0;
1103                 bi = &rx_ring->rx_buffer_info[i];
1104         }
1105
1106 no_buffers:
1107         if (rx_ring->next_to_use != i) {
1108                 rx_ring->next_to_use = i;
1109                 if (i-- == 0)
1110                         i = (rx_ring->count - 1);
1111
1112                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
1113         }
1114 }
1115
1116 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1117 {
1118         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1119 }
1120
1121 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1122 {
1123         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1124 }
1125
1126 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1127 {
1128         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1129                 IXGBE_RXDADV_RSCCNT_MASK) >>
1130                 IXGBE_RXDADV_RSCCNT_SHIFT;
1131 }
1132
1133 /**
1134  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1135  * @skb: pointer to the last skb in the rsc queue
1136  * @count: pointer to number of packets coalesced in this context
1137  *
1138  * This function changes a queue full of hw rsc buffers into a completed
1139  * packet.  It uses the ->prev pointers to find the first packet and then
1140  * turns it into the frag list owner.
1141  **/
1142 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1143                                                         u64 *count)
1144 {
1145         unsigned int frag_list_size = 0;
1146
1147         while (skb->prev) {
1148                 struct sk_buff *prev = skb->prev;
1149                 frag_list_size += skb->len;
1150                 skb->prev = NULL;
1151                 skb = prev;
1152                 *count += 1;
1153         }
1154
1155         skb_shinfo(skb)->frag_list = skb->next;
1156         skb->next = NULL;
1157         skb->len += frag_list_size;
1158         skb->data_len += frag_list_size;
1159         skb->truesize += frag_list_size;
1160         return skb;
1161 }
1162
1163 struct ixgbe_rsc_cb {
1164         dma_addr_t dma;
1165         bool delay_unmap;
1166 };
1167
1168 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1169
1170 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1171                                struct ixgbe_ring *rx_ring,
1172                                int *work_done, int work_to_do)
1173 {
1174         struct ixgbe_adapter *adapter = q_vector->adapter;
1175         struct net_device *netdev = adapter->netdev;
1176         struct pci_dev *pdev = adapter->pdev;
1177         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1178         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1179         struct sk_buff *skb;
1180         unsigned int i, rsc_count = 0;
1181         u32 len, staterr;
1182         u16 hdr_info;
1183         bool cleaned = false;
1184         int cleaned_count = 0;
1185         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1186 #ifdef IXGBE_FCOE
1187         int ddp_bytes = 0;
1188 #endif /* IXGBE_FCOE */
1189
1190         i = rx_ring->next_to_clean;
1191         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1192         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1193         rx_buffer_info = &rx_ring->rx_buffer_info[i];
1194
1195         while (staterr & IXGBE_RXD_STAT_DD) {
1196                 u32 upper_len = 0;
1197                 if (*work_done >= work_to_do)
1198                         break;
1199                 (*work_done)++;
1200
1201                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1202                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1203                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1204                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1205                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1206                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1207                         if ((len > IXGBE_RX_HDR_SIZE) ||
1208                             (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1209                                 len = IXGBE_RX_HDR_SIZE;
1210                 } else {
1211                         len = le16_to_cpu(rx_desc->wb.upper.length);
1212                 }
1213
1214                 cleaned = true;
1215                 skb = rx_buffer_info->skb;
1216                 prefetch(skb->data);
1217                 rx_buffer_info->skb = NULL;
1218
1219                 if (rx_buffer_info->dma) {
1220                         if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1221                             (!(staterr & IXGBE_RXD_STAT_EOP)) &&
1222                                  (!(skb->prev))) {
1223                                 /*
1224                                  * When HWRSC is enabled, delay unmapping
1225                                  * of the first packet. It carries the
1226                                  * header information, HW may still
1227                                  * access the header after the writeback.
1228                                  * Only unmap it when EOP is reached
1229                                  */
1230                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1231                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1232                         } else {
1233                                 dma_unmap_single(&pdev->dev,
1234                                                  rx_buffer_info->dma,
1235                                                  rx_ring->rx_buf_len,
1236                                                  DMA_FROM_DEVICE);
1237                         }
1238                         rx_buffer_info->dma = 0;
1239                         skb_put(skb, len);
1240                 }
1241
1242                 if (upper_len) {
1243                         dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1244                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
1245                         rx_buffer_info->page_dma = 0;
1246                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1247                                            rx_buffer_info->page,
1248                                            rx_buffer_info->page_offset,
1249                                            upper_len);
1250
1251                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1252                             (page_count(rx_buffer_info->page) != 1))
1253                                 rx_buffer_info->page = NULL;
1254                         else
1255                                 get_page(rx_buffer_info->page);
1256
1257                         skb->len += upper_len;
1258                         skb->data_len += upper_len;
1259                         skb->truesize += upper_len;
1260                 }
1261
1262                 i++;
1263                 if (i == rx_ring->count)
1264                         i = 0;
1265
1266                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1267                 prefetch(next_rxd);
1268                 cleaned_count++;
1269
1270                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
1271                         rsc_count = ixgbe_get_rsc_count(rx_desc);
1272
1273                 if (rsc_count) {
1274                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1275                                      IXGBE_RXDADV_NEXTP_SHIFT;
1276                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1277                 } else {
1278                         next_buffer = &rx_ring->rx_buffer_info[i];
1279                 }
1280
1281                 if (staterr & IXGBE_RXD_STAT_EOP) {
1282                         if (skb->prev)
1283                                 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
1284                         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
1285                                 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1286                                         dma_unmap_single(&pdev->dev,
1287                                                          IXGBE_RSC_CB(skb)->dma,
1288                                                          rx_ring->rx_buf_len,
1289                                                          DMA_FROM_DEVICE);
1290                                         IXGBE_RSC_CB(skb)->dma = 0;
1291                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
1292                                 }
1293                                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
1294                                         rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
1295                                 else
1296                                         rx_ring->rsc_count++;
1297                                 rx_ring->rsc_flush++;
1298                         }
1299                         rx_ring->stats.packets++;
1300                         rx_ring->stats.bytes += skb->len;
1301                 } else {
1302                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1303                                 rx_buffer_info->skb = next_buffer->skb;
1304                                 rx_buffer_info->dma = next_buffer->dma;
1305                                 next_buffer->skb = skb;
1306                                 next_buffer->dma = 0;
1307                         } else {
1308                                 skb->next = next_buffer->skb;
1309                                 skb->next->prev = skb;
1310                         }
1311                         rx_ring->non_eop_descs++;
1312                         goto next_desc;
1313                 }
1314
1315                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1316                         dev_kfree_skb_irq(skb);
1317                         goto next_desc;
1318                 }
1319
1320                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1321
1322                 /* probably a little skewed due to removing CRC */
1323                 total_rx_bytes += skb->len;
1324                 total_rx_packets++;
1325
1326                 skb->protocol = eth_type_trans(skb, adapter->netdev);
1327 #ifdef IXGBE_FCOE
1328                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1329                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1330                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1331                         if (!ddp_bytes)
1332                                 goto next_desc;
1333                 }
1334 #endif /* IXGBE_FCOE */
1335                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1336
1337 next_desc:
1338                 rx_desc->wb.upper.status_error = 0;
1339
1340                 /* return some buffers to hardware, one at a time is too slow */
1341                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1342                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1343                         cleaned_count = 0;
1344                 }
1345
1346                 /* use prefetched values */
1347                 rx_desc = next_rxd;
1348                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1349
1350                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1351         }
1352
1353         rx_ring->next_to_clean = i;
1354         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1355
1356         if (cleaned_count)
1357                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1358
1359 #ifdef IXGBE_FCOE
1360         /* include DDPed FCoE data */
1361         if (ddp_bytes > 0) {
1362                 unsigned int mss;
1363
1364                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1365                         sizeof(struct fc_frame_header) -
1366                         sizeof(struct fcoe_crc_eof);
1367                 if (mss > 512)
1368                         mss &= ~511;
1369                 total_rx_bytes += ddp_bytes;
1370                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1371         }
1372 #endif /* IXGBE_FCOE */
1373
1374         rx_ring->total_packets += total_rx_packets;
1375         rx_ring->total_bytes += total_rx_bytes;
1376         netdev->stats.rx_bytes += total_rx_bytes;
1377         netdev->stats.rx_packets += total_rx_packets;
1378
1379         return cleaned;
1380 }
1381
1382 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1383 /**
1384  * ixgbe_configure_msix - Configure MSI-X hardware
1385  * @adapter: board private structure
1386  *
1387  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1388  * interrupts.
1389  **/
1390 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1391 {
1392         struct ixgbe_q_vector *q_vector;
1393         int i, j, q_vectors, v_idx, r_idx;
1394         u32 mask;
1395
1396         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1397
1398         /*
1399          * Populate the IVAR table and set the ITR values to the
1400          * corresponding register.
1401          */
1402         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1403                 q_vector = adapter->q_vector[v_idx];
1404                 /* XXX for_each_set_bit(...) */
1405                 r_idx = find_first_bit(q_vector->rxr_idx,
1406                                        adapter->num_rx_queues);
1407
1408                 for (i = 0; i < q_vector->rxr_count; i++) {
1409                         j = adapter->rx_ring[r_idx]->reg_idx;
1410                         ixgbe_set_ivar(adapter, 0, j, v_idx);
1411                         r_idx = find_next_bit(q_vector->rxr_idx,
1412                                               adapter->num_rx_queues,
1413                                               r_idx + 1);
1414                 }
1415                 r_idx = find_first_bit(q_vector->txr_idx,
1416                                        adapter->num_tx_queues);
1417
1418                 for (i = 0; i < q_vector->txr_count; i++) {
1419                         j = adapter->tx_ring[r_idx]->reg_idx;
1420                         ixgbe_set_ivar(adapter, 1, j, v_idx);
1421                         r_idx = find_next_bit(q_vector->txr_idx,
1422                                               adapter->num_tx_queues,
1423                                               r_idx + 1);
1424                 }
1425
1426                 if (q_vector->txr_count && !q_vector->rxr_count)
1427                         /* tx only */
1428                         q_vector->eitr = adapter->tx_eitr_param;
1429                 else if (q_vector->rxr_count)
1430                         /* rx or mixed */
1431                         q_vector->eitr = adapter->rx_eitr_param;
1432
1433                 ixgbe_write_eitr(q_vector);
1434         }
1435
1436         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1437                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1438                                v_idx);
1439         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1440                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1441         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1442
1443         /* set up to autoclear timer, and the vectors */
1444         mask = IXGBE_EIMS_ENABLE_MASK;
1445         if (adapter->num_vfs)
1446                 mask &= ~(IXGBE_EIMS_OTHER |
1447                           IXGBE_EIMS_MAILBOX |
1448                           IXGBE_EIMS_LSC);
1449         else
1450                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1451         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1452 }
1453
1454 enum latency_range {
1455         lowest_latency = 0,
1456         low_latency = 1,
1457         bulk_latency = 2,
1458         latency_invalid = 255
1459 };
1460
1461 /**
1462  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1463  * @adapter: pointer to adapter
1464  * @eitr: eitr setting (ints per sec) to give last timeslice
1465  * @itr_setting: current throttle rate in ints/second
1466  * @packets: the number of packets during this measurement interval
1467  * @bytes: the number of bytes during this measurement interval
1468  *
1469  *      Stores a new ITR value based on packets and byte
1470  *      counts during the last interrupt.  The advantage of per interrupt
1471  *      computation is faster updates and more accurate ITR for the current
1472  *      traffic pattern.  Constants in this function were computed
1473  *      based on theoretical maximum wire speed and thresholds were set based
1474  *      on testing data as well as attempting to minimize response time
1475  *      while increasing bulk throughput.
1476  *      this functionality is controlled by the InterruptThrottleRate module
1477  *      parameter (see ixgbe_param.c)
1478  **/
1479 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1480                            u32 eitr, u8 itr_setting,
1481                            int packets, int bytes)
1482 {
1483         unsigned int retval = itr_setting;
1484         u32 timepassed_us;
1485         u64 bytes_perint;
1486
1487         if (packets == 0)
1488                 goto update_itr_done;
1489
1490
1491         /* simple throttlerate management
1492          *    0-20MB/s lowest (100000 ints/s)
1493          *   20-100MB/s low   (20000 ints/s)
1494          *  100-1249MB/s bulk (8000 ints/s)
1495          */
1496         /* what was last interrupt timeslice? */
1497         timepassed_us = 1000000/eitr;
1498         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1499
1500         switch (itr_setting) {
1501         case lowest_latency:
1502                 if (bytes_perint > adapter->eitr_low)
1503                         retval = low_latency;
1504                 break;
1505         case low_latency:
1506                 if (bytes_perint > adapter->eitr_high)
1507                         retval = bulk_latency;
1508                 else if (bytes_perint <= adapter->eitr_low)
1509                         retval = lowest_latency;
1510                 break;
1511         case bulk_latency:
1512                 if (bytes_perint <= adapter->eitr_high)
1513                         retval = low_latency;
1514                 break;
1515         }
1516
1517 update_itr_done:
1518         return retval;
1519 }
1520
1521 /**
1522  * ixgbe_write_eitr - write EITR register in hardware specific way
1523  * @q_vector: structure containing interrupt and ring information
1524  *
1525  * This function is made to be called by ethtool and by the driver
1526  * when it needs to update EITR registers at runtime.  Hardware
1527  * specific quirks/differences are taken care of here.
1528  */
1529 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1530 {
1531         struct ixgbe_adapter *adapter = q_vector->adapter;
1532         struct ixgbe_hw *hw = &adapter->hw;
1533         int v_idx = q_vector->v_idx;
1534         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1535
1536         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1537                 /* must write high and low 16 bits to reset counter */
1538                 itr_reg |= (itr_reg << 16);
1539         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1540                 /*
1541                  * 82599 can support a value of zero, so allow it for
1542                  * max interrupt rate, but there is an errata where it can
1543                  * not be zero with RSC
1544                  */
1545                 if (itr_reg == 8 &&
1546                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1547                         itr_reg = 0;
1548
1549                 /*
1550                  * set the WDIS bit to not clear the timer bits and cause an
1551                  * immediate assertion of the interrupt
1552                  */
1553                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1554         }
1555         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1556 }
1557
1558 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1559 {
1560         struct ixgbe_adapter *adapter = q_vector->adapter;
1561         u32 new_itr;
1562         u8 current_itr, ret_itr;
1563         int i, r_idx;
1564         struct ixgbe_ring *rx_ring, *tx_ring;
1565
1566         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1567         for (i = 0; i < q_vector->txr_count; i++) {
1568                 tx_ring = adapter->tx_ring[r_idx];
1569                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1570                                            q_vector->tx_itr,
1571                                            tx_ring->total_packets,
1572                                            tx_ring->total_bytes);
1573                 /* if the result for this queue would decrease interrupt
1574                  * rate for this vector then use that result */
1575                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1576                                     q_vector->tx_itr - 1 : ret_itr);
1577                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1578                                       r_idx + 1);
1579         }
1580
1581         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1582         for (i = 0; i < q_vector->rxr_count; i++) {
1583                 rx_ring = adapter->rx_ring[r_idx];
1584                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1585                                            q_vector->rx_itr,
1586                                            rx_ring->total_packets,
1587                                            rx_ring->total_bytes);
1588                 /* if the result for this queue would decrease interrupt
1589                  * rate for this vector then use that result */
1590                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1591                                     q_vector->rx_itr - 1 : ret_itr);
1592                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1593                                       r_idx + 1);
1594         }
1595
1596         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1597
1598         switch (current_itr) {
1599         /* counts and packets in update_itr are dependent on these numbers */
1600         case lowest_latency:
1601                 new_itr = 100000;
1602                 break;
1603         case low_latency:
1604                 new_itr = 20000; /* aka hwitr = ~200 */
1605                 break;
1606         case bulk_latency:
1607         default:
1608                 new_itr = 8000;
1609                 break;
1610         }
1611
1612         if (new_itr != q_vector->eitr) {
1613                 /* do an exponential smoothing */
1614                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1615
1616                 /* save the algorithm value here, not the smoothed one */
1617                 q_vector->eitr = new_itr;
1618
1619                 ixgbe_write_eitr(q_vector);
1620         }
1621 }
1622
1623 /**
1624  * ixgbe_check_overtemp_task - worker thread to check over tempurature
1625  * @work: pointer to work_struct containing our data
1626  **/
1627 static void ixgbe_check_overtemp_task(struct work_struct *work)
1628 {
1629         struct ixgbe_adapter *adapter = container_of(work,
1630                                                      struct ixgbe_adapter,
1631                                                      check_overtemp_task);
1632         struct ixgbe_hw *hw = &adapter->hw;
1633         u32 eicr = adapter->interrupt_event;
1634
1635         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
1636                 switch (hw->device_id) {
1637                 case IXGBE_DEV_ID_82599_T3_LOM: {
1638                         u32 autoneg;
1639                         bool link_up = false;
1640
1641                         if (hw->mac.ops.check_link)
1642                                 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1643
1644                         if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1645                             (eicr & IXGBE_EICR_LSC))
1646                                 /* Check if this is due to overtemp */
1647                                 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1648                                         break;
1649                         }
1650                         return;
1651                 default:
1652                         if (!(eicr & IXGBE_EICR_GPI_SDP0))
1653                                 return;
1654                         break;
1655                 }
1656                 e_crit(drv, "Network adapter has been stopped because it has "
1657                        "over heated. Restart the computer. If the problem "
1658                        "persists, power off the system and replace the "
1659                        "adapter\n");
1660                 /* write to clear the interrupt */
1661                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1662         }
1663 }
1664
1665 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1666 {
1667         struct ixgbe_hw *hw = &adapter->hw;
1668
1669         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1670             (eicr & IXGBE_EICR_GPI_SDP1)) {
1671                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1672                 /* write to clear the interrupt */
1673                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1674         }
1675 }
1676
1677 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1678 {
1679         struct ixgbe_hw *hw = &adapter->hw;
1680
1681         if (eicr & IXGBE_EICR_GPI_SDP1) {
1682                 /* Clear the interrupt */
1683                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1684                 schedule_work(&adapter->multispeed_fiber_task);
1685         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1686                 /* Clear the interrupt */
1687                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1688                 schedule_work(&adapter->sfp_config_module_task);
1689         } else {
1690                 /* Interrupt isn't for us... */
1691                 return;
1692         }
1693 }
1694
1695 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1696 {
1697         struct ixgbe_hw *hw = &adapter->hw;
1698
1699         adapter->lsc_int++;
1700         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1701         adapter->link_check_timeout = jiffies;
1702         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1703                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1704                 IXGBE_WRITE_FLUSH(hw);
1705                 schedule_work(&adapter->watchdog_task);
1706         }
1707 }
1708
1709 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1710 {
1711         struct net_device *netdev = data;
1712         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1713         struct ixgbe_hw *hw = &adapter->hw;
1714         u32 eicr;
1715
1716         /*
1717          * Workaround for Silicon errata.  Use clear-by-write instead
1718          * of clear-by-read.  Reading with EICS will return the
1719          * interrupt causes without clearing, which later be done
1720          * with the write to EICR.
1721          */
1722         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1723         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1724
1725         if (eicr & IXGBE_EICR_LSC)
1726                 ixgbe_check_lsc(adapter);
1727
1728         if (eicr & IXGBE_EICR_MAILBOX)
1729                 ixgbe_msg_task(adapter);
1730
1731         if (hw->mac.type == ixgbe_mac_82598EB)
1732                 ixgbe_check_fan_failure(adapter, eicr);
1733
1734         if (hw->mac.type == ixgbe_mac_82599EB) {
1735                 ixgbe_check_sfp_event(adapter, eicr);
1736                 adapter->interrupt_event = eicr;
1737                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1738                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1739                         schedule_work(&adapter->check_overtemp_task);
1740
1741                 /* Handle Flow Director Full threshold interrupt */
1742                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1743                         int i;
1744                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1745                         /* Disable transmits before FDIR Re-initialization */
1746                         netif_tx_stop_all_queues(netdev);
1747                         for (i = 0; i < adapter->num_tx_queues; i++) {
1748                                 struct ixgbe_ring *tx_ring =
1749                                                             adapter->tx_ring[i];
1750                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1751                                                        &tx_ring->reinit_state))
1752                                         schedule_work(&adapter->fdir_reinit_task);
1753                         }
1754                 }
1755         }
1756         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1757                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1758
1759         return IRQ_HANDLED;
1760 }
1761
1762 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1763                                            u64 qmask)
1764 {
1765         u32 mask;
1766
1767         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1768                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1769                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1770         } else {
1771                 mask = (qmask & 0xFFFFFFFF);
1772                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1773                 mask = (qmask >> 32);
1774                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1775         }
1776         /* skip the flush */
1777 }
1778
1779 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1780                                             u64 qmask)
1781 {
1782         u32 mask;
1783
1784         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1785                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1786                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1787         } else {
1788                 mask = (qmask & 0xFFFFFFFF);
1789                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1790                 mask = (qmask >> 32);
1791                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1792         }
1793         /* skip the flush */
1794 }
1795
1796 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1797 {
1798         struct ixgbe_q_vector *q_vector = data;
1799         struct ixgbe_adapter  *adapter = q_vector->adapter;
1800         struct ixgbe_ring     *tx_ring;
1801         int i, r_idx;
1802
1803         if (!q_vector->txr_count)
1804                 return IRQ_HANDLED;
1805
1806         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1807         for (i = 0; i < q_vector->txr_count; i++) {
1808                 tx_ring = adapter->tx_ring[r_idx];
1809                 tx_ring->total_bytes = 0;
1810                 tx_ring->total_packets = 0;
1811                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1812                                       r_idx + 1);
1813         }
1814
1815         /* EIAM disabled interrupts (on this vector) for us */
1816         napi_schedule(&q_vector->napi);
1817
1818         return IRQ_HANDLED;
1819 }
1820
1821 /**
1822  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1823  * @irq: unused
1824  * @data: pointer to our q_vector struct for this interrupt vector
1825  **/
1826 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1827 {
1828         struct ixgbe_q_vector *q_vector = data;
1829         struct ixgbe_adapter  *adapter = q_vector->adapter;
1830         struct ixgbe_ring  *rx_ring;
1831         int r_idx;
1832         int i;
1833
1834         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1835         for (i = 0;  i < q_vector->rxr_count; i++) {
1836                 rx_ring = adapter->rx_ring[r_idx];
1837                 rx_ring->total_bytes = 0;
1838                 rx_ring->total_packets = 0;
1839                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1840                                       r_idx + 1);
1841         }
1842
1843         if (!q_vector->rxr_count)
1844                 return IRQ_HANDLED;
1845
1846         /* disable interrupts on this vector only */
1847         /* EIAM disabled interrupts (on this vector) for us */
1848         napi_schedule(&q_vector->napi);
1849
1850         return IRQ_HANDLED;
1851 }
1852
1853 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1854 {
1855         struct ixgbe_q_vector *q_vector = data;
1856         struct ixgbe_adapter  *adapter = q_vector->adapter;
1857         struct ixgbe_ring  *ring;
1858         int r_idx;
1859         int i;
1860
1861         if (!q_vector->txr_count && !q_vector->rxr_count)
1862                 return IRQ_HANDLED;
1863
1864         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1865         for (i = 0; i < q_vector->txr_count; i++) {
1866                 ring = adapter->tx_ring[r_idx];
1867                 ring->total_bytes = 0;
1868                 ring->total_packets = 0;
1869                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1870                                       r_idx + 1);
1871         }
1872
1873         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1874         for (i = 0; i < q_vector->rxr_count; i++) {
1875                 ring = adapter->rx_ring[r_idx];
1876                 ring->total_bytes = 0;
1877                 ring->total_packets = 0;
1878                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1879                                       r_idx + 1);
1880         }
1881
1882         /* EIAM disabled interrupts (on this vector) for us */
1883         napi_schedule(&q_vector->napi);
1884
1885         return IRQ_HANDLED;
1886 }
1887
1888 /**
1889  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1890  * @napi: napi struct with our devices info in it
1891  * @budget: amount of work driver is allowed to do this pass, in packets
1892  *
1893  * This function is optimized for cleaning one queue only on a single
1894  * q_vector!!!
1895  **/
1896 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1897 {
1898         struct ixgbe_q_vector *q_vector =
1899                                container_of(napi, struct ixgbe_q_vector, napi);
1900         struct ixgbe_adapter *adapter = q_vector->adapter;
1901         struct ixgbe_ring *rx_ring = NULL;
1902         int work_done = 0;
1903         long r_idx;
1904
1905         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1906         rx_ring = adapter->rx_ring[r_idx];
1907 #ifdef CONFIG_IXGBE_DCA
1908         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1909                 ixgbe_update_rx_dca(adapter, rx_ring);
1910 #endif
1911
1912         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1913
1914         /* If all Rx work done, exit the polling mode */
1915         if (work_done < budget) {
1916                 napi_complete(napi);
1917                 if (adapter->rx_itr_setting & 1)
1918                         ixgbe_set_itr_msix(q_vector);
1919                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1920                         ixgbe_irq_enable_queues(adapter,
1921                                                 ((u64)1 << q_vector->v_idx));
1922         }
1923
1924         return work_done;
1925 }
1926
1927 /**
1928  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1929  * @napi: napi struct with our devices info in it
1930  * @budget: amount of work driver is allowed to do this pass, in packets
1931  *
1932  * This function will clean more than one rx queue associated with a
1933  * q_vector.
1934  **/
1935 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1936 {
1937         struct ixgbe_q_vector *q_vector =
1938                                container_of(napi, struct ixgbe_q_vector, napi);
1939         struct ixgbe_adapter *adapter = q_vector->adapter;
1940         struct ixgbe_ring *ring = NULL;
1941         int work_done = 0, i;
1942         long r_idx;
1943         bool tx_clean_complete = true;
1944
1945         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1946         for (i = 0; i < q_vector->txr_count; i++) {
1947                 ring = adapter->tx_ring[r_idx];
1948 #ifdef CONFIG_IXGBE_DCA
1949                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1950                         ixgbe_update_tx_dca(adapter, ring);
1951 #endif
1952                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1953                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1954                                       r_idx + 1);
1955         }
1956
1957         /* attempt to distribute budget to each queue fairly, but don't allow
1958          * the budget to go below 1 because we'll exit polling */
1959         budget /= (q_vector->rxr_count ?: 1);
1960         budget = max(budget, 1);
1961         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1962         for (i = 0; i < q_vector->rxr_count; i++) {
1963                 ring = adapter->rx_ring[r_idx];
1964 #ifdef CONFIG_IXGBE_DCA
1965                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1966                         ixgbe_update_rx_dca(adapter, ring);
1967 #endif
1968                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1969                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1970                                       r_idx + 1);
1971         }
1972
1973         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1974         ring = adapter->rx_ring[r_idx];
1975         /* If all Rx work done, exit the polling mode */
1976         if (work_done < budget) {
1977                 napi_complete(napi);
1978                 if (adapter->rx_itr_setting & 1)
1979                         ixgbe_set_itr_msix(q_vector);
1980                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1981                         ixgbe_irq_enable_queues(adapter,
1982                                                 ((u64)1 << q_vector->v_idx));
1983                 return 0;
1984         }
1985
1986         return work_done;
1987 }
1988
1989 /**
1990  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1991  * @napi: napi struct with our devices info in it
1992  * @budget: amount of work driver is allowed to do this pass, in packets
1993  *
1994  * This function is optimized for cleaning one queue only on a single
1995  * q_vector!!!
1996  **/
1997 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1998 {
1999         struct ixgbe_q_vector *q_vector =
2000                                container_of(napi, struct ixgbe_q_vector, napi);
2001         struct ixgbe_adapter *adapter = q_vector->adapter;
2002         struct ixgbe_ring *tx_ring = NULL;
2003         int work_done = 0;
2004         long r_idx;
2005
2006         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2007         tx_ring = adapter->tx_ring[r_idx];
2008 #ifdef CONFIG_IXGBE_DCA
2009         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2010                 ixgbe_update_tx_dca(adapter, tx_ring);
2011 #endif
2012
2013         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2014                 work_done = budget;
2015
2016         /* If all Tx work done, exit the polling mode */
2017         if (work_done < budget) {
2018                 napi_complete(napi);
2019                 if (adapter->tx_itr_setting & 1)
2020                         ixgbe_set_itr_msix(q_vector);
2021                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2022                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2023         }
2024
2025         return work_done;
2026 }
2027
2028 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2029                                      int r_idx)
2030 {
2031         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2032
2033         set_bit(r_idx, q_vector->rxr_idx);
2034         q_vector->rxr_count++;
2035 }
2036
2037 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2038                                      int t_idx)
2039 {
2040         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2041
2042         set_bit(t_idx, q_vector->txr_idx);
2043         q_vector->txr_count++;
2044 }
2045
2046 /**
2047  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2048  * @adapter: board private structure to initialize
2049  * @vectors: allotted vector count for descriptor rings
2050  *
2051  * This function maps descriptor rings to the queue-specific vectors
2052  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2053  * one vector per ring/queue, but on a constrained vector budget, we
2054  * group the rings as "efficiently" as possible.  You would add new
2055  * mapping configurations in here.
2056  **/
2057 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
2058                                       int vectors)
2059 {
2060         int v_start = 0;
2061         int rxr_idx = 0, txr_idx = 0;
2062         int rxr_remaining = adapter->num_rx_queues;
2063         int txr_remaining = adapter->num_tx_queues;
2064         int i, j;
2065         int rqpv, tqpv;
2066         int err = 0;
2067
2068         /* No mapping required if MSI-X is disabled. */
2069         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2070                 goto out;
2071
2072         /*
2073          * The ideal configuration...
2074          * We have enough vectors to map one per queue.
2075          */
2076         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2077                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2078                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2079
2080                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2081                         map_vector_to_txq(adapter, v_start, txr_idx);
2082
2083                 goto out;
2084         }
2085
2086         /*
2087          * If we don't have enough vectors for a 1-to-1
2088          * mapping, we'll have to group them so there are
2089          * multiple queues per vector.
2090          */
2091         /* Re-adjusting *qpv takes care of the remainder. */
2092         for (i = v_start; i < vectors; i++) {
2093                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2094                 for (j = 0; j < rqpv; j++) {
2095                         map_vector_to_rxq(adapter, i, rxr_idx);
2096                         rxr_idx++;
2097                         rxr_remaining--;
2098                 }
2099         }
2100         for (i = v_start; i < vectors; i++) {
2101                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2102                 for (j = 0; j < tqpv; j++) {
2103                         map_vector_to_txq(adapter, i, txr_idx);
2104                         txr_idx++;
2105                         txr_remaining--;
2106                 }
2107         }
2108
2109 out:
2110         return err;
2111 }
2112
2113 /**
2114  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2115  * @adapter: board private structure
2116  *
2117  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2118  * interrupts from the kernel.
2119  **/
2120 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2121 {
2122         struct net_device *netdev = adapter->netdev;
2123         irqreturn_t (*handler)(int, void *);
2124         int i, vector, q_vectors, err;
2125         int ri=0, ti=0;
2126
2127         /* Decrement for Other and TCP Timer vectors */
2128         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2129
2130         /* Map the Tx/Rx rings to the vectors we were allotted. */
2131         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2132         if (err)
2133                 goto out;
2134
2135 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2136                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2137                          &ixgbe_msix_clean_many)
2138         for (vector = 0; vector < q_vectors; vector++) {
2139                 handler = SET_HANDLER(adapter->q_vector[vector]);
2140
2141                 if(handler == &ixgbe_msix_clean_rx) {
2142                         sprintf(adapter->name[vector], "%s-%s-%d",
2143                                 netdev->name, "rx", ri++);
2144                 }
2145                 else if(handler == &ixgbe_msix_clean_tx) {
2146                         sprintf(adapter->name[vector], "%s-%s-%d",
2147                                 netdev->name, "tx", ti++);
2148                 }
2149                 else
2150                         sprintf(adapter->name[vector], "%s-%s-%d",
2151                                 netdev->name, "TxRx", vector);
2152
2153                 err = request_irq(adapter->msix_entries[vector].vector,
2154                                   handler, 0, adapter->name[vector],
2155                                   adapter->q_vector[vector]);
2156                 if (err) {
2157                         e_err(probe, "request_irq failed for MSIX interrupt "
2158                               "Error: %d\n", err);
2159                         goto free_queue_irqs;
2160                 }
2161         }
2162
2163         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2164         err = request_irq(adapter->msix_entries[vector].vector,
2165                           ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
2166         if (err) {
2167                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2168                 goto free_queue_irqs;
2169         }
2170
2171         return 0;
2172
2173 free_queue_irqs:
2174         for (i = vector - 1; i >= 0; i--)
2175                 free_irq(adapter->msix_entries[--vector].vector,
2176                          adapter->q_vector[i]);
2177         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2178         pci_disable_msix(adapter->pdev);
2179         kfree(adapter->msix_entries);
2180         adapter->msix_entries = NULL;
2181 out:
2182         return err;
2183 }
2184
2185 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2186 {
2187         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2188         u8 current_itr;
2189         u32 new_itr = q_vector->eitr;
2190         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2191         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2192
2193         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2194                                             q_vector->tx_itr,
2195                                             tx_ring->total_packets,
2196                                             tx_ring->total_bytes);
2197         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2198                                             q_vector->rx_itr,
2199                                             rx_ring->total_packets,
2200                                             rx_ring->total_bytes);
2201
2202         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2203
2204         switch (current_itr) {
2205         /* counts and packets in update_itr are dependent on these numbers */
2206         case lowest_latency:
2207                 new_itr = 100000;
2208                 break;
2209         case low_latency:
2210                 new_itr = 20000; /* aka hwitr = ~200 */
2211                 break;
2212         case bulk_latency:
2213                 new_itr = 8000;
2214                 break;
2215         default:
2216                 break;
2217         }
2218
2219         if (new_itr != q_vector->eitr) {
2220                 /* do an exponential smoothing */
2221                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
2222
2223                 /* save the algorithm value here, not the smoothed one */
2224                 q_vector->eitr = new_itr;
2225
2226                 ixgbe_write_eitr(q_vector);
2227         }
2228 }
2229
2230 /**
2231  * ixgbe_irq_enable - Enable default interrupt generation settings
2232  * @adapter: board private structure
2233  **/
2234 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
2235 {
2236         u32 mask;
2237
2238         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2239         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2240                 mask |= IXGBE_EIMS_GPI_SDP0;
2241         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2242                 mask |= IXGBE_EIMS_GPI_SDP1;
2243         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2244                 mask |= IXGBE_EIMS_ECC;
2245                 mask |= IXGBE_EIMS_GPI_SDP1;
2246                 mask |= IXGBE_EIMS_GPI_SDP2;
2247                 if (adapter->num_vfs)
2248                         mask |= IXGBE_EIMS_MAILBOX;
2249         }
2250         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2251             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2252                 mask |= IXGBE_EIMS_FLOW_DIR;
2253
2254         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2255         ixgbe_irq_enable_queues(adapter, ~0);
2256         IXGBE_WRITE_FLUSH(&adapter->hw);
2257
2258         if (adapter->num_vfs > 32) {
2259                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2260                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2261         }
2262 }
2263
2264 /**
2265  * ixgbe_intr - legacy mode Interrupt Handler
2266  * @irq: interrupt number
2267  * @data: pointer to a network interface device structure
2268  **/
2269 static irqreturn_t ixgbe_intr(int irq, void *data)
2270 {
2271         struct net_device *netdev = data;
2272         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2273         struct ixgbe_hw *hw = &adapter->hw;
2274         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2275         u32 eicr;
2276
2277         /*
2278          * Workaround for silicon errata.  Mask the interrupts
2279          * before the read of EICR.
2280          */
2281         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2282
2283         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2284          * therefore no explict interrupt disable is necessary */
2285         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2286         if (!eicr) {
2287                 /* shared interrupt alert!
2288                  * make sure interrupts are enabled because the read will
2289                  * have disabled interrupts due to EIAM */
2290                 ixgbe_irq_enable(adapter);
2291                 return IRQ_NONE;        /* Not our interrupt */
2292         }
2293
2294         if (eicr & IXGBE_EICR_LSC)
2295                 ixgbe_check_lsc(adapter);
2296
2297         if (hw->mac.type == ixgbe_mac_82599EB)
2298                 ixgbe_check_sfp_event(adapter, eicr);
2299
2300         ixgbe_check_fan_failure(adapter, eicr);
2301         if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2302             ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2303                 schedule_work(&adapter->check_overtemp_task);
2304
2305         if (napi_schedule_prep(&(q_vector->napi))) {
2306                 adapter->tx_ring[0]->total_packets = 0;
2307                 adapter->tx_ring[0]->total_bytes = 0;
2308                 adapter->rx_ring[0]->total_packets = 0;
2309                 adapter->rx_ring[0]->total_bytes = 0;
2310                 /* would disable interrupts here but EIAM disabled it */
2311                 __napi_schedule(&(q_vector->napi));
2312         }
2313
2314         return IRQ_HANDLED;
2315 }
2316
2317 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2318 {
2319         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2320
2321         for (i = 0; i < q_vectors; i++) {
2322                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2323                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2324                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2325                 q_vector->rxr_count = 0;
2326                 q_vector->txr_count = 0;
2327         }
2328 }
2329
2330 /**
2331  * ixgbe_request_irq - initialize interrupts
2332  * @adapter: board private structure
2333  *
2334  * Attempts to configure interrupts using the best available
2335  * capabilities of the hardware and kernel.
2336  **/
2337 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2338 {
2339         struct net_device *netdev = adapter->netdev;
2340         int err;
2341
2342         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2343                 err = ixgbe_request_msix_irqs(adapter);
2344         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2345                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2346                                   netdev->name, netdev);
2347         } else {
2348                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2349                                   netdev->name, netdev);
2350         }
2351
2352         if (err)
2353                 e_err(probe, "request_irq failed, Error %d\n", err);
2354
2355         return err;
2356 }
2357
2358 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2359 {
2360         struct net_device *netdev = adapter->netdev;
2361
2362         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2363                 int i, q_vectors;
2364
2365                 q_vectors = adapter->num_msix_vectors;
2366
2367                 i = q_vectors - 1;
2368                 free_irq(adapter->msix_entries[i].vector, netdev);
2369
2370                 i--;
2371                 for (; i >= 0; i--) {
2372                         free_irq(adapter->msix_entries[i].vector,
2373                                  adapter->q_vector[i]);
2374                 }
2375
2376                 ixgbe_reset_q_vectors(adapter);
2377         } else {
2378                 free_irq(adapter->pdev->irq, netdev);
2379         }
2380 }
2381
2382 /**
2383  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2384  * @adapter: board private structure
2385  **/
2386 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2387 {
2388         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2389                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2390         } else {
2391                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2392                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2393                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2394                 if (adapter->num_vfs > 32)
2395                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2396         }
2397         IXGBE_WRITE_FLUSH(&adapter->hw);
2398         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2399                 int i;
2400                 for (i = 0; i < adapter->num_msix_vectors; i++)
2401                         synchronize_irq(adapter->msix_entries[i].vector);
2402         } else {
2403                 synchronize_irq(adapter->pdev->irq);
2404         }
2405 }
2406
2407 /**
2408  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2409  *
2410  **/
2411 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2412 {
2413         struct ixgbe_hw *hw = &adapter->hw;
2414
2415         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2416                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2417
2418         ixgbe_set_ivar(adapter, 0, 0, 0);
2419         ixgbe_set_ivar(adapter, 1, 0, 0);
2420
2421         map_vector_to_rxq(adapter, 0, 0);
2422         map_vector_to_txq(adapter, 0, 0);
2423
2424         e_info(hw, "Legacy interrupt IVAR setup done\n");
2425 }
2426
2427 /**
2428  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2429  * @adapter: board private structure
2430  * @ring: structure containing ring specific data
2431  *
2432  * Configure the Tx descriptor ring after a reset.
2433  **/
2434  static void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2435                                      struct ixgbe_ring *ring)
2436 {
2437         struct ixgbe_hw *hw = &adapter->hw;
2438         u64 tdba = ring->dma;
2439         int wait_loop = 10;
2440         u32 txdctl;
2441         u16 reg_idx = ring->reg_idx;
2442
2443         /* disable queue to avoid issues while updating state */
2444         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2445         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2446                         txdctl & ~IXGBE_TXDCTL_ENABLE);
2447         IXGBE_WRITE_FLUSH(hw);
2448
2449         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2450                         (tdba & DMA_BIT_MASK(32)));
2451         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2452         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2453                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2454         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2455         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2456         ring->head = IXGBE_TDH(reg_idx);
2457         ring->tail = IXGBE_TDT(reg_idx);
2458
2459         /* configure fetching thresholds */
2460         if (adapter->rx_itr_setting == 0) {
2461                 /* cannot set wthresh when itr==0 */
2462                 txdctl &= ~0x007F0000;
2463         } else {
2464                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2465                 txdctl |= (8 << 16);
2466         }
2467         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2468                 /* PThresh workaround for Tx hang with DFP enabled. */
2469                 txdctl |= 32;
2470         }
2471
2472         /* reinitialize flowdirector state */
2473         set_bit(__IXGBE_FDIR_INIT_DONE, &ring->reinit_state);
2474
2475         /* enable queue */
2476         txdctl |= IXGBE_TXDCTL_ENABLE;
2477         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2478
2479         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2480         if (hw->mac.type == ixgbe_mac_82598EB &&
2481             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2482                 return;
2483
2484         /* poll to verify queue is enabled */
2485         do {
2486                 msleep(1);
2487                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2488         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2489         if (!wait_loop)
2490                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2491 }
2492
2493 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2494 {
2495         struct ixgbe_hw *hw = &adapter->hw;
2496         u32 rttdcs;
2497         u32 mask;
2498
2499         if (hw->mac.type == ixgbe_mac_82598EB)
2500                 return;
2501
2502         /* disable the arbiter while setting MTQC */
2503         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2504         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2505         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2506
2507         /* set transmit pool layout */
2508         mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2509         switch (adapter->flags & mask) {
2510
2511         case (IXGBE_FLAG_SRIOV_ENABLED):
2512                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2513                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2514                 break;
2515
2516         case (IXGBE_FLAG_DCB_ENABLED):
2517                 /* We enable 8 traffic classes, DCB only */
2518                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2519                               (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2520                 break;
2521
2522         default:
2523                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2524                 break;
2525         }
2526
2527         /* re-enable the arbiter */
2528         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2529         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2530 }
2531
2532 /**
2533  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2534  * @adapter: board private structure
2535  *
2536  * Configure the Tx unit of the MAC after a reset.
2537  **/
2538 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2539 {
2540         struct ixgbe_hw *hw = &adapter->hw;
2541         u32 dmatxctl;
2542         u32 i;
2543
2544         ixgbe_setup_mtqc(adapter);
2545
2546         if (hw->mac.type != ixgbe_mac_82598EB) {
2547                 /* DMATXCTL.EN must be before Tx queues are enabled */
2548                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2549                 dmatxctl |= IXGBE_DMATXCTL_TE;
2550                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2551         }
2552
2553         /* Setup the HW Tx Head and Tail descriptor pointers */
2554         for (i = 0; i < adapter->num_tx_queues; i++)
2555                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2556 }
2557
2558 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2559
2560 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2561                                    struct ixgbe_ring *rx_ring)
2562 {
2563         u32 srrctl;
2564         int index;
2565         struct ixgbe_ring_feature *feature = adapter->ring_feature;
2566
2567         index = rx_ring->reg_idx;
2568         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2569                 unsigned long mask;
2570                 mask = (unsigned long) feature[RING_F_RSS].mask;
2571                 index = index & mask;
2572         }
2573         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2574
2575         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2576         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2577         if (adapter->num_vfs)
2578                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2579
2580         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2581                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2582
2583         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2584 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2585                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2586 #else
2587                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2588 #endif
2589                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2590         } else {
2591                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2592                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2593                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2594         }
2595
2596         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2597 }
2598
2599 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2600 {
2601         struct ixgbe_hw *hw = &adapter->hw;
2602         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2603                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2604                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2605         u32 mrqc = 0, reta = 0;
2606         u32 rxcsum;
2607         int i, j;
2608         int mask;
2609
2610         /* Fill out hash function seeds */
2611         for (i = 0; i < 10; i++)
2612                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2613
2614         /* Fill out redirection table */
2615         for (i = 0, j = 0; i < 128; i++, j++) {
2616                 if (j == adapter->ring_feature[RING_F_RSS].indices)
2617                         j = 0;
2618                 /* reta = 4-byte sliding window of
2619                  * 0x00..(indices-1)(indices-1)00..etc. */
2620                 reta = (reta << 8) | (j * 0x11);
2621                 if ((i & 3) == 3)
2622                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2623         }
2624
2625         /* Disable indicating checksum in descriptor, enables RSS hash */
2626         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2627         rxcsum |= IXGBE_RXCSUM_PCSD;
2628         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2629
2630         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2631                 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2632         else
2633                 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2634 #ifdef CONFIG_IXGBE_DCB
2635                                          | IXGBE_FLAG_DCB_ENABLED
2636 #endif
2637                                          | IXGBE_FLAG_SRIOV_ENABLED
2638                                         );
2639
2640         switch (mask) {
2641         case (IXGBE_FLAG_RSS_ENABLED):
2642                 mrqc = IXGBE_MRQC_RSSEN;
2643                 break;
2644         case (IXGBE_FLAG_SRIOV_ENABLED):
2645                 mrqc = IXGBE_MRQC_VMDQEN;
2646                 break;
2647 #ifdef CONFIG_IXGBE_DCB
2648         case (IXGBE_FLAG_DCB_ENABLED):
2649                 mrqc = IXGBE_MRQC_RT8TCEN;
2650                 break;
2651 #endif /* CONFIG_IXGBE_DCB */
2652         default:
2653                 break;
2654         }
2655
2656         /* Perform hash on these packet types */
2657         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2658               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2659               | IXGBE_MRQC_RSS_FIELD_IPV6
2660               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2661
2662         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2663 }
2664
2665 /**
2666  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2667  * @adapter:    address of board private structure
2668  * @index:      index of ring to set
2669  **/
2670 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2671                                    struct ixgbe_ring *ring)
2672 {
2673         struct ixgbe_hw *hw = &adapter->hw;
2674         u32 rscctrl;
2675         int rx_buf_len;
2676         u16 reg_idx = ring->reg_idx;
2677
2678         if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
2679                 return;
2680
2681         rx_buf_len = ring->rx_buf_len;
2682         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2683         rscctrl |= IXGBE_RSCCTL_RSCEN;
2684         /*
2685          * we must limit the number of descriptors so that the
2686          * total size of max desc * buf_len is not greater
2687          * than 65535
2688          */
2689         if (ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2690 #if (MAX_SKB_FRAGS > 16)
2691                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2692 #elif (MAX_SKB_FRAGS > 8)
2693                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2694 #elif (MAX_SKB_FRAGS > 4)
2695                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2696 #else
2697                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2698 #endif
2699         } else {
2700                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2701                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2702                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2703                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2704                 else
2705                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2706         }
2707         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2708 }
2709
2710 /**
2711  *  ixgbe_set_uta - Set unicast filter table address
2712  *  @adapter: board private structure
2713  *
2714  *  The unicast table address is a register array of 32-bit registers.
2715  *  The table is meant to be used in a way similar to how the MTA is used
2716  *  however due to certain limitations in the hardware it is necessary to
2717  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2718  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
2719  **/
2720 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2721 {
2722         struct ixgbe_hw *hw = &adapter->hw;
2723         int i;
2724
2725         /* The UTA table only exists on 82599 hardware and newer */
2726         if (hw->mac.type < ixgbe_mac_82599EB)
2727                 return;
2728
2729         /* we only need to do this if VMDq is enabled */
2730         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2731                 return;
2732
2733         for (i = 0; i < 128; i++)
2734                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2735 }
2736
2737 #define IXGBE_MAX_RX_DESC_POLL 10
2738 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2739                                        struct ixgbe_ring *ring)
2740 {
2741         struct ixgbe_hw *hw = &adapter->hw;
2742         int reg_idx = ring->reg_idx;
2743         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2744         u32 rxdctl;
2745
2746         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2747         if (hw->mac.type == ixgbe_mac_82598EB &&
2748             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2749                 return;
2750
2751         do {
2752                 msleep(1);
2753                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2754         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2755
2756         if (!wait_loop) {
2757                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2758                       "the polling period\n", reg_idx);
2759         }
2760 }
2761
2762 static void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2763                                     struct ixgbe_ring *ring)
2764 {
2765         struct ixgbe_hw *hw = &adapter->hw;
2766         u64 rdba = ring->dma;
2767         u32 rxdctl;
2768         u16 reg_idx = ring->reg_idx;
2769
2770         /* disable queue to avoid issues while updating state */
2771         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2772         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
2773                         rxdctl & ~IXGBE_RXDCTL_ENABLE);
2774         IXGBE_WRITE_FLUSH(hw);
2775
2776         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2777         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2778         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2779                         ring->count * sizeof(union ixgbe_adv_rx_desc));
2780         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2781         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2782         ring->head = IXGBE_RDH(reg_idx);
2783         ring->tail = IXGBE_RDT(reg_idx);
2784
2785         ixgbe_configure_srrctl(adapter, ring);
2786         ixgbe_configure_rscctl(adapter, ring);
2787
2788         if (hw->mac.type == ixgbe_mac_82598EB) {
2789                 /*
2790                  * enable cache line friendly hardware writes:
2791                  * PTHRESH=32 descriptors (half the internal cache),
2792                  * this also removes ugly rx_no_buffer_count increment
2793                  * HTHRESH=4 descriptors (to minimize latency on fetch)
2794                  * WTHRESH=8 burst writeback up to two cache lines
2795                  */
2796                 rxdctl &= ~0x3FFFFF;
2797                 rxdctl |=  0x080420;
2798         }
2799
2800         /* enable receive descriptor ring */
2801         rxdctl |= IXGBE_RXDCTL_ENABLE;
2802         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2803
2804         ixgbe_rx_desc_queue_enable(adapter, ring);
2805         ixgbe_alloc_rx_buffers(adapter, ring, IXGBE_DESC_UNUSED(ring));
2806 }
2807
2808 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2809 {
2810         struct ixgbe_hw *hw = &adapter->hw;
2811         int p;
2812
2813         /* PSRTYPE must be initialized in non 82598 adapters */
2814         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2815                       IXGBE_PSRTYPE_UDPHDR |
2816                       IXGBE_PSRTYPE_IPV4HDR |
2817                       IXGBE_PSRTYPE_L2HDR |
2818                       IXGBE_PSRTYPE_IPV6HDR;
2819
2820         if (hw->mac.type == ixgbe_mac_82598EB)
2821                 return;
2822
2823         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2824                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2825
2826         for (p = 0; p < adapter->num_rx_pools; p++)
2827                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2828                                 psrtype);
2829 }
2830
2831 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2832 {
2833         struct ixgbe_hw *hw = &adapter->hw;
2834         u32 gcr_ext;
2835         u32 vt_reg_bits;
2836         u32 reg_offset, vf_shift;
2837         u32 vmdctl;
2838
2839         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2840                 return;
2841
2842         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2843         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2844         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2845         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2846
2847         vf_shift = adapter->num_vfs % 32;
2848         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2849
2850         /* Enable only the PF's pool for Tx/Rx */
2851         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2852         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2853         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2854         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2855         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2856
2857         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2858         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2859
2860         /*
2861          * Set up VF register offsets for selected VT Mode,
2862          * i.e. 32 or 64 VFs for SR-IOV
2863          */
2864         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2865         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2866         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2867         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2868
2869         /* enable Tx loopback for VF/PF communication */
2870         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2871 }
2872
2873 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
2874 {
2875         struct ixgbe_hw *hw = &adapter->hw;
2876         struct net_device *netdev = adapter->netdev;
2877         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2878         int rx_buf_len;
2879         struct ixgbe_ring *rx_ring;
2880         int i;
2881         u32 mhadd, hlreg0;
2882
2883         /* Decide whether to use packet split mode or not */
2884         /* Do not use packet split if we're in SR-IOV Mode */
2885         if (!adapter->num_vfs)
2886                 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2887
2888         /* Set the RX buffer length according to the mode */
2889         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2890                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2891         } else {
2892                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2893                     (netdev->mtu <= ETH_DATA_LEN))
2894                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2895                 else
2896                         rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
2897         }
2898
2899 #ifdef IXGBE_FCOE
2900         /* adjust max frame to be able to do baby jumbo for FCoE */
2901         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2902             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2903                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2904
2905 #endif /* IXGBE_FCOE */
2906         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2907         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2908                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2909                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2910
2911                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2912         }
2913
2914         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2915         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2916         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2917         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2918
2919         /*
2920          * Setup the HW Rx Head and Tail Descriptor Pointers and
2921          * the Base and Length of the Rx Descriptor Ring
2922          */
2923         for (i = 0; i < adapter->num_rx_queues; i++) {
2924                 rx_ring = adapter->rx_ring[i];
2925                 rx_ring->rx_buf_len = rx_buf_len;
2926
2927                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2928                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2929                 else
2930                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2931
2932 #ifdef IXGBE_FCOE
2933                 if (netdev->features & NETIF_F_FCOE_MTU)
2934                 {
2935                         struct ixgbe_ring_feature *f;
2936                         f = &adapter->ring_feature[RING_F_FCOE];
2937                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2938                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2939                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2940                                         rx_ring->rx_buf_len =
2941                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2942                         }
2943                 }
2944 #endif /* IXGBE_FCOE */
2945         }
2946
2947 }
2948
2949 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2950 {
2951         struct ixgbe_hw *hw = &adapter->hw;
2952         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2953
2954         switch (hw->mac.type) {
2955         case ixgbe_mac_82598EB:
2956                 /*
2957                  * For VMDq support of different descriptor types or
2958                  * buffer sizes through the use of multiple SRRCTL
2959                  * registers, RDRXCTL.MVMEN must be set to 1
2960                  *
2961                  * also, the manual doesn't mention it clearly but DCA hints
2962                  * will only use queue 0's tags unless this bit is set.  Side
2963                  * effects of setting this bit are only that SRRCTL must be
2964                  * fully programmed [0..15]
2965                  */
2966                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2967                 break;
2968         case ixgbe_mac_82599EB:
2969                 /* Disable RSC for ACK packets */
2970                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2971                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2972                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2973                 /* hardware requires some bits to be set by default */
2974                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
2975                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2976                 break;
2977         default:
2978                 /* We should do nothing since we don't know this hardware */
2979                 return;
2980         }
2981
2982         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2983 }
2984
2985 /**
2986  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2987  * @adapter: board private structure
2988  *
2989  * Configure the Rx unit of the MAC after a reset.
2990  **/
2991 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2992 {
2993         struct ixgbe_hw *hw = &adapter->hw;
2994         int i;
2995         u32 rxctrl;
2996
2997         /* disable receives while setting up the descriptors */
2998         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2999         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3000
3001         ixgbe_setup_psrtype(adapter);
3002         ixgbe_setup_rdrxctl(adapter);
3003
3004         /* Program registers for the distribution of queues */
3005         ixgbe_setup_mrqc(adapter);
3006         ixgbe_configure_virtualization(adapter);
3007
3008         ixgbe_set_uta(adapter);
3009
3010         /* set_rx_buffer_len must be called before ring initialization */
3011         ixgbe_set_rx_buffer_len(adapter);
3012
3013         /*
3014          * Setup the HW Rx Head and Tail Descriptor Pointers and
3015          * the Base and Length of the Rx Descriptor Ring
3016          */
3017         for (i = 0; i < adapter->num_rx_queues; i++)
3018                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3019
3020         /* disable drop enable for 82598 parts */
3021         if (hw->mac.type == ixgbe_mac_82598EB)
3022                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3023
3024         /* enable all receives */
3025         rxctrl |= IXGBE_RXCTRL_RXEN;
3026         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3027 }
3028
3029 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3030 {
3031         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3032         struct ixgbe_hw *hw = &adapter->hw;
3033         int pool_ndx = adapter->num_vfs;
3034
3035         /* add VID to filter table */
3036         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3037 }
3038
3039 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3040 {
3041         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3042         struct ixgbe_hw *hw = &adapter->hw;
3043         int pool_ndx = adapter->num_vfs;
3044
3045         if (!test_bit(__IXGBE_DOWN, &adapter->state))
3046                 ixgbe_irq_disable(adapter);
3047
3048         vlan_group_set_device(adapter->vlgrp, vid, NULL);
3049
3050         if (!test_bit(__IXGBE_DOWN, &adapter->state))
3051                 ixgbe_irq_enable(adapter);
3052
3053         /* remove VID from filter table */
3054         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3055 }
3056
3057 /**
3058  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3059  * @adapter: driver data
3060  */
3061 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3062 {
3063         struct ixgbe_hw *hw = &adapter->hw;
3064         u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3065         int i, j;
3066
3067         switch (hw->mac.type) {
3068         case ixgbe_mac_82598EB:
3069                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
3070 #ifdef CONFIG_IXGBE_DCB
3071                 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3072                         vlnctrl &= ~IXGBE_VLNCTRL_VME;
3073 #endif
3074                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3075                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3076                 break;
3077         case ixgbe_mac_82599EB:
3078                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
3079                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3080                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3081 #ifdef CONFIG_IXGBE_DCB
3082                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
3083                         break;
3084 #endif
3085                 for (i = 0; i < adapter->num_rx_queues; i++) {
3086                         j = adapter->rx_ring[i]->reg_idx;
3087                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3088                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3089                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3090                 }
3091                 break;
3092         default:
3093                 break;
3094         }
3095 }
3096
3097 /**
3098  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3099  * @adapter: driver data
3100  */
3101 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3102 {
3103         struct ixgbe_hw *hw = &adapter->hw;
3104         u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3105         int i, j;
3106
3107         switch (hw->mac.type) {
3108         case ixgbe_mac_82598EB:
3109                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
3110                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3111                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3112                 break;
3113         case ixgbe_mac_82599EB:
3114                 vlnctrl |= IXGBE_VLNCTRL_VFE;
3115                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3116                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3117                 for (i = 0; i < adapter->num_rx_queues; i++) {
3118                         j = adapter->rx_ring[i]->reg_idx;
3119                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3120                         vlnctrl |= IXGBE_RXDCTL_VME;
3121                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3122                 }
3123                 break;
3124         default:
3125                 break;
3126         }
3127 }
3128
3129 static void ixgbe_vlan_rx_register(struct net_device *netdev,
3130                                    struct vlan_group *grp)
3131 {
3132         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3133
3134         if (!test_bit(__IXGBE_DOWN, &adapter->state))
3135                 ixgbe_irq_disable(adapter);
3136         adapter->vlgrp = grp;
3137
3138         /*
3139          * For a DCB driver, always enable VLAN tag stripping so we can
3140          * still receive traffic from a DCB-enabled host even if we're
3141          * not in DCB mode.
3142          */
3143         ixgbe_vlan_filter_enable(adapter);
3144
3145         ixgbe_vlan_rx_add_vid(netdev, 0);
3146
3147         if (!test_bit(__IXGBE_DOWN, &adapter->state))
3148                 ixgbe_irq_enable(adapter);
3149 }
3150
3151 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3152 {
3153         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
3154
3155         if (adapter->vlgrp) {
3156                 u16 vid;
3157                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
3158                         if (!vlan_group_get_device(adapter->vlgrp, vid))
3159                                 continue;
3160                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3161                 }
3162         }
3163 }
3164
3165 /**
3166  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3167  * @netdev: network interface device structure
3168  *
3169  * Writes unicast address list to the RAR table.
3170  * Returns: -ENOMEM on failure/insufficient address space
3171  *                0 on no addresses written
3172  *                X on writing X addresses to the RAR table
3173  **/
3174 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3175 {
3176         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3177         struct ixgbe_hw *hw = &adapter->hw;
3178         unsigned int vfn = adapter->num_vfs;
3179         unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3180         int count = 0;
3181
3182         /* return ENOMEM indicating insufficient memory for addresses */
3183         if (netdev_uc_count(netdev) > rar_entries)
3184                 return -ENOMEM;
3185
3186         if (!netdev_uc_empty(netdev) && rar_entries) {
3187                 struct netdev_hw_addr *ha;
3188                 /* return error if we do not support writing to RAR table */
3189                 if (!hw->mac.ops.set_rar)
3190                         return -ENOMEM;
3191
3192                 netdev_for_each_uc_addr(ha, netdev) {
3193                         if (!rar_entries)
3194                                 break;
3195                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3196                                             vfn, IXGBE_RAH_AV);
3197                         count++;
3198                 }
3199         }
3200         /* write the addresses in reverse order to avoid write combining */
3201         for (; rar_entries > 0 ; rar_entries--)
3202                 hw->mac.ops.clear_rar(hw, rar_entries);
3203
3204         return count;
3205 }
3206
3207 /**
3208  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3209  * @netdev: network interface device structure
3210  *
3211  * The set_rx_method entry point is called whenever the unicast/multicast
3212  * address list or the network interface flags are updated.  This routine is
3213  * responsible for configuring the hardware for proper unicast, multicast and
3214  * promiscuous mode.
3215  **/
3216 void ixgbe_set_rx_mode(struct net_device *netdev)
3217 {
3218         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3219         struct ixgbe_hw *hw = &adapter->hw;
3220         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3221         int count;
3222
3223         /* Check for Promiscuous and All Multicast modes */
3224
3225         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3226
3227         /* set all bits that we expect to always be set */
3228         fctrl |= IXGBE_FCTRL_BAM;
3229         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3230         fctrl |= IXGBE_FCTRL_PMCF;
3231
3232         /* clear the bits we are changing the status of */
3233         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3234
3235         if (netdev->flags & IFF_PROMISC) {
3236                 hw->addr_ctrl.user_set_promisc = true;
3237                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3238                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3239                 /* don't hardware filter vlans in promisc mode */
3240                 ixgbe_vlan_filter_disable(adapter);
3241         } else {
3242                 if (netdev->flags & IFF_ALLMULTI) {
3243                         fctrl |= IXGBE_FCTRL_MPE;
3244                         vmolr |= IXGBE_VMOLR_MPE;
3245                 } else {
3246                         /*
3247                          * Write addresses to the MTA, if the attempt fails
3248                          * then we should just turn on promiscous mode so
3249                          * that we can at least receive multicast traffic
3250                          */
3251                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3252                         vmolr |= IXGBE_VMOLR_ROMPE;
3253                 }
3254                 ixgbe_vlan_filter_enable(adapter);
3255                 hw->addr_ctrl.user_set_promisc = false;
3256                 /*
3257                  * Write addresses to available RAR registers, if there is not
3258                  * sufficient space to store all the addresses then enable
3259                  * unicast promiscous mode
3260                  */
3261                 count = ixgbe_write_uc_addr_list(netdev);
3262                 if (count < 0) {
3263                         fctrl |= IXGBE_FCTRL_UPE;
3264                         vmolr |= IXGBE_VMOLR_ROPE;
3265                 }
3266         }
3267
3268         if (adapter->num_vfs) {
3269                 ixgbe_restore_vf_multicasts(adapter);
3270                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3271                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3272                            IXGBE_VMOLR_ROPE);
3273                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3274         }
3275
3276         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3277 }
3278
3279 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3280 {
3281         int q_idx;
3282         struct ixgbe_q_vector *q_vector;
3283         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3284
3285         /* legacy and MSI only use one vector */
3286         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3287                 q_vectors = 1;
3288
3289         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3290                 struct napi_struct *napi;
3291                 q_vector = adapter->q_vector[q_idx];
3292                 napi = &q_vector->napi;
3293                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3294                         if (!q_vector->rxr_count || !q_vector->txr_count) {
3295                                 if (q_vector->txr_count == 1)
3296                                         napi->poll = &ixgbe_clean_txonly;
3297                                 else if (q_vector->rxr_count == 1)
3298                                         napi->poll = &ixgbe_clean_rxonly;
3299                         }
3300                 }
3301
3302                 napi_enable(napi);
3303         }
3304 }
3305
3306 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3307 {
3308         int q_idx;
3309         struct ixgbe_q_vector *q_vector;
3310         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3311
3312         /* legacy and MSI only use one vector */
3313         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3314                 q_vectors = 1;
3315
3316         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3317                 q_vector = adapter->q_vector[q_idx];
3318                 napi_disable(&q_vector->napi);
3319         }
3320 }
3321
3322 #ifdef CONFIG_IXGBE_DCB
3323 /*
3324  * ixgbe_configure_dcb - Configure DCB hardware
3325  * @adapter: ixgbe adapter struct
3326  *
3327  * This is called by the driver on open to configure the DCB hardware.
3328  * This is also called by the gennetlink interface when reconfiguring
3329  * the DCB state.
3330  */
3331 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3332 {
3333         struct ixgbe_hw *hw = &adapter->hw;
3334         u32 txdctl;
3335         int i, j;
3336
3337         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3338                 if (hw->mac.type == ixgbe_mac_82598EB)
3339                         netif_set_gso_max_size(adapter->netdev, 65536);
3340                 return;
3341         }
3342
3343         if (hw->mac.type == ixgbe_mac_82598EB)
3344                 netif_set_gso_max_size(adapter->netdev, 32768);
3345
3346         ixgbe_dcb_check_config(&adapter->dcb_cfg);
3347         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
3348         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
3349
3350         /* reconfigure the hardware */
3351         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3352
3353         for (i = 0; i < adapter->num_tx_queues; i++) {
3354                 j = adapter->tx_ring[i]->reg_idx;
3355                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3356                 /* PThresh workaround for Tx hang with DFP enabled. */
3357                 txdctl |= 32;
3358                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3359         }
3360         /* Enable VLAN tag insert/strip */
3361         ixgbe_vlan_filter_enable(adapter);
3362
3363         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3364 }
3365
3366 #endif
3367 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3368 {
3369         struct net_device *netdev = adapter->netdev;
3370         struct ixgbe_hw *hw = &adapter->hw;
3371         int i;
3372
3373         ixgbe_set_rx_mode(netdev);
3374
3375         ixgbe_restore_vlan(adapter);
3376 #ifdef CONFIG_IXGBE_DCB
3377         ixgbe_configure_dcb(adapter);
3378 #endif
3379
3380 #ifdef IXGBE_FCOE
3381         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3382                 ixgbe_configure_fcoe(adapter);
3383
3384 #endif /* IXGBE_FCOE */
3385         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3386                 for (i = 0; i < adapter->num_tx_queues; i++)
3387                         adapter->tx_ring[i]->atr_sample_rate =
3388                                                        adapter->atr_sample_rate;
3389                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3390         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3391                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3392         }
3393
3394         ixgbe_configure_tx(adapter);
3395         ixgbe_configure_rx(adapter);
3396 }
3397
3398 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3399 {
3400         switch (hw->phy.type) {
3401         case ixgbe_phy_sfp_avago:
3402         case ixgbe_phy_sfp_ftl:
3403         case ixgbe_phy_sfp_intel:
3404         case ixgbe_phy_sfp_unknown:
3405         case ixgbe_phy_sfp_passive_tyco:
3406         case ixgbe_phy_sfp_passive_unknown:
3407         case ixgbe_phy_sfp_active_unknown:
3408         case ixgbe_phy_sfp_ftl_active:
3409                 return true;
3410         default:
3411                 return false;
3412         }
3413 }
3414
3415 /**
3416  * ixgbe_sfp_link_config - set up SFP+ link
3417  * @adapter: pointer to private adapter struct
3418  **/
3419 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3420 {
3421         struct ixgbe_hw *hw = &adapter->hw;
3422
3423                 if (hw->phy.multispeed_fiber) {
3424                         /*
3425                          * In multispeed fiber setups, the device may not have
3426                          * had a physical connection when the driver loaded.
3427                          * If that's the case, the initial link configuration
3428                          * couldn't get the MAC into 10G or 1G mode, so we'll
3429                          * never have a link status change interrupt fire.
3430                          * We need to try and force an autonegotiation
3431                          * session, then bring up link.
3432                          */
3433                         hw->mac.ops.setup_sfp(hw);
3434                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3435                                 schedule_work(&adapter->multispeed_fiber_task);
3436                 } else {
3437                         /*
3438                          * Direct Attach Cu and non-multispeed fiber modules
3439                          * still need to be configured properly prior to
3440                          * attempting link.
3441                          */
3442                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3443                                 schedule_work(&adapter->sfp_config_module_task);
3444                 }
3445 }
3446
3447 /**
3448  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3449  * @hw: pointer to private hardware struct
3450  *
3451  * Returns 0 on success, negative on failure
3452  **/
3453 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3454 {
3455         u32 autoneg;
3456         bool negotiation, link_up = false;
3457         u32 ret = IXGBE_ERR_LINK_SETUP;
3458
3459         if (hw->mac.ops.check_link)
3460                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3461
3462         if (ret)
3463                 goto link_cfg_out;
3464
3465         if (hw->mac.ops.get_link_capabilities)
3466                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
3467         if (ret)
3468                 goto link_cfg_out;
3469
3470         if (hw->mac.ops.setup_link)
3471                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3472 link_cfg_out:
3473         return ret;
3474 }
3475
3476 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3477 {
3478         struct ixgbe_hw *hw = &adapter->hw;
3479         u32 gpie = 0;
3480
3481         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3482                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3483                        IXGBE_GPIE_OCD;
3484                 gpie |= IXGBE_GPIE_EIAME;
3485                 /*
3486                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3487                  * this saves a register write for every interrupt
3488                  */
3489                 switch (hw->mac.type) {
3490                 case ixgbe_mac_82598EB:
3491                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3492                         break;
3493                 default:
3494                 case ixgbe_mac_82599EB:
3495                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3496                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3497                         break;
3498                 }
3499         } else {
3500                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3501                  * specifically only auto mask tx and rx interrupts */
3502                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3503         }
3504
3505         /* XXX: to interrupt immediately for EICS writes, enable this */
3506         /* gpie |= IXGBE_GPIE_EIMEN; */
3507
3508         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3509                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3510                 gpie |= IXGBE_GPIE_VTMODE_64;
3511         }
3512
3513         /* Enable fan failure interrupt */
3514         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3515                 gpie |= IXGBE_SDP1_GPIEN;
3516
3517         if (hw->mac.type == ixgbe_mac_82599EB)
3518                 gpie |= IXGBE_SDP1_GPIEN;
3519                 gpie |= IXGBE_SDP2_GPIEN;
3520
3521         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3522 }
3523
3524 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3525 {
3526         struct ixgbe_hw *hw = &adapter->hw;
3527         int err;
3528         u32 ctrl_ext;
3529
3530         ixgbe_get_hw_control(adapter);
3531         ixgbe_setup_gpie(adapter);
3532
3533         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3534                 ixgbe_configure_msix(adapter);
3535         else
3536                 ixgbe_configure_msi_and_legacy(adapter);
3537
3538         /* enable the optics */
3539         if (hw->phy.multispeed_fiber)
3540                 hw->mac.ops.enable_tx_laser(hw);
3541
3542         clear_bit(__IXGBE_DOWN, &adapter->state);
3543         ixgbe_napi_enable_all(adapter);
3544
3545         /* clear any pending interrupts, may auto mask */
3546         IXGBE_READ_REG(hw, IXGBE_EICR);
3547         ixgbe_irq_enable(adapter);
3548
3549         /*
3550          * If this adapter has a fan, check to see if we had a failure
3551          * before we enabled the interrupt.
3552          */
3553         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3554                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3555                 if (esdp & IXGBE_ESDP_SDP1)
3556                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3557         }
3558
3559         /*
3560          * For hot-pluggable SFP+ devices, a new SFP+ module may have
3561          * arrived before interrupts were enabled but after probe.  Such
3562          * devices wouldn't have their type identified yet. We need to
3563          * kick off the SFP+ module setup first, then try to bring up link.
3564          * If we're not hot-pluggable SFP+, we just need to configure link
3565          * and bring it up.
3566          */
3567         if (hw->phy.type == ixgbe_phy_unknown) {
3568                 err = hw->phy.ops.identify(hw);
3569                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3570                         /*
3571                          * Take the device down and schedule the sfp tasklet
3572                          * which will unregister_netdev and log it.
3573                          */
3574                         ixgbe_down(adapter);
3575                         schedule_work(&adapter->sfp_config_module_task);
3576                         return err;
3577                 }
3578         }
3579
3580         if (ixgbe_is_sfp(hw)) {
3581                 ixgbe_sfp_link_config(adapter);
3582         } else {
3583                 err = ixgbe_non_sfp_link_config(hw);
3584                 if (err)
3585                         e_err(probe, "link_config FAILED %d\n", err);
3586         }
3587
3588         /* enable transmits */
3589         netif_tx_start_all_queues(adapter->netdev);
3590
3591         /* bring the link up in the watchdog, this could race with our first
3592          * link up interrupt but shouldn't be a problem */
3593         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3594         adapter->link_check_timeout = jiffies;
3595         mod_timer(&adapter->watchdog_timer, jiffies);
3596
3597         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3598         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3599         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3600         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3601
3602         return 0;
3603 }
3604
3605 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3606 {
3607         WARN_ON(in_interrupt());
3608         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3609                 msleep(1);
3610         ixgbe_down(adapter);
3611         /*
3612          * If SR-IOV enabled then wait a bit before bringing the adapter
3613          * back up to give the VFs time to respond to the reset.  The
3614          * two second wait is based upon the watchdog timer cycle in
3615          * the VF driver.
3616          */
3617         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3618                 msleep(2000);
3619         ixgbe_up(adapter);
3620         clear_bit(__IXGBE_RESETTING, &adapter->state);
3621 }
3622
3623 int ixgbe_up(struct ixgbe_adapter *adapter)
3624 {
3625         /* hardware has been reset, we need to reload some things */
3626         ixgbe_configure(adapter);
3627
3628         return ixgbe_up_complete(adapter);
3629 }
3630
3631 void ixgbe_reset(struct ixgbe_adapter *adapter)
3632 {
3633         struct ixgbe_hw *hw = &adapter->hw;
3634         int err;
3635
3636         err = hw->mac.ops.init_hw(hw);
3637         switch (err) {
3638         case 0:
3639         case IXGBE_ERR_SFP_NOT_PRESENT:
3640                 break;
3641         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3642                 e_dev_err("master disable timed out\n");
3643                 break;
3644         case IXGBE_ERR_EEPROM_VERSION:
3645                 /* We are running on a pre-production device, log a warning */
3646                 e_dev_warn("This device is a pre-production adapter/LOM. "
3647                            "Please be aware there may be issuesassociated with "
3648                            "your hardware.  If you are experiencing problems "
3649                            "please contact your Intel or hardware "
3650                            "representative who provided you with this "
3651                            "hardware.\n");
3652                 break;
3653         default:
3654                 e_dev_err("Hardware Error: %d\n", err);
3655         }
3656
3657         /* reprogram the RAR[0] in case user changed it. */
3658         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3659                             IXGBE_RAH_AV);
3660 }
3661
3662 /**
3663  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3664  * @adapter: board private structure
3665  * @rx_ring: ring to free buffers from
3666  **/
3667 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
3668                                 struct ixgbe_ring *rx_ring)
3669 {
3670         struct pci_dev *pdev = adapter->pdev;
3671         unsigned long size;
3672         unsigned int i;
3673
3674         /* Free all the Rx ring sk_buffs */
3675
3676         for (i = 0; i < rx_ring->count; i++) {
3677                 struct ixgbe_rx_buffer *rx_buffer_info;
3678
3679                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3680                 if (rx_buffer_info->dma) {
3681                         dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
3682                                          rx_ring->rx_buf_len,
3683                                          DMA_FROM_DEVICE);
3684                         rx_buffer_info->dma = 0;
3685                 }
3686                 if (rx_buffer_info->skb) {
3687                         struct sk_buff *skb = rx_buffer_info->skb;
3688                         rx_buffer_info->skb = NULL;
3689                         do {
3690                                 struct sk_buff *this = skb;
3691                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3692                                         dma_unmap_single(&pdev->dev,
3693                                                          IXGBE_RSC_CB(this)->dma,
3694                                                          rx_ring->rx_buf_len,
3695                                                          DMA_FROM_DEVICE);
3696                                         IXGBE_RSC_CB(this)->dma = 0;
3697                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3698                                 }
3699                                 skb = skb->prev;
3700                                 dev_kfree_skb(this);
3701                         } while (skb);
3702                 }
3703                 if (!rx_buffer_info->page)
3704                         continue;
3705                 if (rx_buffer_info->page_dma) {
3706                         dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3707                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
3708                         rx_buffer_info->page_dma = 0;
3709                 }
3710                 put_page(rx_buffer_info->page);
3711                 rx_buffer_info->page = NULL;
3712                 rx_buffer_info->page_offset = 0;
3713         }
3714
3715         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3716         memset(rx_ring->rx_buffer_info, 0, size);
3717
3718         /* Zero out the descriptor ring */
3719         memset(rx_ring->desc, 0, rx_ring->size);
3720
3721         rx_ring->next_to_clean = 0;
3722         rx_ring->next_to_use = 0;
3723
3724         if (rx_ring->head)
3725                 writel(0, adapter->hw.hw_addr + rx_ring->head);
3726         if (rx_ring->tail)
3727                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
3728 }
3729
3730 /**
3731  * ixgbe_clean_tx_ring - Free Tx Buffers
3732  * @adapter: board private structure
3733  * @tx_ring: ring to be cleaned
3734  **/
3735 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
3736                                 struct ixgbe_ring *tx_ring)
3737 {
3738         struct ixgbe_tx_buffer *tx_buffer_info;
3739         unsigned long size;
3740         unsigned int i;
3741
3742         /* Free all the Tx ring sk_buffs */
3743
3744         for (i = 0; i < tx_ring->count; i++) {
3745                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3746                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3747         }
3748
3749         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3750         memset(tx_ring->tx_buffer_info, 0, size);
3751
3752         /* Zero out the descriptor ring */
3753         memset(tx_ring->desc, 0, tx_ring->size);
3754
3755         tx_ring->next_to_use = 0;
3756         tx_ring->next_to_clean = 0;
3757
3758         if (tx_ring->head)
3759                 writel(0, adapter->hw.hw_addr + tx_ring->head);
3760         if (tx_ring->tail)
3761                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
3762 }
3763
3764 /**
3765  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3766  * @adapter: board private structure
3767  **/
3768 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3769 {
3770         int i;
3771
3772         for (i = 0; i < adapter->num_rx_queues; i++)
3773                 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
3774 }
3775
3776 /**
3777  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3778  * @adapter: board private structure
3779  **/
3780 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3781 {
3782         int i;
3783
3784         for (i = 0; i < adapter->num_tx_queues; i++)
3785                 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
3786 }
3787
3788 void ixgbe_down(struct ixgbe_adapter *adapter)
3789 {
3790         struct net_device *netdev = adapter->netdev;
3791         struct ixgbe_hw *hw = &adapter->hw;
3792         u32 rxctrl;
3793         u32 txdctl;
3794         int i, j;
3795
3796         /* signal that we are down to the interrupt handler */
3797         set_bit(__IXGBE_DOWN, &adapter->state);
3798
3799         /* disable receive for all VFs and wait one second */
3800         if (adapter->num_vfs) {
3801                 /* ping all the active vfs to let them know we are going down */
3802                 ixgbe_ping_all_vfs(adapter);
3803
3804                 /* Disable all VFTE/VFRE TX/RX */
3805                 ixgbe_disable_tx_rx(adapter);
3806
3807                 /* Mark all the VFs as inactive */
3808                 for (i = 0 ; i < adapter->num_vfs; i++)
3809                         adapter->vfinfo[i].clear_to_send = 0;
3810         }
3811
3812         /* disable receives */
3813         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3814         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3815
3816         IXGBE_WRITE_FLUSH(hw);
3817         msleep(10);
3818
3819         netif_tx_stop_all_queues(netdev);
3820
3821         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3822         del_timer_sync(&adapter->sfp_timer);
3823         del_timer_sync(&adapter->watchdog_timer);
3824         cancel_work_sync(&adapter->watchdog_task);
3825
3826         netif_carrier_off(netdev);
3827         netif_tx_disable(netdev);
3828
3829         ixgbe_irq_disable(adapter);
3830
3831         ixgbe_napi_disable_all(adapter);
3832
3833         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3834             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3835                 cancel_work_sync(&adapter->fdir_reinit_task);
3836
3837         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3838                 cancel_work_sync(&adapter->check_overtemp_task);
3839
3840         /* disable transmits in the hardware now that interrupts are off */
3841         for (i = 0; i < adapter->num_tx_queues; i++) {
3842                 j = adapter->tx_ring[i]->reg_idx;
3843                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3844                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3845                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3846         }
3847         /* Disable the Tx DMA engine on 82599 */
3848         if (hw->mac.type == ixgbe_mac_82599EB)
3849                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3850                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3851                                  ~IXGBE_DMATXCTL_TE));
3852
3853         /* power down the optics */
3854         if (hw->phy.multispeed_fiber)
3855                 hw->mac.ops.disable_tx_laser(hw);
3856
3857         /* clear n-tuple filters that are cached */
3858         ethtool_ntuple_flush(netdev);
3859
3860         if (!pci_channel_offline(adapter->pdev))
3861                 ixgbe_reset(adapter);
3862         ixgbe_clean_all_tx_rings(adapter);
3863         ixgbe_clean_all_rx_rings(adapter);
3864
3865 #ifdef CONFIG_IXGBE_DCA
3866         /* since we reset the hardware DCA settings were cleared */
3867         ixgbe_setup_dca(adapter);
3868 #endif
3869 }
3870
3871 /**
3872  * ixgbe_poll - NAPI Rx polling callback
3873  * @napi: structure for representing this polling device
3874  * @budget: how many packets driver is allowed to clean
3875  *
3876  * This function is used for legacy and MSI, NAPI mode
3877  **/
3878 static int ixgbe_poll(struct napi_struct *napi, int budget)
3879 {
3880         struct ixgbe_q_vector *q_vector =
3881                                 container_of(napi, struct ixgbe_q_vector, napi);
3882         struct ixgbe_adapter *adapter = q_vector->adapter;
3883         int tx_clean_complete, work_done = 0;
3884
3885 #ifdef CONFIG_IXGBE_DCA
3886         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3887                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3888                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
3889         }
3890 #endif
3891
3892         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3893         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
3894
3895         if (!tx_clean_complete)
3896                 work_done = budget;
3897
3898         /* If budget not fully consumed, exit the polling mode */
3899         if (work_done < budget) {
3900                 napi_complete(napi);
3901                 if (adapter->rx_itr_setting & 1)
3902                         ixgbe_set_itr(adapter);
3903                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3904                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3905         }
3906         return work_done;
3907 }
3908
3909 /**
3910  * ixgbe_tx_timeout - Respond to a Tx Hang
3911  * @netdev: network interface device structure
3912  **/
3913 static void ixgbe_tx_timeout(struct net_device *netdev)
3914 {
3915         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3916
3917         /* Do the reset outside of interrupt context */
3918         schedule_work(&adapter->reset_task);
3919 }
3920
3921 static void ixgbe_reset_task(struct work_struct *work)
3922 {
3923         struct ixgbe_adapter *adapter;
3924         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3925
3926         /* If we're already down or resetting, just bail */
3927         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3928             test_bit(__IXGBE_RESETTING, &adapter->state))
3929                 return;
3930
3931         adapter->tx_timeout_count++;
3932
3933         ixgbe_dump(adapter);
3934         netdev_err(adapter->netdev, "Reset adapter\n");
3935         ixgbe_reinit_locked(adapter);
3936 }
3937
3938 #ifdef CONFIG_IXGBE_DCB
3939 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3940 {
3941         bool ret = false;
3942         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3943
3944         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3945                 return ret;
3946
3947         f->mask = 0x7 << 3;
3948         adapter->num_rx_queues = f->indices;
3949         adapter->num_tx_queues = f->indices;
3950         ret = true;
3951
3952         return ret;
3953 }
3954 #endif
3955
3956 /**
3957  * ixgbe_set_rss_queues: Allocate queues for RSS
3958  * @adapter: board private structure to initialize
3959  *
3960  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3961  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3962  *
3963  **/
3964 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3965 {
3966         bool ret = false;
3967         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3968
3969         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3970                 f->mask = 0xF;
3971                 adapter->num_rx_queues = f->indices;
3972                 adapter->num_tx_queues = f->indices;
3973                 ret = true;
3974         } else {
3975                 ret = false;
3976         }
3977
3978         return ret;
3979 }
3980
3981 /**
3982  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3983  * @adapter: board private structure to initialize
3984  *
3985  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3986  * to the original CPU that initiated the Tx session.  This runs in addition
3987  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3988  * Rx load across CPUs using RSS.
3989  *
3990  **/
3991 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3992 {
3993         bool ret = false;
3994         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3995
3996         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3997         f_fdir->mask = 0;
3998
3999         /* Flow Director must have RSS enabled */
4000         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4001             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4002              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4003                 adapter->num_tx_queues = f_fdir->indices;
4004                 adapter->num_rx_queues = f_fdir->indices;
4005                 ret = true;
4006         } else {
4007                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4008                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4009         }
4010         return ret;
4011 }
4012
4013 #ifdef IXGBE_FCOE
4014 /**
4015  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4016  * @adapter: board private structure to initialize
4017  *
4018  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4019  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4020  * rx queues out of the max number of rx queues, instead, it is used as the
4021  * index of the first rx queue used by FCoE.
4022  *
4023  **/
4024 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4025 {
4026         bool ret = false;
4027         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4028
4029         f->indices = min((int)num_online_cpus(), f->indices);
4030         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4031                 adapter->num_rx_queues = 1;
4032                 adapter->num_tx_queues = 1;
4033 #ifdef CONFIG_IXGBE_DCB
4034                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4035                         e_info(probe, "FCoE enabled with DCB\n");
4036                         ixgbe_set_dcb_queues(adapter);
4037                 }
4038 #endif
4039                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4040                         e_info(probe, "FCoE enabled with RSS\n");
4041                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4042                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4043                                 ixgbe_set_fdir_queues(adapter);
4044                         else
4045                                 ixgbe_set_rss_queues(adapter);
4046                 }
4047                 /* adding FCoE rx rings to the end */
4048                 f->mask = adapter->num_rx_queues;
4049                 adapter->num_rx_queues += f->indices;
4050                 adapter->num_tx_queues += f->indices;
4051
4052                 ret = true;
4053         }
4054
4055         return ret;
4056 }
4057
4058 #endif /* IXGBE_FCOE */
4059 /**
4060  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4061  * @adapter: board private structure to initialize
4062  *
4063  * IOV doesn't actually use anything, so just NAK the
4064  * request for now and let the other queue routines
4065  * figure out what to do.
4066  */
4067 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4068 {
4069         return false;
4070 }
4071
4072 /*
4073  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4074  * @adapter: board private structure to initialize
4075  *
4076  * This is the top level queue allocation routine.  The order here is very
4077  * important, starting with the "most" number of features turned on at once,
4078  * and ending with the smallest set of features.  This way large combinations
4079  * can be allocated if they're turned on, and smaller combinations are the
4080  * fallthrough conditions.
4081  *
4082  **/
4083 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4084 {
4085         /* Start with base case */
4086         adapter->num_rx_queues = 1;
4087         adapter->num_tx_queues = 1;
4088         adapter->num_rx_pools = adapter->num_rx_queues;
4089         adapter->num_rx_queues_per_pool = 1;
4090
4091         if (ixgbe_set_sriov_queues(adapter))
4092                 return;
4093
4094 #ifdef IXGBE_FCOE
4095         if (ixgbe_set_fcoe_queues(adapter))
4096                 goto done;
4097
4098 #endif /* IXGBE_FCOE */
4099 #ifdef CONFIG_IXGBE_DCB
4100         if (ixgbe_set_dcb_queues(adapter))
4101                 goto done;
4102
4103 #endif
4104         if (ixgbe_set_fdir_queues(adapter))
4105                 goto done;
4106
4107         if (ixgbe_set_rss_queues(adapter))
4108                 goto done;
4109
4110         /* fallback to base case */
4111         adapter->num_rx_queues = 1;
4112         adapter->num_tx_queues = 1;
4113
4114 done:
4115         /* Notify the stack of the (possibly) reduced Tx Queue count. */
4116         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4117 }
4118
4119 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4120                                        int vectors)
4121 {
4122         int err, vector_threshold;
4123
4124         /* We'll want at least 3 (vector_threshold):
4125          * 1) TxQ[0] Cleanup
4126          * 2) RxQ[0] Cleanup
4127          * 3) Other (Link Status Change, etc.)
4128          * 4) TCP Timer (optional)
4129          */
4130         vector_threshold = MIN_MSIX_COUNT;
4131
4132         /* The more we get, the more we will assign to Tx/Rx Cleanup
4133          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4134          * Right now, we simply care about how many we'll get; we'll
4135          * set them up later while requesting irq's.
4136          */
4137         while (vectors >= vector_threshold) {
4138                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4139                                       vectors);
4140                 if (!err) /* Success in acquiring all requested vectors. */
4141                         break;
4142                 else if (err < 0)
4143                         vectors = 0; /* Nasty failure, quit now */
4144                 else /* err == number of vectors we should try again with */
4145                         vectors = err;
4146         }
4147
4148         if (vectors < vector_threshold) {
4149                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4150                  * This just means we'll go with either a single MSI
4151                  * vector or fall back to legacy interrupts.
4152                  */
4153                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4154                              "Unable to allocate MSI-X interrupts\n");
4155                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4156                 kfree(adapter->msix_entries);
4157                 adapter->msix_entries = NULL;
4158         } else {
4159                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4160                 /*
4161                  * Adjust for only the vectors we'll use, which is minimum
4162                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4163                  * vectors we were allocated.
4164                  */
4165                 adapter->num_msix_vectors = min(vectors,
4166                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4167         }
4168 }
4169
4170 /**
4171  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4172  * @adapter: board private structure to initialize
4173  *
4174  * Cache the descriptor ring offsets for RSS to the assigned rings.
4175  *
4176  **/
4177 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4178 {
4179         int i;
4180         bool ret = false;
4181
4182         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4183                 for (i = 0; i < adapter->num_rx_queues; i++)
4184                         adapter->rx_ring[i]->reg_idx = i;
4185                 for (i = 0; i < adapter->num_tx_queues; i++)
4186                         adapter->tx_ring[i]->reg_idx = i;
4187                 ret = true;
4188         } else {
4189                 ret = false;
4190         }
4191
4192         return ret;
4193 }
4194
4195 #ifdef CONFIG_IXGBE_DCB
4196 /**
4197  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4198  * @adapter: board private structure to initialize
4199  *
4200  * Cache the descriptor ring offsets for DCB to the assigned rings.
4201  *
4202  **/
4203 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4204 {
4205         int i;
4206         bool ret = false;
4207         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4208
4209         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4210                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
4211                         /* the number of queues is assumed to be symmetric */
4212                         for (i = 0; i < dcb_i; i++) {
4213                                 adapter->rx_ring[i]->reg_idx = i << 3;
4214                                 adapter->tx_ring[i]->reg_idx = i << 2;
4215                         }
4216                         ret = true;
4217                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
4218                         if (dcb_i == 8) {
4219                                 /*
4220                                  * Tx TC0 starts at: descriptor queue 0
4221                                  * Tx TC1 starts at: descriptor queue 32
4222                                  * Tx TC2 starts at: descriptor queue 64
4223                                  * Tx TC3 starts at: descriptor queue 80
4224                                  * Tx TC4 starts at: descriptor queue 96
4225                                  * Tx TC5 starts at: descriptor queue 104
4226                                  * Tx TC6 starts at: descriptor queue 112
4227                                  * Tx TC7 starts at: descriptor queue 120
4228                                  *
4229                                  * Rx TC0-TC7 are offset by 16 queues each
4230                                  */
4231                                 for (i = 0; i < 3; i++) {
4232                                         adapter->tx_ring[i]->reg_idx = i << 5;
4233                                         adapter->rx_ring[i]->reg_idx = i << 4;
4234                                 }
4235                                 for ( ; i < 5; i++) {
4236                                         adapter->tx_ring[i]->reg_idx =
4237                                                                  ((i + 2) << 4);
4238                                         adapter->rx_ring[i]->reg_idx = i << 4;
4239                                 }
4240                                 for ( ; i < dcb_i; i++) {
4241                                         adapter->tx_ring[i]->reg_idx =
4242                                                                  ((i + 8) << 3);
4243                                         adapter->rx_ring[i]->reg_idx = i << 4;
4244                                 }
4245
4246                                 ret = true;
4247                         } else if (dcb_i == 4) {
4248                                 /*
4249                                  * Tx TC0 starts at: descriptor queue 0
4250                                  * Tx TC1 starts at: descriptor queue 64
4251                                  * Tx TC2 starts at: descriptor queue 96
4252                                  * Tx TC3 starts at: descriptor queue 112
4253                                  *
4254                                  * Rx TC0-TC3 are offset by 32 queues each
4255                                  */
4256                                 adapter->tx_ring[0]->reg_idx = 0;
4257                                 adapter->tx_ring[1]->reg_idx = 64;
4258                                 adapter->tx_ring[2]->reg_idx = 96;
4259                                 adapter->tx_ring[3]->reg_idx = 112;
4260                                 for (i = 0 ; i < dcb_i; i++)
4261                                         adapter->rx_ring[i]->reg_idx = i << 5;
4262
4263                                 ret = true;
4264                         } else {
4265                                 ret = false;
4266                         }
4267                 } else {
4268                         ret = false;
4269                 }
4270         } else {
4271                 ret = false;
4272         }
4273
4274         return ret;
4275 }
4276 #endif
4277
4278 /**
4279  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4280  * @adapter: board private structure to initialize
4281  *
4282  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4283  *
4284  **/
4285 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4286 {
4287         int i;
4288         bool ret = false;
4289
4290         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4291             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4292              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4293                 for (i = 0; i < adapter->num_rx_queues; i++)
4294                         adapter->rx_ring[i]->reg_idx = i;
4295                 for (i = 0; i < adapter->num_tx_queues; i++)
4296                         adapter->tx_ring[i]->reg_idx = i;
4297                 ret = true;
4298         }
4299
4300         return ret;
4301 }
4302
4303 #ifdef IXGBE_FCOE
4304 /**
4305  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4306  * @adapter: board private structure to initialize
4307  *
4308  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4309  *
4310  */
4311 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4312 {
4313         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
4314         bool ret = false;
4315         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4316
4317         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4318 #ifdef CONFIG_IXGBE_DCB
4319                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4320                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4321
4322                         ixgbe_cache_ring_dcb(adapter);
4323                         /* find out queues in TC for FCoE */
4324                         fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4325                         fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4326                         /*
4327                          * In 82599, the number of Tx queues for each traffic
4328                          * class for both 8-TC and 4-TC modes are:
4329                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4330                          * 8 TCs:  32  32  16  16   8   8   8   8
4331                          * 4 TCs:  64  64  32  32
4332                          * We have max 8 queues for FCoE, where 8 the is
4333                          * FCoE redirection table size. If TC for FCoE is
4334                          * less than or equal to TC3, we have enough queues
4335                          * to add max of 8 queues for FCoE, so we start FCoE
4336                          * tx descriptor from the next one, i.e., reg_idx + 1.
4337                          * If TC for FCoE is above TC3, implying 8 TC mode,
4338                          * and we need 8 for FCoE, we have to take all queues
4339                          * in that traffic class for FCoE.
4340                          */
4341                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4342                                 fcoe_tx_i--;
4343                 }
4344 #endif /* CONFIG_IXGBE_DCB */
4345                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4346                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4347                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4348                                 ixgbe_cache_ring_fdir(adapter);
4349                         else
4350                                 ixgbe_cache_ring_rss(adapter);
4351
4352                         fcoe_rx_i = f->mask;
4353                         fcoe_tx_i = f->mask;
4354                 }
4355                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4356                         adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4357                         adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4358                 }
4359                 ret = true;
4360         }
4361         return ret;
4362 }
4363
4364 #endif /* IXGBE_FCOE */
4365 /**
4366  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4367  * @adapter: board private structure to initialize
4368  *
4369  * SR-IOV doesn't use any descriptor rings but changes the default if
4370  * no other mapping is used.
4371  *
4372  */
4373 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4374 {
4375         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4376         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4377         if (adapter->num_vfs)
4378                 return true;
4379         else
4380                 return false;
4381 }
4382
4383 /**
4384  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4385  * @adapter: board private structure to initialize
4386  *
4387  * Once we know the feature-set enabled for the device, we'll cache
4388  * the register offset the descriptor ring is assigned to.
4389  *
4390  * Note, the order the various feature calls is important.  It must start with
4391  * the "most" features enabled at the same time, then trickle down to the
4392  * least amount of features turned on at once.
4393  **/
4394 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4395 {
4396         /* start with default case */
4397         adapter->rx_ring[0]->reg_idx = 0;
4398         adapter->tx_ring[0]->reg_idx = 0;
4399
4400         if (ixgbe_cache_ring_sriov(adapter))
4401                 return;
4402
4403 #ifdef IXGBE_FCOE
4404         if (ixgbe_cache_ring_fcoe(adapter))
4405                 return;
4406
4407 #endif /* IXGBE_FCOE */
4408 #ifdef CONFIG_IXGBE_DCB
4409         if (ixgbe_cache_ring_dcb(adapter))
4410                 return;
4411
4412 #endif
4413         if (ixgbe_cache_ring_fdir(adapter))
4414                 return;
4415
4416         if (ixgbe_cache_ring_rss(adapter))
4417                 return;
4418 }
4419
4420 /**
4421  * ixgbe_alloc_queues - Allocate memory for all rings
4422  * @adapter: board private structure to initialize
4423  *
4424  * We allocate one ring per queue at run-time since we don't know the
4425  * number of queues at compile-time.  The polling_netdev array is
4426  * intended for Multiqueue, but should work fine with a single queue.
4427  **/
4428 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4429 {
4430         int i;
4431         int orig_node = adapter->node;
4432
4433         for (i = 0; i < adapter->num_tx_queues; i++) {
4434                 struct ixgbe_ring *ring = adapter->tx_ring[i];
4435                 if (orig_node == -1) {
4436                         int cur_node = next_online_node(adapter->node);
4437                         if (cur_node == MAX_NUMNODES)
4438                                 cur_node = first_online_node;
4439                         adapter->node = cur_node;
4440                 }
4441                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4442                                     adapter->node);
4443                 if (!ring)
4444                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4445                 if (!ring)
4446                         goto err_tx_ring_allocation;
4447                 ring->count = adapter->tx_ring_count;
4448                 ring->queue_index = i;
4449                 ring->numa_node = adapter->node;
4450
4451                 adapter->tx_ring[i] = ring;
4452         }
4453
4454         /* Restore the adapter's original node */
4455         adapter->node = orig_node;
4456
4457         for (i = 0; i < adapter->num_rx_queues; i++) {
4458                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4459                 if (orig_node == -1) {
4460                         int cur_node = next_online_node(adapter->node);
4461                         if (cur_node == MAX_NUMNODES)
4462                                 cur_node = first_online_node;
4463                         adapter->node = cur_node;
4464                 }
4465                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4466                                     adapter->node);
4467                 if (!ring)
4468                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4469                 if (!ring)
4470                         goto err_rx_ring_allocation;
4471                 ring->count = adapter->rx_ring_count;
4472                 ring->queue_index = i;
4473                 ring->numa_node = adapter->node;
4474
4475                 adapter->rx_ring[i] = ring;
4476         }
4477
4478         /* Restore the adapter's original node */
4479         adapter->node = orig_node;
4480
4481         ixgbe_cache_ring_register(adapter);
4482
4483         return 0;
4484
4485 err_rx_ring_allocation:
4486         for (i = 0; i < adapter->num_tx_queues; i++)
4487                 kfree(adapter->tx_ring[i]);
4488 err_tx_ring_allocation:
4489         return -ENOMEM;
4490 }
4491
4492 /**
4493  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4494  * @adapter: board private structure to initialize
4495  *
4496  * Attempt to configure the interrupts using the best available
4497  * capabilities of the hardware and the kernel.
4498  **/
4499 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4500 {
4501         struct ixgbe_hw *hw = &adapter->hw;
4502         int err = 0;
4503         int vector, v_budget;
4504
4505         /*
4506          * It's easy to be greedy for MSI-X vectors, but it really
4507          * doesn't do us much good if we have a lot more vectors
4508          * than CPU's.  So let's be conservative and only ask for
4509          * (roughly) the same number of vectors as there are CPU's.
4510          */
4511         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4512                        (int)num_online_cpus()) + NON_Q_VECTORS;
4513
4514         /*
4515          * At the same time, hardware can only support a maximum of
4516          * hw.mac->max_msix_vectors vectors.  With features
4517          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4518          * descriptor queues supported by our device.  Thus, we cap it off in
4519          * those rare cases where the cpu count also exceeds our vector limit.
4520          */
4521         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4522
4523         /* A failure in MSI-X entry allocation isn't fatal, but it does
4524          * mean we disable MSI-X capabilities of the adapter. */
4525         adapter->msix_entries = kcalloc(v_budget,
4526                                         sizeof(struct msix_entry), GFP_KERNEL);
4527         if (adapter->msix_entries) {
4528                 for (vector = 0; vector < v_budget; vector++)
4529                         adapter->msix_entries[vector].entry = vector;
4530
4531                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4532
4533                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4534                         goto out;
4535         }
4536
4537         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4538         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4539         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4540         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4541         adapter->atr_sample_rate = 0;
4542         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4543                 ixgbe_disable_sriov(adapter);
4544
4545         ixgbe_set_num_queues(adapter);
4546
4547         err = pci_enable_msi(adapter->pdev);
4548         if (!err) {
4549                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4550         } else {
4551                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4552                              "Unable to allocate MSI interrupt, "
4553                              "falling back to legacy.  Error: %d\n", err);
4554                 /* reset err */
4555                 err = 0;
4556         }
4557
4558 out:
4559         return err;
4560 }
4561
4562 /**
4563  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4564  * @adapter: board private structure to initialize
4565  *
4566  * We allocate one q_vector per queue interrupt.  If allocation fails we
4567  * return -ENOMEM.
4568  **/
4569 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4570 {
4571         int q_idx, num_q_vectors;
4572         struct ixgbe_q_vector *q_vector;
4573         int napi_vectors;
4574         int (*poll)(struct napi_struct *, int);
4575
4576         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4577                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4578                 napi_vectors = adapter->num_rx_queues;
4579                 poll = &ixgbe_clean_rxtx_many;
4580         } else {
4581                 num_q_vectors = 1;
4582                 napi_vectors = 1;
4583                 poll = &ixgbe_poll;
4584         }
4585
4586         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4587                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4588                                         GFP_KERNEL, adapter->node);
4589                 if (!q_vector)
4590                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4591                                            GFP_KERNEL);
4592                 if (!q_vector)
4593                         goto err_out;
4594                 q_vector->adapter = adapter;
4595                 if (q_vector->txr_count && !q_vector->rxr_count)
4596                         q_vector->eitr = adapter->tx_eitr_param;
4597                 else
4598                         q_vector->eitr = adapter->rx_eitr_param;
4599                 q_vector->v_idx = q_idx;
4600                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4601                 adapter->q_vector[q_idx] = q_vector;
4602         }
4603
4604         return 0;
4605
4606 err_out:
4607         while (q_idx) {
4608                 q_idx--;
4609                 q_vector = adapter->q_vector[q_idx];
4610                 netif_napi_del(&q_vector->napi);
4611                 kfree(q_vector);
4612                 adapter->q_vector[q_idx] = NULL;
4613         }
4614         return -ENOMEM;
4615 }
4616
4617 /**
4618  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4619  * @adapter: board private structure to initialize
4620  *
4621  * This function frees the memory allocated to the q_vectors.  In addition if
4622  * NAPI is enabled it will delete any references to the NAPI struct prior
4623  * to freeing the q_vector.
4624  **/
4625 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4626 {
4627         int q_idx, num_q_vectors;
4628
4629         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4630                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4631         else
4632                 num_q_vectors = 1;
4633
4634         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4635                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4636                 adapter->q_vector[q_idx] = NULL;
4637                 netif_napi_del(&q_vector->napi);
4638                 kfree(q_vector);
4639         }
4640 }
4641
4642 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4643 {
4644         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4645                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4646                 pci_disable_msix(adapter->pdev);
4647                 kfree(adapter->msix_entries);
4648                 adapter->msix_entries = NULL;
4649         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4650                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4651                 pci_disable_msi(adapter->pdev);
4652         }
4653 }
4654
4655 /**
4656  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4657  * @adapter: board private structure to initialize
4658  *
4659  * We determine which interrupt scheme to use based on...
4660  * - Kernel support (MSI, MSI-X)
4661  *   - which can be user-defined (via MODULE_PARAM)
4662  * - Hardware queue count (num_*_queues)
4663  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4664  **/
4665 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4666 {
4667         int err;
4668
4669         /* Number of supported queues */
4670         ixgbe_set_num_queues(adapter);
4671
4672         err = ixgbe_set_interrupt_capability(adapter);
4673         if (err) {
4674                 e_dev_err("Unable to setup interrupt capabilities\n");
4675                 goto err_set_interrupt;
4676         }
4677
4678         err = ixgbe_alloc_q_vectors(adapter);
4679         if (err) {
4680                 e_dev_err("Unable to allocate memory for queue vectors\n");
4681                 goto err_alloc_q_vectors;
4682         }
4683
4684         err = ixgbe_alloc_queues(adapter);
4685         if (err) {
4686                 e_dev_err("Unable to allocate memory for queues\n");
4687                 goto err_alloc_queues;
4688         }
4689
4690         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4691                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4692                    adapter->num_rx_queues, adapter->num_tx_queues);
4693
4694         set_bit(__IXGBE_DOWN, &adapter->state);
4695
4696         return 0;
4697
4698 err_alloc_queues:
4699         ixgbe_free_q_vectors(adapter);
4700 err_alloc_q_vectors:
4701         ixgbe_reset_interrupt_capability(adapter);
4702 err_set_interrupt:
4703         return err;
4704 }
4705
4706 /**
4707  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4708  * @adapter: board private structure to clear interrupt scheme on
4709  *
4710  * We go through and clear interrupt specific resources and reset the structure
4711  * to pre-load conditions
4712  **/
4713 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4714 {
4715         int i;
4716
4717         for (i = 0; i < adapter->num_tx_queues; i++) {
4718                 kfree(adapter->tx_ring[i]);
4719                 adapter->tx_ring[i] = NULL;
4720         }
4721         for (i = 0; i < adapter->num_rx_queues; i++) {
4722                 kfree(adapter->rx_ring[i]);
4723                 adapter->rx_ring[i] = NULL;
4724         }
4725
4726         ixgbe_free_q_vectors(adapter);
4727         ixgbe_reset_interrupt_capability(adapter);
4728 }
4729
4730 /**
4731  * ixgbe_sfp_timer - worker thread to find a missing module
4732  * @data: pointer to our adapter struct
4733  **/
4734 static void ixgbe_sfp_timer(unsigned long data)
4735 {
4736         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4737
4738         /*
4739          * Do the sfp_timer outside of interrupt context due to the
4740          * delays that sfp+ detection requires
4741          */
4742         schedule_work(&adapter->sfp_task);
4743 }
4744
4745 /**
4746  * ixgbe_sfp_task - worker thread to find a missing module
4747  * @work: pointer to work_struct containing our data
4748  **/
4749 static void ixgbe_sfp_task(struct work_struct *work)
4750 {
4751         struct ixgbe_adapter *adapter = container_of(work,
4752                                                      struct ixgbe_adapter,
4753                                                      sfp_task);
4754         struct ixgbe_hw *hw = &adapter->hw;
4755
4756         if ((hw->phy.type == ixgbe_phy_nl) &&
4757             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4758                 s32 ret = hw->phy.ops.identify_sfp(hw);
4759                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4760                         goto reschedule;
4761                 ret = hw->phy.ops.reset(hw);
4762                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4763                         e_dev_err("failed to initialize because an unsupported "
4764                                   "SFP+ module type was detected.\n");
4765                         e_dev_err("Reload the driver after installing a "
4766                                   "supported module.\n");
4767                         unregister_netdev(adapter->netdev);
4768                 } else {
4769                         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
4770                 }
4771                 /* don't need this routine any more */
4772                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4773         }
4774         return;
4775 reschedule:
4776         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4777                 mod_timer(&adapter->sfp_timer,
4778                           round_jiffies(jiffies + (2 * HZ)));
4779 }
4780
4781 /**
4782  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4783  * @adapter: board private structure to initialize
4784  *
4785  * ixgbe_sw_init initializes the Adapter private data structure.
4786  * Fields are initialized based on PCI device information and
4787  * OS network device settings (MTU size).
4788  **/
4789 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4790 {
4791         struct ixgbe_hw *hw = &adapter->hw;
4792         struct pci_dev *pdev = adapter->pdev;
4793         struct net_device *dev = adapter->netdev;
4794         unsigned int rss;
4795 #ifdef CONFIG_IXGBE_DCB
4796         int j;
4797         struct tc_configuration *tc;
4798 #endif
4799
4800         /* PCI config space info */
4801
4802         hw->vendor_id = pdev->vendor;
4803         hw->device_id = pdev->device;
4804         hw->revision_id = pdev->revision;
4805         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4806         hw->subsystem_device_id = pdev->subsystem_device;
4807
4808         /* Set capability flags */
4809         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4810         adapter->ring_feature[RING_F_RSS].indices = rss;
4811         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4812         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4813         if (hw->mac.type == ixgbe_mac_82598EB) {
4814                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4815                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4816                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4817         } else if (hw->mac.type == ixgbe_mac_82599EB) {
4818                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4819                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4820                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4821                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4822                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4823                 if (dev->features & NETIF_F_NTUPLE) {
4824                         /* Flow Director perfect filter enabled */
4825                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4826                         adapter->atr_sample_rate = 0;
4827                         spin_lock_init(&adapter->fdir_perfect_lock);
4828                 } else {
4829                         /* Flow Director hash filters enabled */
4830                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4831                         adapter->atr_sample_rate = 20;
4832                 }
4833                 adapter->ring_feature[RING_F_FDIR].indices =
4834                                                          IXGBE_MAX_FDIR_INDICES;
4835                 adapter->fdir_pballoc = 0;
4836 #ifdef IXGBE_FCOE
4837                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4838                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4839                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4840 #ifdef CONFIG_IXGBE_DCB
4841                 /* Default traffic class to use for FCoE */
4842                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4843                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4844 #endif
4845 #endif /* IXGBE_FCOE */
4846         }
4847
4848 #ifdef CONFIG_IXGBE_DCB
4849         /* Configure DCB traffic classes */
4850         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4851                 tc = &adapter->dcb_cfg.tc_config[j];
4852                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4853                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4854                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4855                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4856                 tc->dcb_pfc = pfc_disabled;
4857         }
4858         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4859         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4860         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4861         adapter->dcb_cfg.pfc_mode_enable = false;
4862         adapter->dcb_cfg.round_robin_enable = false;
4863         adapter->dcb_set_bitmap = 0x00;
4864         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4865                            adapter->ring_feature[RING_F_DCB].indices);
4866
4867 #endif
4868
4869         /* default flow control settings */
4870         hw->fc.requested_mode = ixgbe_fc_full;
4871         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
4872 #ifdef CONFIG_DCB
4873         adapter->last_lfc_mode = hw->fc.current_mode;
4874 #endif
4875         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4876         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4877         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4878         hw->fc.send_xon = true;
4879         hw->fc.disable_fc_autoneg = false;
4880
4881         /* enable itr by default in dynamic mode */
4882         adapter->rx_itr_setting = 1;
4883         adapter->rx_eitr_param = 20000;
4884         adapter->tx_itr_setting = 1;
4885         adapter->tx_eitr_param = 10000;
4886
4887         /* set defaults for eitr in MegaBytes */
4888         adapter->eitr_low = 10;
4889         adapter->eitr_high = 20;
4890
4891         /* set default ring sizes */
4892         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4893         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4894
4895         /* initialize eeprom parameters */
4896         if (ixgbe_init_eeprom_params_generic(hw)) {
4897                 e_dev_err("EEPROM initialization failed\n");
4898                 return -EIO;
4899         }
4900
4901         /* enable rx csum by default */
4902         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4903
4904         /* get assigned NUMA node */
4905         adapter->node = dev_to_node(&pdev->dev);
4906
4907         set_bit(__IXGBE_DOWN, &adapter->state);
4908
4909         return 0;
4910 }
4911
4912 /**
4913  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4914  * @adapter: board private structure
4915  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4916  *
4917  * Return 0 on success, negative on failure
4918  **/
4919 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4920                              struct ixgbe_ring *tx_ring)
4921 {
4922         struct pci_dev *pdev = adapter->pdev;
4923         int size;
4924
4925         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4926         tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
4927         if (!tx_ring->tx_buffer_info)
4928                 tx_ring->tx_buffer_info = vmalloc(size);
4929         if (!tx_ring->tx_buffer_info)
4930                 goto err;
4931         memset(tx_ring->tx_buffer_info, 0, size);
4932
4933         /* round up to nearest 4K */
4934         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4935         tx_ring->size = ALIGN(tx_ring->size, 4096);
4936
4937         tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4938                                            &tx_ring->dma, GFP_KERNEL);
4939         if (!tx_ring->desc)
4940                 goto err;
4941
4942         tx_ring->next_to_use = 0;
4943         tx_ring->next_to_clean = 0;
4944         tx_ring->work_limit = tx_ring->count;
4945         return 0;
4946
4947 err:
4948         vfree(tx_ring->tx_buffer_info);
4949         tx_ring->tx_buffer_info = NULL;
4950         e_err(probe, "Unable to allocate memory for the Tx descriptor ring\n");
4951         return -ENOMEM;
4952 }
4953
4954 /**
4955  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4956  * @adapter: board private structure
4957  *
4958  * If this function returns with an error, then it's possible one or
4959  * more of the rings is populated (while the rest are not).  It is the
4960  * callers duty to clean those orphaned rings.
4961  *
4962  * Return 0 on success, negative on failure
4963  **/
4964 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4965 {
4966         int i, err = 0;
4967
4968         for (i = 0; i < adapter->num_tx_queues; i++) {
4969                 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
4970                 if (!err)
4971                         continue;
4972                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4973                 break;
4974         }
4975
4976         return err;
4977 }
4978
4979 /**
4980  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4981  * @adapter: board private structure
4982  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
4983  *
4984  * Returns 0 on success, negative on failure
4985  **/
4986 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4987                              struct ixgbe_ring *rx_ring)
4988 {
4989         struct pci_dev *pdev = adapter->pdev;
4990         int size;
4991
4992         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4993         rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4994         if (!rx_ring->rx_buffer_info)
4995                 rx_ring->rx_buffer_info = vmalloc(size);
4996         if (!rx_ring->rx_buffer_info) {
4997                 e_err(probe, "vmalloc allocation failed for the Rx "
4998                       "descriptor ring\n");
4999                 goto alloc_failed;
5000         }
5001         memset(rx_ring->rx_buffer_info, 0, size);
5002
5003         /* Round up to nearest 4K */
5004         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5005         rx_ring->size = ALIGN(rx_ring->size, 4096);
5006
5007         rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
5008                                            &rx_ring->dma, GFP_KERNEL);
5009
5010         if (!rx_ring->desc) {
5011                 e_err(probe, "Memory allocation failed for the Rx "
5012                       "descriptor ring\n");
5013                 vfree(rx_ring->rx_buffer_info);
5014                 goto alloc_failed;
5015         }
5016
5017         rx_ring->next_to_clean = 0;
5018         rx_ring->next_to_use = 0;
5019
5020         return 0;
5021
5022 alloc_failed:
5023         return -ENOMEM;
5024 }
5025
5026 /**
5027  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5028  * @adapter: board private structure
5029  *
5030  * If this function returns with an error, then it's possible one or
5031  * more of the rings is populated (while the rest are not).  It is the
5032  * callers duty to clean those orphaned rings.
5033  *
5034  * Return 0 on success, negative on failure
5035  **/
5036
5037 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5038 {
5039         int i, err = 0;
5040
5041         for (i = 0; i < adapter->num_rx_queues; i++) {
5042                 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
5043                 if (!err)
5044                         continue;
5045                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5046                 break;
5047         }
5048
5049         return err;
5050 }
5051
5052 /**
5053  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5054  * @adapter: board private structure
5055  * @tx_ring: Tx descriptor ring for a specific queue
5056  *
5057  * Free all transmit software resources
5058  **/
5059 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
5060                              struct ixgbe_ring *tx_ring)
5061 {
5062         struct pci_dev *pdev = adapter->pdev;
5063
5064         ixgbe_clean_tx_ring(adapter, tx_ring);
5065
5066         vfree(tx_ring->tx_buffer_info);
5067         tx_ring->tx_buffer_info = NULL;
5068
5069         dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
5070                           tx_ring->dma);
5071
5072         tx_ring->desc = NULL;
5073 }
5074
5075 /**
5076  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5077  * @adapter: board private structure
5078  *
5079  * Free all transmit software resources
5080  **/
5081 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5082 {
5083         int i;
5084
5085         for (i = 0; i < adapter->num_tx_queues; i++)
5086                 if (adapter->tx_ring[i]->desc)
5087                         ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
5088 }
5089
5090 /**
5091  * ixgbe_free_rx_resources - Free Rx Resources
5092  * @adapter: board private structure
5093  * @rx_ring: ring to clean the resources from
5094  *
5095  * Free all receive software resources
5096  **/
5097 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
5098                              struct ixgbe_ring *rx_ring)
5099 {
5100         struct pci_dev *pdev = adapter->pdev;
5101
5102         ixgbe_clean_rx_ring(adapter, rx_ring);
5103
5104         vfree(rx_ring->rx_buffer_info);
5105         rx_ring->rx_buffer_info = NULL;
5106
5107         dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
5108                           rx_ring->dma);
5109
5110         rx_ring->desc = NULL;
5111 }
5112
5113 /**
5114  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5115  * @adapter: board private structure
5116  *
5117  * Free all receive software resources
5118  **/
5119 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5120 {
5121         int i;
5122
5123         for (i = 0; i < adapter->num_rx_queues; i++)
5124                 if (adapter->rx_ring[i]->desc)
5125                         ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
5126 }
5127
5128 /**
5129  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5130  * @netdev: network interface device structure
5131  * @new_mtu: new value for maximum frame size
5132  *
5133  * Returns 0 on success, negative on failure
5134  **/
5135 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5136 {
5137         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5138         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5139
5140         /* MTU < 68 is an error and causes problems on some kernels */
5141         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5142                 return -EINVAL;
5143
5144         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5145         /* must set new MTU before calling down or up */
5146         netdev->mtu = new_mtu;
5147
5148         if (netif_running(netdev))
5149                 ixgbe_reinit_locked(adapter);
5150
5151         return 0;
5152 }
5153
5154 /**
5155  * ixgbe_open - Called when a network interface is made active
5156  * @netdev: network interface device structure
5157  *
5158  * Returns 0 on success, negative value on failure
5159  *
5160  * The open entry point is called when a network interface is made
5161  * active by the system (IFF_UP).  At this point all resources needed
5162  * for transmit and receive operations are allocated, the interrupt
5163  * handler is registered with the OS, the watchdog timer is started,
5164  * and the stack is notified that the interface is ready.
5165  **/
5166 static int ixgbe_open(struct net_device *netdev)
5167 {
5168         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5169         int err;
5170
5171         /* disallow open during test */
5172         if (test_bit(__IXGBE_TESTING, &adapter->state))
5173                 return -EBUSY;
5174
5175         netif_carrier_off(netdev);
5176
5177         /* allocate transmit descriptors */
5178         err = ixgbe_setup_all_tx_resources(adapter);
5179         if (err)
5180                 goto err_setup_tx;
5181
5182         /* allocate receive descriptors */
5183         err = ixgbe_setup_all_rx_resources(adapter);
5184         if (err)
5185                 goto err_setup_rx;
5186
5187         ixgbe_configure(adapter);
5188
5189         err = ixgbe_request_irq(adapter);
5190         if (err)
5191                 goto err_req_irq;
5192
5193         err = ixgbe_up_complete(adapter);
5194         if (err)
5195                 goto err_up;
5196
5197         netif_tx_start_all_queues(netdev);
5198
5199         return 0;
5200
5201 err_up:
5202         ixgbe_release_hw_control(adapter);
5203         ixgbe_free_irq(adapter);
5204 err_req_irq:
5205 err_setup_rx:
5206         ixgbe_free_all_rx_resources(adapter);
5207 err_setup_tx:
5208         ixgbe_free_all_tx_resources(adapter);
5209         ixgbe_reset(adapter);
5210
5211         return err;
5212 }
5213
5214 /**
5215  * ixgbe_close - Disables a network interface
5216  * @netdev: network interface device structure
5217  *
5218  * Returns 0, this is not allowed to fail
5219  *
5220  * The close entry point is called when an interface is de-activated
5221  * by the OS.  The hardware is still under the drivers control, but
5222  * needs to be disabled.  A global MAC reset is issued to stop the
5223  * hardware, and all transmit and receive resources are freed.
5224  **/
5225 static int ixgbe_close(struct net_device *netdev)
5226 {
5227         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5228
5229         ixgbe_down(adapter);
5230         ixgbe_free_irq(adapter);
5231
5232         ixgbe_free_all_tx_resources(adapter);
5233         ixgbe_free_all_rx_resources(adapter);
5234
5235         ixgbe_release_hw_control(adapter);
5236
5237         return 0;
5238 }
5239
5240 #ifdef CONFIG_PM
5241 static int ixgbe_resume(struct pci_dev *pdev)
5242 {
5243         struct net_device *netdev = pci_get_drvdata(pdev);
5244         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5245         u32 err;
5246
5247         pci_set_power_state(pdev, PCI_D0);
5248         pci_restore_state(pdev);
5249         /*
5250          * pci_restore_state clears dev->state_saved so call
5251          * pci_save_state to restore it.
5252          */
5253         pci_save_state(pdev);
5254
5255         err = pci_enable_device_mem(pdev);
5256         if (err) {
5257                 e_dev_err("Cannot enable PCI device from suspend\n");
5258                 return err;
5259         }
5260         pci_set_master(pdev);
5261
5262         pci_wake_from_d3(pdev, false);
5263
5264         err = ixgbe_init_interrupt_scheme(adapter);
5265         if (err) {
5266                 e_dev_err("Cannot initialize interrupts for device\n");
5267                 return err;
5268         }
5269
5270         ixgbe_reset(adapter);
5271
5272         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5273
5274         if (netif_running(netdev)) {
5275                 err = ixgbe_open(adapter->netdev);
5276                 if (err)
5277                         return err;
5278         }
5279
5280         netif_device_attach(netdev);
5281
5282         return 0;
5283 }
5284 #endif /* CONFIG_PM */
5285
5286 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5287 {
5288         struct net_device *netdev = pci_get_drvdata(pdev);
5289         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5290         struct ixgbe_hw *hw = &adapter->hw;
5291         u32 ctrl, fctrl;
5292         u32 wufc = adapter->wol;
5293 #ifdef CONFIG_PM
5294         int retval = 0;
5295 #endif
5296
5297         netif_device_detach(netdev);
5298
5299         if (netif_running(netdev)) {
5300                 ixgbe_down(adapter);
5301                 ixgbe_free_irq(adapter);
5302                 ixgbe_free_all_tx_resources(adapter);
5303                 ixgbe_free_all_rx_resources(adapter);
5304         }
5305
5306 #ifdef CONFIG_PM
5307         retval = pci_save_state(pdev);
5308         if (retval)
5309                 return retval;
5310
5311 #endif
5312         if (wufc) {
5313                 ixgbe_set_rx_mode(netdev);
5314
5315                 /* turn on all-multi mode if wake on multicast is enabled */
5316                 if (wufc & IXGBE_WUFC_MC) {
5317                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5318                         fctrl |= IXGBE_FCTRL_MPE;
5319                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5320                 }
5321
5322                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5323                 ctrl |= IXGBE_CTRL_GIO_DIS;
5324                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5325
5326                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5327         } else {
5328                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5329                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5330         }
5331
5332         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5333                 pci_wake_from_d3(pdev, true);
5334         else
5335                 pci_wake_from_d3(pdev, false);
5336
5337         *enable_wake = !!wufc;
5338
5339         ixgbe_clear_interrupt_scheme(adapter);
5340
5341         ixgbe_release_hw_control(adapter);
5342
5343         pci_disable_device(pdev);
5344
5345         return 0;
5346 }
5347
5348 #ifdef CONFIG_PM
5349 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5350 {
5351         int retval;
5352         bool wake;
5353
5354         retval = __ixgbe_shutdown(pdev, &wake);
5355         if (retval)
5356                 return retval;
5357
5358         if (wake) {
5359                 pci_prepare_to_sleep(pdev);
5360         } else {
5361                 pci_wake_from_d3(pdev, false);
5362                 pci_set_power_state(pdev, PCI_D3hot);
5363         }
5364
5365         return 0;
5366 }
5367 #endif /* CONFIG_PM */
5368
5369 static void ixgbe_shutdown(struct pci_dev *pdev)
5370 {
5371         bool wake;
5372
5373         __ixgbe_shutdown(pdev, &wake);
5374
5375         if (system_state == SYSTEM_POWER_OFF) {
5376                 pci_wake_from_d3(pdev, wake);
5377                 pci_set_power_state(pdev, PCI_D3hot);
5378         }
5379 }
5380
5381 /**
5382  * ixgbe_update_stats - Update the board statistics counters.
5383  * @adapter: board private structure
5384  **/
5385 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5386 {
5387         struct net_device *netdev = adapter->netdev;
5388         struct ixgbe_hw *hw = &adapter->hw;
5389         u64 total_mpc = 0;
5390         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5391         u64 non_eop_descs = 0, restart_queue = 0;
5392
5393         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5394             test_bit(__IXGBE_RESETTING, &adapter->state))
5395                 return;
5396
5397         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5398                 u64 rsc_count = 0;
5399                 u64 rsc_flush = 0;
5400                 for (i = 0; i < 16; i++)
5401                         adapter->hw_rx_no_dma_resources +=
5402                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5403                 for (i = 0; i < adapter->num_rx_queues; i++) {
5404                         rsc_count += adapter->rx_ring[i]->rsc_count;
5405                         rsc_flush += adapter->rx_ring[i]->rsc_flush;
5406                 }
5407                 adapter->rsc_total_count = rsc_count;
5408                 adapter->rsc_total_flush = rsc_flush;
5409         }
5410
5411         /* gather some stats to the adapter struct that are per queue */
5412         for (i = 0; i < adapter->num_tx_queues; i++)
5413                 restart_queue += adapter->tx_ring[i]->restart_queue;
5414         adapter->restart_queue = restart_queue;
5415
5416         for (i = 0; i < adapter->num_rx_queues; i++)
5417                 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
5418         adapter->non_eop_descs = non_eop_descs;
5419
5420         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5421         for (i = 0; i < 8; i++) {
5422                 /* for packet buffers not used, the register should read 0 */
5423                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5424                 missed_rx += mpc;
5425                 adapter->stats.mpc[i] += mpc;
5426                 total_mpc += adapter->stats.mpc[i];
5427                 if (hw->mac.type == ixgbe_mac_82598EB)
5428                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5429                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5430                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5431                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5432                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5433                 if (hw->mac.type == ixgbe_mac_82599EB) {
5434                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5435                                                             IXGBE_PXONRXCNT(i));
5436                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5437                                                            IXGBE_PXOFFRXCNT(i));
5438                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5439                 } else {
5440                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5441                                                               IXGBE_PXONRXC(i));
5442                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5443                                                              IXGBE_PXOFFRXC(i));
5444                 }
5445                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
5446                                                             IXGBE_PXONTXC(i));
5447                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
5448                                                              IXGBE_PXOFFTXC(i));
5449         }
5450         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5451         /* work around hardware counting issue */
5452         adapter->stats.gprc -= missed_rx;
5453
5454         /* 82598 hardware only has a 32 bit counter in the high register */
5455         if (hw->mac.type == ixgbe_mac_82599EB) {
5456                 u64 tmp;
5457                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5458                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
5459                 adapter->stats.gorc += (tmp << 32);
5460                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5461                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
5462                 adapter->stats.gotc += (tmp << 32);
5463                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5464                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5465                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5466                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5467                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5468                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5469 #ifdef IXGBE_FCOE
5470                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5471                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5472                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5473                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5474                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5475                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5476 #endif /* IXGBE_FCOE */
5477         } else {
5478                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5479                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5480                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5481                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5482                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5483         }
5484         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5485         adapter->stats.bprc += bprc;
5486         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5487         if (hw->mac.type == ixgbe_mac_82598EB)
5488                 adapter->stats.mprc -= bprc;
5489         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5490         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5491         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5492         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5493         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5494         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5495         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5496         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5497         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5498         adapter->stats.lxontxc += lxon;
5499         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5500         adapter->stats.lxofftxc += lxoff;
5501         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5502         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5503         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5504         /*
5505          * 82598 errata - tx of flow control packets is included in tx counters
5506          */
5507         xon_off_tot = lxon + lxoff;
5508         adapter->stats.gptc -= xon_off_tot;
5509         adapter->stats.mptc -= xon_off_tot;
5510         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5511         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5512         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5513         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5514         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5515         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5516         adapter->stats.ptc64 -= xon_off_tot;
5517         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5518         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5519         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5520         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5521         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5522         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5523
5524         /* Fill out the OS statistics structure */
5525         netdev->stats.multicast = adapter->stats.mprc;
5526
5527         /* Rx Errors */
5528         netdev->stats.rx_errors = adapter->stats.crcerrs +
5529                                        adapter->stats.rlec;
5530         netdev->stats.rx_dropped = 0;
5531         netdev->stats.rx_length_errors = adapter->stats.rlec;
5532         netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5533         netdev->stats.rx_missed_errors = total_mpc;
5534 }
5535
5536 /**
5537  * ixgbe_watchdog - Timer Call-back
5538  * @data: pointer to adapter cast into an unsigned long
5539  **/
5540 static void ixgbe_watchdog(unsigned long data)
5541 {
5542         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5543         struct ixgbe_hw *hw = &adapter->hw;
5544         u64 eics = 0;
5545         int i;
5546
5547         /*
5548          *  Do the watchdog outside of interrupt context due to the lovely
5549          * delays that some of the newer hardware requires
5550          */
5551
5552         if (test_bit(__IXGBE_DOWN, &adapter->state))
5553                 goto watchdog_short_circuit;
5554
5555         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5556                 /*
5557                  * for legacy and MSI interrupts don't set any bits
5558                  * that are enabled for EIAM, because this operation
5559                  * would set *both* EIMS and EICS for any bit in EIAM
5560                  */
5561                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5562                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5563                 goto watchdog_reschedule;
5564         }
5565
5566         /* get one bit for every active tx/rx interrupt vector */
5567         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5568                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5569                 if (qv->rxr_count || qv->txr_count)
5570                         eics |= ((u64)1 << i);
5571         }
5572
5573         /* Cause software interrupt to ensure rx rings are cleaned */
5574         ixgbe_irq_rearm_queues(adapter, eics);
5575
5576 watchdog_reschedule:
5577         /* Reset the timer */
5578         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5579
5580 watchdog_short_circuit:
5581         schedule_work(&adapter->watchdog_task);
5582 }
5583
5584 /**
5585  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5586  * @work: pointer to work_struct containing our data
5587  **/
5588 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5589 {
5590         struct ixgbe_adapter *adapter = container_of(work,
5591                                                      struct ixgbe_adapter,
5592                                                      multispeed_fiber_task);
5593         struct ixgbe_hw *hw = &adapter->hw;
5594         u32 autoneg;
5595         bool negotiation;
5596
5597         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5598         autoneg = hw->phy.autoneg_advertised;
5599         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5600                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5601         hw->mac.autotry_restart = false;
5602         if (hw->mac.ops.setup_link)
5603                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5604         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5605         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5606 }
5607
5608 /**
5609  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5610  * @work: pointer to work_struct containing our data
5611  **/
5612 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5613 {
5614         struct ixgbe_adapter *adapter = container_of(work,
5615                                                      struct ixgbe_adapter,
5616                                                      sfp_config_module_task);
5617         struct ixgbe_hw *hw = &adapter->hw;
5618         u32 err;
5619
5620         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5621
5622         /* Time for electrical oscillations to settle down */
5623         msleep(100);
5624         err = hw->phy.ops.identify_sfp(hw);
5625
5626         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5627                 e_dev_err("failed to initialize because an unsupported SFP+ "
5628                           "module type was detected.\n");
5629                 e_dev_err("Reload the driver after installing a supported "
5630                           "module.\n");
5631                 unregister_netdev(adapter->netdev);
5632                 return;
5633         }
5634         hw->mac.ops.setup_sfp(hw);
5635
5636         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5637                 /* This will also work for DA Twinax connections */
5638                 schedule_work(&adapter->multispeed_fiber_task);
5639         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5640 }
5641
5642 /**
5643  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5644  * @work: pointer to work_struct containing our data
5645  **/
5646 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5647 {
5648         struct ixgbe_adapter *adapter = container_of(work,
5649                                                      struct ixgbe_adapter,
5650                                                      fdir_reinit_task);
5651         struct ixgbe_hw *hw = &adapter->hw;
5652         int i;
5653
5654         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5655                 for (i = 0; i < adapter->num_tx_queues; i++)
5656                         set_bit(__IXGBE_FDIR_INIT_DONE,
5657                                 &(adapter->tx_ring[i]->reinit_state));
5658         } else {
5659                 e_err(probe, "failed to finish FDIR re-initialization, "
5660                       "ignored adding FDIR ATR filters\n");
5661         }
5662         /* Done FDIR Re-initialization, enable transmits */
5663         netif_tx_start_all_queues(adapter->netdev);
5664 }
5665
5666 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5667
5668 /**
5669  * ixgbe_watchdog_task - worker thread to bring link up
5670  * @work: pointer to work_struct containing our data
5671  **/
5672 static void ixgbe_watchdog_task(struct work_struct *work)
5673 {
5674         struct ixgbe_adapter *adapter = container_of(work,
5675                                                      struct ixgbe_adapter,
5676                                                      watchdog_task);
5677         struct net_device *netdev = adapter->netdev;
5678         struct ixgbe_hw *hw = &adapter->hw;
5679         u32 link_speed;
5680         bool link_up;
5681         int i;
5682         struct ixgbe_ring *tx_ring;
5683         int some_tx_pending = 0;
5684
5685         mutex_lock(&ixgbe_watchdog_lock);
5686
5687         link_up = adapter->link_up;
5688         link_speed = adapter->link_speed;
5689
5690         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5691                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5692                 if (link_up) {
5693 #ifdef CONFIG_DCB
5694                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5695                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5696                                         hw->mac.ops.fc_enable(hw, i);
5697                         } else {
5698                                 hw->mac.ops.fc_enable(hw, 0);
5699                         }
5700 #else
5701                         hw->mac.ops.fc_enable(hw, 0);
5702 #endif
5703                 }
5704
5705                 if (link_up ||
5706                     time_after(jiffies, (adapter->link_check_timeout +
5707                                          IXGBE_TRY_LINK_TIMEOUT))) {
5708                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5709                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5710                 }
5711                 adapter->link_up = link_up;
5712                 adapter->link_speed = link_speed;
5713         }
5714
5715         if (link_up) {
5716                 if (!netif_carrier_ok(netdev)) {
5717                         bool flow_rx, flow_tx;
5718
5719                         if (hw->mac.type == ixgbe_mac_82599EB) {
5720                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5721                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5722                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5723                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5724                         } else {
5725                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5726                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5727                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5728                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5729                         }
5730
5731                         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5732                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5733                                "10 Gbps" :
5734                                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5735                                "1 Gbps" : "unknown speed")),
5736                                ((flow_rx && flow_tx) ? "RX/TX" :
5737                                (flow_rx ? "RX" :
5738                                (flow_tx ? "TX" : "None"))));
5739
5740                         netif_carrier_on(netdev);
5741                 } else {
5742                         /* Force detection of hung controller */
5743                         adapter->detect_tx_hung = true;
5744                 }
5745         } else {
5746                 adapter->link_up = false;
5747                 adapter->link_speed = 0;
5748                 if (netif_carrier_ok(netdev)) {
5749                         e_info(drv, "NIC Link is Down\n");
5750                         netif_carrier_off(netdev);
5751                 }
5752         }
5753
5754         if (!netif_carrier_ok(netdev)) {
5755                 for (i = 0; i < adapter->num_tx_queues; i++) {
5756                         tx_ring = adapter->tx_ring[i];
5757                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5758                                 some_tx_pending = 1;
5759                                 break;
5760                         }
5761                 }
5762
5763                 if (some_tx_pending) {
5764                         /* We've lost link, so the controller stops DMA,
5765                          * but we've got queued Tx work that's never going
5766                          * to get done, so reset controller to flush Tx.
5767                          * (Do the reset outside of interrupt context).
5768                          */
5769                          schedule_work(&adapter->reset_task);
5770                 }
5771         }
5772
5773         ixgbe_update_stats(adapter);
5774         mutex_unlock(&ixgbe_watchdog_lock);
5775 }
5776
5777 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5778                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5779                      u32 tx_flags, u8 *hdr_len)
5780 {
5781         struct ixgbe_adv_tx_context_desc *context_desc;
5782         unsigned int i;
5783         int err;
5784         struct ixgbe_tx_buffer *tx_buffer_info;
5785         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5786         u32 mss_l4len_idx, l4len;
5787
5788         if (skb_is_gso(skb)) {
5789                 if (skb_header_cloned(skb)) {
5790                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5791                         if (err)
5792                                 return err;
5793                 }
5794                 l4len = tcp_hdrlen(skb);
5795                 *hdr_len += l4len;
5796
5797                 if (skb->protocol == htons(ETH_P_IP)) {
5798                         struct iphdr *iph = ip_hdr(skb);
5799                         iph->tot_len = 0;
5800                         iph->check = 0;
5801                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5802                                                                  iph->daddr, 0,
5803                                                                  IPPROTO_TCP,
5804                                                                  0);
5805                 } else if (skb_is_gso_v6(skb)) {
5806                         ipv6_hdr(skb)->payload_len = 0;
5807                         tcp_hdr(skb)->check =
5808                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5809                                              &ipv6_hdr(skb)->daddr,
5810                                              0, IPPROTO_TCP, 0);
5811                 }
5812
5813                 i = tx_ring->next_to_use;
5814
5815                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5816                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
5817
5818                 /* VLAN MACLEN IPLEN */
5819                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5820                         vlan_macip_lens |=
5821                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5822                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5823                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5824                 *hdr_len += skb_network_offset(skb);
5825                 vlan_macip_lens |=
5826                     (skb_transport_header(skb) - skb_network_header(skb));
5827                 *hdr_len +=
5828                     (skb_transport_header(skb) - skb_network_header(skb));
5829                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5830                 context_desc->seqnum_seed = 0;
5831
5832                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5833                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5834                                    IXGBE_ADVTXD_DTYP_CTXT);
5835
5836                 if (skb->protocol == htons(ETH_P_IP))
5837                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5838                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5839                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5840
5841                 /* MSS L4LEN IDX */
5842                 mss_l4len_idx =
5843                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5844                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5845                 /* use index 1 for TSO */
5846                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5847                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5848
5849                 tx_buffer_info->time_stamp = jiffies;
5850                 tx_buffer_info->next_to_watch = i;
5851
5852                 i++;
5853                 if (i == tx_ring->count)
5854                         i = 0;
5855                 tx_ring->next_to_use = i;
5856
5857                 return true;
5858         }
5859         return false;
5860 }
5861
5862 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5863                           struct ixgbe_ring *tx_ring,
5864                           struct sk_buff *skb, u32 tx_flags)
5865 {
5866         struct ixgbe_adv_tx_context_desc *context_desc;
5867         unsigned int i;
5868         struct ixgbe_tx_buffer *tx_buffer_info;
5869         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5870
5871         if (skb->ip_summed == CHECKSUM_PARTIAL ||
5872             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5873                 i = tx_ring->next_to_use;
5874                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5875                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
5876
5877                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5878                         vlan_macip_lens |=
5879                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5880                 vlan_macip_lens |= (skb_network_offset(skb) <<
5881                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5882                 if (skb->ip_summed == CHECKSUM_PARTIAL)
5883                         vlan_macip_lens |= (skb_transport_header(skb) -
5884                                             skb_network_header(skb));
5885
5886                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5887                 context_desc->seqnum_seed = 0;
5888
5889                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
5890                                     IXGBE_ADVTXD_DTYP_CTXT);
5891
5892                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5893                         __be16 protocol;
5894
5895                         if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5896                                 const struct vlan_ethhdr *vhdr =
5897                                         (const struct vlan_ethhdr *)skb->data;
5898
5899                                 protocol = vhdr->h_vlan_encapsulated_proto;
5900                         } else {
5901                                 protocol = skb->protocol;
5902                         }
5903
5904                         switch (protocol) {
5905                         case cpu_to_be16(ETH_P_IP):
5906                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5907                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5908                                         type_tucmd_mlhl |=
5909                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5910                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5911                                         type_tucmd_mlhl |=
5912                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5913                                 break;
5914                         case cpu_to_be16(ETH_P_IPV6):
5915                                 /* XXX what about other V6 headers?? */
5916                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5917                                         type_tucmd_mlhl |=
5918                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5919                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5920                                         type_tucmd_mlhl |=
5921                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5922                                 break;
5923                         default:
5924                                 if (unlikely(net_ratelimit())) {
5925                                         e_warn(probe, "partial checksum "
5926                                                "but proto=%x!\n",
5927                                                skb->protocol);
5928                                 }
5929                                 break;
5930                         }
5931                 }
5932
5933                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5934                 /* use index zero for tx checksum offload */
5935                 context_desc->mss_l4len_idx = 0;
5936
5937                 tx_buffer_info->time_stamp = jiffies;
5938                 tx_buffer_info->next_to_watch = i;
5939
5940                 i++;
5941                 if (i == tx_ring->count)
5942                         i = 0;
5943                 tx_ring->next_to_use = i;
5944
5945                 return true;
5946         }
5947
5948         return false;
5949 }
5950
5951 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5952                         struct ixgbe_ring *tx_ring,
5953                         struct sk_buff *skb, u32 tx_flags,
5954                         unsigned int first)
5955 {
5956         struct pci_dev *pdev = adapter->pdev;
5957         struct ixgbe_tx_buffer *tx_buffer_info;
5958         unsigned int len;
5959         unsigned int total = skb->len;
5960         unsigned int offset = 0, size, count = 0, i;
5961         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5962         unsigned int f;
5963
5964         i = tx_ring->next_to_use;
5965
5966         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5967                 /* excluding fcoe_crc_eof for FCoE */
5968                 total -= sizeof(struct fcoe_crc_eof);
5969
5970         len = min(skb_headlen(skb), total);
5971         while (len) {
5972                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5973                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5974
5975                 tx_buffer_info->length = size;
5976                 tx_buffer_info->mapped_as_page = false;
5977                 tx_buffer_info->dma = dma_map_single(&pdev->dev,
5978                                                      skb->data + offset,
5979                                                      size, DMA_TO_DEVICE);
5980                 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
5981                         goto dma_error;
5982                 tx_buffer_info->time_stamp = jiffies;
5983                 tx_buffer_info->next_to_watch = i;
5984
5985                 len -= size;
5986                 total -= size;
5987                 offset += size;
5988                 count++;
5989
5990                 if (len) {
5991                         i++;
5992                         if (i == tx_ring->count)
5993                                 i = 0;
5994                 }
5995         }
5996
5997         for (f = 0; f < nr_frags; f++) {
5998                 struct skb_frag_struct *frag;
5999
6000                 frag = &skb_shinfo(skb)->frags[f];
6001                 len = min((unsigned int)frag->size, total);
6002                 offset = frag->page_offset;
6003
6004                 while (len) {
6005                         i++;
6006                         if (i == tx_ring->count)
6007                                 i = 0;
6008
6009                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
6010                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6011
6012                         tx_buffer_info->length = size;
6013                         tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
6014                                                            frag->page,
6015                                                            offset, size,
6016                                                            DMA_TO_DEVICE);
6017                         tx_buffer_info->mapped_as_page = true;
6018                         if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
6019                                 goto dma_error;
6020                         tx_buffer_info->time_stamp = jiffies;
6021                         tx_buffer_info->next_to_watch = i;
6022
6023                         len -= size;
6024                         total -= size;
6025                         offset += size;
6026                         count++;
6027                 }
6028                 if (total == 0)
6029                         break;
6030         }
6031
6032         tx_ring->tx_buffer_info[i].skb = skb;
6033         tx_ring->tx_buffer_info[first].next_to_watch = i;
6034
6035         return count;
6036
6037 dma_error:
6038         e_dev_err("TX DMA map failed\n");
6039
6040         /* clear timestamp and dma mappings for failed tx_buffer_info map */
6041         tx_buffer_info->dma = 0;
6042         tx_buffer_info->time_stamp = 0;
6043         tx_buffer_info->next_to_watch = 0;
6044         if (count)
6045                 count--;
6046
6047         /* clear timestamp and dma mappings for remaining portion of packet */
6048         while (count--) {
6049                 if (i==0)
6050                         i += tx_ring->count;
6051                 i--;
6052                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6053                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
6054         }
6055
6056         return 0;
6057 }
6058
6059 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
6060                            struct ixgbe_ring *tx_ring,
6061                            int tx_flags, int count, u32 paylen, u8 hdr_len)
6062 {
6063         union ixgbe_adv_tx_desc *tx_desc = NULL;
6064         struct ixgbe_tx_buffer *tx_buffer_info;
6065         u32 olinfo_status = 0, cmd_type_len = 0;
6066         unsigned int i;
6067         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6068
6069         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6070
6071         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6072
6073         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6074                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6075
6076         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6077                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6078
6079                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6080                                  IXGBE_ADVTXD_POPTS_SHIFT;
6081
6082                 /* use index 1 context for tso */
6083                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6084                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6085                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6086                                          IXGBE_ADVTXD_POPTS_SHIFT;
6087
6088         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6089                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6090                                  IXGBE_ADVTXD_POPTS_SHIFT;
6091
6092         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6093                 olinfo_status |= IXGBE_ADVTXD_CC;
6094                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6095                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6096                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6097         }
6098
6099         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6100
6101         i = tx_ring->next_to_use;
6102         while (count--) {
6103                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6104                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6105                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6106                 tx_desc->read.cmd_type_len =
6107                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6108                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6109                 i++;
6110                 if (i == tx_ring->count)
6111                         i = 0;
6112         }
6113
6114         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6115
6116         /*
6117          * Force memory writes to complete before letting h/w
6118          * know there are new descriptors to fetch.  (Only
6119          * applicable for weak-ordered memory model archs,
6120          * such as IA-64).
6121          */
6122         wmb();
6123
6124         tx_ring->next_to_use = i;
6125         writel(i, adapter->hw.hw_addr + tx_ring->tail);
6126 }
6127
6128 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6129                       int queue, u32 tx_flags)
6130 {
6131         struct ixgbe_atr_input atr_input;
6132         struct tcphdr *th;
6133         struct iphdr *iph = ip_hdr(skb);
6134         struct ethhdr *eth = (struct ethhdr *)skb->data;
6135         u16 vlan_id, src_port, dst_port, flex_bytes;
6136         u32 src_ipv4_addr, dst_ipv4_addr;
6137         u8 l4type = 0;
6138
6139         /* Right now, we support IPv4 only */
6140         if (skb->protocol != htons(ETH_P_IP))
6141                 return;
6142         /* check if we're UDP or TCP */
6143         if (iph->protocol == IPPROTO_TCP) {
6144                 th = tcp_hdr(skb);
6145                 src_port = th->source;
6146                 dst_port = th->dest;
6147                 l4type |= IXGBE_ATR_L4TYPE_TCP;
6148                 /* l4type IPv4 type is 0, no need to assign */
6149         } else {
6150                 /* Unsupported L4 header, just bail here */
6151                 return;
6152         }
6153
6154         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6155
6156         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6157                    IXGBE_TX_FLAGS_VLAN_SHIFT;
6158         src_ipv4_addr = iph->saddr;
6159         dst_ipv4_addr = iph->daddr;
6160         flex_bytes = eth->h_proto;
6161
6162         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6163         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6164         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6165         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6166         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6167         /* src and dst are inverted, think how the receiver sees them */
6168         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6169         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6170
6171         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6172         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6173 }
6174
6175 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
6176                                  struct ixgbe_ring *tx_ring, int size)
6177 {
6178         netif_stop_subqueue(netdev, tx_ring->queue_index);
6179         /* Herbert's original patch had:
6180          *  smp_mb__after_netif_stop_queue();
6181          * but since that doesn't exist yet, just open code it. */
6182         smp_mb();
6183
6184         /* We need to check again in a case another CPU has just
6185          * made room available. */
6186         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6187                 return -EBUSY;
6188
6189         /* A reprieve! - use start_queue because it doesn't call schedule */
6190         netif_start_subqueue(netdev, tx_ring->queue_index);
6191         ++tx_ring->restart_queue;
6192         return 0;
6193 }
6194
6195 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
6196                               struct ixgbe_ring *tx_ring, int size)
6197 {
6198         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6199                 return 0;
6200         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6201 }
6202
6203 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6204 {
6205         struct ixgbe_adapter *adapter = netdev_priv(dev);
6206         int txq = smp_processor_id();
6207
6208 #ifdef IXGBE_FCOE
6209         if ((skb->protocol == htons(ETH_P_FCOE)) ||
6210             (skb->protocol == htons(ETH_P_FIP))) {
6211                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6212                         txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6213                         txq += adapter->ring_feature[RING_F_FCOE].mask;
6214                         return txq;
6215 #ifdef CONFIG_IXGBE_DCB
6216                 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6217                         txq = adapter->fcoe.up;
6218                         return txq;
6219 #endif
6220                 }
6221         }
6222 #endif
6223
6224         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6225                 while (unlikely(txq >= dev->real_num_tx_queues))
6226                         txq -= dev->real_num_tx_queues;
6227                 return txq;
6228         }
6229
6230         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6231                 if (skb->priority == TC_PRIO_CONTROL)
6232                         txq = adapter->ring_feature[RING_F_DCB].indices-1;
6233                 else
6234                         txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6235                                >> 13;
6236                 return txq;
6237         }
6238
6239         return skb_tx_hash(dev, skb);
6240 }
6241
6242 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6243                                     struct net_device *netdev)
6244 {
6245         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6246         struct ixgbe_ring *tx_ring;
6247         struct netdev_queue *txq;
6248         unsigned int first;
6249         unsigned int tx_flags = 0;
6250         u8 hdr_len = 0;
6251         int tso;
6252         int count = 0;
6253         unsigned int f;
6254
6255         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
6256                 tx_flags |= vlan_tx_tag_get(skb);
6257                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6258                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6259                         tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6260                 }
6261                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6262                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6263         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6264                    skb->priority != TC_PRIO_CONTROL) {
6265                 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6266                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6267                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6268         }
6269
6270         tx_ring = adapter->tx_ring[skb->queue_mapping];
6271
6272 #ifdef IXGBE_FCOE
6273         /* for FCoE with DCB, we force the priority to what
6274          * was specified by the switch */
6275         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6276             (skb->protocol == htons(ETH_P_FCOE) ||
6277              skb->protocol == htons(ETH_P_FIP))) {
6278 #ifdef CONFIG_IXGBE_DCB
6279                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6280                         tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6281                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6282                         tx_flags |= ((adapter->fcoe.up << 13)
6283                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6284                 }
6285 #endif
6286                 /* flag for FCoE offloads */
6287                 if (skb->protocol == htons(ETH_P_FCOE))
6288                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6289         }
6290 #endif
6291
6292         /* four things can cause us to need a context descriptor */
6293         if (skb_is_gso(skb) ||
6294             (skb->ip_summed == CHECKSUM_PARTIAL) ||
6295             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6296             (tx_flags & IXGBE_TX_FLAGS_FCOE))
6297                 count++;
6298
6299         count += TXD_USE_COUNT(skb_headlen(skb));
6300         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6301                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6302
6303         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
6304                 adapter->tx_busy++;
6305                 return NETDEV_TX_BUSY;
6306         }
6307
6308         first = tx_ring->next_to_use;
6309         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6310 #ifdef IXGBE_FCOE
6311                 /* setup tx offload for FCoE */
6312                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6313                 if (tso < 0) {
6314                         dev_kfree_skb_any(skb);
6315                         return NETDEV_TX_OK;
6316                 }
6317                 if (tso)
6318                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6319 #endif /* IXGBE_FCOE */
6320         } else {
6321                 if (skb->protocol == htons(ETH_P_IP))
6322                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6323                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6324                 if (tso < 0) {
6325                         dev_kfree_skb_any(skb);
6326                         return NETDEV_TX_OK;
6327                 }
6328
6329                 if (tso)
6330                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6331                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
6332                          (skb->ip_summed == CHECKSUM_PARTIAL))
6333                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6334         }
6335
6336         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
6337         if (count) {
6338                 /* add the ATR filter if ATR is on */
6339                 if (tx_ring->atr_sample_rate) {
6340                         ++tx_ring->atr_count;
6341                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6342                              test_bit(__IXGBE_FDIR_INIT_DONE,
6343                                       &tx_ring->reinit_state)) {
6344                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6345                                           tx_flags);
6346                                 tx_ring->atr_count = 0;
6347                         }
6348                 }
6349                 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6350                 txq->tx_bytes += skb->len;
6351                 txq->tx_packets++;
6352                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
6353                                hdr_len);
6354                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
6355
6356         } else {
6357                 dev_kfree_skb_any(skb);
6358                 tx_ring->tx_buffer_info[first].time_stamp = 0;
6359                 tx_ring->next_to_use = first;
6360         }
6361
6362         return NETDEV_TX_OK;
6363 }
6364
6365 /**
6366  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6367  * @netdev: network interface device structure
6368  * @p: pointer to an address structure
6369  *
6370  * Returns 0 on success, negative on failure
6371  **/
6372 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6373 {
6374         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6375         struct ixgbe_hw *hw = &adapter->hw;
6376         struct sockaddr *addr = p;
6377
6378         if (!is_valid_ether_addr(addr->sa_data))
6379                 return -EADDRNOTAVAIL;
6380
6381         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6382         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6383
6384         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6385                             IXGBE_RAH_AV);
6386
6387         return 0;
6388 }
6389
6390 static int
6391 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6392 {
6393         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6394         struct ixgbe_hw *hw = &adapter->hw;
6395         u16 value;
6396         int rc;
6397
6398         if (prtad != hw->phy.mdio.prtad)
6399                 return -EINVAL;
6400         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6401         if (!rc)
6402                 rc = value;
6403         return rc;
6404 }
6405
6406 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6407                             u16 addr, u16 value)
6408 {
6409         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6410         struct ixgbe_hw *hw = &adapter->hw;
6411
6412         if (prtad != hw->phy.mdio.prtad)
6413                 return -EINVAL;
6414         return hw->phy.ops.write_reg(hw, addr, devad, value);
6415 }
6416
6417 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6418 {
6419         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6420
6421         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6422 }
6423
6424 /**
6425  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6426  * netdev->dev_addrs
6427  * @netdev: network interface device structure
6428  *
6429  * Returns non-zero on failure
6430  **/
6431 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6432 {
6433         int err = 0;
6434         struct ixgbe_adapter *adapter = netdev_priv(dev);
6435         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6436
6437         if (is_valid_ether_addr(mac->san_addr)) {
6438                 rtnl_lock();
6439                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6440                 rtnl_unlock();
6441         }
6442         return err;
6443 }
6444
6445 /**
6446  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6447  * netdev->dev_addrs
6448  * @netdev: network interface device structure
6449  *
6450  * Returns non-zero on failure
6451  **/
6452 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6453 {
6454         int err = 0;
6455         struct ixgbe_adapter *adapter = netdev_priv(dev);
6456         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6457
6458         if (is_valid_ether_addr(mac->san_addr)) {
6459                 rtnl_lock();
6460                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6461                 rtnl_unlock();
6462         }
6463         return err;
6464 }
6465
6466 #ifdef CONFIG_NET_POLL_CONTROLLER
6467 /*
6468  * Polling 'interrupt' - used by things like netconsole to send skbs
6469  * without having to re-enable interrupts. It's not called while
6470  * the interrupt routine is executing.
6471  */
6472 static void ixgbe_netpoll(struct net_device *netdev)
6473 {
6474         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6475         int i;
6476
6477         /* if interface is down do nothing */
6478         if (test_bit(__IXGBE_DOWN, &adapter->state))
6479                 return;
6480
6481         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6482         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6483                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6484                 for (i = 0; i < num_q_vectors; i++) {
6485                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6486                         ixgbe_msix_clean_many(0, q_vector);
6487                 }
6488         } else {
6489                 ixgbe_intr(adapter->pdev->irq, netdev);
6490         }
6491         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6492 }
6493 #endif
6494
6495 static const struct net_device_ops ixgbe_netdev_ops = {
6496         .ndo_open               = ixgbe_open,
6497         .ndo_stop               = ixgbe_close,
6498         .ndo_start_xmit         = ixgbe_xmit_frame,
6499         .ndo_select_queue       = ixgbe_select_queue,
6500         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
6501         .ndo_set_multicast_list = ixgbe_set_rx_mode,
6502         .ndo_validate_addr      = eth_validate_addr,
6503         .ndo_set_mac_address    = ixgbe_set_mac,
6504         .ndo_change_mtu         = ixgbe_change_mtu,
6505         .ndo_tx_timeout         = ixgbe_tx_timeout,
6506         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
6507         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
6508         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
6509         .ndo_do_ioctl           = ixgbe_ioctl,
6510         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
6511         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
6512         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
6513         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
6514 #ifdef CONFIG_NET_POLL_CONTROLLER
6515         .ndo_poll_controller    = ixgbe_netpoll,
6516 #endif
6517 #ifdef IXGBE_FCOE
6518         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6519         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6520         .ndo_fcoe_enable = ixgbe_fcoe_enable,
6521         .ndo_fcoe_disable = ixgbe_fcoe_disable,
6522         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6523 #endif /* IXGBE_FCOE */
6524 };
6525
6526 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6527                            const struct ixgbe_info *ii)
6528 {
6529 #ifdef CONFIG_PCI_IOV
6530         struct ixgbe_hw *hw = &adapter->hw;
6531         int err;
6532
6533         if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6534                 return;
6535
6536         /* The 82599 supports up to 64 VFs per physical function
6537          * but this implementation limits allocation to 63 so that
6538          * basic networking resources are still available to the
6539          * physical function
6540          */
6541         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6542         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6543         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6544         if (err) {
6545                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
6546                 goto err_novfs;
6547         }
6548         /* If call to enable VFs succeeded then allocate memory
6549          * for per VF control structures.
6550          */
6551         adapter->vfinfo =
6552                 kcalloc(adapter->num_vfs,
6553                         sizeof(struct vf_data_storage), GFP_KERNEL);
6554         if (adapter->vfinfo) {
6555                 /* Now that we're sure SR-IOV is enabled
6556                  * and memory allocated set up the mailbox parameters
6557                  */
6558                 ixgbe_init_mbx_params_pf(hw);
6559                 memcpy(&hw->mbx.ops, ii->mbx_ops,
6560                        sizeof(hw->mbx.ops));
6561
6562                 /* Disable RSC when in SR-IOV mode */
6563                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6564                                      IXGBE_FLAG2_RSC_ENABLED);
6565                 return;
6566         }
6567
6568         /* Oh oh */
6569         e_err(probe, "Unable to allocate memory for VF Data Storage - "
6570               "SRIOV disabled\n");
6571         pci_disable_sriov(adapter->pdev);
6572
6573 err_novfs:
6574         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6575         adapter->num_vfs = 0;
6576 #endif /* CONFIG_PCI_IOV */
6577 }
6578
6579 /**
6580  * ixgbe_probe - Device Initialization Routine
6581  * @pdev: PCI device information struct
6582  * @ent: entry in ixgbe_pci_tbl
6583  *
6584  * Returns 0 on success, negative on failure
6585  *
6586  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6587  * The OS initialization, configuring of the adapter private structure,
6588  * and a hardware reset occur.
6589  **/
6590 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6591                                  const struct pci_device_id *ent)
6592 {
6593         struct net_device *netdev;
6594         struct ixgbe_adapter *adapter = NULL;
6595         struct ixgbe_hw *hw;
6596         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6597         static int cards_found;
6598         int i, err, pci_using_dac;
6599         unsigned int indices = num_possible_cpus();
6600 #ifdef IXGBE_FCOE
6601         u16 device_caps;
6602 #endif
6603         u32 part_num, eec;
6604
6605         /* Catch broken hardware that put the wrong VF device ID in
6606          * the PCIe SR-IOV capability.
6607          */
6608         if (pdev->is_virtfn) {
6609                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6610                      pci_name(pdev), pdev->vendor, pdev->device);
6611                 return -EINVAL;
6612         }
6613
6614         err = pci_enable_device_mem(pdev);
6615         if (err)
6616                 return err;
6617
6618         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6619             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6620                 pci_using_dac = 1;
6621         } else {
6622                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6623                 if (err) {
6624                         err = dma_set_coherent_mask(&pdev->dev,
6625                                                     DMA_BIT_MASK(32));
6626                         if (err) {
6627                                 dev_err(&pdev->dev,
6628                                         "No usable DMA configuration, aborting\n");
6629                                 goto err_dma;
6630                         }
6631                 }
6632                 pci_using_dac = 0;
6633         }
6634
6635         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6636                                            IORESOURCE_MEM), ixgbe_driver_name);
6637         if (err) {
6638                 dev_err(&pdev->dev,
6639                         "pci_request_selected_regions failed 0x%x\n", err);
6640                 goto err_pci_reg;
6641         }
6642
6643         pci_enable_pcie_error_reporting(pdev);
6644
6645         pci_set_master(pdev);
6646         pci_save_state(pdev);
6647
6648         if (ii->mac == ixgbe_mac_82598EB)
6649                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6650         else
6651                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6652
6653         indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6654 #ifdef IXGBE_FCOE
6655         indices += min_t(unsigned int, num_possible_cpus(),
6656                          IXGBE_MAX_FCOE_INDICES);
6657 #endif
6658         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6659         if (!netdev) {
6660                 err = -ENOMEM;
6661                 goto err_alloc_etherdev;
6662         }
6663
6664         SET_NETDEV_DEV(netdev, &pdev->dev);
6665
6666         pci_set_drvdata(pdev, netdev);
6667         adapter = netdev_priv(netdev);
6668
6669         adapter->netdev = netdev;
6670         adapter->pdev = pdev;
6671         hw = &adapter->hw;
6672         hw->back = adapter;
6673         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6674
6675         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6676                               pci_resource_len(pdev, 0));
6677         if (!hw->hw_addr) {
6678                 err = -EIO;
6679                 goto err_ioremap;
6680         }
6681
6682         for (i = 1; i <= 5; i++) {
6683                 if (pci_resource_len(pdev, i) == 0)
6684                         continue;
6685         }
6686
6687         netdev->netdev_ops = &ixgbe_netdev_ops;
6688         ixgbe_set_ethtool_ops(netdev);
6689         netdev->watchdog_timeo = 5 * HZ;
6690         strcpy(netdev->name, pci_name(pdev));
6691
6692         adapter->bd_number = cards_found;
6693
6694         /* Setup hw api */
6695         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6696         hw->mac.type  = ii->mac;
6697
6698         /* EEPROM */
6699         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6700         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6701         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6702         if (!(eec & (1 << 8)))
6703                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6704
6705         /* PHY */
6706         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6707         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6708         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6709         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6710         hw->phy.mdio.mmds = 0;
6711         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6712         hw->phy.mdio.dev = netdev;
6713         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6714         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6715
6716         /* set up this timer and work struct before calling get_invariants
6717          * which might start the timer
6718          */
6719         init_timer(&adapter->sfp_timer);
6720         adapter->sfp_timer.function = &ixgbe_sfp_timer;
6721         adapter->sfp_timer.data = (unsigned long) adapter;
6722
6723         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6724
6725         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6726         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6727
6728         /* a new SFP+ module arrival, called from GPI SDP2 context */
6729         INIT_WORK(&adapter->sfp_config_module_task,
6730                   ixgbe_sfp_config_module_task);
6731
6732         ii->get_invariants(hw);
6733
6734         /* setup the private structure */
6735         err = ixgbe_sw_init(adapter);
6736         if (err)
6737                 goto err_sw_init;
6738
6739         /* Make it possible the adapter to be woken up via WOL */
6740         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6741                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6742
6743         /*
6744          * If there is a fan on this device and it has failed log the
6745          * failure.
6746          */
6747         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6748                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6749                 if (esdp & IXGBE_ESDP_SDP1)
6750                         e_crit(probe, "Fan has stopped, replace the adapter\n");
6751         }
6752
6753         /* reset_hw fills in the perm_addr as well */
6754         hw->phy.reset_if_overtemp = true;
6755         err = hw->mac.ops.reset_hw(hw);
6756         hw->phy.reset_if_overtemp = false;
6757         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6758             hw->mac.type == ixgbe_mac_82598EB) {
6759                 /*
6760                  * Start a kernel thread to watch for a module to arrive.
6761                  * Only do this for 82598, since 82599 will generate
6762                  * interrupts on module arrival.
6763                  */
6764                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6765                 mod_timer(&adapter->sfp_timer,
6766                           round_jiffies(jiffies + (2 * HZ)));
6767                 err = 0;
6768         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6769                 e_dev_err("failed to initialize because an unsupported SFP+ "
6770                           "module type was detected.\n");
6771                 e_dev_err("Reload the driver after installing a supported "
6772                           "module.\n");
6773                 goto err_sw_init;
6774         } else if (err) {
6775                 e_dev_err("HW Init failed: %d\n", err);
6776                 goto err_sw_init;
6777         }
6778
6779         ixgbe_probe_vf(adapter, ii);
6780
6781         netdev->features = NETIF_F_SG |
6782                            NETIF_F_IP_CSUM |
6783                            NETIF_F_HW_VLAN_TX |
6784                            NETIF_F_HW_VLAN_RX |
6785                            NETIF_F_HW_VLAN_FILTER;
6786
6787         netdev->features |= NETIF_F_IPV6_CSUM;
6788         netdev->features |= NETIF_F_TSO;
6789         netdev->features |= NETIF_F_TSO6;
6790         netdev->features |= NETIF_F_GRO;
6791
6792         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6793                 netdev->features |= NETIF_F_SCTP_CSUM;
6794
6795         netdev->vlan_features |= NETIF_F_TSO;
6796         netdev->vlan_features |= NETIF_F_TSO6;
6797         netdev->vlan_features |= NETIF_F_IP_CSUM;
6798         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6799         netdev->vlan_features |= NETIF_F_SG;
6800
6801         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6802                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6803                                     IXGBE_FLAG_DCB_ENABLED);
6804         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6805                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6806
6807 #ifdef CONFIG_IXGBE_DCB
6808         netdev->dcbnl_ops = &dcbnl_ops;
6809 #endif
6810
6811 #ifdef IXGBE_FCOE
6812         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6813                 if (hw->mac.ops.get_device_caps) {
6814                         hw->mac.ops.get_device_caps(hw, &device_caps);
6815                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6816                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6817                 }
6818         }
6819         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6820                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6821                 netdev->vlan_features |= NETIF_F_FSO;
6822                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6823         }
6824 #endif /* IXGBE_FCOE */
6825         if (pci_using_dac)
6826                 netdev->features |= NETIF_F_HIGHDMA;
6827
6828         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6829                 netdev->features |= NETIF_F_LRO;
6830
6831         /* make sure the EEPROM is good */
6832         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
6833                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
6834                 err = -EIO;
6835                 goto err_eeprom;
6836         }
6837
6838         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6839         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6840
6841         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6842                 e_dev_err("invalid MAC address\n");
6843                 err = -EIO;
6844                 goto err_eeprom;
6845         }
6846
6847         /* power down the optics */
6848         if (hw->phy.multispeed_fiber)
6849                 hw->mac.ops.disable_tx_laser(hw);
6850
6851         init_timer(&adapter->watchdog_timer);
6852         adapter->watchdog_timer.function = &ixgbe_watchdog;
6853         adapter->watchdog_timer.data = (unsigned long)adapter;
6854
6855         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
6856         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
6857
6858         err = ixgbe_init_interrupt_scheme(adapter);
6859         if (err)
6860                 goto err_sw_init;
6861
6862         switch (pdev->device) {
6863         case IXGBE_DEV_ID_82599_KX4:
6864                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6865                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
6866                 break;
6867         default:
6868                 adapter->wol = 0;
6869                 break;
6870         }
6871         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6872
6873         /* pick up the PCI bus settings for reporting later */
6874         hw->mac.ops.get_bus_info(hw);
6875
6876         /* print bus type/speed/width info */
6877         e_dev_info("(PCI Express:%s:%s) %pM\n",
6878                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6879                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6880                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6881                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6882                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
6883                  "Unknown"),
6884                 netdev->dev_addr);
6885         ixgbe_read_pba_num_generic(hw, &part_num);
6886         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6887                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
6888                            "PBA No: %06x-%03x\n",
6889                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6890                            (part_num >> 8), (part_num & 0xff));
6891         else
6892                 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6893                            hw->mac.type, hw->phy.type,
6894                            (part_num >> 8), (part_num & 0xff));
6895
6896         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
6897                 e_dev_warn("PCI-Express bandwidth available for this card is "
6898                            "not sufficient for optimal performance.\n");
6899                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
6900                            "is required.\n");
6901         }
6902
6903         /* save off EEPROM version number */
6904         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6905
6906         /* reset the hardware with the new settings */
6907         err = hw->mac.ops.start_hw(hw);
6908
6909         if (err == IXGBE_ERR_EEPROM_VERSION) {
6910                 /* We are running on a pre-production device, log a warning */
6911                 e_dev_warn("This device is a pre-production adapter/LOM. "
6912                            "Please be aware there may be issues associated "
6913                            "with your hardware.  If you are experiencing "
6914                            "problems please contact your Intel or hardware "
6915                            "representative who provided you with this "
6916                            "hardware.\n");
6917         }
6918         strcpy(netdev->name, "eth%d");
6919         err = register_netdev(netdev);
6920         if (err)
6921                 goto err_register;
6922
6923         /* carrier off reporting is important to ethtool even BEFORE open */
6924         netif_carrier_off(netdev);
6925
6926         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6927             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6928                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6929
6930         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
6931                 INIT_WORK(&adapter->check_overtemp_task, ixgbe_check_overtemp_task);
6932 #ifdef CONFIG_IXGBE_DCA
6933         if (dca_add_requester(&pdev->dev) == 0) {
6934                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
6935                 ixgbe_setup_dca(adapter);
6936         }
6937 #endif
6938         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6939                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
6940                 for (i = 0; i < adapter->num_vfs; i++)
6941                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
6942         }
6943
6944         /* add san mac addr to netdev */
6945         ixgbe_add_sanmac_netdev(netdev);
6946
6947         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
6948         cards_found++;
6949         return 0;
6950
6951 err_register:
6952         ixgbe_release_hw_control(adapter);
6953         ixgbe_clear_interrupt_scheme(adapter);
6954 err_sw_init:
6955 err_eeprom:
6956         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6957                 ixgbe_disable_sriov(adapter);
6958         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6959         del_timer_sync(&adapter->sfp_timer);
6960         cancel_work_sync(&adapter->sfp_task);
6961         cancel_work_sync(&adapter->multispeed_fiber_task);
6962         cancel_work_sync(&adapter->sfp_config_module_task);
6963         iounmap(hw->hw_addr);
6964 err_ioremap:
6965         free_netdev(netdev);
6966 err_alloc_etherdev:
6967         pci_release_selected_regions(pdev, pci_select_bars(pdev,
6968                                      IORESOURCE_MEM));
6969 err_pci_reg:
6970 err_dma:
6971         pci_disable_device(pdev);
6972         return err;
6973 }
6974
6975 /**
6976  * ixgbe_remove - Device Removal Routine
6977  * @pdev: PCI device information struct
6978  *
6979  * ixgbe_remove is called by the PCI subsystem to alert the driver
6980  * that it should release a PCI device.  The could be caused by a
6981  * Hot-Plug event, or because the driver is going to be removed from
6982  * memory.
6983  **/
6984 static void __devexit ixgbe_remove(struct pci_dev *pdev)
6985 {
6986         struct net_device *netdev = pci_get_drvdata(pdev);
6987         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6988
6989         set_bit(__IXGBE_DOWN, &adapter->state);
6990         /* clear the module not found bit to make sure the worker won't
6991          * reschedule
6992          */
6993         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6994         del_timer_sync(&adapter->watchdog_timer);
6995
6996         del_timer_sync(&adapter->sfp_timer);
6997         cancel_work_sync(&adapter->watchdog_task);
6998         cancel_work_sync(&adapter->sfp_task);
6999         cancel_work_sync(&adapter->multispeed_fiber_task);
7000         cancel_work_sync(&adapter->sfp_config_module_task);
7001         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7002             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7003                 cancel_work_sync(&adapter->fdir_reinit_task);
7004         flush_scheduled_work();
7005
7006 #ifdef CONFIG_IXGBE_DCA
7007         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7008                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7009                 dca_remove_requester(&pdev->dev);
7010                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7011         }
7012
7013 #endif
7014 #ifdef IXGBE_FCOE
7015         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7016                 ixgbe_cleanup_fcoe(adapter);
7017
7018 #endif /* IXGBE_FCOE */
7019
7020         /* remove the added san mac */
7021         ixgbe_del_sanmac_netdev(netdev);
7022
7023         if (netdev->reg_state == NETREG_REGISTERED)
7024                 unregister_netdev(netdev);
7025
7026         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7027                 ixgbe_disable_sriov(adapter);
7028
7029         ixgbe_clear_interrupt_scheme(adapter);
7030
7031         ixgbe_release_hw_control(adapter);
7032
7033         iounmap(adapter->hw.hw_addr);
7034         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7035                                      IORESOURCE_MEM));
7036
7037         e_dev_info("complete\n");
7038
7039         free_netdev(netdev);
7040
7041         pci_disable_pcie_error_reporting(pdev);
7042
7043         pci_disable_device(pdev);
7044 }
7045
7046 /**
7047  * ixgbe_io_error_detected - called when PCI error is detected
7048  * @pdev: Pointer to PCI device
7049  * @state: The current pci connection state
7050  *
7051  * This function is called after a PCI bus error affecting
7052  * this device has been detected.
7053  */
7054 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7055                                                 pci_channel_state_t state)
7056 {
7057         struct net_device *netdev = pci_get_drvdata(pdev);
7058         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7059
7060         netif_device_detach(netdev);
7061
7062         if (state == pci_channel_io_perm_failure)
7063                 return PCI_ERS_RESULT_DISCONNECT;
7064
7065         if (netif_running(netdev))
7066                 ixgbe_down(adapter);
7067         pci_disable_device(pdev);
7068
7069         /* Request a slot reset. */
7070         return PCI_ERS_RESULT_NEED_RESET;
7071 }
7072
7073 /**
7074  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7075  * @pdev: Pointer to PCI device
7076  *
7077  * Restart the card from scratch, as if from a cold-boot.
7078  */
7079 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7080 {
7081         struct net_device *netdev = pci_get_drvdata(pdev);
7082         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7083         pci_ers_result_t result;
7084         int err;
7085
7086         if (pci_enable_device_mem(pdev)) {
7087                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7088                 result = PCI_ERS_RESULT_DISCONNECT;
7089         } else {
7090                 pci_set_master(pdev);
7091                 pci_restore_state(pdev);
7092                 pci_save_state(pdev);
7093
7094                 pci_wake_from_d3(pdev, false);
7095
7096                 ixgbe_reset(adapter);
7097                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7098                 result = PCI_ERS_RESULT_RECOVERED;
7099         }
7100
7101         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7102         if (err) {
7103                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7104                           "failed 0x%0x\n", err);
7105                 /* non-fatal, continue */
7106         }
7107
7108         return result;
7109 }
7110
7111 /**
7112  * ixgbe_io_resume - called when traffic can start flowing again.
7113  * @pdev: Pointer to PCI device
7114  *
7115  * This callback is called when the error recovery driver tells us that
7116  * its OK to resume normal operation.
7117  */
7118 static void ixgbe_io_resume(struct pci_dev *pdev)
7119 {
7120         struct net_device *netdev = pci_get_drvdata(pdev);
7121         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7122
7123         if (netif_running(netdev)) {
7124                 if (ixgbe_up(adapter)) {
7125                         e_info(probe, "ixgbe_up failed after reset\n");
7126                         return;
7127                 }
7128         }
7129
7130         netif_device_attach(netdev);
7131 }
7132
7133 static struct pci_error_handlers ixgbe_err_handler = {
7134         .error_detected = ixgbe_io_error_detected,
7135         .slot_reset = ixgbe_io_slot_reset,
7136         .resume = ixgbe_io_resume,
7137 };
7138
7139 static struct pci_driver ixgbe_driver = {
7140         .name     = ixgbe_driver_name,
7141         .id_table = ixgbe_pci_tbl,
7142         .probe    = ixgbe_probe,
7143         .remove   = __devexit_p(ixgbe_remove),
7144 #ifdef CONFIG_PM
7145         .suspend  = ixgbe_suspend,
7146         .resume   = ixgbe_resume,
7147 #endif
7148         .shutdown = ixgbe_shutdown,
7149         .err_handler = &ixgbe_err_handler
7150 };
7151
7152 /**
7153  * ixgbe_init_module - Driver Registration Routine
7154  *
7155  * ixgbe_init_module is the first routine called when the driver is
7156  * loaded. All it does is register with the PCI subsystem.
7157  **/
7158 static int __init ixgbe_init_module(void)
7159 {
7160         int ret;
7161         pr_info("%s - version %s\n", ixgbe_driver_string,
7162                    ixgbe_driver_version);
7163         pr_info("%s\n", ixgbe_copyright);
7164
7165 #ifdef CONFIG_IXGBE_DCA
7166         dca_register_notify(&dca_notifier);
7167 #endif
7168
7169         ret = pci_register_driver(&ixgbe_driver);
7170         return ret;
7171 }
7172
7173 module_init(ixgbe_init_module);
7174
7175 /**
7176  * ixgbe_exit_module - Driver Exit Cleanup Routine
7177  *
7178  * ixgbe_exit_module is called just before the driver is removed
7179  * from memory.
7180  **/
7181 static void __exit ixgbe_exit_module(void)
7182 {
7183 #ifdef CONFIG_IXGBE_DCA
7184         dca_unregister_notify(&dca_notifier);
7185 #endif
7186         pci_unregister_driver(&ixgbe_driver);
7187 }
7188
7189 #ifdef CONFIG_IXGBE_DCA
7190 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7191                             void *p)
7192 {
7193         int ret_val;
7194
7195         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7196                                          __ixgbe_notify_dca);
7197
7198         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7199 }
7200
7201 #endif /* CONFIG_IXGBE_DCA */
7202
7203 /**
7204  * ixgbe_get_hw_dev return device
7205  * used by hardware layer to print debugging information
7206  **/
7207 struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7208 {
7209         struct ixgbe_adapter *adapter = hw->back;
7210         return adapter->netdev;
7211 }
7212
7213 module_exit(ixgbe_exit_module);
7214
7215 /* ixgbe_main.c */