drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <linux/slab.h>
  40 #include <net/checksum.h>
  41 #include <net/ip6_checksum.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/if_vlan.h>
  44 #include <scsi/fc/fc_fcoe.h>
  45
  46 #include "ixgbe.h"
  47 #include "ixgbe_common.h"
  48 #include "ixgbe_dcb_82599.h"
  49 #include "ixgbe_sriov.h"
  50
  51 char ixgbe_driver_name[] = "ixgbe";
  52 static const char ixgbe_driver_string[] =
  53                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  54
  55 #define DRV_VERSION "2.0.84-k2"
  56 const char ixgbe_driver_version[] = DRV_VERSION;
  57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
  58
  59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  60         [board_82598] = &ixgbe_82598_info,
  61         [board_82599] = &ixgbe_82599_info,
  62 };
  63
  64 /* ixgbe_pci_tbl - PCI Device ID Table
  65  *
  66  * Wildcard entries (PCI_ANY_ID) should come last
  67  * Last entry must be all 0s
  68  *
  69  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  70  *   Class, Class Mask, private data (not used) }
  71  */
  72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  96          board_82598 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 110          board_82599 },
 111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 112          board_82599 },
 113         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 114          board_82599 },
 115
 116         /* required last entry */
 117         {0, }
 118 };
 119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 120
 121 #ifdef CONFIG_IXGBE_DCA
 122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 123                             void *p);
 124 static struct notifier_block dca_notifier = {
 125         .notifier_call = ixgbe_notify_dca,
 126         .next          = NULL,
 127         .priority      = 0
 128 };
 129 #endif
 130
 131 #ifdef CONFIG_PCI_IOV
 132 static unsigned int max_vfs;
 133 module_param(max_vfs, uint, 0);
 134 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
 135                  "per physical function");
 136 #endif /* CONFIG_PCI_IOV */
 137
 138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 140 MODULE_LICENSE("GPL");
 141 MODULE_VERSION(DRV_VERSION);
 142
 143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 144
 145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 146 {
 147         struct ixgbe_hw *hw = &adapter->hw;
 148         u32 gcr;
 149         u32 gpie;
 150         u32 vmdctl;
 151
 152 #ifdef CONFIG_PCI_IOV
 153         /* disable iov and allow time for transactions to clear */
 154         pci_disable_sriov(adapter->pdev);
 155 #endif
 156
 157         /* turn off device IOV mode */
 158         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 159         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 160         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 161         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 162         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 163         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 164
 165         /* set default pool back to 0 */
 166         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 167         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 168         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 169
 170         /* take a breather then clean up driver data */
 171         msleep(100);
 172         if (adapter->vfinfo)
 173                 kfree(adapter->vfinfo);
 174         adapter->vfinfo = NULL;
 175
 176         adapter->num_vfs = 0;
 177         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 178 }
 179
 180 struct ixgbe_reg_info {
 181         u32 ofs;
 182         char *name;
 183 };
 184
 185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 186
 187         /* General Registers */
 188         {IXGBE_CTRL, "CTRL"},
 189         {IXGBE_STATUS, "STATUS"},
 190         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 191
 192         /* Interrupt Registers */
 193         {IXGBE_EICR, "EICR"},
 194
 195         /* RX Registers */
 196         {IXGBE_SRRCTL(0), "SRRCTL"},
 197         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 198         {IXGBE_RDLEN(0), "RDLEN"},
 199         {IXGBE_RDH(0), "RDH"},
 200         {IXGBE_RDT(0), "RDT"},
 201         {IXGBE_RXDCTL(0), "RXDCTL"},
 202         {IXGBE_RDBAL(0), "RDBAL"},
 203         {IXGBE_RDBAH(0), "RDBAH"},
 204
 205         /* TX Registers */
 206         {IXGBE_TDBAL(0), "TDBAL"},
 207         {IXGBE_TDBAH(0), "TDBAH"},
 208         {IXGBE_TDLEN(0), "TDLEN"},
 209         {IXGBE_TDH(0), "TDH"},
 210         {IXGBE_TDT(0), "TDT"},
 211         {IXGBE_TXDCTL(0), "TXDCTL"},
 212
 213         /* List Terminator */
 214         {}
 215 };
 216
 217
 218 /*
 219  * ixgbe_regdump - register printout routine
 220  */
 221 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 222 {
 223         int i = 0, j = 0;
 224         char rname[16];
 225         u32 regs[64];
 226
 227         switch (reginfo->ofs) {
 228         case IXGBE_SRRCTL(0):
 229                 for (i = 0; i < 64; i++)
 230                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 231                 break;
 232         case IXGBE_DCA_RXCTRL(0):
 233                 for (i = 0; i < 64; i++)
 234                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 235                 break;
 236         case IXGBE_RDLEN(0):
 237                 for (i = 0; i < 64; i++)
 238                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 239                 break;
 240         case IXGBE_RDH(0):
 241                 for (i = 0; i < 64; i++)
 242                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 243                 break;
 244         case IXGBE_RDT(0):
 245                 for (i = 0; i < 64; i++)
 246                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 247                 break;
 248         case IXGBE_RXDCTL(0):
 249                 for (i = 0; i < 64; i++)
 250                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 251                 break;
 252         case IXGBE_RDBAL(0):
 253                 for (i = 0; i < 64; i++)
 254                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 255                 break;
 256         case IXGBE_RDBAH(0):
 257                 for (i = 0; i < 64; i++)
 258                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 259                 break;
 260         case IXGBE_TDBAL(0):
 261                 for (i = 0; i < 64; i++)
 262                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 263                 break;
 264         case IXGBE_TDBAH(0):
 265                 for (i = 0; i < 64; i++)
 266                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 267                 break;
 268         case IXGBE_TDLEN(0):
 269                 for (i = 0; i < 64; i++)
 270                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 271                 break;
 272         case IXGBE_TDH(0):
 273                 for (i = 0; i < 64; i++)
 274                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 275                 break;
 276         case IXGBE_TDT(0):
 277                 for (i = 0; i < 64; i++)
 278                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 279                 break;
 280         case IXGBE_TXDCTL(0):
 281                 for (i = 0; i < 64; i++)
 282                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 283                 break;
 284         default:
 285                 printk(KERN_INFO "%-15s %08x\n", reginfo->name,
 286                         IXGBE_READ_REG(hw, reginfo->ofs));
 287                 return;
 288         }
 289
 290         for (i = 0; i < 8; i++) {
 291                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 292                 printk(KERN_ERR "%-15s ", rname);
 293                 for (j = 0; j < 8; j++)
 294                         printk(KERN_CONT "%08x ", regs[i*8+j]);
 295                 printk(KERN_CONT "\n");
 296         }
 297
 298 }
 299
 300 /*
 301  * ixgbe_dump - Print registers, tx-rings and rx-rings
 302  */
 303 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 304 {
 305         struct net_device *netdev = adapter->netdev;
 306         struct ixgbe_hw *hw = &adapter->hw;
 307         struct ixgbe_reg_info *reginfo;
 308         int n = 0;
 309         struct ixgbe_ring *tx_ring;
 310         struct ixgbe_tx_buffer *tx_buffer_info;
 311         union ixgbe_adv_tx_desc *tx_desc;
 312         struct my_u0 { u64 a; u64 b; } *u0;
 313         struct ixgbe_ring *rx_ring;
 314         union ixgbe_adv_rx_desc *rx_desc;
 315         struct ixgbe_rx_buffer *rx_buffer_info;
 316         u32 staterr;
 317         int i = 0;
 318
 319         if (!netif_msg_hw(adapter))
 320                 return;
 321
 322         /* Print netdevice Info */
 323         if (netdev) {
 324                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 325                 printk(KERN_INFO "Device Name     state            "
 326                         "trans_start      last_rx\n");
 327                 printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
 328                 netdev->name,
 329                 netdev->state,
 330                 netdev->trans_start,
 331                 netdev->last_rx);
 332         }
 333
 334         /* Print Registers */
 335         dev_info(&adapter->pdev->dev, "Register Dump\n");
 336         printk(KERN_INFO " Register Name   Value\n");
 337         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 338              reginfo->name; reginfo++) {
 339                 ixgbe_regdump(hw, reginfo);
 340         }
 341
 342         /* Print TX Ring Summary */
 343         if (!netdev || !netif_running(netdev))
 344                 goto exit;
 345
 346         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 347         printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma  ] "
 348                 "leng ntw timestamp\n");
 349         for (n = 0; n < adapter->num_tx_queues; n++) {
 350                 tx_ring = adapter->tx_ring[n];
 351                 tx_buffer_info =
 352                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 353                 printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n",
 354                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 355                            (u64)tx_buffer_info->dma,
 356                            tx_buffer_info->length,
 357                            tx_buffer_info->next_to_watch,
 358                            (u64)tx_buffer_info->time_stamp);
 359         }
 360
 361         /* Print TX Rings */
 362         if (!netif_msg_tx_done(adapter))
 363                 goto rx_ring_summary;
 364
 365         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 366
 367         /* Transmit Descriptor Formats
 368          *
 369          * Advanced Transmit Descriptor
 370          *   +--------------------------------------------------------------+
 371          * 0 |         Buffer Address [63:0]                                |
 372          *   +--------------------------------------------------------------+
 373          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 374          *   +--------------------------------------------------------------+
 375          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 376          */
 377
 378         for (n = 0; n < adapter->num_tx_queues; n++) {
 379                 tx_ring = adapter->tx_ring[n];
 380                 printk(KERN_INFO "------------------------------------\n");
 381                 printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 382                 printk(KERN_INFO "------------------------------------\n");
 383                 printk(KERN_INFO "T [desc]     [address 63:0  ] "
 384                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 385                         "leng  ntw timestamp        bi->skb\n");
 386
 387                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 388                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 389                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 390                         u0 = (struct my_u0 *)tx_desc;
 391                         printk(KERN_INFO "T [0x%03X]    %016llX %016llX %016llX"
 392                                 " %04X  %3X %016llX %p", i,
 393                                 le64_to_cpu(u0->a),
 394                                 le64_to_cpu(u0->b),
 395                                 (u64)tx_buffer_info->dma,
 396                                 tx_buffer_info->length,
 397                                 tx_buffer_info->next_to_watch,
 398                                 (u64)tx_buffer_info->time_stamp,
 399                                 tx_buffer_info->skb);
 400                         if (i == tx_ring->next_to_use &&
 401                                 i == tx_ring->next_to_clean)
 402                                 printk(KERN_CONT " NTC/U\n");
 403                         else if (i == tx_ring->next_to_use)
 404                                 printk(KERN_CONT " NTU\n");
 405                         else if (i == tx_ring->next_to_clean)
 406                                 printk(KERN_CONT " NTC\n");
 407                         else
 408                                 printk(KERN_CONT "\n");
 409
 410                         if (netif_msg_pktdata(adapter) &&
 411                                 tx_buffer_info->dma != 0)
 412                                 print_hex_dump(KERN_INFO, "",
 413                                         DUMP_PREFIX_ADDRESS, 16, 1,
 414                                         phys_to_virt(tx_buffer_info->dma),
 415                                         tx_buffer_info->length, true);
 416                 }
 417         }
 418
 419         /* Print RX Rings Summary */
 420 rx_ring_summary:
 421         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 422         printk(KERN_INFO "Queue [NTU] [NTC]\n");
 423         for (n = 0; n < adapter->num_rx_queues; n++) {
 424                 rx_ring = adapter->rx_ring[n];
 425                 printk(KERN_INFO "%5d %5X %5X\n", n,
 426                            rx_ring->next_to_use, rx_ring->next_to_clean);
 427         }
 428
 429         /* Print RX Rings */
 430         if (!netif_msg_rx_status(adapter))
 431                 goto exit;
 432
 433         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 434
 435         /* Advanced Receive Descriptor (Read) Format
 436          *    63                                           1        0
 437          *    +-----------------------------------------------------+
 438          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 439          *    +----------------------------------------------+------+
 440          *  8 |       Header Buffer Address [63:1]           |  DD  |
 441          *    +-----------------------------------------------------+
 442          *
 443          *
 444          * Advanced Receive Descriptor (Write-Back) Format
 445          *
 446          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 447          *   +------------------------------------------------------+
 448          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 449          *   | Checksum   Ident  |   |           |    | Type | Type |
 450          *   +------------------------------------------------------+
 451          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 452          *   +------------------------------------------------------+
 453          *   63       48 47    32 31            20 19               0
 454          */
 455         for (n = 0; n < adapter->num_rx_queues; n++) {
 456                 rx_ring = adapter->rx_ring[n];
 457                 printk(KERN_INFO "------------------------------------\n");
 458                 printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 459                 printk(KERN_INFO "------------------------------------\n");
 460                 printk(KERN_INFO "R  [desc]      [ PktBuf     A0] "
 461                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 462                         "<-- Adv Rx Read format\n");
 463                 printk(KERN_INFO "RWB[desc]      [PcsmIpSHl PtRs] "
 464                         "[vl er S cks ln] ---------------- [bi->skb] "
 465                         "<-- Adv Rx Write-Back format\n");
 466
 467                 for (i = 0; i < rx_ring->count; i++) {
 468                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 469                         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 470                         u0 = (struct my_u0 *)rx_desc;
 471                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 472                         if (staterr & IXGBE_RXD_STAT_DD) {
 473                                 /* Descriptor Done */
 474                                 printk(KERN_INFO "RWB[0x%03X]     %016llX "
 475                                         "%016llX ---------------- %p", i,
 476                                         le64_to_cpu(u0->a),
 477                                         le64_to_cpu(u0->b),
 478                                         rx_buffer_info->skb);
 479                         } else {
 480                                 printk(KERN_INFO "R  [0x%03X]     %016llX "
 481                                         "%016llX %016llX %p", i,
 482                                         le64_to_cpu(u0->a),
 483                                         le64_to_cpu(u0->b),
 484                                         (u64)rx_buffer_info->dma,
 485                                         rx_buffer_info->skb);
 486
 487                                 if (netif_msg_pktdata(adapter)) {
 488                                         print_hex_dump(KERN_INFO, "",
 489                                            DUMP_PREFIX_ADDRESS, 16, 1,
 490                                            phys_to_virt(rx_buffer_info->dma),
 491                                            rx_ring->rx_buf_len, true);
 492
 493                                         if (rx_ring->rx_buf_len
 494                                                 < IXGBE_RXBUFFER_2048)
 495                                                 print_hex_dump(KERN_INFO, "",
 496                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 497                                                   phys_to_virt(
 498                                                     rx_buffer_info->page_dma +
 499                                                     rx_buffer_info->page_offset
 500                                                   ),
 501                                                   PAGE_SIZE/2, true);
 502                                 }
 503                         }
 504
 505                         if (i == rx_ring->next_to_use)
 506                                 printk(KERN_CONT " NTU\n");
 507                         else if (i == rx_ring->next_to_clean)
 508                                 printk(KERN_CONT " NTC\n");
 509                         else
 510                                 printk(KERN_CONT "\n");
 511
 512                 }
 513         }
 514
 515 exit:
 516         return;
 517 }
 518
 519 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 520 {
 521         u32 ctrl_ext;
 522
 523         /* Let firmware take over control of h/w */
 524         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 525         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 526                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 527 }
 528
 529 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 530 {
 531         u32 ctrl_ext;
 532
 533         /* Let firmware know the driver has taken over */
 534         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 535         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 536                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 537 }
 538
 539 /*
 540  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 541  * @adapter: pointer to adapter struct
 542  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 543  * @queue: queue to map the corresponding interrupt to
 544  * @msix_vector: the vector to map to the corresponding queue
 545  *
 546  */
 547 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 548                            u8 queue, u8 msix_vector)
 549 {
 550         u32 ivar, index;
 551         struct ixgbe_hw *hw = &adapter->hw;
 552         switch (hw->mac.type) {
 553         case ixgbe_mac_82598EB:
 554                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 555                 if (direction == -1)
 556                         direction = 0;
 557                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 558                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 559                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 560                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 561                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 562                 break;
 563         case ixgbe_mac_82599EB:
 564                 if (direction == -1) {
 565                         /* other causes */
 566                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 567                         index = ((queue & 1) * 8);
 568                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 569                         ivar &= ~(0xFF << index);
 570                         ivar |= (msix_vector << index);
 571                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 572                         break;
 573                 } else {
 574                         /* tx or rx causes */
 575                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 576                         index = ((16 * (queue & 1)) + (8 * direction));
 577                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 578                         ivar &= ~(0xFF << index);
 579                         ivar |= (msix_vector << index);
 580                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 581                         break;
 582                 }
 583         default:
 584                 break;
 585         }
 586 }
 587
 588 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 589                                           u64 qmask)
 590 {
 591         u32 mask;
 592
 593         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 594                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 595                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 596         } else {
 597                 mask = (qmask & 0xFFFFFFFF);
 598                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 599                 mask = (qmask >> 32);
 600                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 601         }
 602 }
 603
 604 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 605                                              struct ixgbe_tx_buffer
 606                                              *tx_buffer_info)
 607 {
 608         if (tx_buffer_info->dma) {
 609                 if (tx_buffer_info->mapped_as_page)
 610                         dma_unmap_page(&adapter->pdev->dev,
 611                                        tx_buffer_info->dma,
 612                                        tx_buffer_info->length,
 613                                        DMA_TO_DEVICE);
 614                 else
 615                         dma_unmap_single(&adapter->pdev->dev,
 616                                          tx_buffer_info->dma,
 617                                          tx_buffer_info->length,
 618                                          DMA_TO_DEVICE);
 619                 tx_buffer_info->dma = 0;
 620         }
 621         if (tx_buffer_info->skb) {
 622                 dev_kfree_skb_any(tx_buffer_info->skb);
 623                 tx_buffer_info->skb = NULL;
 624         }
 625         tx_buffer_info->time_stamp = 0;
 626         /* tx_buffer_info must be completely set up in the transmit path */
 627 }
 628
 629 /**
 630  * ixgbe_tx_xon_state - check the tx ring xon state
 631  * @adapter: the ixgbe adapter
 632  * @tx_ring: the corresponding tx_ring
 633  *
 634  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 635  * corresponding TC of this tx_ring when checking TFCS.
 636  *
 637  * Returns : true if in xon state (currently not paused)
 638  */
 639 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
 640                                       struct ixgbe_ring *tx_ring)
 641 {
 642         u32 txoff = IXGBE_TFCS_TXOFF;
 643
 644 #ifdef CONFIG_IXGBE_DCB
 645         if (adapter->dcb_cfg.pfc_mode_enable) {
 646                 int tc;
 647                 int reg_idx = tx_ring->reg_idx;
 648                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 649
 650                 switch (adapter->hw.mac.type) {
 651                 case ixgbe_mac_82598EB:
 652                         tc = reg_idx >> 2;
 653                         txoff = IXGBE_TFCS_TXOFF0;
 654                         break;
 655                 case ixgbe_mac_82599EB:
 656                         tc = 0;
 657                         txoff = IXGBE_TFCS_TXOFF;
 658                         if (dcb_i == 8) {
 659                                 /* TC0, TC1 */
 660                                 tc = reg_idx >> 5;
 661                                 if (tc == 2) /* TC2, TC3 */
 662                                         tc += (reg_idx - 64) >> 4;
 663                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 664                                         tc += 1 + ((reg_idx - 96) >> 3);
 665                         } else if (dcb_i == 4) {
 666                                 /* TC0, TC1 */
 667                                 tc = reg_idx >> 6;
 668                                 if (tc == 1) {
 669                                         tc += (reg_idx - 64) >> 5;
 670                                         if (tc == 2) /* TC2, TC3 */
 671                                                 tc += (reg_idx - 96) >> 4;
 672                                 }
 673                         }
 674                         break;
 675                 default:
 676                         tc = 0;
 677                 }
 678                 txoff <<= tc;
 679         }
 680 #endif
 681         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 682 }
 683
 684 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 685                                        struct ixgbe_ring *tx_ring,
 686                                        unsigned int eop)
 687 {
 688         struct ixgbe_hw *hw = &adapter->hw;
 689
 690         /* Detect a transmit hang in hardware, this serializes the
 691          * check with the clearing of time_stamp and movement of eop */
 692         adapter->detect_tx_hung = false;
 693         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 694             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 695             ixgbe_tx_xon_state(adapter, tx_ring)) {
 696                 /* detected Tx unit hang */
 697                 union ixgbe_adv_tx_desc *tx_desc;
 698                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 699                 e_err(drv, "Detected Tx Unit Hang\n"
 700                       "  Tx Queue             <%d>\n"
 701                       "  TDH, TDT             <%x>, <%x>\n"
 702                       "  next_to_use          <%x>\n"
 703                       "  next_to_clean        <%x>\n"
 704                       "tx_buffer_info[next_to_clean]\n"
 705                       "  time_stamp           <%lx>\n"
 706                       "  jiffies              <%lx>\n",
 707                       tx_ring->queue_index,
 708                       IXGBE_READ_REG(hw, tx_ring->head),
 709                       IXGBE_READ_REG(hw, tx_ring->tail),
 710                       tx_ring->next_to_use, eop,
 711                       tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 712                 return true;
 713         }
 714
 715         return false;
 716 }
 717
 718 #define IXGBE_MAX_TXD_PWR       14
 719 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 720
 721 /* Tx Descriptors needed, worst case */
 722 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 723                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 724 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 725         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 726
 727 static void ixgbe_tx_timeout(struct net_device *netdev);
 728
 729 /**
 730  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 731  * @q_vector: structure containing interrupt and ring information
 732  * @tx_ring: tx ring to clean
 733  **/
 734 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 735                                struct ixgbe_ring *tx_ring)
 736 {
 737         struct ixgbe_adapter *adapter = q_vector->adapter;
 738         struct net_device *netdev = adapter->netdev;
 739         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 740         struct ixgbe_tx_buffer *tx_buffer_info;
 741         unsigned int i, eop, count = 0;
 742         unsigned int total_bytes = 0, total_packets = 0;
 743
 744         i = tx_ring->next_to_clean;
 745         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 746         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 747
 748         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 749                (count < tx_ring->work_limit)) {
 750                 bool cleaned = false;
 751                 rmb(); /* read buffer_info after eop_desc */
 752                 for ( ; !cleaned; count++) {
 753                         struct sk_buff *skb;
 754                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 755                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 756                         cleaned = (i == eop);
 757                         skb = tx_buffer_info->skb;
 758
 759                         if (cleaned && skb) {
 760                                 unsigned int segs, bytecount;
 761                                 unsigned int hlen = skb_headlen(skb);
 762
 763                                 /* gso_segs is currently only valid for tcp */
 764                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 765 #ifdef IXGBE_FCOE
 766                                 /* adjust for FCoE Sequence Offload */
 767                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 768                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 769                                     skb_is_gso(skb)) {
 770                                         hlen = skb_transport_offset(skb) +
 771                                                 sizeof(struct fc_frame_header) +
 772                                                 sizeof(struct fcoe_crc_eof);
 773                                         segs = DIV_ROUND_UP(skb->len - hlen,
 774                                                 skb_shinfo(skb)->gso_size);
 775                                 }
 776 #endif /* IXGBE_FCOE */
 777                                 /* multiply data chunks by size of headers */
 778                                 bytecount = ((segs - 1) * hlen) + skb->len;
 779                                 total_packets += segs;
 780                                 total_bytes += bytecount;
 781                         }
 782
 783                         ixgbe_unmap_and_free_tx_resource(adapter,
 784                                                          tx_buffer_info);
 785
 786                         tx_desc->wb.status = 0;
 787
 788                         i++;
 789                         if (i == tx_ring->count)
 790                                 i = 0;
 791                 }
 792
 793                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 794                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 795         }
 796
 797         tx_ring->next_to_clean = i;
 798
 799 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 800         if (unlikely(count && netif_carrier_ok(netdev) &&
 801                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 802                 /* Make sure that anybody stopping the queue after this
 803                  * sees the new next_to_clean.
 804                  */
 805                 smp_mb();
 806                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 807                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 808                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 809                         ++tx_ring->restart_queue;
 810                 }
 811         }
 812
 813         if (adapter->detect_tx_hung) {
 814                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 815                         /* schedule immediate reset if we believe we hung */
 816                         e_info(probe, "tx hang %d detected, resetting "
 817                                "adapter\n", adapter->tx_timeout_count + 1);
 818                         ixgbe_tx_timeout(adapter->netdev);
 819                 }
 820         }
 821
 822         /* re-arm the interrupt */
 823         if (count >= tx_ring->work_limit)
 824                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 825
 826         tx_ring->total_bytes += total_bytes;
 827         tx_ring->total_packets += total_packets;
 828         tx_ring->stats.packets += total_packets;
 829         tx_ring->stats.bytes += total_bytes;
 830         return (count < tx_ring->work_limit);
 831 }
 832
 833 #ifdef CONFIG_IXGBE_DCA
 834 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 835                                 struct ixgbe_ring *rx_ring)
 836 {
 837         u32 rxctrl;
 838         int cpu = get_cpu();
 839         int q = rx_ring->reg_idx;
 840
 841         if (rx_ring->cpu != cpu) {
 842                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 843                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 844                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 845                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 846                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 847                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 848                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 849                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 850                 }
 851                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 852                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 853                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 854                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 855                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 856                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 857                 rx_ring->cpu = cpu;
 858         }
 859         put_cpu();
 860 }
 861
 862 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 863                                 struct ixgbe_ring *tx_ring)
 864 {
 865         u32 txctrl;
 866         int cpu = get_cpu();
 867         int q = tx_ring->reg_idx;
 868         struct ixgbe_hw *hw = &adapter->hw;
 869
 870         if (tx_ring->cpu != cpu) {
 871                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 872                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
 873                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 874                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 875                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 876                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
 877                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 878                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
 879                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 880                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 881                                   IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 882                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 883                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
 884                 }
 885                 tx_ring->cpu = cpu;
 886         }
 887         put_cpu();
 888 }
 889
 890 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 891 {
 892         int i;
 893
 894         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 895                 return;
 896
 897         /* always use CB2 mode, difference is masked in the CB driver */
 898         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 899
 900         for (i = 0; i < adapter->num_tx_queues; i++) {
 901                 adapter->tx_ring[i]->cpu = -1;
 902                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
 903         }
 904         for (i = 0; i < adapter->num_rx_queues; i++) {
 905                 adapter->rx_ring[i]->cpu = -1;
 906                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
 907         }
 908 }
 909
 910 static int __ixgbe_notify_dca(struct device *dev, void *data)
 911 {
 912         struct net_device *netdev = dev_get_drvdata(dev);
 913         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 914         unsigned long event = *(unsigned long *)data;
 915
 916         switch (event) {
 917         case DCA_PROVIDER_ADD:
 918                 /* if we're already enabled, don't do it again */
 919                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 920                         break;
 921                 if (dca_add_requester(dev) == 0) {
 922                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 923                         ixgbe_setup_dca(adapter);
 924                         break;
 925                 }
 926                 /* Fall Through since DCA is disabled. */
 927         case DCA_PROVIDER_REMOVE:
 928                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 929                         dca_remove_requester(dev);
 930                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 931                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 932                 }
 933                 break;
 934         }
 935
 936         return 0;
 937 }
 938
 939 #endif /* CONFIG_IXGBE_DCA */
 940 /**
 941  * ixgbe_receive_skb - Send a completed packet up the stack
 942  * @adapter: board private structure
 943  * @skb: packet to send up
 944  * @status: hardware indication of status of receive
 945  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 946  * @rx_desc: rx descriptor
 947  **/
 948 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 949                               struct sk_buff *skb, u8 status,
 950                               struct ixgbe_ring *ring,
 951                               union ixgbe_adv_rx_desc *rx_desc)
 952 {
 953         struct ixgbe_adapter *adapter = q_vector->adapter;
 954         struct napi_struct *napi = &q_vector->napi;
 955         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 956         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 957
 958         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 959                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 960                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 961                 else
 962                         napi_gro_receive(napi, skb);
 963         } else {
 964                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 965                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 966                 else
 967                         netif_rx(skb);
 968         }
 969 }
 970
 971 /**
 972  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 973  * @adapter: address of board private structure
 974  * @status_err: hardware indication of status of receive
 975  * @skb: skb currently being received and modified
 976  **/
 977 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 978                                      union ixgbe_adv_rx_desc *rx_desc,
 979                                      struct sk_buff *skb)
 980 {
 981         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 982
 983         skb->ip_summed = CHECKSUM_NONE;
 984
 985         /* Rx csum disabled */
 986         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 987                 return;
 988
 989         /* if IP and error */
 990         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 991             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 992                 adapter->hw_csum_rx_error++;
 993                 return;
 994         }
 995
 996         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 997                 return;
 998
 999         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1000                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1001
1002                 /*
1003                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1004                  * checksum errors.
1005                  */
1006                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1007                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1008                         return;
1009
1010                 adapter->hw_csum_rx_error++;
1011                 return;
1012         }
1013
1014         /* It must be a TCP or UDP packet with a valid checksum */
1015         skb->ip_summed = CHECKSUM_UNNECESSARY;
1016 }
1017
1018 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
1019                                          struct ixgbe_ring *rx_ring, u32 val)
1020 {
1021         /*
1022          * Force memory writes to complete before letting h/w
1023          * know there are new descriptors to fetch.  (Only
1024          * applicable for weak-ordered memory model archs,
1025          * such as IA-64).
1026          */
1027         wmb();
1028         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1029 }
1030
1031 /**
1032  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1033  * @adapter: address of board private structure
1034  **/
1035 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
1036                                    struct ixgbe_ring *rx_ring,
1037                                    int cleaned_count)
1038 {
1039         struct net_device *netdev = adapter->netdev;
1040         struct pci_dev *pdev = adapter->pdev;
1041         union ixgbe_adv_rx_desc *rx_desc;
1042         struct ixgbe_rx_buffer *bi;
1043         unsigned int i;
1044         unsigned int bufsz = rx_ring->rx_buf_len;
1045
1046         i = rx_ring->next_to_use;
1047         bi = &rx_ring->rx_buffer_info[i];
1048
1049         while (cleaned_count--) {
1050                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1051
1052                 if (!bi->page_dma &&
1053                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
1054                         if (!bi->page) {
1055                                 bi->page = netdev_alloc_page(netdev);
1056                                 if (!bi->page) {
1057                                         adapter->alloc_rx_page_failed++;
1058                                         goto no_buffers;
1059                                 }
1060                                 bi->page_offset = 0;
1061                         } else {
1062                                 /* use a half page if we're re-using */
1063                                 bi->page_offset ^= (PAGE_SIZE / 2);
1064                         }
1065
1066                         bi->page_dma = dma_map_page(&pdev->dev, bi->page,
1067                                                     bi->page_offset,
1068                                                     (PAGE_SIZE / 2),
1069                                                     DMA_FROM_DEVICE);
1070                 }
1071
1072                 if (!bi->skb) {
1073                         struct sk_buff *skb = netdev_alloc_skb_ip_align(netdev,
1074                                                                         bufsz);
1075                         bi->skb = skb;
1076
1077                         if (!skb) {
1078                                 adapter->alloc_rx_buff_failed++;
1079                                 goto no_buffers;
1080                         }
1081                         /* initialize queue mapping */
1082                         skb_record_rx_queue(skb, rx_ring->queue_index);
1083                 }
1084
1085                 if (!bi->dma) {
1086                         bi->dma = dma_map_single(&pdev->dev,
1087                                                  bi->skb->data,
1088                                                  rx_ring->rx_buf_len,
1089                                                  DMA_FROM_DEVICE);
1090                 }
1091                 /* Refresh the desc even if buffer_addrs didn't change because
1092                  * each write-back erases this info. */
1093                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1094                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1095                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1096                 } else {
1097                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1098                 }
1099
1100                 i++;
1101                 if (i == rx_ring->count)
1102                         i = 0;
1103                 bi = &rx_ring->rx_buffer_info[i];
1104         }
1105
1106 no_buffers:
1107         if (rx_ring->next_to_use != i) {
1108                 rx_ring->next_to_use = i;
1109                 if (i-- == 0)
1110                         i = (rx_ring->count - 1);
1111
1112                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
1113         }
1114 }
1115
1116 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1117 {
1118         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1119 }
1120
1121 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1122 {
1123         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1124 }
1125
1126 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1127 {
1128         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1129                 IXGBE_RXDADV_RSCCNT_MASK) >>
1130                 IXGBE_RXDADV_RSCCNT_SHIFT;
1131 }
1132
1133 /**
1134  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1135  * @skb: pointer to the last skb in the rsc queue
1136  * @count: pointer to number of packets coalesced in this context
1137  *
1138  * This function changes a queue full of hw rsc buffers into a completed
1139  * packet.  It uses the ->prev pointers to find the first packet and then
1140  * turns it into the frag list owner.
1141  **/
1142 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1143                                                         u64 *count)
1144 {
1145         unsigned int frag_list_size = 0;
1146
1147         while (skb->prev) {
1148                 struct sk_buff *prev = skb->prev;
1149                 frag_list_size += skb->len;
1150                 skb->prev = NULL;
1151                 skb = prev;
1152                 *count += 1;
1153         }
1154
1155         skb_shinfo(skb)->frag_list = skb->next;
1156         skb->next = NULL;
1157         skb->len += frag_list_size;
1158         skb->data_len += frag_list_size;
1159         skb->truesize += frag_list_size;
1160         return skb;
1161 }
1162
1163 struct ixgbe_rsc_cb {
1164         dma_addr_t dma;
1165         bool delay_unmap;
1166 };
1167
1168 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1169
1170 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1171                                struct ixgbe_ring *rx_ring,
1172                                int *work_done, int work_to_do)
1173 {
1174         struct ixgbe_adapter *adapter = q_vector->adapter;
1175         struct net_device *netdev = adapter->netdev;
1176         struct pci_dev *pdev = adapter->pdev;
1177         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1178         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1179         struct sk_buff *skb;
1180         unsigned int i, rsc_count = 0;
1181         u32 len, staterr;
1182         u16 hdr_info;
1183         bool cleaned = false;
1184         int cleaned_count = 0;
1185         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1186 #ifdef IXGBE_FCOE
1187         int ddp_bytes = 0;
1188 #endif /* IXGBE_FCOE */
1189
1190         i = rx_ring->next_to_clean;
1191         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1192         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1193         rx_buffer_info = &rx_ring->rx_buffer_info[i];
1194
1195         while (staterr & IXGBE_RXD_STAT_DD) {
1196                 u32 upper_len = 0;
1197                 if (*work_done >= work_to_do)
1198                         break;
1199                 (*work_done)++;
1200
1201                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1202                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1203                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1204                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1205                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1206                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1207                         if ((len > IXGBE_RX_HDR_SIZE) ||
1208                             (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1209                                 len = IXGBE_RX_HDR_SIZE;
1210                 } else {
1211                         len = le16_to_cpu(rx_desc->wb.upper.length);
1212                 }
1213
1214                 cleaned = true;
1215                 skb = rx_buffer_info->skb;
1216                 prefetch(skb->data);
1217                 rx_buffer_info->skb = NULL;
1218
1219                 if (rx_buffer_info->dma) {
1220                         if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1221                             (!(staterr & IXGBE_RXD_STAT_EOP)) &&
1222                                  (!(skb->prev))) {
1223                                 /*
1224                                  * When HWRSC is enabled, delay unmapping
1225                                  * of the first packet. It carries the
1226                                  * header information, HW may still
1227                                  * access the header after the writeback.
1228                                  * Only unmap it when EOP is reached
1229                                  */
1230                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1231                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1232                         } else {
1233                                 dma_unmap_single(&pdev->dev,
1234                                                  rx_buffer_info->dma,
1235                                                  rx_ring->rx_buf_len,
1236                                                  DMA_FROM_DEVICE);
1237                         }
1238                         rx_buffer_info->dma = 0;
1239                         skb_put(skb, len);
1240                 }
1241
1242                 if (upper_len) {
1243                         dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1244                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
1245                         rx_buffer_info->page_dma = 0;
1246                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1247                                            rx_buffer_info->page,
1248                                            rx_buffer_info->page_offset,
1249                                            upper_len);
1250
1251                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1252                             (page_count(rx_buffer_info->page) != 1))
1253                                 rx_buffer_info->page = NULL;
1254                         else
1255                                 get_page(rx_buffer_info->page);
1256
1257                         skb->len += upper_len;
1258                         skb->data_len += upper_len;
1259                         skb->truesize += upper_len;
1260                 }
1261
1262                 i++;
1263                 if (i == rx_ring->count)
1264                         i = 0;
1265
1266                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
1267                 prefetch(next_rxd);
1268                 cleaned_count++;
1269
1270                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
1271                         rsc_count = ixgbe_get_rsc_count(rx_desc);
1272
1273                 if (rsc_count) {
1274                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1275                                      IXGBE_RXDADV_NEXTP_SHIFT;
1276                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1277                 } else {
1278                         next_buffer = &rx_ring->rx_buffer_info[i];
1279                 }
1280
1281                 if (staterr & IXGBE_RXD_STAT_EOP) {
1282                         if (skb->prev)
1283                                 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
1284                         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
1285                                 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1286                                         dma_unmap_single(&pdev->dev,
1287                                                          IXGBE_RSC_CB(skb)->dma,
1288                                                          rx_ring->rx_buf_len,
1289                                                          DMA_FROM_DEVICE);
1290                                         IXGBE_RSC_CB(skb)->dma = 0;
1291                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
1292                                 }
1293                                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
1294                                         rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
1295                                 else
1296                                         rx_ring->rsc_count++;
1297                                 rx_ring->rsc_flush++;
1298                         }
1299                         rx_ring->stats.packets++;
1300                         rx_ring->stats.bytes += skb->len;
1301                 } else {
1302                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1303                                 rx_buffer_info->skb = next_buffer->skb;
1304                                 rx_buffer_info->dma = next_buffer->dma;
1305                                 next_buffer->skb = skb;
1306                                 next_buffer->dma = 0;
1307                         } else {
1308                                 skb->next = next_buffer->skb;
1309                                 skb->next->prev = skb;
1310                         }
1311                         rx_ring->non_eop_descs++;
1312                         goto next_desc;
1313                 }
1314
1315                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1316                         dev_kfree_skb_irq(skb);
1317                         goto next_desc;
1318                 }
1319
1320                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1321
1322                 /* probably a little skewed due to removing CRC */
1323                 total_rx_bytes += skb->len;
1324                 total_rx_packets++;
1325
1326                 skb->protocol = eth_type_trans(skb, adapter->netdev);
1327 #ifdef IXGBE_FCOE
1328                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1329                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1330                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1331                         if (!ddp_bytes)
1332                                 goto next_desc;
1333                 }
1334 #endif /* IXGBE_FCOE */
1335                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1336
1337 next_desc:
1338                 rx_desc->wb.upper.status_error = 0;
1339
1340                 /* return some buffers to hardware, one at a time is too slow */
1341                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1342                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1343                         cleaned_count = 0;
1344                 }
1345
1346                 /* use prefetched values */
1347                 rx_desc = next_rxd;
1348                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1349
1350                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1351         }
1352
1353         rx_ring->next_to_clean = i;
1354         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1355
1356         if (cleaned_count)
1357                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1358
1359 #ifdef IXGBE_FCOE
1360         /* include DDPed FCoE data */
1361         if (ddp_bytes > 0) {
1362                 unsigned int mss;
1363
1364                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1365                         sizeof(struct fc_frame_header) -
1366                         sizeof(struct fcoe_crc_eof);
1367                 if (mss > 512)
1368                         mss &= ~511;
1369                 total_rx_bytes += ddp_bytes;
1370                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1371         }
1372 #endif /* IXGBE_FCOE */
1373
1374         rx_ring->total_packets += total_rx_packets;
1375         rx_ring->total_bytes += total_rx_bytes;
1376         netdev->stats.rx_bytes += total_rx_bytes;
1377         netdev->stats.rx_packets += total_rx_packets;
1378
1379         return cleaned;
1380 }
1381
1382 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1383 /**
1384  * ixgbe_configure_msix - Configure MSI-X hardware
1385  * @adapter: board private structure
1386  *
1387  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1388  * interrupts.
1389  **/
1390 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1391 {
1392         struct ixgbe_q_vector *q_vector;
1393         int i, j, q_vectors, v_idx, r_idx;
1394         u32 mask;
1395
1396         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1397
1398         /*
1399          * Populate the IVAR table and set the ITR values to the
1400          * corresponding register.
1401          */
1402         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1403                 q_vector = adapter->q_vector[v_idx];
1404                 /* XXX for_each_set_bit(...) */
1405                 r_idx = find_first_bit(q_vector->rxr_idx,
1406                                        adapter->num_rx_queues);
1407
1408                 for (i = 0; i < q_vector->rxr_count; i++) {
1409                         j = adapter->rx_ring[r_idx]->reg_idx;
1410                         ixgbe_set_ivar(adapter, 0, j, v_idx);
1411                         r_idx = find_next_bit(q_vector->rxr_idx,
1412                                               adapter->num_rx_queues,
1413                                               r_idx + 1);
1414                 }
1415                 r_idx = find_first_bit(q_vector->txr_idx,
1416                                        adapter->num_tx_queues);
1417
1418                 for (i = 0; i < q_vector->txr_count; i++) {
1419                         j = adapter->tx_ring[r_idx]->reg_idx;
1420                         ixgbe_set_ivar(adapter, 1, j, v_idx);
1421                         r_idx = find_next_bit(q_vector->txr_idx,
1422                                               adapter->num_tx_queues,
1423                                               r_idx + 1);
1424                 }
1425
1426                 if (q_vector->txr_count && !q_vector->rxr_count)
1427                         /* tx only */
1428                         q_vector->eitr = adapter->tx_eitr_param;
1429                 else if (q_vector->rxr_count)
1430                         /* rx or mixed */
1431                         q_vector->eitr = adapter->rx_eitr_param;
1432
1433                 ixgbe_write_eitr(q_vector);
1434         }
1435
1436         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1437                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1438                                v_idx);
1439         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1440                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1441         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1442
1443         /* set up to autoclear timer, and the vectors */
1444         mask = IXGBE_EIMS_ENABLE_MASK;
1445         if (adapter->num_vfs)
1446                 mask &= ~(IXGBE_EIMS_OTHER |
1447                           IXGBE_EIMS_MAILBOX |
1448                           IXGBE_EIMS_LSC);
1449         else
1450                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1451         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1452 }
1453
1454 enum latency_range {
1455         lowest_latency = 0,
1456         low_latency = 1,
1457         bulk_latency = 2,
1458         latency_invalid = 255
1459 };
1460
1461 /**
1462  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1463  * @adapter: pointer to adapter
1464  * @eitr: eitr setting (ints per sec) to give last timeslice
1465  * @itr_setting: current throttle rate in ints/second
1466  * @packets: the number of packets during this measurement interval
1467  * @bytes: the number of bytes during this measurement interval
1468  *
1469  *      Stores a new ITR value based on packets and byte
1470  *      counts during the last interrupt.  The advantage of per interrupt
1471  *      computation is faster updates and more accurate ITR for the current
1472  *      traffic pattern.  Constants in this function were computed
1473  *      based on theoretical maximum wire speed and thresholds were set based
1474  *      on testing data as well as attempting to minimize response time
1475  *      while increasing bulk throughput.
1476  *      this functionality is controlled by the InterruptThrottleRate module
1477  *      parameter (see ixgbe_param.c)
1478  **/
1479 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1480                            u32 eitr, u8 itr_setting,
1481                            int packets, int bytes)
1482 {
1483         unsigned int retval = itr_setting;
1484         u32 timepassed_us;
1485         u64 bytes_perint;
1486
1487         if (packets == 0)
1488                 goto update_itr_done;
1489
1490
1491         /* simple throttlerate management
1492          *    0-20MB/s lowest (100000 ints/s)
1493          *   20-100MB/s low   (20000 ints/s)
1494          *  100-1249MB/s bulk (8000 ints/s)
1495          */
1496         /* what was last interrupt timeslice? */
1497         timepassed_us = 1000000/eitr;
1498         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1499
1500         switch (itr_setting) {
1501         case lowest_latency:
1502                 if (bytes_perint > adapter->eitr_low)
1503                         retval = low_latency;
1504                 break;
1505         case low_latency:
1506                 if (bytes_perint > adapter->eitr_high)
1507                         retval = bulk_latency;
1508                 else if (bytes_perint <= adapter->eitr_low)
1509                         retval = lowest_latency;
1510                 break;
1511         case bulk_latency:
1512                 if (bytes_perint <= adapter->eitr_high)
1513                         retval = low_latency;
1514                 break;
1515         }
1516
1517 update_itr_done:
1518         return retval;
1519 }
1520
1521 /**
1522  * ixgbe_write_eitr - write EITR register in hardware specific way
1523  * @q_vector: structure containing interrupt and ring information
1524  *
1525  * This function is made to be called by ethtool and by the driver
1526  * when it needs to update EITR registers at runtime.  Hardware
1527  * specific quirks/differences are taken care of here.
1528  */
1529 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1530 {
1531         struct ixgbe_adapter *adapter = q_vector->adapter;
1532         struct ixgbe_hw *hw = &adapter->hw;
1533         int v_idx = q_vector->v_idx;
1534         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1535
1536         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1537                 /* must write high and low 16 bits to reset counter */
1538                 itr_reg |= (itr_reg << 16);
1539         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1540                 /*
1541                  * 82599 can support a value of zero, so allow it for
1542                  * max interrupt rate, but there is an errata where it can
1543                  * not be zero with RSC
1544                  */
1545                 if (itr_reg == 8 &&
1546                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1547                         itr_reg = 0;
1548
1549                 /*
1550                  * set the WDIS bit to not clear the timer bits and cause an
1551                  * immediate assertion of the interrupt
1552                  */
1553                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1554         }
1555         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1556 }
1557
1558 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1559 {
1560         struct ixgbe_adapter *adapter = q_vector->adapter;
1561         u32 new_itr;
1562         u8 current_itr, ret_itr;
1563         int i, r_idx;
1564         struct ixgbe_ring *rx_ring, *tx_ring;
1565
1566         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1567         for (i = 0; i < q_vector->txr_count; i++) {
1568                 tx_ring = adapter->tx_ring[r_idx];
1569                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1570                                            q_vector->tx_itr,
1571                                            tx_ring->total_packets,
1572                                            tx_ring->total_bytes);
1573                 /* if the result for this queue would decrease interrupt
1574                  * rate for this vector then use that result */
1575                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1576                                     q_vector->tx_itr - 1 : ret_itr);
1577                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1578                                       r_idx + 1);
1579         }
1580
1581         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1582         for (i = 0; i < q_vector->rxr_count; i++) {
1583                 rx_ring = adapter->rx_ring[r_idx];
1584                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1585                                            q_vector->rx_itr,
1586                                            rx_ring->total_packets,
1587                                            rx_ring->total_bytes);
1588                 /* if the result for this queue would decrease interrupt
1589                  * rate for this vector then use that result */
1590                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1591                                     q_vector->rx_itr - 1 : ret_itr);
1592                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1593                                       r_idx + 1);
1594         }
1595
1596         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1597
1598         switch (current_itr) {
1599         /* counts and packets in update_itr are dependent on these numbers */
1600         case lowest_latency:
1601                 new_itr = 100000;
1602                 break;
1603         case low_latency:
1604                 new_itr = 20000; /* aka hwitr = ~200 */
1605                 break;
1606         case bulk_latency:
1607         default:
1608                 new_itr = 8000;
1609                 break;
1610         }
1611
1612         if (new_itr != q_vector->eitr) {
1613                 /* do an exponential smoothing */
1614                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1615
1616                 /* save the algorithm value here, not the smoothed one */
1617                 q_vector->eitr = new_itr;
1618
1619                 ixgbe_write_eitr(q_vector);
1620         }
1621 }
1622
1623 /**
1624  * ixgbe_check_overtemp_task - worker thread to check over tempurature
1625  * @work: pointer to work_struct containing our data
1626  **/
1627 static void ixgbe_check_overtemp_task(struct work_struct *work)
1628 {
1629         struct ixgbe_adapter *adapter = container_of(work,
1630                                                      struct ixgbe_adapter,
1631                                                      check_overtemp_task);
1632         struct ixgbe_hw *hw = &adapter->hw;
1633         u32 eicr = adapter->interrupt_event;
1634
1635         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
1636                 switch (hw->device_id) {
1637                 case IXGBE_DEV_ID_82599_T3_LOM: {
1638                         u32 autoneg;
1639                         bool link_up = false;
1640
1641                         if (hw->mac.ops.check_link)
1642                                 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1643
1644                         if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1645                             (eicr & IXGBE_EICR_LSC))
1646                                 /* Check if this is due to overtemp */
1647                                 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1648                                         break;
1649                         }
1650                         return;
1651                 default:
1652                         if (!(eicr & IXGBE_EICR_GPI_SDP0))
1653                                 return;
1654                         break;
1655                 }
1656                 e_crit(drv, "Network adapter has been stopped because it has "
1657                        "over heated. Restart the computer. If the problem "
1658                        "persists, power off the system and replace the "
1659                        "adapter\n");
1660                 /* write to clear the interrupt */
1661                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1662         }
1663 }
1664
1665 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1666 {
1667         struct ixgbe_hw *hw = &adapter->hw;
1668
1669         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1670             (eicr & IXGBE_EICR_GPI_SDP1)) {
1671                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1672                 /* write to clear the interrupt */
1673                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1674         }
1675 }
1676
1677 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1678 {
1679         struct ixgbe_hw *hw = &adapter->hw;
1680
1681         if (eicr & IXGBE_EICR_GPI_SDP1) {
1682                 /* Clear the interrupt */
1683                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1684                 schedule_work(&adapter->multispeed_fiber_task);
1685         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1686                 /* Clear the interrupt */
1687                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1688                 schedule_work(&adapter->sfp_config_module_task);
1689         } else {
1690                 /* Interrupt isn't for us... */
1691                 return;
1692         }
1693 }
1694
1695 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1696 {
1697         struct ixgbe_hw *hw = &adapter->hw;
1698
1699         adapter->lsc_int++;
1700         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1701         adapter->link_check_timeout = jiffies;
1702         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1703                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1704                 IXGBE_WRITE_FLUSH(hw);
1705                 schedule_work(&adapter->watchdog_task);
1706         }
1707 }
1708
1709 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1710 {
1711         struct net_device *netdev = data;
1712         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1713         struct ixgbe_hw *hw = &adapter->hw;
1714         u32 eicr;
1715
1716         /*
1717          * Workaround for Silicon errata.  Use clear-by-write instead
1718          * of clear-by-read.  Reading with EICS will return the
1719          * interrupt causes without clearing, which later be done
1720          * with the write to EICR.
1721          */
1722         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1723         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1724
1725         if (eicr & IXGBE_EICR_LSC)
1726                 ixgbe_check_lsc(adapter);
1727
1728         if (eicr & IXGBE_EICR_MAILBOX)
1729                 ixgbe_msg_task(adapter);
1730
1731         if (hw->mac.type == ixgbe_mac_82598EB)
1732                 ixgbe_check_fan_failure(adapter, eicr);
1733
1734         if (hw->mac.type == ixgbe_mac_82599EB) {
1735                 ixgbe_check_sfp_event(adapter, eicr);
1736                 adapter->interrupt_event = eicr;
1737                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1738                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1739                         schedule_work(&adapter->check_overtemp_task);
1740
1741                 /* Handle Flow Director Full threshold interrupt */
1742                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1743                         int i;
1744                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1745                         /* Disable transmits before FDIR Re-initialization */
1746                         netif_tx_stop_all_queues(netdev);
1747                         for (i = 0; i < adapter->num_tx_queues; i++) {
1748                                 struct ixgbe_ring *tx_ring =
1749                                                             adapter->tx_ring[i];
1750                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1751                                                        &tx_ring->reinit_state))
1752                                         schedule_work(&adapter->fdir_reinit_task);
1753                         }
1754                 }
1755         }
1756         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1757                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1758
1759         return IRQ_HANDLED;
1760 }
1761
1762 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1763                                            u64 qmask)
1764 {
1765         u32 mask;
1766
1767         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1768                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1769                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1770         } else {
1771                 mask = (qmask & 0xFFFFFFFF);
1772                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1773                 mask = (qmask >> 32);
1774                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1775         }
1776         /* skip the flush */
1777 }
1778
1779 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1780                                             u64 qmask)
1781 {
1782         u32 mask;
1783
1784         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1785                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1786                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1787         } else {
1788                 mask = (qmask & 0xFFFFFFFF);
1789                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1790                 mask = (qmask >> 32);
1791                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1792         }
1793         /* skip the flush */
1794 }
1795
1796 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1797 {
1798         struct ixgbe_q_vector *q_vector = data;
1799         struct ixgbe_adapter  *adapter = q_vector->adapter;
1800         struct ixgbe_ring     *tx_ring;
1801         int i, r_idx;
1802
1803         if (!q_vector->txr_count)
1804                 return IRQ_HANDLED;
1805
1806         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1807         for (i = 0; i < q_vector->txr_count; i++) {
1808                 tx_ring = adapter->tx_ring[r_idx];
1809                 tx_ring->total_bytes = 0;
1810                 tx_ring->total_packets = 0;
1811                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1812                                       r_idx + 1);
1813         }
1814
1815         /* EIAM disabled interrupts (on this vector) for us */
1816         napi_schedule(&q_vector->napi);
1817
1818         return IRQ_HANDLED;
1819 }
1820
1821 /**
1822  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1823  * @irq: unused
1824  * @data: pointer to our q_vector struct for this interrupt vector
1825  **/
1826 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1827 {
1828         struct ixgbe_q_vector *q_vector = data;
1829         struct ixgbe_adapter  *adapter = q_vector->adapter;
1830         struct ixgbe_ring  *rx_ring;
1831         int r_idx;
1832         int i;
1833
1834         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1835         for (i = 0;  i < q_vector->rxr_count; i++) {
1836                 rx_ring = adapter->rx_ring[r_idx];
1837                 rx_ring->total_bytes = 0;
1838                 rx_ring->total_packets = 0;
1839                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1840                                       r_idx + 1);
1841         }
1842
1843         if (!q_vector->rxr_count)
1844                 return IRQ_HANDLED;
1845
1846         /* disable interrupts on this vector only */
1847         /* EIAM disabled interrupts (on this vector) for us */
1848         napi_schedule(&q_vector->napi);
1849
1850         return IRQ_HANDLED;
1851 }
1852
1853 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1854 {
1855         struct ixgbe_q_vector *q_vector = data;
1856         struct ixgbe_adapter  *adapter = q_vector->adapter;
1857         struct ixgbe_ring  *ring;
1858         int r_idx;
1859         int i;
1860
1861         if (!q_vector->txr_count && !q_vector->rxr_count)
1862                 return IRQ_HANDLED;
1863
1864         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1865         for (i = 0; i < q_vector->txr_count; i++) {
1866                 ring = adapter->tx_ring[r_idx];
1867                 ring->total_bytes = 0;
1868                 ring->total_packets = 0;
1869                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1870                                       r_idx + 1);
1871         }
1872
1873         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1874         for (i = 0; i < q_vector->rxr_count; i++) {
1875                 ring = adapter->rx_ring[r_idx];
1876                 ring->total_bytes = 0;
1877                 ring->total_packets = 0;
1878                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1879                                       r_idx + 1);
1880         }
1881
1882         /* EIAM disabled interrupts (on this vector) for us */
1883         napi_schedule(&q_vector->napi);
1884
1885         return IRQ_HANDLED;
1886 }
1887
1888 /**
1889  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1890  * @napi: napi struct with our devices info in it
1891  * @budget: amount of work driver is allowed to do this pass, in packets
1892  *
1893  * This function is optimized for cleaning one queue only on a single
1894  * q_vector!!!
1895  **/
1896 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1897 {
1898         struct ixgbe_q_vector *q_vector =
1899                                container_of(napi, struct ixgbe_q_vector, napi);
1900         struct ixgbe_adapter *adapter = q_vector->adapter;
1901         struct ixgbe_ring *rx_ring = NULL;
1902         int work_done = 0;
1903         long r_idx;
1904
1905         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1906         rx_ring = adapter->rx_ring[r_idx];
1907 #ifdef CONFIG_IXGBE_DCA
1908         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1909                 ixgbe_update_rx_dca(adapter, rx_ring);
1910 #endif
1911
1912         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1913
1914         /* If all Rx work done, exit the polling mode */
1915         if (work_done < budget) {
1916                 napi_complete(napi);
1917                 if (adapter->rx_itr_setting & 1)
1918                         ixgbe_set_itr_msix(q_vector);
1919                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1920                         ixgbe_irq_enable_queues(adapter,
1921                                                 ((u64)1 << q_vector->v_idx));
1922         }
1923
1924         return work_done;
1925 }
1926
1927 /**
1928  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1929  * @napi: napi struct with our devices info in it
1930  * @budget: amount of work driver is allowed to do this pass, in packets
1931  *
1932  * This function will clean more than one rx queue associated with a
1933  * q_vector.
1934  **/
1935 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1936 {
1937         struct ixgbe_q_vector *q_vector =
1938                                container_of(napi, struct ixgbe_q_vector, napi);
1939         struct ixgbe_adapter *adapter = q_vector->adapter;
1940         struct ixgbe_ring *ring = NULL;
1941         int work_done = 0, i;
1942         long r_idx;
1943         bool tx_clean_complete = true;
1944
1945         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1946         for (i = 0; i < q_vector->txr_count; i++) {
1947                 ring = adapter->tx_ring[r_idx];
1948 #ifdef CONFIG_IXGBE_DCA
1949                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1950                         ixgbe_update_tx_dca(adapter, ring);
1951 #endif
1952                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1953                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1954                                       r_idx + 1);
1955         }
1956
1957         /* attempt to distribute budget to each queue fairly, but don't allow
1958          * the budget to go below 1 because we'll exit polling */
1959         budget /= (q_vector->rxr_count ?: 1);
1960         budget = max(budget, 1);
1961         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1962         for (i = 0; i < q_vector->rxr_count; i++) {
1963                 ring = adapter->rx_ring[r_idx];
1964 #ifdef CONFIG_IXGBE_DCA
1965                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1966                         ixgbe_update_rx_dca(adapter, ring);
1967 #endif
1968                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1969                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1970                                       r_idx + 1);
1971         }
1972
1973         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1974         ring = adapter->rx_ring[r_idx];
1975         /* If all Rx work done, exit the polling mode */
1976         if (work_done < budget) {
1977                 napi_complete(napi);
1978                 if (adapter->rx_itr_setting & 1)
1979                         ixgbe_set_itr_msix(q_vector);
1980                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1981                         ixgbe_irq_enable_queues(adapter,
1982                                                 ((u64)1 << q_vector->v_idx));
1983                 return 0;
1984         }
1985
1986         return work_done;
1987 }
1988
1989 /**
1990  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1991  * @napi: napi struct with our devices info in it
1992  * @budget: amount of work driver is allowed to do this pass, in packets
1993  *
1994  * This function is optimized for cleaning one queue only on a single
1995  * q_vector!!!
1996  **/
1997 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1998 {
1999         struct ixgbe_q_vector *q_vector =
2000                                container_of(napi, struct ixgbe_q_vector, napi);
2001         struct ixgbe_adapter *adapter = q_vector->adapter;
2002         struct ixgbe_ring *tx_ring = NULL;
2003         int work_done = 0;
2004         long r_idx;
2005
2006         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2007         tx_ring = adapter->tx_ring[r_idx];
2008 #ifdef CONFIG_IXGBE_DCA
2009         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2010                 ixgbe_update_tx_dca(adapter, tx_ring);
2011 #endif
2012
2013         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2014                 work_done = budget;
2015
2016         /* If all Tx work done, exit the polling mode */
2017         if (work_done < budget) {
2018                 napi_complete(napi);
2019                 if (adapter->tx_itr_setting & 1)
2020                         ixgbe_set_itr_msix(q_vector);
2021                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2022                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2023         }
2024
2025         return work_done;
2026 }
2027
2028 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2029                                      int r_idx)
2030 {
2031         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2032
2033         set_bit(r_idx, q_vector->rxr_idx);
2034         q_vector->rxr_count++;
2035 }
2036
2037 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2038                                      int t_idx)
2039 {
2040         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2041
2042         set_bit(t_idx, q_vector->txr_idx);
2043         q_vector->txr_count++;
2044 }
2045
2046 /**
2047  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2048  * @adapter: board private structure to initialize
2049  * @vectors: allotted vector count for descriptor rings
2050  *
2051  * This function maps descriptor rings to the queue-specific vectors
2052  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2053  * one vector per ring/queue, but on a constrained vector budget, we
2054  * group the rings as "efficiently" as possible.  You would add new
2055  * mapping configurations in here.
2056  **/
2057 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
2058                                       int vectors)
2059 {
2060         int v_start = 0;
2061         int rxr_idx = 0, txr_idx = 0;
2062         int rxr_remaining = adapter->num_rx_queues;
2063         int txr_remaining = adapter->num_tx_queues;
2064         int i, j;
2065         int rqpv, tqpv;
2066         int err = 0;
2067
2068         /* No mapping required if MSI-X is disabled. */
2069         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2070                 goto out;
2071
2072         /*
2073          * The ideal configuration...
2074          * We have enough vectors to map one per queue.
2075          */
2076         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2077                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2078                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2079
2080                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2081                         map_vector_to_txq(adapter, v_start, txr_idx);
2082
2083                 goto out;
2084         }
2085
2086         /*
2087          * If we don't have enough vectors for a 1-to-1
2088          * mapping, we'll have to group them so there are
2089          * multiple queues per vector.
2090          */
2091         /* Re-adjusting *qpv takes care of the remainder. */
2092         for (i = v_start; i < vectors; i++) {
2093                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2094                 for (j = 0; j < rqpv; j++) {
2095                         map_vector_to_rxq(adapter, i, rxr_idx);
2096                         rxr_idx++;
2097                         rxr_remaining--;
2098                 }
2099         }
2100         for (i = v_start; i < vectors; i++) {
2101                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2102                 for (j = 0; j < tqpv; j++) {
2103                         map_vector_to_txq(adapter, i, txr_idx);
2104                         txr_idx++;
2105                         txr_remaining--;
2106                 }
2107         }
2108
2109 out:
2110         return err;
2111 }
2112
2113 /**
2114  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2115  * @adapter: board private structure
2116  *
2117  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2118  * interrupts from the kernel.
2119  **/
2120 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2121 {
2122         struct net_device *netdev = adapter->netdev;
2123         irqreturn_t (*handler)(int, void *);
2124         int i, vector, q_vectors, err;
2125         int ri=0, ti=0;
2126
2127         /* Decrement for Other and TCP Timer vectors */
2128         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2129
2130         /* Map the Tx/Rx rings to the vectors we were allotted. */
2131         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2132         if (err)
2133                 goto out;
2134
2135 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2136                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2137                          &ixgbe_msix_clean_many)
2138         for (vector = 0; vector < q_vectors; vector++) {
2139                 handler = SET_HANDLER(adapter->q_vector[vector]);
2140
2141                 if(handler == &ixgbe_msix_clean_rx) {
2142                         sprintf(adapter->name[vector], "%s-%s-%d",
2143                                 netdev->name, "rx", ri++);
2144                 }
2145                 else if(handler == &ixgbe_msix_clean_tx) {
2146                         sprintf(adapter->name[vector], "%s-%s-%d",
2147                                 netdev->name, "tx", ti++);
2148                 }
2149                 else
2150                         sprintf(adapter->name[vector], "%s-%s-%d",
2151                                 netdev->name, "TxRx", vector);
2152
2153                 err = request_irq(adapter->msix_entries[vector].vector,
2154                                   handler, 0, adapter->name[vector],
2155                                   adapter->q_vector[vector]);
2156                 if (err) {
2157                         e_err(probe, "request_irq failed for MSIX interrupt "
2158                               "Error: %d\n", err);
2159                         goto free_queue_irqs;
2160                 }
2161         }
2162
2163         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2164         err = request_irq(adapter->msix_entries[vector].vector,
2165                           ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
2166         if (err) {
2167                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2168                 goto free_queue_irqs;
2169         }
2170
2171         return 0;
2172
2173 free_queue_irqs:
2174         for (i = vector - 1; i >= 0; i--)
2175                 free_irq(adapter->msix_entries[--vector].vector,
2176                          adapter->q_vector[i]);
2177         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2178         pci_disable_msix(adapter->pdev);
2179         kfree(adapter->msix_entries);
2180         adapter->msix_entries = NULL;
2181 out:
2182         return err;
2183 }
2184
2185 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2186 {
2187         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2188         u8 current_itr;
2189         u32 new_itr = q_vector->eitr;
2190         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2191         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2192
2193         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2194                                             q_vector->tx_itr,
2195                                             tx_ring->total_packets,
2196                                             tx_ring->total_bytes);
2197         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2198                                             q_vector->rx_itr,
2199                                             rx_ring->total_packets,
2200                                             rx_ring->total_bytes);
2201
2202         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2203
2204         switch (current_itr) {
2205         /* counts and packets in update_itr are dependent on these numbers */
2206         case lowest_latency:
2207                 new_itr = 100000;
2208                 break;
2209         case low_latency:
2210                 new_itr = 20000; /* aka hwitr = ~200 */
2211                 break;
2212         case bulk_latency:
2213                 new_itr = 8000;
2214                 break;
2215         default:
2216                 break;
2217         }
2218
2219         if (new_itr != q_vector->eitr) {
2220                 /* do an exponential smoothing */
2221                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
2222
2223                 /* save the algorithm value here, not the smoothed one */
2224                 q_vector->eitr = new_itr;
2225
2226                 ixgbe_write_eitr(q_vector);
2227         }
2228 }
2229
2230 /**
2231  * ixgbe_irq_enable - Enable default interrupt generation settings
2232  * @adapter: board private structure
2233  **/
2234 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
2235 {
2236         u32 mask;
2237
2238         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2239         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2240                 mask |= IXGBE_EIMS_GPI_SDP0;
2241         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2242                 mask |= IXGBE_EIMS_GPI_SDP1;
2243         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2244                 mask |= IXGBE_EIMS_ECC;
2245                 mask |= IXGBE_EIMS_GPI_SDP1;
2246                 mask |= IXGBE_EIMS_GPI_SDP2;
2247                 if (adapter->num_vfs)
2248                         mask |= IXGBE_EIMS_MAILBOX;
2249         }
2250         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2251             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2252                 mask |= IXGBE_EIMS_FLOW_DIR;
2253
2254         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2255         ixgbe_irq_enable_queues(adapter, ~0);
2256         IXGBE_WRITE_FLUSH(&adapter->hw);
2257
2258         if (adapter->num_vfs > 32) {
2259                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2260                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2261         }
2262 }
2263
2264 /**
2265  * ixgbe_intr - legacy mode Interrupt Handler
2266  * @irq: interrupt number
2267  * @data: pointer to a network interface device structure
2268  **/
2269 static irqreturn_t ixgbe_intr(int irq, void *data)
2270 {
2271         struct net_device *netdev = data;
2272         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2273         struct ixgbe_hw *hw = &adapter->hw;
2274         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2275         u32 eicr;
2276
2277         /*
2278          * Workaround for silicon errata.  Mask the interrupts
2279          * before the read of EICR.
2280          */
2281         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2282
2283         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2284          * therefore no explict interrupt disable is necessary */
2285         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2286         if (!eicr) {
2287                 /* shared interrupt alert!
2288                  * make sure interrupts are enabled because the read will
2289                  * have disabled interrupts due to EIAM */
2290                 ixgbe_irq_enable(adapter);
2291                 return IRQ_NONE;        /* Not our interrupt */
2292         }
2293
2294         if (eicr & IXGBE_EICR_LSC)
2295                 ixgbe_check_lsc(adapter);
2296
2297         if (hw->mac.type == ixgbe_mac_82599EB)
2298                 ixgbe_check_sfp_event(adapter, eicr);
2299
2300         ixgbe_check_fan_failure(adapter, eicr);
2301         if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2302             ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2303                 schedule_work(&adapter->check_overtemp_task);
2304
2305         if (napi_schedule_prep(&(q_vector->napi))) {
2306                 adapter->tx_ring[0]->total_packets = 0;
2307                 adapter->tx_ring[0]->total_bytes = 0;
2308                 adapter->rx_ring[0]->total_packets = 0;
2309                 adapter->rx_ring[0]->total_bytes = 0;
2310                 /* would disable interrupts here but EIAM disabled it */
2311                 __napi_schedule(&(q_vector->napi));
2312         }
2313
2314         return IRQ_HANDLED;
2315 }
2316
2317 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2318 {
2319         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2320
2321         for (i = 0; i < q_vectors; i++) {
2322                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2323                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2324                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2325                 q_vector->rxr_count = 0;
2326                 q_vector->txr_count = 0;
2327         }
2328 }
2329
2330 /**
2331  * ixgbe_request_irq - initialize interrupts
2332  * @adapter: board private structure
2333  *
2334  * Attempts to configure interrupts using the best available
2335  * capabilities of the hardware and kernel.
2336  **/
2337 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2338 {
2339         struct net_device *netdev = adapter->netdev;
2340         int err;
2341
2342         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2343                 err = ixgbe_request_msix_irqs(adapter);
2344         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2345                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2346                                   netdev->name, netdev);
2347         } else {
2348                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2349                                   netdev->name, netdev);
2350         }
2351
2352         if (err)
2353                 e_err(probe, "request_irq failed, Error %d\n", err);
2354
2355         return err;
2356 }
2357
2358 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2359 {
2360         struct net_device *netdev = adapter->netdev;
2361
2362         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2363                 int i, q_vectors;
2364
2365                 q_vectors = adapter->num_msix_vectors;
2366
2367                 i = q_vectors - 1;
2368                 free_irq(adapter->msix_entries[i].vector, netdev);
2369
2370                 i--;
2371                 for (; i >= 0; i--) {
2372                         free_irq(adapter->msix_entries[i].vector,
2373                                  adapter->q_vector[i]);
2374                 }
2375
2376                 ixgbe_reset_q_vectors(adapter);
2377         } else {
2378                 free_irq(adapter->pdev->irq, netdev);
2379         }
2380 }
2381
2382 /**
2383  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2384  * @adapter: board private structure
2385  **/
2386 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2387 {
2388         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2389                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2390         } else {
2391                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2392                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2393                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2394                 if (adapter->num_vfs > 32)
2395                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2396         }
2397         IXGBE_WRITE_FLUSH(&adapter->hw);
2398         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2399                 int i;
2400                 for (i = 0; i < adapter->num_msix_vectors; i++)
2401                         synchronize_irq(adapter->msix_entries[i].vector);
2402         } else {
2403                 synchronize_irq(adapter->pdev->irq);
2404         }
2405 }
2406
2407 /**
2408  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2409  *
2410  **/
2411 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2412 {
2413         struct ixgbe_hw *hw = &adapter->hw;
2414
2415         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2416                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2417
2418         ixgbe_set_ivar(adapter, 0, 0, 0);
2419         ixgbe_set_ivar(adapter, 1, 0, 0);
2420
2421         map_vector_to_rxq(adapter, 0, 0);
2422         map_vector_to_txq(adapter, 0, 0);
2423
2424         e_info(hw, "Legacy interrupt IVAR setup done\n");
2425 }
2426
2427 /**
2428  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2429  * @adapter: board private structure
2430  * @ring: structure containing ring specific data
2431  *
2432  * Configure the Tx descriptor ring after a reset.
2433  **/
2434  static void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2435                                      struct ixgbe_ring *ring)
2436 {
2437         struct ixgbe_hw *hw = &adapter->hw;
2438         u64 tdba = ring->dma;
2439         u16 reg_idx = ring->reg_idx;
2440
2441         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2442                         (tdba & DMA_BIT_MASK(32)));
2443         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2444         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2445                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2446         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2447         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2448         ring->head = IXGBE_TDH(reg_idx);
2449         ring->tail = IXGBE_TDT(reg_idx);
2450
2451 }
2452
2453 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2454 {
2455         struct ixgbe_hw *hw = &adapter->hw;
2456         u32 rttdcs;
2457         u32 mask;
2458
2459         if (hw->mac.type == ixgbe_mac_82598EB)
2460                 return;
2461
2462         /* disable the arbiter while setting MTQC */
2463         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2464         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2465         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2466
2467         /* set transmit pool layout */
2468         mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2469         switch (adapter->flags & mask) {
2470
2471         case (IXGBE_FLAG_SRIOV_ENABLED):
2472                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2473                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2474                 break;
2475
2476         case (IXGBE_FLAG_DCB_ENABLED):
2477                 /* We enable 8 traffic classes, DCB only */
2478                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2479                               (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2480                 break;
2481
2482         default:
2483                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2484                 break;
2485         }
2486
2487         /* re-enable the arbiter */
2488         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2489         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2490 }
2491
2492 /**
2493  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2494  * @adapter: board private structure
2495  *
2496  * Configure the Tx unit of the MAC after a reset.
2497  **/
2498 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2499 {
2500         u32 i;
2501
2502         /* Setup the HW Tx Head and Tail descriptor pointers */
2503         for (i = 0; i < adapter->num_tx_queues; i++)
2504                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2505
2506         ixgbe_setup_mtqc(adapter);
2507 }
2508
2509 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2510
2511 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2512                                    struct ixgbe_ring *rx_ring)
2513 {
2514         u32 srrctl;
2515         int index;
2516         struct ixgbe_ring_feature *feature = adapter->ring_feature;
2517
2518         index = rx_ring->reg_idx;
2519         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2520                 unsigned long mask;
2521                 mask = (unsigned long) feature[RING_F_RSS].mask;
2522                 index = index & mask;
2523         }
2524         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2525
2526         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2527         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2528
2529         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2530                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2531
2532         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2533 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2534                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2535 #else
2536                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2537 #endif
2538                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2539         } else {
2540                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2541                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2542                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2543         }
2544
2545         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2546 }
2547
2548 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2549 {
2550         struct ixgbe_hw *hw = &adapter->hw;
2551         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2552                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2553                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2554         u32 mrqc = 0, reta = 0;
2555         u32 rxcsum;
2556         int i, j;
2557         int mask;
2558
2559         /* Fill out hash function seeds */
2560         for (i = 0; i < 10; i++)
2561                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2562
2563         /* Fill out redirection table */
2564         for (i = 0, j = 0; i < 128; i++, j++) {
2565                 if (j == adapter->ring_feature[RING_F_RSS].indices)
2566                         j = 0;
2567                 /* reta = 4-byte sliding window of
2568                  * 0x00..(indices-1)(indices-1)00..etc. */
2569                 reta = (reta << 8) | (j * 0x11);
2570                 if ((i & 3) == 3)
2571                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2572         }
2573
2574         /* Disable indicating checksum in descriptor, enables RSS hash */
2575         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2576         rxcsum |= IXGBE_RXCSUM_PCSD;
2577         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2578
2579         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2580                 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2581         else
2582                 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2583 #ifdef CONFIG_IXGBE_DCB
2584                                          | IXGBE_FLAG_DCB_ENABLED
2585 #endif
2586                                          | IXGBE_FLAG_SRIOV_ENABLED
2587                                         );
2588
2589         switch (mask) {
2590         case (IXGBE_FLAG_RSS_ENABLED):
2591                 mrqc = IXGBE_MRQC_RSSEN;
2592                 break;
2593         case (IXGBE_FLAG_SRIOV_ENABLED):
2594                 mrqc = IXGBE_MRQC_VMDQEN;
2595                 break;
2596 #ifdef CONFIG_IXGBE_DCB
2597         case (IXGBE_FLAG_DCB_ENABLED):
2598                 mrqc = IXGBE_MRQC_RT8TCEN;
2599                 break;
2600 #endif /* CONFIG_IXGBE_DCB */
2601         default:
2602                 break;
2603         }
2604
2605         /* Perform hash on these packet types */
2606         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2607               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2608               | IXGBE_MRQC_RSS_FIELD_IPV6
2609               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2610
2611         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2612 }
2613
2614 /**
2615  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2616  * @adapter:    address of board private structure
2617  * @index:      index of ring to set
2618  **/
2619 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
2620 {
2621         struct ixgbe_ring *rx_ring;
2622         struct ixgbe_hw *hw = &adapter->hw;
2623         int j;
2624         u32 rscctrl;
2625         int rx_buf_len;
2626
2627         rx_ring = adapter->rx_ring[index];
2628         j = rx_ring->reg_idx;
2629         rx_buf_len = rx_ring->rx_buf_len;
2630         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2631         rscctrl |= IXGBE_RSCCTL_RSCEN;
2632         /*
2633          * we must limit the number of descriptors so that the
2634          * total size of max desc * buf_len is not greater
2635          * than 65535
2636          */
2637         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2638 #if (MAX_SKB_FRAGS > 16)
2639                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2640 #elif (MAX_SKB_FRAGS > 8)
2641                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2642 #elif (MAX_SKB_FRAGS > 4)
2643                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2644 #else
2645                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2646 #endif
2647         } else {
2648                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2649                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2650                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2651                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2652                 else
2653                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2654         }
2655         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2656 }
2657
2658 static void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2659                                     struct ixgbe_ring *ring)
2660 {
2661         struct ixgbe_hw *hw = &adapter->hw;
2662         u64 rdba = ring->dma;
2663         u16 reg_idx = ring->reg_idx;
2664
2665         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2666         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2667         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2668                         ring->count * sizeof(union ixgbe_adv_rx_desc));
2669         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2670         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2671         ring->head = IXGBE_RDH(reg_idx);
2672         ring->tail = IXGBE_RDT(reg_idx);
2673 }
2674
2675 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2676 {
2677         struct ixgbe_hw *hw = &adapter->hw;
2678         int p;
2679
2680         /* PSRTYPE must be initialized in non 82598 adapters */
2681         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2682                       IXGBE_PSRTYPE_UDPHDR |
2683                       IXGBE_PSRTYPE_IPV4HDR |
2684                       IXGBE_PSRTYPE_L2HDR |
2685                       IXGBE_PSRTYPE_IPV6HDR;
2686
2687         if (hw->mac.type == ixgbe_mac_82598EB)
2688                 return;
2689
2690         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2691                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2692
2693         for (p = 0; p < adapter->num_rx_pools; p++)
2694                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2695                                 psrtype);
2696 }
2697
2698 /**
2699  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2700  * @adapter: board private structure
2701  *
2702  * Configure the Rx unit of the MAC after a reset.
2703  **/
2704 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2705 {
2706         struct ixgbe_hw *hw = &adapter->hw;
2707         struct ixgbe_ring *rx_ring;
2708         struct net_device *netdev = adapter->netdev;
2709         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2710         int i;
2711         u32 rxctrl;
2712         u32 fctrl, hlreg0;
2713         u32 rdrxctl;
2714         int rx_buf_len;
2715
2716         ixgbe_setup_psrtype(adapter);
2717
2718         /* Decide whether to use packet split mode or not */
2719         /* Do not use packet split if we're in SR-IOV Mode */
2720         if (!adapter->num_vfs)
2721                 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2722
2723         /* Set the RX buffer length according to the mode */
2724         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2725                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2726         } else {
2727                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2728                     (netdev->mtu <= ETH_DATA_LEN))
2729                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2730                 else
2731                         rx_buf_len = ALIGN(max_frame, 1024);
2732         }
2733
2734         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2735         fctrl |= IXGBE_FCTRL_BAM;
2736         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2737         fctrl |= IXGBE_FCTRL_PMCF;
2738         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2739
2740         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2741         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2742                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2743         else
2744                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2745 #ifdef IXGBE_FCOE
2746         if (netdev->features & NETIF_F_FCOE_MTU)
2747                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2748 #endif
2749         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2750
2751         /* disable receives while setting up the descriptors */
2752         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2753         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2754
2755         /*
2756          * Setup the HW Rx Head and Tail Descriptor Pointers and
2757          * the Base and Length of the Rx Descriptor Ring
2758          */
2759         for (i = 0; i < adapter->num_rx_queues; i++) {
2760                 rx_ring = adapter->rx_ring[i];
2761                 rx_ring->rx_buf_len = rx_buf_len;
2762
2763                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2764                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2765                 else
2766                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2767
2768 #ifdef IXGBE_FCOE
2769                 if (netdev->features & NETIF_F_FCOE_MTU) {
2770                         struct ixgbe_ring_feature *f;
2771                         f = &adapter->ring_feature[RING_F_FCOE];
2772                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2773                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2774                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2775                                         rx_ring->rx_buf_len =
2776                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2777                         }
2778                 }
2779
2780 #endif /* IXGBE_FCOE */
2781                 ixgbe_configure_rx_ring(adapter, rx_ring);
2782                 ixgbe_configure_srrctl(adapter, rx_ring);
2783         }
2784
2785         if (hw->mac.type == ixgbe_mac_82598EB) {
2786                 /*
2787                  * For VMDq support of different descriptor types or
2788                  * buffer sizes through the use of multiple SRRCTL
2789                  * registers, RDRXCTL.MVMEN must be set to 1
2790                  *
2791                  * also, the manual doesn't mention it clearly but DCA hints
2792                  * will only use queue 0's tags unless this bit is set.  Side
2793                  * effects of setting this bit are only that SRRCTL must be
2794                  * fully programmed [0..15]
2795                  */
2796                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2797                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2798                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2799         }
2800
2801         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2802                 u32 vt_reg_bits;
2803                 u32 reg_offset, vf_shift;
2804                 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2805                 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2806                         | IXGBE_VT_CTL_REPLEN;
2807                 vt_reg_bits |= (adapter->num_vfs <<
2808                                 IXGBE_VT_CTL_POOL_SHIFT);
2809                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2810                 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2811
2812                 vf_shift = adapter->num_vfs % 32;
2813                 reg_offset = adapter->num_vfs / 32;
2814                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2815                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2816                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2817                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2818                 /* Enable only the PF's pool for Tx/Rx */
2819                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2820                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2821                 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2822                 ixgbe_set_vmolr(hw, adapter->num_vfs, true);
2823         }
2824
2825         /* Program MRQC for the distribution of queues */
2826         ixgbe_setup_mrqc(adapter);
2827
2828         if (adapter->num_vfs) {
2829                 u32 reg;
2830
2831                 /* Map PF MAC address in RAR Entry 0 to first pool
2832                  * following VFs */
2833                 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2834
2835                 /* Set up VF register offsets for selected VT Mode, i.e.
2836                  * 64 VFs for SR-IOV */
2837                 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2838                 reg |= IXGBE_GCR_EXT_SRIOV;
2839                 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);
2840         }
2841
2842         if (hw->mac.type == ixgbe_mac_82599EB) {
2843                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2844                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2845                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2846                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2847         }
2848
2849         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2850                 /* Enable 82599 HW-RSC */
2851                 for (i = 0; i < adapter->num_rx_queues; i++)
2852                         ixgbe_configure_rscctl(adapter, i);
2853
2854                 /* Disable RSC for ACK packets */
2855                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2856                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2857         }
2858 }
2859
2860 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2861 {
2862         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2863         struct ixgbe_hw *hw = &adapter->hw;
2864         int pool_ndx = adapter->num_vfs;
2865
2866         /* add VID to filter table */
2867         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
2868 }
2869
2870 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2871 {
2872         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2873         struct ixgbe_hw *hw = &adapter->hw;
2874         int pool_ndx = adapter->num_vfs;
2875
2876         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2877                 ixgbe_irq_disable(adapter);
2878
2879         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2880
2881         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2882                 ixgbe_irq_enable(adapter);
2883
2884         /* remove VID from filter table */
2885         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
2886 }
2887
2888 /**
2889  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
2890  * @adapter: driver data
2891  */
2892 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
2893 {
2894         struct ixgbe_hw *hw = &adapter->hw;
2895         u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2896         int i, j;
2897
2898         switch (hw->mac.type) {
2899         case ixgbe_mac_82598EB:
2900                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2901 #ifdef CONFIG_IXGBE_DCB
2902                 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
2903                         vlnctrl &= ~IXGBE_VLNCTRL_VME;
2904 #endif
2905                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2906                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2907                 break;
2908         case ixgbe_mac_82599EB:
2909                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2910                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2911                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2912 #ifdef CONFIG_IXGBE_DCB
2913                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
2914                         break;
2915 #endif
2916                 for (i = 0; i < adapter->num_rx_queues; i++) {
2917                         j = adapter->rx_ring[i]->reg_idx;
2918                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2919                         vlnctrl &= ~IXGBE_RXDCTL_VME;
2920                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2921                 }
2922                 break;
2923         default:
2924                 break;
2925         }
2926 }
2927
2928 /**
2929  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
2930  * @adapter: driver data
2931  */
2932 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
2933 {
2934         struct ixgbe_hw *hw = &adapter->hw;
2935         u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2936         int i, j;
2937
2938         switch (hw->mac.type) {
2939         case ixgbe_mac_82598EB:
2940                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2941                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2942                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2943                 break;
2944         case ixgbe_mac_82599EB:
2945                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2946                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2947                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2948                 for (i = 0; i < adapter->num_rx_queues; i++) {
2949                         j = adapter->rx_ring[i]->reg_idx;
2950                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2951                         vlnctrl |= IXGBE_RXDCTL_VME;
2952                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2953                 }
2954                 break;
2955         default:
2956                 break;
2957         }
2958 }
2959
2960 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2961                                    struct vlan_group *grp)
2962 {
2963         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2964
2965         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2966                 ixgbe_irq_disable(adapter);
2967         adapter->vlgrp = grp;
2968
2969         /*
2970          * For a DCB driver, always enable VLAN tag stripping so we can
2971          * still receive traffic from a DCB-enabled host even if we're
2972          * not in DCB mode.
2973          */
2974         ixgbe_vlan_filter_enable(adapter);
2975
2976         ixgbe_vlan_rx_add_vid(netdev, 0);
2977
2978         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2979                 ixgbe_irq_enable(adapter);
2980 }
2981
2982 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2983 {
2984         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2985
2986         if (adapter->vlgrp) {
2987                 u16 vid;
2988                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2989                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2990                                 continue;
2991                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2992                 }
2993         }
2994 }
2995
2996 /**
2997  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
2998  * @netdev: network interface device structure
2999  *
3000  * Writes unicast address list to the RAR table.
3001  * Returns: -ENOMEM on failure/insufficient address space
3002  *                0 on no addresses written
3003  *                X on writing X addresses to the RAR table
3004  **/
3005 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3006 {
3007         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3008         struct ixgbe_hw *hw = &adapter->hw;
3009         unsigned int vfn = adapter->num_vfs;
3010         unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3011         int count = 0;
3012
3013         /* return ENOMEM indicating insufficient memory for addresses */
3014         if (netdev_uc_count(netdev) > rar_entries)
3015                 return -ENOMEM;
3016
3017         if (!netdev_uc_empty(netdev) && rar_entries) {
3018                 struct netdev_hw_addr *ha;
3019                 /* return error if we do not support writing to RAR table */
3020                 if (!hw->mac.ops.set_rar)
3021                         return -ENOMEM;
3022
3023                 netdev_for_each_uc_addr(ha, netdev) {
3024                         if (!rar_entries)
3025                                 break;
3026                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3027                                             vfn, IXGBE_RAH_AV);
3028                         count++;
3029                 }
3030         }
3031         /* write the addresses in reverse order to avoid write combining */
3032         for (; rar_entries > 0 ; rar_entries--)
3033                 hw->mac.ops.clear_rar(hw, rar_entries);
3034
3035         return count;
3036 }
3037
3038 /**
3039  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3040  * @netdev: network interface device structure
3041  *
3042  * The set_rx_method entry point is called whenever the unicast/multicast
3043  * address list or the network interface flags are updated.  This routine is
3044  * responsible for configuring the hardware for proper unicast, multicast and
3045  * promiscuous mode.
3046  **/
3047 void ixgbe_set_rx_mode(struct net_device *netdev)
3048 {
3049         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3050         struct ixgbe_hw *hw = &adapter->hw;
3051         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3052         int count;
3053
3054         /* Check for Promiscuous and All Multicast modes */
3055
3056         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3057
3058         /* clear the bits we are changing the status of */
3059         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3060
3061         if (netdev->flags & IFF_PROMISC) {
3062                 hw->addr_ctrl.user_set_promisc = true;
3063                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3064                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3065                 /* don't hardware filter vlans in promisc mode */
3066                 ixgbe_vlan_filter_disable(adapter);
3067         } else {
3068                 if (netdev->flags & IFF_ALLMULTI) {
3069                         fctrl |= IXGBE_FCTRL_MPE;
3070                         vmolr |= IXGBE_VMOLR_MPE;
3071                 } else {
3072                         /*
3073                          * Write addresses to the MTA, if the attempt fails
3074                          * then we should just turn on promiscous mode so
3075                          * that we can at least receive multicast traffic
3076                          */
3077                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3078                         vmolr |= IXGBE_VMOLR_ROMPE;
3079                 }
3080                 ixgbe_vlan_filter_enable(adapter);
3081                 hw->addr_ctrl.user_set_promisc = false;
3082                 /*
3083                  * Write addresses to available RAR registers, if there is not
3084                  * sufficient space to store all the addresses then enable
3085                  * unicast promiscous mode
3086                  */
3087                 count = ixgbe_write_uc_addr_list(netdev);
3088                 if (count < 0) {
3089                         fctrl |= IXGBE_FCTRL_UPE;
3090                         vmolr |= IXGBE_VMOLR_ROPE;
3091                 }
3092         }
3093
3094         if (adapter->num_vfs) {
3095                 ixgbe_restore_vf_multicasts(adapter);
3096                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3097                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3098                            IXGBE_VMOLR_ROPE);
3099                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3100         }
3101
3102         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3103 }
3104
3105 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3106 {
3107         int q_idx;
3108         struct ixgbe_q_vector *q_vector;
3109         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3110
3111         /* legacy and MSI only use one vector */
3112         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3113                 q_vectors = 1;
3114
3115         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3116                 struct napi_struct *napi;
3117                 q_vector = adapter->q_vector[q_idx];
3118                 napi = &q_vector->napi;
3119                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3120                         if (!q_vector->rxr_count || !q_vector->txr_count) {
3121                                 if (q_vector->txr_count == 1)
3122                                         napi->poll = &ixgbe_clean_txonly;
3123                                 else if (q_vector->rxr_count == 1)
3124                                         napi->poll = &ixgbe_clean_rxonly;
3125                         }
3126                 }
3127
3128                 napi_enable(napi);
3129         }
3130 }
3131
3132 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3133 {
3134         int q_idx;
3135         struct ixgbe_q_vector *q_vector;
3136         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3137
3138         /* legacy and MSI only use one vector */
3139         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3140                 q_vectors = 1;
3141
3142         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3143                 q_vector = adapter->q_vector[q_idx];
3144                 napi_disable(&q_vector->napi);
3145         }
3146 }
3147
3148 #ifdef CONFIG_IXGBE_DCB
3149 /*
3150  * ixgbe_configure_dcb - Configure DCB hardware
3151  * @adapter: ixgbe adapter struct
3152  *
3153  * This is called by the driver on open to configure the DCB hardware.
3154  * This is also called by the gennetlink interface when reconfiguring
3155  * the DCB state.
3156  */
3157 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3158 {
3159         struct ixgbe_hw *hw = &adapter->hw;
3160         u32 txdctl;
3161         int i, j;
3162
3163         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3164                 if (hw->mac.type == ixgbe_mac_82598EB)
3165                         netif_set_gso_max_size(adapter->netdev, 65536);
3166                 return;
3167         }
3168
3169         if (hw->mac.type == ixgbe_mac_82598EB)
3170                 netif_set_gso_max_size(adapter->netdev, 32768);
3171
3172         ixgbe_dcb_check_config(&adapter->dcb_cfg);
3173         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
3174         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
3175
3176         /* reconfigure the hardware */
3177         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3178
3179         for (i = 0; i < adapter->num_tx_queues; i++) {
3180                 j = adapter->tx_ring[i]->reg_idx;
3181                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3182                 /* PThresh workaround for Tx hang with DFP enabled. */
3183                 txdctl |= 32;
3184                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3185         }
3186         /* Enable VLAN tag insert/strip */
3187         ixgbe_vlan_filter_enable(adapter);
3188
3189         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3190 }
3191
3192 #endif
3193 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3194 {
3195         struct net_device *netdev = adapter->netdev;
3196         struct ixgbe_hw *hw = &adapter->hw;
3197         int i;
3198
3199         ixgbe_set_rx_mode(netdev);
3200
3201         ixgbe_restore_vlan(adapter);
3202 #ifdef CONFIG_IXGBE_DCB
3203         ixgbe_configure_dcb(adapter);
3204 #endif
3205
3206 #ifdef IXGBE_FCOE
3207         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3208                 ixgbe_configure_fcoe(adapter);
3209
3210 #endif /* IXGBE_FCOE */
3211         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3212                 for (i = 0; i < adapter->num_tx_queues; i++)
3213                         adapter->tx_ring[i]->atr_sample_rate =
3214                                                        adapter->atr_sample_rate;
3215                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3216         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3217                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3218         }
3219
3220         ixgbe_configure_tx(adapter);
3221         ixgbe_configure_rx(adapter);
3222         for (i = 0; i < adapter->num_rx_queues; i++)
3223                 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
3224                                        (adapter->rx_ring[i]->count - 1));
3225 }
3226
3227 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3228 {
3229         switch (hw->phy.type) {
3230         case ixgbe_phy_sfp_avago:
3231         case ixgbe_phy_sfp_ftl:
3232         case ixgbe_phy_sfp_intel:
3233         case ixgbe_phy_sfp_unknown:
3234         case ixgbe_phy_sfp_passive_tyco:
3235         case ixgbe_phy_sfp_passive_unknown:
3236         case ixgbe_phy_sfp_active_unknown:
3237         case ixgbe_phy_sfp_ftl_active:
3238                 return true;
3239         default:
3240                 return false;
3241         }
3242 }
3243
3244 /**
3245  * ixgbe_sfp_link_config - set up SFP+ link
3246  * @adapter: pointer to private adapter struct
3247  **/
3248 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3249 {
3250         struct ixgbe_hw *hw = &adapter->hw;
3251
3252                 if (hw->phy.multispeed_fiber) {
3253                         /*
3254                          * In multispeed fiber setups, the device may not have
3255                          * had a physical connection when the driver loaded.
3256                          * If that's the case, the initial link configuration
3257                          * couldn't get the MAC into 10G or 1G mode, so we'll
3258                          * never have a link status change interrupt fire.
3259                          * We need to try and force an autonegotiation
3260                          * session, then bring up link.
3261                          */
3262                         hw->mac.ops.setup_sfp(hw);
3263                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3264                                 schedule_work(&adapter->multispeed_fiber_task);
3265                 } else {
3266                         /*
3267                          * Direct Attach Cu and non-multispeed fiber modules
3268                          * still need to be configured properly prior to
3269                          * attempting link.
3270                          */
3271                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3272                                 schedule_work(&adapter->sfp_config_module_task);
3273                 }
3274 }
3275
3276 /**
3277  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3278  * @hw: pointer to private hardware struct
3279  *
3280  * Returns 0 on success, negative on failure
3281  **/
3282 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3283 {
3284         u32 autoneg;
3285         bool negotiation, link_up = false;
3286         u32 ret = IXGBE_ERR_LINK_SETUP;
3287
3288         if (hw->mac.ops.check_link)
3289                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3290
3291         if (ret)
3292                 goto link_cfg_out;
3293
3294         if (hw->mac.ops.get_link_capabilities)
3295                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
3296         if (ret)
3297                 goto link_cfg_out;
3298
3299         if (hw->mac.ops.setup_link)
3300                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3301 link_cfg_out:
3302         return ret;
3303 }
3304
3305 #define IXGBE_MAX_RX_DESC_POLL 10
3306 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3307                                               int rxr)
3308 {
3309         int j = adapter->rx_ring[rxr]->reg_idx;
3310         int k;
3311
3312         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
3313                 if (IXGBE_READ_REG(&adapter->hw,
3314                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
3315                         break;
3316                 else
3317                         msleep(1);
3318         }
3319         if (k >= IXGBE_MAX_RX_DESC_POLL) {
3320                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3321                       "the polling period\n", rxr);
3322         }
3323         ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
3324                               (adapter->rx_ring[rxr]->count - 1));
3325 }
3326
3327 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3328 {
3329         struct net_device *netdev = adapter->netdev;
3330         struct ixgbe_hw *hw = &adapter->hw;
3331         int i, j = 0;
3332         int num_rx_rings = adapter->num_rx_queues;
3333         int err;
3334         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3335         u32 txdctl, rxdctl, mhadd;
3336         u32 dmatxctl;
3337         u32 gpie;
3338         u32 ctrl_ext;
3339
3340         ixgbe_get_hw_control(adapter);
3341
3342         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
3343             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
3344                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3345                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
3346                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
3347                 } else {
3348                         /* MSI only */
3349                         gpie = 0;
3350                 }
3351                 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3352                         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3353                         gpie |= IXGBE_GPIE_VTMODE_64;
3354                 }
3355                 /* XXX: to interrupt immediately for EICS writes, enable this */
3356                 /* gpie |= IXGBE_GPIE_EIMEN; */
3357                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3358         }
3359
3360         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3361                 /*
3362                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3363                  * this saves a register write for every interrupt
3364                  */
3365                 switch (hw->mac.type) {
3366                 case ixgbe_mac_82598EB:
3367                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3368                         break;
3369                 default:
3370                 case ixgbe_mac_82599EB:
3371                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3372                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3373                         break;
3374                 }
3375         } else {
3376                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3377                  * specifically only auto mask tx and rx interrupts */
3378                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3379         }
3380
3381         /* Enable Thermal over heat sensor interrupt */
3382         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3383                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3384                 gpie |= IXGBE_SDP0_GPIEN;
3385                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3386         }
3387
3388         /* Enable fan failure interrupt if media type is copper */
3389         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3390                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3391                 gpie |= IXGBE_SDP1_GPIEN;
3392                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3393         }
3394
3395         if (hw->mac.type == ixgbe_mac_82599EB) {
3396                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3397                 gpie |= IXGBE_SDP1_GPIEN;
3398                 gpie |= IXGBE_SDP2_GPIEN;
3399                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3400         }
3401
3402 #ifdef IXGBE_FCOE
3403         /* adjust max frame to be able to do baby jumbo for FCoE */
3404         if ((netdev->features & NETIF_F_FCOE_MTU) &&
3405             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3406                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3407
3408 #endif /* IXGBE_FCOE */
3409         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3410         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3411                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3412                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3413
3414                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3415         }
3416
3417         if (hw->mac.type == ixgbe_mac_82599EB) {
3418                 /* DMATXCTL.EN must be set after all Tx queue config is done */
3419                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3420                 dmatxctl |= IXGBE_DMATXCTL_TE;
3421                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3422         }
3423         for (i = 0; i < adapter->num_tx_queues; i++) {
3424                 j = adapter->tx_ring[i]->reg_idx;
3425                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3426                 if (adapter->rx_itr_setting == 0) {
3427                         /* cannot set wthresh when itr==0 */
3428                         txdctl &= ~0x007F0000;
3429                 } else {
3430                         /* enable WTHRESH=8 descriptors, to encourage burst writeback */
3431                         txdctl |= (8 << 16);
3432                 }
3433                 txdctl |= IXGBE_TXDCTL_ENABLE;
3434                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3435                 if (hw->mac.type == ixgbe_mac_82599EB) {
3436                         int wait_loop = 10;
3437                         /* poll for Tx Enable ready */
3438                         do {
3439                                 msleep(1);
3440                                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3441                         } while (--wait_loop &&
3442                                  !(txdctl & IXGBE_TXDCTL_ENABLE));
3443                         if (!wait_loop)
3444                                 e_err(drv, "Could not enable Tx Queue %d\n", j);
3445                 }
3446         }
3447
3448         for (i = 0; i < num_rx_rings; i++) {
3449                 j = adapter->rx_ring[i]->reg_idx;
3450                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3451                 /* enable PTHRESH=32 descriptors (half the internal cache)
3452                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
3453                  * this also removes a pesky rx_no_buffer_count increment */
3454                 rxdctl |= 0x0020;
3455                 rxdctl |= IXGBE_RXDCTL_ENABLE;
3456                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
3457                 if (hw->mac.type == ixgbe_mac_82599EB)
3458                         ixgbe_rx_desc_queue_enable(adapter, i);
3459         }
3460         /* enable all receives */
3461         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3462         if (hw->mac.type == ixgbe_mac_82598EB)
3463                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
3464         else
3465                 rxdctl |= IXGBE_RXCTRL_RXEN;
3466         hw->mac.ops.enable_rx_dma(hw, rxdctl);
3467
3468         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3469                 ixgbe_configure_msix(adapter);
3470         else
3471                 ixgbe_configure_msi_and_legacy(adapter);
3472
3473         /* enable the optics */
3474         if (hw->phy.multispeed_fiber)
3475                 hw->mac.ops.enable_tx_laser(hw);
3476
3477         clear_bit(__IXGBE_DOWN, &adapter->state);
3478         ixgbe_napi_enable_all(adapter);
3479
3480         /* clear any pending interrupts, may auto mask */
3481         IXGBE_READ_REG(hw, IXGBE_EICR);
3482
3483         ixgbe_irq_enable(adapter);
3484
3485         /*
3486          * If this adapter has a fan, check to see if we had a failure
3487          * before we enabled the interrupt.
3488          */
3489         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3490                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3491                 if (esdp & IXGBE_ESDP_SDP1)
3492                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3493         }
3494
3495         /*
3496          * For hot-pluggable SFP+ devices, a new SFP+ module may have
3497          * arrived before interrupts were enabled but after probe.  Such
3498          * devices wouldn't have their type identified yet. We need to
3499          * kick off the SFP+ module setup first, then try to bring up link.
3500          * If we're not hot-pluggable SFP+, we just need to configure link
3501          * and bring it up.
3502          */
3503         if (hw->phy.type == ixgbe_phy_unknown) {
3504                 err = hw->phy.ops.identify(hw);
3505                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3506                         /*
3507                          * Take the device down and schedule the sfp tasklet
3508                          * which will unregister_netdev and log it.
3509                          */
3510                         ixgbe_down(adapter);
3511                         schedule_work(&adapter->sfp_config_module_task);
3512                         return err;
3513                 }
3514         }
3515
3516         if (ixgbe_is_sfp(hw)) {
3517                 ixgbe_sfp_link_config(adapter);
3518         } else {
3519                 err = ixgbe_non_sfp_link_config(hw);
3520                 if (err)
3521                         e_err(probe, "link_config FAILED %d\n", err);
3522         }
3523
3524         for (i = 0; i < adapter->num_tx_queues; i++)
3525                 set_bit(__IXGBE_FDIR_INIT_DONE,
3526                         &(adapter->tx_ring[i]->reinit_state));
3527
3528         /* enable transmits */
3529         netif_tx_start_all_queues(netdev);
3530
3531         /* bring the link up in the watchdog, this could race with our first
3532          * link up interrupt but shouldn't be a problem */
3533         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3534         adapter->link_check_timeout = jiffies;
3535         mod_timer(&adapter->watchdog_timer, jiffies);
3536
3537         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3538         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3539         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3540         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3541
3542         return 0;
3543 }
3544
3545 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3546 {
3547         WARN_ON(in_interrupt());
3548         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3549                 msleep(1);
3550         ixgbe_down(adapter);
3551         /*
3552          * If SR-IOV enabled then wait a bit before bringing the adapter
3553          * back up to give the VFs time to respond to the reset.  The
3554          * two second wait is based upon the watchdog timer cycle in
3555          * the VF driver.
3556          */
3557         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3558                 msleep(2000);
3559         ixgbe_up(adapter);
3560         clear_bit(__IXGBE_RESETTING, &adapter->state);
3561 }
3562
3563 int ixgbe_up(struct ixgbe_adapter *adapter)
3564 {
3565         /* hardware has been reset, we need to reload some things */
3566         ixgbe_configure(adapter);
3567
3568         return ixgbe_up_complete(adapter);
3569 }
3570
3571 void ixgbe_reset(struct ixgbe_adapter *adapter)
3572 {
3573         struct ixgbe_hw *hw = &adapter->hw;
3574         int err;
3575
3576         err = hw->mac.ops.init_hw(hw);
3577         switch (err) {
3578         case 0:
3579         case IXGBE_ERR_SFP_NOT_PRESENT:
3580                 break;
3581         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3582                 e_dev_err("master disable timed out\n");
3583                 break;
3584         case IXGBE_ERR_EEPROM_VERSION:
3585                 /* We are running on a pre-production device, log a warning */
3586                 e_dev_warn("This device is a pre-production adapter/LOM. "
3587                            "Please be aware there may be issuesassociated with "
3588                            "your hardware.  If you are experiencing problems "
3589                            "please contact your Intel or hardware "
3590                            "representative who provided you with this "
3591                            "hardware.\n");
3592                 break;
3593         default:
3594                 e_dev_err("Hardware Error: %d\n", err);
3595         }
3596
3597         /* reprogram the RAR[0] in case user changed it. */
3598         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3599                             IXGBE_RAH_AV);
3600 }
3601
3602 /**
3603  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3604  * @adapter: board private structure
3605  * @rx_ring: ring to free buffers from
3606  **/
3607 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
3608                                 struct ixgbe_ring *rx_ring)
3609 {
3610         struct pci_dev *pdev = adapter->pdev;
3611         unsigned long size;
3612         unsigned int i;
3613
3614         /* Free all the Rx ring sk_buffs */
3615
3616         for (i = 0; i < rx_ring->count; i++) {
3617                 struct ixgbe_rx_buffer *rx_buffer_info;
3618
3619                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3620                 if (rx_buffer_info->dma) {
3621                         dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
3622                                          rx_ring->rx_buf_len,
3623                                          DMA_FROM_DEVICE);
3624                         rx_buffer_info->dma = 0;
3625                 }
3626                 if (rx_buffer_info->skb) {
3627                         struct sk_buff *skb = rx_buffer_info->skb;
3628                         rx_buffer_info->skb = NULL;
3629                         do {
3630                                 struct sk_buff *this = skb;
3631                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3632                                         dma_unmap_single(&pdev->dev,
3633                                                          IXGBE_RSC_CB(this)->dma,
3634                                                          rx_ring->rx_buf_len,
3635                                                          DMA_FROM_DEVICE);
3636                                         IXGBE_RSC_CB(this)->dma = 0;
3637                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3638                                 }
3639                                 skb = skb->prev;
3640                                 dev_kfree_skb(this);
3641                         } while (skb);
3642                 }
3643                 if (!rx_buffer_info->page)
3644                         continue;
3645                 if (rx_buffer_info->page_dma) {
3646                         dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3647                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
3648                         rx_buffer_info->page_dma = 0;
3649                 }
3650                 put_page(rx_buffer_info->page);
3651                 rx_buffer_info->page = NULL;
3652                 rx_buffer_info->page_offset = 0;
3653         }
3654
3655         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3656         memset(rx_ring->rx_buffer_info, 0, size);
3657
3658         /* Zero out the descriptor ring */
3659         memset(rx_ring->desc, 0, rx_ring->size);
3660
3661         rx_ring->next_to_clean = 0;
3662         rx_ring->next_to_use = 0;
3663
3664         if (rx_ring->head)
3665                 writel(0, adapter->hw.hw_addr + rx_ring->head);
3666         if (rx_ring->tail)
3667                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
3668 }
3669
3670 /**
3671  * ixgbe_clean_tx_ring - Free Tx Buffers
3672  * @adapter: board private structure
3673  * @tx_ring: ring to be cleaned
3674  **/
3675 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
3676                                 struct ixgbe_ring *tx_ring)
3677 {
3678         struct ixgbe_tx_buffer *tx_buffer_info;
3679         unsigned long size;
3680         unsigned int i;
3681
3682         /* Free all the Tx ring sk_buffs */
3683
3684         for (i = 0; i < tx_ring->count; i++) {
3685                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3686                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3687         }
3688
3689         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3690         memset(tx_ring->tx_buffer_info, 0, size);
3691
3692         /* Zero out the descriptor ring */
3693         memset(tx_ring->desc, 0, tx_ring->size);
3694
3695         tx_ring->next_to_use = 0;
3696         tx_ring->next_to_clean = 0;
3697
3698         if (tx_ring->head)
3699                 writel(0, adapter->hw.hw_addr + tx_ring->head);
3700         if (tx_ring->tail)
3701                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
3702 }
3703
3704 /**
3705  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3706  * @adapter: board private structure
3707  **/
3708 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3709 {
3710         int i;
3711
3712         for (i = 0; i < adapter->num_rx_queues; i++)
3713                 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
3714 }
3715
3716 /**
3717  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3718  * @adapter: board private structure
3719  **/
3720 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3721 {
3722         int i;
3723
3724         for (i = 0; i < adapter->num_tx_queues; i++)
3725                 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
3726 }
3727
3728 void ixgbe_down(struct ixgbe_adapter *adapter)
3729 {
3730         struct net_device *netdev = adapter->netdev;
3731         struct ixgbe_hw *hw = &adapter->hw;
3732         u32 rxctrl;
3733         u32 txdctl;
3734         int i, j;
3735
3736         /* signal that we are down to the interrupt handler */
3737         set_bit(__IXGBE_DOWN, &adapter->state);
3738
3739         /* disable receive for all VFs and wait one second */
3740         if (adapter->num_vfs) {
3741                 /* ping all the active vfs to let them know we are going down */
3742                 ixgbe_ping_all_vfs(adapter);
3743
3744                 /* Disable all VFTE/VFRE TX/RX */
3745                 ixgbe_disable_tx_rx(adapter);
3746
3747                 /* Mark all the VFs as inactive */
3748                 for (i = 0 ; i < adapter->num_vfs; i++)
3749                         adapter->vfinfo[i].clear_to_send = 0;
3750         }
3751
3752         /* disable receives */
3753         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3754         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3755
3756         IXGBE_WRITE_FLUSH(hw);
3757         msleep(10);
3758
3759         netif_tx_stop_all_queues(netdev);
3760
3761         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3762         del_timer_sync(&adapter->sfp_timer);
3763         del_timer_sync(&adapter->watchdog_timer);
3764         cancel_work_sync(&adapter->watchdog_task);
3765
3766         netif_carrier_off(netdev);
3767         netif_tx_disable(netdev);
3768
3769         ixgbe_irq_disable(adapter);
3770
3771         ixgbe_napi_disable_all(adapter);
3772
3773         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3774             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3775                 cancel_work_sync(&adapter->fdir_reinit_task);
3776
3777         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3778                 cancel_work_sync(&adapter->check_overtemp_task);
3779
3780         /* disable transmits in the hardware now that interrupts are off */
3781         for (i = 0; i < adapter->num_tx_queues; i++) {
3782                 j = adapter->tx_ring[i]->reg_idx;
3783                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3784                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3785                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3786         }
3787         /* Disable the Tx DMA engine on 82599 */
3788         if (hw->mac.type == ixgbe_mac_82599EB)
3789                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3790                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3791                                  ~IXGBE_DMATXCTL_TE));
3792
3793         /* power down the optics */
3794         if (hw->phy.multispeed_fiber)
3795                 hw->mac.ops.disable_tx_laser(hw);
3796
3797         /* clear n-tuple filters that are cached */
3798         ethtool_ntuple_flush(netdev);
3799
3800         if (!pci_channel_offline(adapter->pdev))
3801                 ixgbe_reset(adapter);
3802         ixgbe_clean_all_tx_rings(adapter);
3803         ixgbe_clean_all_rx_rings(adapter);
3804
3805 #ifdef CONFIG_IXGBE_DCA
3806         /* since we reset the hardware DCA settings were cleared */
3807         ixgbe_setup_dca(adapter);
3808 #endif
3809 }
3810
3811 /**
3812  * ixgbe_poll - NAPI Rx polling callback
3813  * @napi: structure for representing this polling device
3814  * @budget: how many packets driver is allowed to clean
3815  *
3816  * This function is used for legacy and MSI, NAPI mode
3817  **/
3818 static int ixgbe_poll(struct napi_struct *napi, int budget)
3819 {
3820         struct ixgbe_q_vector *q_vector =
3821                                 container_of(napi, struct ixgbe_q_vector, napi);
3822         struct ixgbe_adapter *adapter = q_vector->adapter;
3823         int tx_clean_complete, work_done = 0;
3824
3825 #ifdef CONFIG_IXGBE_DCA
3826         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3827                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3828                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
3829         }
3830 #endif
3831
3832         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3833         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
3834
3835         if (!tx_clean_complete)
3836                 work_done = budget;
3837
3838         /* If budget not fully consumed, exit the polling mode */
3839         if (work_done < budget) {
3840                 napi_complete(napi);
3841                 if (adapter->rx_itr_setting & 1)
3842                         ixgbe_set_itr(adapter);
3843                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3844                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3845         }
3846         return work_done;
3847 }
3848
3849 /**
3850  * ixgbe_tx_timeout - Respond to a Tx Hang
3851  * @netdev: network interface device structure
3852  **/
3853 static void ixgbe_tx_timeout(struct net_device *netdev)
3854 {
3855         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3856
3857         /* Do the reset outside of interrupt context */
3858         schedule_work(&adapter->reset_task);
3859 }
3860
3861 static void ixgbe_reset_task(struct work_struct *work)
3862 {
3863         struct ixgbe_adapter *adapter;
3864         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3865
3866         /* If we're already down or resetting, just bail */
3867         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3868             test_bit(__IXGBE_RESETTING, &adapter->state))
3869                 return;
3870
3871         adapter->tx_timeout_count++;
3872
3873         ixgbe_dump(adapter);
3874         netdev_err(adapter->netdev, "Reset adapter\n");
3875         ixgbe_reinit_locked(adapter);
3876 }
3877
3878 #ifdef CONFIG_IXGBE_DCB
3879 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3880 {
3881         bool ret = false;
3882         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3883
3884         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3885                 return ret;
3886
3887         f->mask = 0x7 << 3;
3888         adapter->num_rx_queues = f->indices;
3889         adapter->num_tx_queues = f->indices;
3890         ret = true;
3891
3892         return ret;
3893 }
3894 #endif
3895
3896 /**
3897  * ixgbe_set_rss_queues: Allocate queues for RSS
3898  * @adapter: board private structure to initialize
3899  *
3900  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3901  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3902  *
3903  **/
3904 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3905 {
3906         bool ret = false;
3907         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3908
3909         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3910                 f->mask = 0xF;
3911                 adapter->num_rx_queues = f->indices;
3912                 adapter->num_tx_queues = f->indices;
3913                 ret = true;
3914         } else {
3915                 ret = false;
3916         }
3917
3918         return ret;
3919 }
3920
3921 /**
3922  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3923  * @adapter: board private structure to initialize
3924  *
3925  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3926  * to the original CPU that initiated the Tx session.  This runs in addition
3927  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3928  * Rx load across CPUs using RSS.
3929  *
3930  **/
3931 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3932 {
3933         bool ret = false;
3934         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3935
3936         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3937         f_fdir->mask = 0;
3938
3939         /* Flow Director must have RSS enabled */
3940         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3941             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3942              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3943                 adapter->num_tx_queues = f_fdir->indices;
3944                 adapter->num_rx_queues = f_fdir->indices;
3945                 ret = true;
3946         } else {
3947                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3948                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3949         }
3950         return ret;
3951 }
3952
3953 #ifdef IXGBE_FCOE
3954 /**
3955  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3956  * @adapter: board private structure to initialize
3957  *
3958  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3959  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3960  * rx queues out of the max number of rx queues, instead, it is used as the
3961  * index of the first rx queue used by FCoE.
3962  *
3963  **/
3964 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3965 {
3966         bool ret = false;
3967         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3968
3969         f->indices = min((int)num_online_cpus(), f->indices);
3970         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3971                 adapter->num_rx_queues = 1;
3972                 adapter->num_tx_queues = 1;
3973 #ifdef CONFIG_IXGBE_DCB
3974                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3975                         e_info(probe, "FCoE enabled with DCB\n");
3976                         ixgbe_set_dcb_queues(adapter);
3977                 }
3978 #endif
3979                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3980                         e_info(probe, "FCoE enabled with RSS\n");
3981                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3982                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3983                                 ixgbe_set_fdir_queues(adapter);
3984                         else
3985                                 ixgbe_set_rss_queues(adapter);
3986                 }
3987                 /* adding FCoE rx rings to the end */
3988                 f->mask = adapter->num_rx_queues;
3989                 adapter->num_rx_queues += f->indices;
3990                 adapter->num_tx_queues += f->indices;
3991
3992                 ret = true;
3993         }
3994
3995         return ret;
3996 }
3997
3998 #endif /* IXGBE_FCOE */
3999 /**
4000  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4001  * @adapter: board private structure to initialize
4002  *
4003  * IOV doesn't actually use anything, so just NAK the
4004  * request for now and let the other queue routines
4005  * figure out what to do.
4006  */
4007 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4008 {
4009         return false;
4010 }
4011
4012 /*
4013  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4014  * @adapter: board private structure to initialize
4015  *
4016  * This is the top level queue allocation routine.  The order here is very
4017  * important, starting with the "most" number of features turned on at once,
4018  * and ending with the smallest set of features.  This way large combinations
4019  * can be allocated if they're turned on, and smaller combinations are the
4020  * fallthrough conditions.
4021  *
4022  **/
4023 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4024 {
4025         /* Start with base case */
4026         adapter->num_rx_queues = 1;
4027         adapter->num_tx_queues = 1;
4028         adapter->num_rx_pools = adapter->num_rx_queues;
4029         adapter->num_rx_queues_per_pool = 1;
4030
4031         if (ixgbe_set_sriov_queues(adapter))
4032                 return;
4033
4034 #ifdef IXGBE_FCOE
4035         if (ixgbe_set_fcoe_queues(adapter))
4036                 goto done;
4037
4038 #endif /* IXGBE_FCOE */
4039 #ifdef CONFIG_IXGBE_DCB
4040         if (ixgbe_set_dcb_queues(adapter))
4041                 goto done;
4042
4043 #endif
4044         if (ixgbe_set_fdir_queues(adapter))
4045                 goto done;
4046
4047         if (ixgbe_set_rss_queues(adapter))
4048                 goto done;
4049
4050         /* fallback to base case */
4051         adapter->num_rx_queues = 1;
4052         adapter->num_tx_queues = 1;
4053
4054 done:
4055         /* Notify the stack of the (possibly) reduced Tx Queue count. */
4056         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4057 }
4058
4059 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4060                                        int vectors)
4061 {
4062         int err, vector_threshold;
4063
4064         /* We'll want at least 3 (vector_threshold):
4065          * 1) TxQ[0] Cleanup
4066          * 2) RxQ[0] Cleanup
4067          * 3) Other (Link Status Change, etc.)
4068          * 4) TCP Timer (optional)
4069          */
4070         vector_threshold = MIN_MSIX_COUNT;
4071
4072         /* The more we get, the more we will assign to Tx/Rx Cleanup
4073          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4074          * Right now, we simply care about how many we'll get; we'll
4075          * set them up later while requesting irq's.
4076          */
4077         while (vectors >= vector_threshold) {
4078                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4079                                       vectors);
4080                 if (!err) /* Success in acquiring all requested vectors. */
4081                         break;
4082                 else if (err < 0)
4083                         vectors = 0; /* Nasty failure, quit now */
4084                 else /* err == number of vectors we should try again with */
4085                         vectors = err;
4086         }
4087
4088         if (vectors < vector_threshold) {
4089                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4090                  * This just means we'll go with either a single MSI
4091                  * vector or fall back to legacy interrupts.
4092                  */
4093                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4094                              "Unable to allocate MSI-X interrupts\n");
4095                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4096                 kfree(adapter->msix_entries);
4097                 adapter->msix_entries = NULL;
4098         } else {
4099                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4100                 /*
4101                  * Adjust for only the vectors we'll use, which is minimum
4102                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4103                  * vectors we were allocated.
4104                  */
4105                 adapter->num_msix_vectors = min(vectors,
4106                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4107         }
4108 }
4109
4110 /**
4111  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4112  * @adapter: board private structure to initialize
4113  *
4114  * Cache the descriptor ring offsets for RSS to the assigned rings.
4115  *
4116  **/
4117 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4118 {
4119         int i;
4120         bool ret = false;
4121
4122         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4123                 for (i = 0; i < adapter->num_rx_queues; i++)
4124                         adapter->rx_ring[i]->reg_idx = i;
4125                 for (i = 0; i < adapter->num_tx_queues; i++)
4126                         adapter->tx_ring[i]->reg_idx = i;
4127                 ret = true;
4128         } else {
4129                 ret = false;
4130         }
4131
4132         return ret;
4133 }
4134
4135 #ifdef CONFIG_IXGBE_DCB
4136 /**
4137  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4138  * @adapter: board private structure to initialize
4139  *
4140  * Cache the descriptor ring offsets for DCB to the assigned rings.
4141  *
4142  **/
4143 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4144 {
4145         int i;
4146         bool ret = false;
4147         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4148
4149         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4150                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
4151                         /* the number of queues is assumed to be symmetric */
4152                         for (i = 0; i < dcb_i; i++) {
4153                                 adapter->rx_ring[i]->reg_idx = i << 3;
4154                                 adapter->tx_ring[i]->reg_idx = i << 2;
4155                         }
4156                         ret = true;
4157                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
4158                         if (dcb_i == 8) {
4159                                 /*
4160                                  * Tx TC0 starts at: descriptor queue 0
4161                                  * Tx TC1 starts at: descriptor queue 32
4162                                  * Tx TC2 starts at: descriptor queue 64
4163                                  * Tx TC3 starts at: descriptor queue 80
4164                                  * Tx TC4 starts at: descriptor queue 96
4165                                  * Tx TC5 starts at: descriptor queue 104
4166                                  * Tx TC6 starts at: descriptor queue 112
4167                                  * Tx TC7 starts at: descriptor queue 120
4168                                  *
4169                                  * Rx TC0-TC7 are offset by 16 queues each
4170                                  */
4171                                 for (i = 0; i < 3; i++) {
4172                                         adapter->tx_ring[i]->reg_idx = i << 5;
4173                                         adapter->rx_ring[i]->reg_idx = i << 4;
4174                                 }
4175                                 for ( ; i < 5; i++) {
4176                                         adapter->tx_ring[i]->reg_idx =
4177                                                                  ((i + 2) << 4);
4178                                         adapter->rx_ring[i]->reg_idx = i << 4;
4179                                 }
4180                                 for ( ; i < dcb_i; i++) {
4181                                         adapter->tx_ring[i]->reg_idx =
4182                                                                  ((i + 8) << 3);
4183                                         adapter->rx_ring[i]->reg_idx = i << 4;
4184                                 }
4185
4186                                 ret = true;
4187                         } else if (dcb_i == 4) {
4188                                 /*
4189                                  * Tx TC0 starts at: descriptor queue 0
4190                                  * Tx TC1 starts at: descriptor queue 64
4191                                  * Tx TC2 starts at: descriptor queue 96
4192                                  * Tx TC3 starts at: descriptor queue 112
4193                                  *
4194                                  * Rx TC0-TC3 are offset by 32 queues each
4195                                  */
4196                                 adapter->tx_ring[0]->reg_idx = 0;
4197                                 adapter->tx_ring[1]->reg_idx = 64;
4198                                 adapter->tx_ring[2]->reg_idx = 96;
4199                                 adapter->tx_ring[3]->reg_idx = 112;
4200                                 for (i = 0 ; i < dcb_i; i++)
4201                                         adapter->rx_ring[i]->reg_idx = i << 5;
4202
4203                                 ret = true;
4204                         } else {
4205                                 ret = false;
4206                         }
4207                 } else {
4208                         ret = false;
4209                 }
4210         } else {
4211                 ret = false;
4212         }
4213
4214         return ret;
4215 }
4216 #endif
4217
4218 /**
4219  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4220  * @adapter: board private structure to initialize
4221  *
4222  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4223  *
4224  **/
4225 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4226 {
4227         int i;
4228         bool ret = false;
4229
4230         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4231             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4232              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4233                 for (i = 0; i < adapter->num_rx_queues; i++)
4234                         adapter->rx_ring[i]->reg_idx = i;
4235                 for (i = 0; i < adapter->num_tx_queues; i++)
4236                         adapter->tx_ring[i]->reg_idx = i;
4237                 ret = true;
4238         }
4239
4240         return ret;
4241 }
4242
4243 #ifdef IXGBE_FCOE
4244 /**
4245  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4246  * @adapter: board private structure to initialize
4247  *
4248  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4249  *
4250  */
4251 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4252 {
4253         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
4254         bool ret = false;
4255         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4256
4257         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4258 #ifdef CONFIG_IXGBE_DCB
4259                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4260                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4261
4262                         ixgbe_cache_ring_dcb(adapter);
4263                         /* find out queues in TC for FCoE */
4264                         fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4265                         fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4266                         /*
4267                          * In 82599, the number of Tx queues for each traffic
4268                          * class for both 8-TC and 4-TC modes are:
4269                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4270                          * 8 TCs:  32  32  16  16   8   8   8   8
4271                          * 4 TCs:  64  64  32  32
4272                          * We have max 8 queues for FCoE, where 8 the is
4273                          * FCoE redirection table size. If TC for FCoE is
4274                          * less than or equal to TC3, we have enough queues
4275                          * to add max of 8 queues for FCoE, so we start FCoE
4276                          * tx descriptor from the next one, i.e., reg_idx + 1.
4277                          * If TC for FCoE is above TC3, implying 8 TC mode,
4278                          * and we need 8 for FCoE, we have to take all queues
4279                          * in that traffic class for FCoE.
4280                          */
4281                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4282                                 fcoe_tx_i--;
4283                 }
4284 #endif /* CONFIG_IXGBE_DCB */
4285                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4286                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4287                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4288                                 ixgbe_cache_ring_fdir(adapter);
4289                         else
4290                                 ixgbe_cache_ring_rss(adapter);
4291
4292                         fcoe_rx_i = f->mask;
4293                         fcoe_tx_i = f->mask;
4294                 }
4295                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4296                         adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4297                         adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4298                 }
4299                 ret = true;
4300         }
4301         return ret;
4302 }
4303
4304 #endif /* IXGBE_FCOE */
4305 /**
4306  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4307  * @adapter: board private structure to initialize
4308  *
4309  * SR-IOV doesn't use any descriptor rings but changes the default if
4310  * no other mapping is used.
4311  *
4312  */
4313 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4314 {
4315         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4316         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4317         if (adapter->num_vfs)
4318                 return true;
4319         else
4320                 return false;
4321 }
4322
4323 /**
4324  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4325  * @adapter: board private structure to initialize
4326  *
4327  * Once we know the feature-set enabled for the device, we'll cache
4328  * the register offset the descriptor ring is assigned to.
4329  *
4330  * Note, the order the various feature calls is important.  It must start with
4331  * the "most" features enabled at the same time, then trickle down to the
4332  * least amount of features turned on at once.
4333  **/
4334 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4335 {
4336         /* start with default case */
4337         adapter->rx_ring[0]->reg_idx = 0;
4338         adapter->tx_ring[0]->reg_idx = 0;
4339
4340         if (ixgbe_cache_ring_sriov(adapter))
4341                 return;
4342
4343 #ifdef IXGBE_FCOE
4344         if (ixgbe_cache_ring_fcoe(adapter))
4345                 return;
4346
4347 #endif /* IXGBE_FCOE */
4348 #ifdef CONFIG_IXGBE_DCB
4349         if (ixgbe_cache_ring_dcb(adapter))
4350                 return;
4351
4352 #endif
4353         if (ixgbe_cache_ring_fdir(adapter))
4354                 return;
4355
4356         if (ixgbe_cache_ring_rss(adapter))
4357                 return;
4358 }
4359
4360 /**
4361  * ixgbe_alloc_queues - Allocate memory for all rings
4362  * @adapter: board private structure to initialize
4363  *
4364  * We allocate one ring per queue at run-time since we don't know the
4365  * number of queues at compile-time.  The polling_netdev array is
4366  * intended for Multiqueue, but should work fine with a single queue.
4367  **/
4368 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4369 {
4370         int i;
4371         int orig_node = adapter->node;
4372
4373         for (i = 0; i < adapter->num_tx_queues; i++) {
4374                 struct ixgbe_ring *ring = adapter->tx_ring[i];
4375                 if (orig_node == -1) {
4376                         int cur_node = next_online_node(adapter->node);
4377                         if (cur_node == MAX_NUMNODES)
4378                                 cur_node = first_online_node;
4379                         adapter->node = cur_node;
4380                 }
4381                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4382                                     adapter->node);
4383                 if (!ring)
4384                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4385                 if (!ring)
4386                         goto err_tx_ring_allocation;
4387                 ring->count = adapter->tx_ring_count;
4388                 ring->queue_index = i;
4389                 ring->numa_node = adapter->node;
4390
4391                 adapter->tx_ring[i] = ring;
4392         }
4393
4394         /* Restore the adapter's original node */
4395         adapter->node = orig_node;
4396
4397         for (i = 0; i < adapter->num_rx_queues; i++) {
4398                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4399                 if (orig_node == -1) {
4400                         int cur_node = next_online_node(adapter->node);
4401                         if (cur_node == MAX_NUMNODES)
4402                                 cur_node = first_online_node;
4403                         adapter->node = cur_node;
4404                 }
4405                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4406                                     adapter->node);
4407                 if (!ring)
4408                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4409                 if (!ring)
4410                         goto err_rx_ring_allocation;
4411                 ring->count = adapter->rx_ring_count;
4412                 ring->queue_index = i;
4413                 ring->numa_node = adapter->node;
4414
4415                 adapter->rx_ring[i] = ring;
4416         }
4417
4418         /* Restore the adapter's original node */
4419         adapter->node = orig_node;
4420
4421         ixgbe_cache_ring_register(adapter);
4422
4423         return 0;
4424
4425 err_rx_ring_allocation:
4426         for (i = 0; i < adapter->num_tx_queues; i++)
4427                 kfree(adapter->tx_ring[i]);
4428 err_tx_ring_allocation:
4429         return -ENOMEM;
4430 }
4431
4432 /**
4433  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4434  * @adapter: board private structure to initialize
4435  *
4436  * Attempt to configure the interrupts using the best available
4437  * capabilities of the hardware and the kernel.
4438  **/
4439 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4440 {
4441         struct ixgbe_hw *hw = &adapter->hw;
4442         int err = 0;
4443         int vector, v_budget;
4444
4445         /*
4446          * It's easy to be greedy for MSI-X vectors, but it really
4447          * doesn't do us much good if we have a lot more vectors
4448          * than CPU's.  So let's be conservative and only ask for
4449          * (roughly) the same number of vectors as there are CPU's.
4450          */
4451         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4452                        (int)num_online_cpus()) + NON_Q_VECTORS;
4453
4454         /*
4455          * At the same time, hardware can only support a maximum of
4456          * hw.mac->max_msix_vectors vectors.  With features
4457          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4458          * descriptor queues supported by our device.  Thus, we cap it off in
4459          * those rare cases where the cpu count also exceeds our vector limit.
4460          */
4461         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4462
4463         /* A failure in MSI-X entry allocation isn't fatal, but it does
4464          * mean we disable MSI-X capabilities of the adapter. */
4465         adapter->msix_entries = kcalloc(v_budget,
4466                                         sizeof(struct msix_entry), GFP_KERNEL);
4467         if (adapter->msix_entries) {
4468                 for (vector = 0; vector < v_budget; vector++)
4469                         adapter->msix_entries[vector].entry = vector;
4470
4471                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4472
4473                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4474                         goto out;
4475         }
4476
4477         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4478         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4479         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4480         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4481         adapter->atr_sample_rate = 0;
4482         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4483                 ixgbe_disable_sriov(adapter);
4484
4485         ixgbe_set_num_queues(adapter);
4486
4487         err = pci_enable_msi(adapter->pdev);
4488         if (!err) {
4489                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4490         } else {
4491                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4492                              "Unable to allocate MSI interrupt, "
4493                              "falling back to legacy.  Error: %d\n", err);
4494                 /* reset err */
4495                 err = 0;
4496         }
4497
4498 out:
4499         return err;
4500 }
4501
4502 /**
4503  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4504  * @adapter: board private structure to initialize
4505  *
4506  * We allocate one q_vector per queue interrupt.  If allocation fails we
4507  * return -ENOMEM.
4508  **/
4509 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4510 {
4511         int q_idx, num_q_vectors;
4512         struct ixgbe_q_vector *q_vector;
4513         int napi_vectors;
4514         int (*poll)(struct napi_struct *, int);
4515
4516         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4517                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4518                 napi_vectors = adapter->num_rx_queues;
4519                 poll = &ixgbe_clean_rxtx_many;
4520         } else {
4521                 num_q_vectors = 1;
4522                 napi_vectors = 1;
4523                 poll = &ixgbe_poll;
4524         }
4525
4526         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4527                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4528                                         GFP_KERNEL, adapter->node);
4529                 if (!q_vector)
4530                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4531                                            GFP_KERNEL);
4532                 if (!q_vector)
4533                         goto err_out;
4534                 q_vector->adapter = adapter;
4535                 if (q_vector->txr_count && !q_vector->rxr_count)
4536                         q_vector->eitr = adapter->tx_eitr_param;
4537                 else
4538                         q_vector->eitr = adapter->rx_eitr_param;
4539                 q_vector->v_idx = q_idx;
4540                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4541                 adapter->q_vector[q_idx] = q_vector;
4542         }
4543
4544         return 0;
4545
4546 err_out:
4547         while (q_idx) {
4548                 q_idx--;
4549                 q_vector = adapter->q_vector[q_idx];
4550                 netif_napi_del(&q_vector->napi);
4551                 kfree(q_vector);
4552                 adapter->q_vector[q_idx] = NULL;
4553         }
4554         return -ENOMEM;
4555 }
4556
4557 /**
4558  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4559  * @adapter: board private structure to initialize
4560  *
4561  * This function frees the memory allocated to the q_vectors.  In addition if
4562  * NAPI is enabled it will delete any references to the NAPI struct prior
4563  * to freeing the q_vector.
4564  **/
4565 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4566 {
4567         int q_idx, num_q_vectors;
4568
4569         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4570                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4571         else
4572                 num_q_vectors = 1;
4573
4574         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4575                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4576                 adapter->q_vector[q_idx] = NULL;
4577                 netif_napi_del(&q_vector->napi);
4578                 kfree(q_vector);
4579         }
4580 }
4581
4582 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4583 {
4584         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4585                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4586                 pci_disable_msix(adapter->pdev);
4587                 kfree(adapter->msix_entries);
4588                 adapter->msix_entries = NULL;
4589         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4590                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4591                 pci_disable_msi(adapter->pdev);
4592         }
4593 }
4594
4595 /**
4596  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4597  * @adapter: board private structure to initialize
4598  *
4599  * We determine which interrupt scheme to use based on...
4600  * - Kernel support (MSI, MSI-X)
4601  *   - which can be user-defined (via MODULE_PARAM)
4602  * - Hardware queue count (num_*_queues)
4603  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4604  **/
4605 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4606 {
4607         int err;
4608
4609         /* Number of supported queues */
4610         ixgbe_set_num_queues(adapter);
4611
4612         err = ixgbe_set_interrupt_capability(adapter);
4613         if (err) {
4614                 e_dev_err("Unable to setup interrupt capabilities\n");
4615                 goto err_set_interrupt;
4616         }
4617
4618         err = ixgbe_alloc_q_vectors(adapter);
4619         if (err) {
4620                 e_dev_err("Unable to allocate memory for queue vectors\n");
4621                 goto err_alloc_q_vectors;
4622         }
4623
4624         err = ixgbe_alloc_queues(adapter);
4625         if (err) {
4626                 e_dev_err("Unable to allocate memory for queues\n");
4627                 goto err_alloc_queues;
4628         }
4629
4630         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4631                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4632                    adapter->num_rx_queues, adapter->num_tx_queues);
4633
4634         set_bit(__IXGBE_DOWN, &adapter->state);
4635
4636         return 0;
4637
4638 err_alloc_queues:
4639         ixgbe_free_q_vectors(adapter);
4640 err_alloc_q_vectors:
4641         ixgbe_reset_interrupt_capability(adapter);
4642 err_set_interrupt:
4643         return err;
4644 }
4645
4646 /**
4647  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4648  * @adapter: board private structure to clear interrupt scheme on
4649  *
4650  * We go through and clear interrupt specific resources and reset the structure
4651  * to pre-load conditions
4652  **/
4653 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4654 {
4655         int i;
4656
4657         for (i = 0; i < adapter->num_tx_queues; i++) {
4658                 kfree(adapter->tx_ring[i]);
4659                 adapter->tx_ring[i] = NULL;
4660         }
4661         for (i = 0; i < adapter->num_rx_queues; i++) {
4662                 kfree(adapter->rx_ring[i]);
4663                 adapter->rx_ring[i] = NULL;
4664         }
4665
4666         ixgbe_free_q_vectors(adapter);
4667         ixgbe_reset_interrupt_capability(adapter);
4668 }
4669
4670 /**
4671  * ixgbe_sfp_timer - worker thread to find a missing module
4672  * @data: pointer to our adapter struct
4673  **/
4674 static void ixgbe_sfp_timer(unsigned long data)
4675 {
4676         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4677
4678         /*
4679          * Do the sfp_timer outside of interrupt context due to the
4680          * delays that sfp+ detection requires
4681          */
4682         schedule_work(&adapter->sfp_task);
4683 }
4684
4685 /**
4686  * ixgbe_sfp_task - worker thread to find a missing module
4687  * @work: pointer to work_struct containing our data
4688  **/
4689 static void ixgbe_sfp_task(struct work_struct *work)
4690 {
4691         struct ixgbe_adapter *adapter = container_of(work,
4692                                                      struct ixgbe_adapter,
4693                                                      sfp_task);
4694         struct ixgbe_hw *hw = &adapter->hw;
4695
4696         if ((hw->phy.type == ixgbe_phy_nl) &&
4697             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4698                 s32 ret = hw->phy.ops.identify_sfp(hw);
4699                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4700                         goto reschedule;
4701                 ret = hw->phy.ops.reset(hw);
4702                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4703                         e_dev_err("failed to initialize because an unsupported "
4704                                   "SFP+ module type was detected.\n");
4705                         e_dev_err("Reload the driver after installing a "
4706                                   "supported module.\n");
4707                         unregister_netdev(adapter->netdev);
4708                 } else {
4709                         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
4710                 }
4711                 /* don't need this routine any more */
4712                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4713         }
4714         return;
4715 reschedule:
4716         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4717                 mod_timer(&adapter->sfp_timer,
4718                           round_jiffies(jiffies + (2 * HZ)));
4719 }
4720
4721 /**
4722  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4723  * @adapter: board private structure to initialize
4724  *
4725  * ixgbe_sw_init initializes the Adapter private data structure.
4726  * Fields are initialized based on PCI device information and
4727  * OS network device settings (MTU size).
4728  **/
4729 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4730 {
4731         struct ixgbe_hw *hw = &adapter->hw;
4732         struct pci_dev *pdev = adapter->pdev;
4733         struct net_device *dev = adapter->netdev;
4734         unsigned int rss;
4735 #ifdef CONFIG_IXGBE_DCB
4736         int j;
4737         struct tc_configuration *tc;
4738 #endif
4739
4740         /* PCI config space info */
4741
4742         hw->vendor_id = pdev->vendor;
4743         hw->device_id = pdev->device;
4744         hw->revision_id = pdev->revision;
4745         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4746         hw->subsystem_device_id = pdev->subsystem_device;
4747
4748         /* Set capability flags */
4749         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4750         adapter->ring_feature[RING_F_RSS].indices = rss;
4751         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4752         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4753         if (hw->mac.type == ixgbe_mac_82598EB) {
4754                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4755                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4756                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4757         } else if (hw->mac.type == ixgbe_mac_82599EB) {
4758                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4759                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4760                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4761                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4762                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4763                 if (dev->features & NETIF_F_NTUPLE) {
4764                         /* Flow Director perfect filter enabled */
4765                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4766                         adapter->atr_sample_rate = 0;
4767                         spin_lock_init(&adapter->fdir_perfect_lock);
4768                 } else {
4769                         /* Flow Director hash filters enabled */
4770                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4771                         adapter->atr_sample_rate = 20;
4772                 }
4773                 adapter->ring_feature[RING_F_FDIR].indices =
4774                                                          IXGBE_MAX_FDIR_INDICES;
4775                 adapter->fdir_pballoc = 0;
4776 #ifdef IXGBE_FCOE
4777                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4778                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4779                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4780 #ifdef CONFIG_IXGBE_DCB
4781                 /* Default traffic class to use for FCoE */
4782                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4783                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4784 #endif
4785 #endif /* IXGBE_FCOE */
4786         }
4787
4788 #ifdef CONFIG_IXGBE_DCB
4789         /* Configure DCB traffic classes */
4790         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4791                 tc = &adapter->dcb_cfg.tc_config[j];
4792                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4793                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4794                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4795                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4796                 tc->dcb_pfc = pfc_disabled;
4797         }
4798         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4799         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4800         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4801         adapter->dcb_cfg.pfc_mode_enable = false;
4802         adapter->dcb_cfg.round_robin_enable = false;
4803         adapter->dcb_set_bitmap = 0x00;
4804         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4805                            adapter->ring_feature[RING_F_DCB].indices);
4806
4807 #endif
4808
4809         /* default flow control settings */
4810         hw->fc.requested_mode = ixgbe_fc_full;
4811         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
4812 #ifdef CONFIG_DCB
4813         adapter->last_lfc_mode = hw->fc.current_mode;
4814 #endif
4815         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4816         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4817         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4818         hw->fc.send_xon = true;
4819         hw->fc.disable_fc_autoneg = false;
4820
4821         /* enable itr by default in dynamic mode */
4822         adapter->rx_itr_setting = 1;
4823         adapter->rx_eitr_param = 20000;
4824         adapter->tx_itr_setting = 1;
4825         adapter->tx_eitr_param = 10000;
4826
4827         /* set defaults for eitr in MegaBytes */
4828         adapter->eitr_low = 10;
4829         adapter->eitr_high = 20;
4830
4831         /* set default ring sizes */
4832         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4833         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4834
4835         /* initialize eeprom parameters */
4836         if (ixgbe_init_eeprom_params_generic(hw)) {
4837                 e_dev_err("EEPROM initialization failed\n");
4838                 return -EIO;
4839         }
4840
4841         /* enable rx csum by default */
4842         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4843
4844         /* get assigned NUMA node */
4845         adapter->node = dev_to_node(&pdev->dev);
4846
4847         set_bit(__IXGBE_DOWN, &adapter->state);
4848
4849         return 0;
4850 }
4851
4852 /**
4853  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4854  * @adapter: board private structure
4855  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4856  *
4857  * Return 0 on success, negative on failure
4858  **/
4859 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4860                              struct ixgbe_ring *tx_ring)
4861 {
4862         struct pci_dev *pdev = adapter->pdev;
4863         int size;
4864
4865         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4866         tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
4867         if (!tx_ring->tx_buffer_info)
4868                 tx_ring->tx_buffer_info = vmalloc(size);
4869         if (!tx_ring->tx_buffer_info)
4870                 goto err;
4871         memset(tx_ring->tx_buffer_info, 0, size);
4872
4873         /* round up to nearest 4K */
4874         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4875         tx_ring->size = ALIGN(tx_ring->size, 4096);
4876
4877         tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4878                                            &tx_ring->dma, GFP_KERNEL);
4879         if (!tx_ring->desc)
4880                 goto err;
4881
4882         tx_ring->next_to_use = 0;
4883         tx_ring->next_to_clean = 0;
4884         tx_ring->work_limit = tx_ring->count;
4885         return 0;
4886
4887 err:
4888         vfree(tx_ring->tx_buffer_info);
4889         tx_ring->tx_buffer_info = NULL;
4890         e_err(probe, "Unable to allocate memory for the Tx descriptor ring\n");
4891         return -ENOMEM;
4892 }
4893
4894 /**
4895  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4896  * @adapter: board private structure
4897  *
4898  * If this function returns with an error, then it's possible one or
4899  * more of the rings is populated (while the rest are not).  It is the
4900  * callers duty to clean those orphaned rings.
4901  *
4902  * Return 0 on success, negative on failure
4903  **/
4904 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4905 {
4906         int i, err = 0;
4907
4908         for (i = 0; i < adapter->num_tx_queues; i++) {
4909                 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
4910                 if (!err)
4911                         continue;
4912                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4913                 break;
4914         }
4915
4916         return err;
4917 }
4918
4919 /**
4920  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4921  * @adapter: board private structure
4922  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
4923  *
4924  * Returns 0 on success, negative on failure
4925  **/
4926 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4927                              struct ixgbe_ring *rx_ring)
4928 {
4929         struct pci_dev *pdev = adapter->pdev;
4930         int size;
4931
4932         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4933         rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4934         if (!rx_ring->rx_buffer_info)
4935                 rx_ring->rx_buffer_info = vmalloc(size);
4936         if (!rx_ring->rx_buffer_info) {
4937                 e_err(probe, "vmalloc allocation failed for the Rx "
4938                       "descriptor ring\n");
4939                 goto alloc_failed;
4940         }
4941         memset(rx_ring->rx_buffer_info, 0, size);
4942
4943         /* Round up to nearest 4K */
4944         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4945         rx_ring->size = ALIGN(rx_ring->size, 4096);
4946
4947         rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
4948                                            &rx_ring->dma, GFP_KERNEL);
4949
4950         if (!rx_ring->desc) {
4951                 e_err(probe, "Memory allocation failed for the Rx "
4952                       "descriptor ring\n");
4953                 vfree(rx_ring->rx_buffer_info);
4954                 goto alloc_failed;
4955         }
4956
4957         rx_ring->next_to_clean = 0;
4958         rx_ring->next_to_use = 0;
4959
4960         return 0;
4961
4962 alloc_failed:
4963         return -ENOMEM;
4964 }
4965
4966 /**
4967  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4968  * @adapter: board private structure
4969  *
4970  * If this function returns with an error, then it's possible one or
4971  * more of the rings is populated (while the rest are not).  It is the
4972  * callers duty to clean those orphaned rings.
4973  *
4974  * Return 0 on success, negative on failure
4975  **/
4976
4977 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4978 {
4979         int i, err = 0;
4980
4981         for (i = 0; i < adapter->num_rx_queues; i++) {
4982                 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
4983                 if (!err)
4984                         continue;
4985                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
4986                 break;
4987         }
4988
4989         return err;
4990 }
4991
4992 /**
4993  * ixgbe_free_tx_resources - Free Tx Resources per Queue
4994  * @adapter: board private structure
4995  * @tx_ring: Tx descriptor ring for a specific queue
4996  *
4997  * Free all transmit software resources
4998  **/
4999 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
5000                              struct ixgbe_ring *tx_ring)
5001 {
5002         struct pci_dev *pdev = adapter->pdev;
5003
5004         ixgbe_clean_tx_ring(adapter, tx_ring);
5005
5006         vfree(tx_ring->tx_buffer_info);
5007         tx_ring->tx_buffer_info = NULL;
5008
5009         dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
5010                           tx_ring->dma);
5011
5012         tx_ring->desc = NULL;
5013 }
5014
5015 /**
5016  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5017  * @adapter: board private structure
5018  *
5019  * Free all transmit software resources
5020  **/
5021 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5022 {
5023         int i;
5024
5025         for (i = 0; i < adapter->num_tx_queues; i++)
5026                 if (adapter->tx_ring[i]->desc)
5027                         ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
5028 }
5029
5030 /**
5031  * ixgbe_free_rx_resources - Free Rx Resources
5032  * @adapter: board private structure
5033  * @rx_ring: ring to clean the resources from
5034  *
5035  * Free all receive software resources
5036  **/
5037 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
5038                              struct ixgbe_ring *rx_ring)
5039 {
5040         struct pci_dev *pdev = adapter->pdev;
5041
5042         ixgbe_clean_rx_ring(adapter, rx_ring);
5043
5044         vfree(rx_ring->rx_buffer_info);
5045         rx_ring->rx_buffer_info = NULL;
5046
5047         dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
5048                           rx_ring->dma);
5049
5050         rx_ring->desc = NULL;
5051 }
5052
5053 /**
5054  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5055  * @adapter: board private structure
5056  *
5057  * Free all receive software resources
5058  **/
5059 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5060 {
5061         int i;
5062
5063         for (i = 0; i < adapter->num_rx_queues; i++)
5064                 if (adapter->rx_ring[i]->desc)
5065                         ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
5066 }
5067
5068 /**
5069  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5070  * @netdev: network interface device structure
5071  * @new_mtu: new value for maximum frame size
5072  *
5073  * Returns 0 on success, negative on failure
5074  **/
5075 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5076 {
5077         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5078         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5079
5080         /* MTU < 68 is an error and causes problems on some kernels */
5081         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5082                 return -EINVAL;
5083
5084         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5085         /* must set new MTU before calling down or up */
5086         netdev->mtu = new_mtu;
5087
5088         if (netif_running(netdev))
5089                 ixgbe_reinit_locked(adapter);
5090
5091         return 0;
5092 }
5093
5094 /**
5095  * ixgbe_open - Called when a network interface is made active
5096  * @netdev: network interface device structure
5097  *
5098  * Returns 0 on success, negative value on failure
5099  *
5100  * The open entry point is called when a network interface is made
5101  * active by the system (IFF_UP).  At this point all resources needed
5102  * for transmit and receive operations are allocated, the interrupt
5103  * handler is registered with the OS, the watchdog timer is started,
5104  * and the stack is notified that the interface is ready.
5105  **/
5106 static int ixgbe_open(struct net_device *netdev)
5107 {
5108         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5109         int err;
5110
5111         /* disallow open during test */
5112         if (test_bit(__IXGBE_TESTING, &adapter->state))
5113                 return -EBUSY;
5114
5115         netif_carrier_off(netdev);
5116
5117         /* allocate transmit descriptors */
5118         err = ixgbe_setup_all_tx_resources(adapter);
5119         if (err)
5120                 goto err_setup_tx;
5121
5122         /* allocate receive descriptors */
5123         err = ixgbe_setup_all_rx_resources(adapter);
5124         if (err)
5125                 goto err_setup_rx;
5126
5127         ixgbe_configure(adapter);
5128
5129         err = ixgbe_request_irq(adapter);
5130         if (err)
5131                 goto err_req_irq;
5132
5133         err = ixgbe_up_complete(adapter);
5134         if (err)
5135                 goto err_up;
5136
5137         netif_tx_start_all_queues(netdev);
5138
5139         return 0;
5140
5141 err_up:
5142         ixgbe_release_hw_control(adapter);
5143         ixgbe_free_irq(adapter);
5144 err_req_irq:
5145 err_setup_rx:
5146         ixgbe_free_all_rx_resources(adapter);
5147 err_setup_tx:
5148         ixgbe_free_all_tx_resources(adapter);
5149         ixgbe_reset(adapter);
5150
5151         return err;
5152 }
5153
5154 /**
5155  * ixgbe_close - Disables a network interface
5156  * @netdev: network interface device structure
5157  *
5158  * Returns 0, this is not allowed to fail
5159  *
5160  * The close entry point is called when an interface is de-activated
5161  * by the OS.  The hardware is still under the drivers control, but
5162  * needs to be disabled.  A global MAC reset is issued to stop the
5163  * hardware, and all transmit and receive resources are freed.
5164  **/
5165 static int ixgbe_close(struct net_device *netdev)
5166 {
5167         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5168
5169         ixgbe_down(adapter);
5170         ixgbe_free_irq(adapter);
5171
5172         ixgbe_free_all_tx_resources(adapter);
5173         ixgbe_free_all_rx_resources(adapter);
5174
5175         ixgbe_release_hw_control(adapter);
5176
5177         return 0;
5178 }
5179
5180 #ifdef CONFIG_PM
5181 static int ixgbe_resume(struct pci_dev *pdev)
5182 {
5183         struct net_device *netdev = pci_get_drvdata(pdev);
5184         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5185         u32 err;
5186
5187         pci_set_power_state(pdev, PCI_D0);
5188         pci_restore_state(pdev);
5189         /*
5190          * pci_restore_state clears dev->state_saved so call
5191          * pci_save_state to restore it.
5192          */
5193         pci_save_state(pdev);
5194
5195         err = pci_enable_device_mem(pdev);
5196         if (err) {
5197                 e_dev_err("Cannot enable PCI device from suspend\n");
5198                 return err;
5199         }
5200         pci_set_master(pdev);
5201
5202         pci_wake_from_d3(pdev, false);
5203
5204         err = ixgbe_init_interrupt_scheme(adapter);
5205         if (err) {
5206                 e_dev_err("Cannot initialize interrupts for device\n");
5207                 return err;
5208         }
5209
5210         ixgbe_reset(adapter);
5211
5212         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5213
5214         if (netif_running(netdev)) {
5215                 err = ixgbe_open(adapter->netdev);
5216                 if (err)
5217                         return err;
5218         }
5219
5220         netif_device_attach(netdev);
5221
5222         return 0;
5223 }
5224 #endif /* CONFIG_PM */
5225
5226 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5227 {
5228         struct net_device *netdev = pci_get_drvdata(pdev);
5229         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5230         struct ixgbe_hw *hw = &adapter->hw;
5231         u32 ctrl, fctrl;
5232         u32 wufc = adapter->wol;
5233 #ifdef CONFIG_PM
5234         int retval = 0;
5235 #endif
5236
5237         netif_device_detach(netdev);
5238
5239         if (netif_running(netdev)) {
5240                 ixgbe_down(adapter);
5241                 ixgbe_free_irq(adapter);
5242                 ixgbe_free_all_tx_resources(adapter);
5243                 ixgbe_free_all_rx_resources(adapter);
5244         }
5245
5246 #ifdef CONFIG_PM
5247         retval = pci_save_state(pdev);
5248         if (retval)
5249                 return retval;
5250
5251 #endif
5252         if (wufc) {
5253                 ixgbe_set_rx_mode(netdev);
5254
5255                 /* turn on all-multi mode if wake on multicast is enabled */
5256                 if (wufc & IXGBE_WUFC_MC) {
5257                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5258                         fctrl |= IXGBE_FCTRL_MPE;
5259                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5260                 }
5261
5262                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5263                 ctrl |= IXGBE_CTRL_GIO_DIS;
5264                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5265
5266                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5267         } else {
5268                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5269                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5270         }
5271
5272         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5273                 pci_wake_from_d3(pdev, true);
5274         else
5275                 pci_wake_from_d3(pdev, false);
5276
5277         *enable_wake = !!wufc;
5278
5279         ixgbe_clear_interrupt_scheme(adapter);
5280
5281         ixgbe_release_hw_control(adapter);
5282
5283         pci_disable_device(pdev);
5284
5285         return 0;
5286 }
5287
5288 #ifdef CONFIG_PM
5289 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5290 {
5291         int retval;
5292         bool wake;
5293
5294         retval = __ixgbe_shutdown(pdev, &wake);
5295         if (retval)
5296                 return retval;
5297
5298         if (wake) {
5299                 pci_prepare_to_sleep(pdev);
5300         } else {
5301                 pci_wake_from_d3(pdev, false);
5302                 pci_set_power_state(pdev, PCI_D3hot);
5303         }
5304
5305         return 0;
5306 }
5307 #endif /* CONFIG_PM */
5308
5309 static void ixgbe_shutdown(struct pci_dev *pdev)
5310 {
5311         bool wake;
5312
5313         __ixgbe_shutdown(pdev, &wake);
5314
5315         if (system_state == SYSTEM_POWER_OFF) {
5316                 pci_wake_from_d3(pdev, wake);
5317                 pci_set_power_state(pdev, PCI_D3hot);
5318         }
5319 }
5320
5321 /**
5322  * ixgbe_update_stats - Update the board statistics counters.
5323  * @adapter: board private structure
5324  **/
5325 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5326 {
5327         struct net_device *netdev = adapter->netdev;
5328         struct ixgbe_hw *hw = &adapter->hw;
5329         u64 total_mpc = 0;
5330         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5331         u64 non_eop_descs = 0, restart_queue = 0;
5332
5333         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5334             test_bit(__IXGBE_RESETTING, &adapter->state))
5335                 return;
5336
5337         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5338                 u64 rsc_count = 0;
5339                 u64 rsc_flush = 0;
5340                 for (i = 0; i < 16; i++)
5341                         adapter->hw_rx_no_dma_resources +=
5342                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5343                 for (i = 0; i < adapter->num_rx_queues; i++) {
5344                         rsc_count += adapter->rx_ring[i]->rsc_count;
5345                         rsc_flush += adapter->rx_ring[i]->rsc_flush;
5346                 }
5347                 adapter->rsc_total_count = rsc_count;
5348                 adapter->rsc_total_flush = rsc_flush;
5349         }
5350
5351         /* gather some stats to the adapter struct that are per queue */
5352         for (i = 0; i < adapter->num_tx_queues; i++)
5353                 restart_queue += adapter->tx_ring[i]->restart_queue;
5354         adapter->restart_queue = restart_queue;
5355
5356         for (i = 0; i < adapter->num_rx_queues; i++)
5357                 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
5358         adapter->non_eop_descs = non_eop_descs;
5359
5360         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5361         for (i = 0; i < 8; i++) {
5362                 /* for packet buffers not used, the register should read 0 */
5363                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5364                 missed_rx += mpc;
5365                 adapter->stats.mpc[i] += mpc;
5366                 total_mpc += adapter->stats.mpc[i];
5367                 if (hw->mac.type == ixgbe_mac_82598EB)
5368                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5369                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5370                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5371                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5372                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5373                 if (hw->mac.type == ixgbe_mac_82599EB) {
5374                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5375                                                             IXGBE_PXONRXCNT(i));
5376                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5377                                                            IXGBE_PXOFFRXCNT(i));
5378                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5379                 } else {
5380                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5381                                                               IXGBE_PXONRXC(i));
5382                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5383                                                              IXGBE_PXOFFRXC(i));
5384                 }
5385                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
5386                                                             IXGBE_PXONTXC(i));
5387                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
5388                                                              IXGBE_PXOFFTXC(i));
5389         }
5390         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5391         /* work around hardware counting issue */
5392         adapter->stats.gprc -= missed_rx;
5393
5394         /* 82598 hardware only has a 32 bit counter in the high register */
5395         if (hw->mac.type == ixgbe_mac_82599EB) {
5396                 u64 tmp;
5397                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5398                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
5399                 adapter->stats.gorc += (tmp << 32);
5400                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5401                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
5402                 adapter->stats.gotc += (tmp << 32);
5403                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5404                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5405                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5406                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5407                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5408                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5409 #ifdef IXGBE_FCOE
5410                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5411                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5412                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5413                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5414                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5415                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5416 #endif /* IXGBE_FCOE */
5417         } else {
5418                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5419                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5420                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5421                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5422                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5423         }
5424         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5425         adapter->stats.bprc += bprc;
5426         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5427         if (hw->mac.type == ixgbe_mac_82598EB)
5428                 adapter->stats.mprc -= bprc;
5429         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5430         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5431         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5432         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5433         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5434         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5435         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5436         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5437         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5438         adapter->stats.lxontxc += lxon;
5439         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5440         adapter->stats.lxofftxc += lxoff;
5441         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5442         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5443         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5444         /*
5445          * 82598 errata - tx of flow control packets is included in tx counters
5446          */
5447         xon_off_tot = lxon + lxoff;
5448         adapter->stats.gptc -= xon_off_tot;
5449         adapter->stats.mptc -= xon_off_tot;
5450         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5451         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5452         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5453         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5454         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5455         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5456         adapter->stats.ptc64 -= xon_off_tot;
5457         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5458         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5459         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5460         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5461         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5462         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5463
5464         /* Fill out the OS statistics structure */
5465         netdev->stats.multicast = adapter->stats.mprc;
5466
5467         /* Rx Errors */
5468         netdev->stats.rx_errors = adapter->stats.crcerrs +
5469                                        adapter->stats.rlec;
5470         netdev->stats.rx_dropped = 0;
5471         netdev->stats.rx_length_errors = adapter->stats.rlec;
5472         netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5473         netdev->stats.rx_missed_errors = total_mpc;
5474 }
5475
5476 /**
5477  * ixgbe_watchdog - Timer Call-back
5478  * @data: pointer to adapter cast into an unsigned long
5479  **/
5480 static void ixgbe_watchdog(unsigned long data)
5481 {
5482         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5483         struct ixgbe_hw *hw = &adapter->hw;
5484         u64 eics = 0;
5485         int i;
5486
5487         /*
5488          *  Do the watchdog outside of interrupt context due to the lovely
5489          * delays that some of the newer hardware requires
5490          */
5491
5492         if (test_bit(__IXGBE_DOWN, &adapter->state))
5493                 goto watchdog_short_circuit;
5494
5495         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5496                 /*
5497                  * for legacy and MSI interrupts don't set any bits
5498                  * that are enabled for EIAM, because this operation
5499                  * would set *both* EIMS and EICS for any bit in EIAM
5500                  */
5501                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5502                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5503                 goto watchdog_reschedule;
5504         }
5505
5506         /* get one bit for every active tx/rx interrupt vector */
5507         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5508                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5509                 if (qv->rxr_count || qv->txr_count)
5510                         eics |= ((u64)1 << i);
5511         }
5512
5513         /* Cause software interrupt to ensure rx rings are cleaned */
5514         ixgbe_irq_rearm_queues(adapter, eics);
5515
5516 watchdog_reschedule:
5517         /* Reset the timer */
5518         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5519
5520 watchdog_short_circuit:
5521         schedule_work(&adapter->watchdog_task);
5522 }
5523
5524 /**
5525  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5526  * @work: pointer to work_struct containing our data
5527  **/
5528 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5529 {
5530         struct ixgbe_adapter *adapter = container_of(work,
5531                                                      struct ixgbe_adapter,
5532                                                      multispeed_fiber_task);
5533         struct ixgbe_hw *hw = &adapter->hw;
5534         u32 autoneg;
5535         bool negotiation;
5536
5537         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5538         autoneg = hw->phy.autoneg_advertised;
5539         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5540                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5541         hw->mac.autotry_restart = false;
5542         if (hw->mac.ops.setup_link)
5543                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5544         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5545         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5546 }
5547
5548 /**
5549  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5550  * @work: pointer to work_struct containing our data
5551  **/
5552 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5553 {
5554         struct ixgbe_adapter *adapter = container_of(work,
5555                                                      struct ixgbe_adapter,
5556                                                      sfp_config_module_task);
5557         struct ixgbe_hw *hw = &adapter->hw;
5558         u32 err;
5559
5560         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5561
5562         /* Time for electrical oscillations to settle down */
5563         msleep(100);
5564         err = hw->phy.ops.identify_sfp(hw);
5565
5566         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5567                 e_dev_err("failed to initialize because an unsupported SFP+ "
5568                           "module type was detected.\n");
5569                 e_dev_err("Reload the driver after installing a supported "
5570                           "module.\n");
5571                 unregister_netdev(adapter->netdev);
5572                 return;
5573         }
5574         hw->mac.ops.setup_sfp(hw);
5575
5576         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5577                 /* This will also work for DA Twinax connections */
5578                 schedule_work(&adapter->multispeed_fiber_task);
5579         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5580 }
5581
5582 /**
5583  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5584  * @work: pointer to work_struct containing our data
5585  **/
5586 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5587 {
5588         struct ixgbe_adapter *adapter = container_of(work,
5589                                                      struct ixgbe_adapter,
5590                                                      fdir_reinit_task);
5591         struct ixgbe_hw *hw = &adapter->hw;
5592         int i;
5593
5594         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5595                 for (i = 0; i < adapter->num_tx_queues; i++)
5596                         set_bit(__IXGBE_FDIR_INIT_DONE,
5597                                 &(adapter->tx_ring[i]->reinit_state));
5598         } else {
5599                 e_err(probe, "failed to finish FDIR re-initialization, "
5600                       "ignored adding FDIR ATR filters\n");
5601         }
5602         /* Done FDIR Re-initialization, enable transmits */
5603         netif_tx_start_all_queues(adapter->netdev);
5604 }
5605
5606 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5607
5608 /**
5609  * ixgbe_watchdog_task - worker thread to bring link up
5610  * @work: pointer to work_struct containing our data
5611  **/
5612 static void ixgbe_watchdog_task(struct work_struct *work)
5613 {
5614         struct ixgbe_adapter *adapter = container_of(work,
5615                                                      struct ixgbe_adapter,
5616                                                      watchdog_task);
5617         struct net_device *netdev = adapter->netdev;
5618         struct ixgbe_hw *hw = &adapter->hw;
5619         u32 link_speed;
5620         bool link_up;
5621         int i;
5622         struct ixgbe_ring *tx_ring;
5623         int some_tx_pending = 0;
5624
5625         mutex_lock(&ixgbe_watchdog_lock);
5626
5627         link_up = adapter->link_up;
5628         link_speed = adapter->link_speed;
5629
5630         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5631                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5632                 if (link_up) {
5633 #ifdef CONFIG_DCB
5634                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5635                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5636                                         hw->mac.ops.fc_enable(hw, i);
5637                         } else {
5638                                 hw->mac.ops.fc_enable(hw, 0);
5639                         }
5640 #else
5641                         hw->mac.ops.fc_enable(hw, 0);
5642 #endif
5643                 }
5644
5645                 if (link_up ||
5646                     time_after(jiffies, (adapter->link_check_timeout +
5647                                          IXGBE_TRY_LINK_TIMEOUT))) {
5648                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5649                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5650                 }
5651                 adapter->link_up = link_up;
5652                 adapter->link_speed = link_speed;
5653         }
5654
5655         if (link_up) {
5656                 if (!netif_carrier_ok(netdev)) {
5657                         bool flow_rx, flow_tx;
5658
5659                         if (hw->mac.type == ixgbe_mac_82599EB) {
5660                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5661                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5662                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5663                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5664                         } else {
5665                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5666                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5667                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5668                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5669                         }
5670
5671                         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5672                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5673                                "10 Gbps" :
5674                                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5675                                "1 Gbps" : "unknown speed")),
5676                                ((flow_rx && flow_tx) ? "RX/TX" :
5677                                (flow_rx ? "RX" :
5678                                (flow_tx ? "TX" : "None"))));
5679
5680                         netif_carrier_on(netdev);
5681                 } else {
5682                         /* Force detection of hung controller */
5683                         adapter->detect_tx_hung = true;
5684                 }
5685         } else {
5686                 adapter->link_up = false;
5687                 adapter->link_speed = 0;
5688                 if (netif_carrier_ok(netdev)) {
5689                         e_info(drv, "NIC Link is Down\n");
5690                         netif_carrier_off(netdev);
5691                 }
5692         }
5693
5694         if (!netif_carrier_ok(netdev)) {
5695                 for (i = 0; i < adapter->num_tx_queues; i++) {
5696                         tx_ring = adapter->tx_ring[i];
5697                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5698                                 some_tx_pending = 1;
5699                                 break;
5700                         }
5701                 }
5702
5703                 if (some_tx_pending) {
5704                         /* We've lost link, so the controller stops DMA,
5705                          * but we've got queued Tx work that's never going
5706                          * to get done, so reset controller to flush Tx.
5707                          * (Do the reset outside of interrupt context).
5708                          */
5709                          schedule_work(&adapter->reset_task);
5710                 }
5711         }
5712
5713         ixgbe_update_stats(adapter);
5714         mutex_unlock(&ixgbe_watchdog_lock);
5715 }
5716
5717 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5718                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5719                      u32 tx_flags, u8 *hdr_len)
5720 {
5721         struct ixgbe_adv_tx_context_desc *context_desc;
5722         unsigned int i;
5723         int err;
5724         struct ixgbe_tx_buffer *tx_buffer_info;
5725         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5726         u32 mss_l4len_idx, l4len;
5727
5728         if (skb_is_gso(skb)) {
5729                 if (skb_header_cloned(skb)) {
5730                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5731                         if (err)
5732                                 return err;
5733                 }
5734                 l4len = tcp_hdrlen(skb);
5735                 *hdr_len += l4len;
5736
5737                 if (skb->protocol == htons(ETH_P_IP)) {
5738                         struct iphdr *iph = ip_hdr(skb);
5739                         iph->tot_len = 0;
5740                         iph->check = 0;
5741                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5742                                                                  iph->daddr, 0,
5743                                                                  IPPROTO_TCP,
5744                                                                  0);
5745                 } else if (skb_is_gso_v6(skb)) {
5746                         ipv6_hdr(skb)->payload_len = 0;
5747                         tcp_hdr(skb)->check =
5748                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5749                                              &ipv6_hdr(skb)->daddr,
5750                                              0, IPPROTO_TCP, 0);
5751                 }
5752
5753                 i = tx_ring->next_to_use;
5754
5755                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5756                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5757
5758                 /* VLAN MACLEN IPLEN */
5759                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5760                         vlan_macip_lens |=
5761                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5762                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5763                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5764                 *hdr_len += skb_network_offset(skb);
5765                 vlan_macip_lens |=
5766                     (skb_transport_header(skb) - skb_network_header(skb));
5767                 *hdr_len +=
5768                     (skb_transport_header(skb) - skb_network_header(skb));
5769                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5770                 context_desc->seqnum_seed = 0;
5771
5772                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5773                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5774                                    IXGBE_ADVTXD_DTYP_CTXT);
5775
5776                 if (skb->protocol == htons(ETH_P_IP))
5777                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5778                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5779                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5780
5781                 /* MSS L4LEN IDX */
5782                 mss_l4len_idx =
5783                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5784                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5785                 /* use index 1 for TSO */
5786                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5787                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5788
5789                 tx_buffer_info->time_stamp = jiffies;
5790                 tx_buffer_info->next_to_watch = i;
5791
5792                 i++;
5793                 if (i == tx_ring->count)
5794                         i = 0;
5795                 tx_ring->next_to_use = i;
5796
5797                 return true;
5798         }
5799         return false;
5800 }
5801
5802 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5803                           struct ixgbe_ring *tx_ring,
5804                           struct sk_buff *skb, u32 tx_flags)
5805 {
5806         struct ixgbe_adv_tx_context_desc *context_desc;
5807         unsigned int i;
5808         struct ixgbe_tx_buffer *tx_buffer_info;
5809         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5810
5811         if (skb->ip_summed == CHECKSUM_PARTIAL ||
5812             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5813                 i = tx_ring->next_to_use;
5814                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5815                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5816
5817                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5818                         vlan_macip_lens |=
5819                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5820                 vlan_macip_lens |= (skb_network_offset(skb) <<
5821                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5822                 if (skb->ip_summed == CHECKSUM_PARTIAL)
5823                         vlan_macip_lens |= (skb_transport_header(skb) -
5824                                             skb_network_header(skb));
5825
5826                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5827                 context_desc->seqnum_seed = 0;
5828
5829                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
5830                                     IXGBE_ADVTXD_DTYP_CTXT);
5831
5832                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5833                         __be16 protocol;
5834
5835                         if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5836                                 const struct vlan_ethhdr *vhdr =
5837                                         (const struct vlan_ethhdr *)skb->data;
5838
5839                                 protocol = vhdr->h_vlan_encapsulated_proto;
5840                         } else {
5841                                 protocol = skb->protocol;
5842                         }
5843
5844                         switch (protocol) {
5845                         case cpu_to_be16(ETH_P_IP):
5846                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5847                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5848                                         type_tucmd_mlhl |=
5849                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5850                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5851                                         type_tucmd_mlhl |=
5852                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5853                                 break;
5854                         case cpu_to_be16(ETH_P_IPV6):
5855                                 /* XXX what about other V6 headers?? */
5856                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5857                                         type_tucmd_mlhl |=
5858                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5859                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5860                                         type_tucmd_mlhl |=
5861                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5862                                 break;
5863                         default:
5864                                 if (unlikely(net_ratelimit())) {
5865                                         e_warn(probe, "partial checksum "
5866                                                "but proto=%x!\n",
5867                                                skb->protocol);
5868                                 }
5869                                 break;
5870                         }
5871                 }
5872
5873                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5874                 /* use index zero for tx checksum offload */
5875                 context_desc->mss_l4len_idx = 0;
5876
5877                 tx_buffer_info->time_stamp = jiffies;
5878                 tx_buffer_info->next_to_watch = i;
5879
5880                 i++;
5881                 if (i == tx_ring->count)
5882                         i = 0;
5883                 tx_ring->next_to_use = i;
5884
5885                 return true;
5886         }
5887
5888         return false;
5889 }
5890
5891 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5892                         struct ixgbe_ring *tx_ring,
5893                         struct sk_buff *skb, u32 tx_flags,
5894                         unsigned int first)
5895 {
5896         struct pci_dev *pdev = adapter->pdev;
5897         struct ixgbe_tx_buffer *tx_buffer_info;
5898         unsigned int len;
5899         unsigned int total = skb->len;
5900         unsigned int offset = 0, size, count = 0, i;
5901         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5902         unsigned int f;
5903
5904         i = tx_ring->next_to_use;
5905
5906         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5907                 /* excluding fcoe_crc_eof for FCoE */
5908                 total -= sizeof(struct fcoe_crc_eof);
5909
5910         len = min(skb_headlen(skb), total);
5911         while (len) {
5912                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5913                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5914
5915                 tx_buffer_info->length = size;
5916                 tx_buffer_info->mapped_as_page = false;
5917                 tx_buffer_info->dma = dma_map_single(&pdev->dev,
5918                                                      skb->data + offset,
5919                                                      size, DMA_TO_DEVICE);
5920                 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
5921                         goto dma_error;
5922                 tx_buffer_info->time_stamp = jiffies;
5923                 tx_buffer_info->next_to_watch = i;
5924
5925                 len -= size;
5926                 total -= size;
5927                 offset += size;
5928                 count++;
5929
5930                 if (len) {
5931                         i++;
5932                         if (i == tx_ring->count)
5933                                 i = 0;
5934                 }
5935         }
5936
5937         for (f = 0; f < nr_frags; f++) {
5938                 struct skb_frag_struct *frag;
5939
5940                 frag = &skb_shinfo(skb)->frags[f];
5941                 len = min((unsigned int)frag->size, total);
5942                 offset = frag->page_offset;
5943
5944                 while (len) {
5945                         i++;
5946                         if (i == tx_ring->count)
5947                                 i = 0;
5948
5949                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
5950                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5951
5952                         tx_buffer_info->length = size;
5953                         tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
5954                                                            frag->page,
5955                                                            offset, size,
5956                                                            DMA_TO_DEVICE);
5957                         tx_buffer_info->mapped_as_page = true;
5958                         if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
5959                                 goto dma_error;
5960                         tx_buffer_info->time_stamp = jiffies;
5961                         tx_buffer_info->next_to_watch = i;
5962
5963                         len -= size;
5964                         total -= size;
5965                         offset += size;
5966                         count++;
5967                 }
5968                 if (total == 0)
5969                         break;
5970         }
5971
5972         tx_ring->tx_buffer_info[i].skb = skb;
5973         tx_ring->tx_buffer_info[first].next_to_watch = i;
5974
5975         return count;
5976
5977 dma_error:
5978         e_dev_err("TX DMA map failed\n");
5979
5980         /* clear timestamp and dma mappings for failed tx_buffer_info map */
5981         tx_buffer_info->dma = 0;
5982         tx_buffer_info->time_stamp = 0;
5983         tx_buffer_info->next_to_watch = 0;
5984         if (count)
5985                 count--;
5986
5987         /* clear timestamp and dma mappings for remaining portion of packet */
5988         while (count--) {
5989                 if (i==0)
5990                         i += tx_ring->count;
5991                 i--;
5992                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5993                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5994         }
5995
5996         return 0;
5997 }
5998
5999 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
6000                            struct ixgbe_ring *tx_ring,
6001                            int tx_flags, int count, u32 paylen, u8 hdr_len)
6002 {
6003         union ixgbe_adv_tx_desc *tx_desc = NULL;
6004         struct ixgbe_tx_buffer *tx_buffer_info;
6005         u32 olinfo_status = 0, cmd_type_len = 0;
6006         unsigned int i;
6007         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6008
6009         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6010
6011         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6012
6013         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6014                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6015
6016         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6017                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6018
6019                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6020                                  IXGBE_ADVTXD_POPTS_SHIFT;
6021
6022                 /* use index 1 context for tso */
6023                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6024                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6025                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6026                                          IXGBE_ADVTXD_POPTS_SHIFT;
6027
6028         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6029                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6030                                  IXGBE_ADVTXD_POPTS_SHIFT;
6031
6032         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6033                 olinfo_status |= IXGBE_ADVTXD_CC;
6034                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6035                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6036                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6037         }
6038
6039         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6040
6041         i = tx_ring->next_to_use;
6042         while (count--) {
6043                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6044                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
6045                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6046                 tx_desc->read.cmd_type_len =
6047                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6048                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6049                 i++;
6050                 if (i == tx_ring->count)
6051                         i = 0;
6052         }
6053
6054         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6055
6056         /*
6057          * Force memory writes to complete before letting h/w
6058          * know there are new descriptors to fetch.  (Only
6059          * applicable for weak-ordered memory model archs,
6060          * such as IA-64).
6061          */
6062         wmb();
6063
6064         tx_ring->next_to_use = i;
6065         writel(i, adapter->hw.hw_addr + tx_ring->tail);
6066 }
6067
6068 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6069                       int queue, u32 tx_flags)
6070 {
6071         struct ixgbe_atr_input atr_input;
6072         struct tcphdr *th;
6073         struct iphdr *iph = ip_hdr(skb);
6074         struct ethhdr *eth = (struct ethhdr *)skb->data;
6075         u16 vlan_id, src_port, dst_port, flex_bytes;
6076         u32 src_ipv4_addr, dst_ipv4_addr;
6077         u8 l4type = 0;
6078
6079         /* Right now, we support IPv4 only */
6080         if (skb->protocol != htons(ETH_P_IP))
6081                 return;
6082         /* check if we're UDP or TCP */
6083         if (iph->protocol == IPPROTO_TCP) {
6084                 th = tcp_hdr(skb);
6085                 src_port = th->source;
6086                 dst_port = th->dest;
6087                 l4type |= IXGBE_ATR_L4TYPE_TCP;
6088                 /* l4type IPv4 type is 0, no need to assign */
6089         } else {
6090                 /* Unsupported L4 header, just bail here */
6091                 return;
6092         }
6093
6094         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6095
6096         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6097                    IXGBE_TX_FLAGS_VLAN_SHIFT;
6098         src_ipv4_addr = iph->saddr;
6099         dst_ipv4_addr = iph->daddr;
6100         flex_bytes = eth->h_proto;
6101
6102         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6103         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6104         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6105         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6106         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6107         /* src and dst are inverted, think how the receiver sees them */
6108         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6109         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6110
6111         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6112         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6113 }
6114
6115 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
6116                                  struct ixgbe_ring *tx_ring, int size)
6117 {
6118         netif_stop_subqueue(netdev, tx_ring->queue_index);
6119         /* Herbert's original patch had:
6120          *  smp_mb__after_netif_stop_queue();
6121          * but since that doesn't exist yet, just open code it. */
6122         smp_mb();
6123
6124         /* We need to check again in a case another CPU has just
6125          * made room available. */
6126         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6127                 return -EBUSY;
6128
6129         /* A reprieve! - use start_queue because it doesn't call schedule */
6130         netif_start_subqueue(netdev, tx_ring->queue_index);
6131         ++tx_ring->restart_queue;
6132         return 0;
6133 }
6134
6135 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
6136                               struct ixgbe_ring *tx_ring, int size)
6137 {
6138         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6139                 return 0;
6140         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6141 }
6142
6143 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6144 {
6145         struct ixgbe_adapter *adapter = netdev_priv(dev);
6146         int txq = smp_processor_id();
6147
6148 #ifdef IXGBE_FCOE
6149         if ((skb->protocol == htons(ETH_P_FCOE)) ||
6150             (skb->protocol == htons(ETH_P_FIP))) {
6151                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6152                         txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6153                         txq += adapter->ring_feature[RING_F_FCOE].mask;
6154                         return txq;
6155 #ifdef CONFIG_IXGBE_DCB
6156                 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6157                         txq = adapter->fcoe.up;
6158                         return txq;
6159 #endif
6160                 }
6161         }
6162 #endif
6163
6164         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6165                 while (unlikely(txq >= dev->real_num_tx_queues))
6166                         txq -= dev->real_num_tx_queues;
6167                 return txq;
6168         }
6169
6170         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6171                 if (skb->priority == TC_PRIO_CONTROL)
6172                         txq = adapter->ring_feature[RING_F_DCB].indices-1;
6173                 else
6174                         txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6175                                >> 13;
6176                 return txq;
6177         }
6178
6179         return skb_tx_hash(dev, skb);
6180 }
6181
6182 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6183                                     struct net_device *netdev)
6184 {
6185         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6186         struct ixgbe_ring *tx_ring;
6187         struct netdev_queue *txq;
6188         unsigned int first;
6189         unsigned int tx_flags = 0;
6190         u8 hdr_len = 0;
6191         int tso;
6192         int count = 0;
6193         unsigned int f;
6194
6195         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
6196                 tx_flags |= vlan_tx_tag_get(skb);
6197                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6198                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6199                         tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6200                 }
6201                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6202                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6203         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6204                    skb->priority != TC_PRIO_CONTROL) {
6205                 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6206                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6207                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6208         }
6209
6210         tx_ring = adapter->tx_ring[skb->queue_mapping];
6211
6212 #ifdef IXGBE_FCOE
6213         /* for FCoE with DCB, we force the priority to what
6214          * was specified by the switch */
6215         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6216             (skb->protocol == htons(ETH_P_FCOE) ||
6217              skb->protocol == htons(ETH_P_FIP))) {
6218 #ifdef CONFIG_IXGBE_DCB
6219                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6220                         tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6221                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6222                         tx_flags |= ((adapter->fcoe.up << 13)
6223                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6224                 }
6225 #endif
6226                 /* flag for FCoE offloads */
6227                 if (skb->protocol == htons(ETH_P_FCOE))
6228                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6229         }
6230 #endif
6231
6232         /* four things can cause us to need a context descriptor */
6233         if (skb_is_gso(skb) ||
6234             (skb->ip_summed == CHECKSUM_PARTIAL) ||
6235             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6236             (tx_flags & IXGBE_TX_FLAGS_FCOE))
6237                 count++;
6238
6239         count += TXD_USE_COUNT(skb_headlen(skb));
6240         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6241                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6242
6243         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
6244                 adapter->tx_busy++;
6245                 return NETDEV_TX_BUSY;
6246         }
6247
6248         first = tx_ring->next_to_use;
6249         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6250 #ifdef IXGBE_FCOE
6251                 /* setup tx offload for FCoE */
6252                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6253                 if (tso < 0) {
6254                         dev_kfree_skb_any(skb);
6255                         return NETDEV_TX_OK;
6256                 }
6257                 if (tso)
6258                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6259 #endif /* IXGBE_FCOE */
6260         } else {
6261                 if (skb->protocol == htons(ETH_P_IP))
6262                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6263                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6264                 if (tso < 0) {
6265                         dev_kfree_skb_any(skb);
6266                         return NETDEV_TX_OK;
6267                 }
6268
6269                 if (tso)
6270                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6271                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
6272                          (skb->ip_summed == CHECKSUM_PARTIAL))
6273                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6274         }
6275
6276         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
6277         if (count) {
6278                 /* add the ATR filter if ATR is on */
6279                 if (tx_ring->atr_sample_rate) {
6280                         ++tx_ring->atr_count;
6281                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6282                              test_bit(__IXGBE_FDIR_INIT_DONE,
6283                                       &tx_ring->reinit_state)) {
6284                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6285                                           tx_flags);
6286                                 tx_ring->atr_count = 0;
6287                         }
6288                 }
6289                 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6290                 txq->tx_bytes += skb->len;
6291                 txq->tx_packets++;
6292                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
6293                                hdr_len);
6294                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
6295
6296         } else {
6297                 dev_kfree_skb_any(skb);
6298                 tx_ring->tx_buffer_info[first].time_stamp = 0;
6299                 tx_ring->next_to_use = first;
6300         }
6301
6302         return NETDEV_TX_OK;
6303 }
6304
6305 /**
6306  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6307  * @netdev: network interface device structure
6308  * @p: pointer to an address structure
6309  *
6310  * Returns 0 on success, negative on failure
6311  **/
6312 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6313 {
6314         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6315         struct ixgbe_hw *hw = &adapter->hw;
6316         struct sockaddr *addr = p;
6317
6318         if (!is_valid_ether_addr(addr->sa_data))
6319                 return -EADDRNOTAVAIL;
6320
6321         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6322         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6323
6324         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6325                             IXGBE_RAH_AV);
6326
6327         return 0;
6328 }
6329
6330 static int
6331 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6332 {
6333         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6334         struct ixgbe_hw *hw = &adapter->hw;
6335         u16 value;
6336         int rc;
6337
6338         if (prtad != hw->phy.mdio.prtad)
6339                 return -EINVAL;
6340         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6341         if (!rc)
6342                 rc = value;
6343         return rc;
6344 }
6345
6346 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6347                             u16 addr, u16 value)
6348 {
6349         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6350         struct ixgbe_hw *hw = &adapter->hw;
6351
6352         if (prtad != hw->phy.mdio.prtad)
6353                 return -EINVAL;
6354         return hw->phy.ops.write_reg(hw, addr, devad, value);
6355 }
6356
6357 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6358 {
6359         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6360
6361         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6362 }
6363
6364 /**
6365  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6366  * netdev->dev_addrs
6367  * @netdev: network interface device structure
6368  *
6369  * Returns non-zero on failure
6370  **/
6371 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6372 {
6373         int err = 0;
6374         struct ixgbe_adapter *adapter = netdev_priv(dev);
6375         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6376
6377         if (is_valid_ether_addr(mac->san_addr)) {
6378                 rtnl_lock();
6379                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6380                 rtnl_unlock();
6381         }
6382         return err;
6383 }
6384
6385 /**
6386  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6387  * netdev->dev_addrs
6388  * @netdev: network interface device structure
6389  *
6390  * Returns non-zero on failure
6391  **/
6392 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6393 {
6394         int err = 0;
6395         struct ixgbe_adapter *adapter = netdev_priv(dev);
6396         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6397
6398         if (is_valid_ether_addr(mac->san_addr)) {
6399                 rtnl_lock();
6400                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6401                 rtnl_unlock();
6402         }
6403         return err;
6404 }
6405
6406 #ifdef CONFIG_NET_POLL_CONTROLLER
6407 /*
6408  * Polling 'interrupt' - used by things like netconsole to send skbs
6409  * without having to re-enable interrupts. It's not called while
6410  * the interrupt routine is executing.
6411  */
6412 static void ixgbe_netpoll(struct net_device *netdev)
6413 {
6414         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6415         int i;
6416
6417         /* if interface is down do nothing */
6418         if (test_bit(__IXGBE_DOWN, &adapter->state))
6419                 return;
6420
6421         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6422         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6423                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6424                 for (i = 0; i < num_q_vectors; i++) {
6425                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6426                         ixgbe_msix_clean_many(0, q_vector);
6427                 }
6428         } else {
6429                 ixgbe_intr(adapter->pdev->irq, netdev);
6430         }
6431         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6432 }
6433 #endif
6434
6435 static const struct net_device_ops ixgbe_netdev_ops = {
6436         .ndo_open               = ixgbe_open,
6437         .ndo_stop               = ixgbe_close,
6438         .ndo_start_xmit         = ixgbe_xmit_frame,
6439         .ndo_select_queue       = ixgbe_select_queue,
6440         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
6441         .ndo_set_multicast_list = ixgbe_set_rx_mode,
6442         .ndo_validate_addr      = eth_validate_addr,
6443         .ndo_set_mac_address    = ixgbe_set_mac,
6444         .ndo_change_mtu         = ixgbe_change_mtu,
6445         .ndo_tx_timeout         = ixgbe_tx_timeout,
6446         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
6447         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
6448         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
6449         .ndo_do_ioctl           = ixgbe_ioctl,
6450         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
6451         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
6452         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
6453         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
6454 #ifdef CONFIG_NET_POLL_CONTROLLER
6455         .ndo_poll_controller    = ixgbe_netpoll,
6456 #endif
6457 #ifdef IXGBE_FCOE
6458         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6459         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6460         .ndo_fcoe_enable = ixgbe_fcoe_enable,
6461         .ndo_fcoe_disable = ixgbe_fcoe_disable,
6462         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6463 #endif /* IXGBE_FCOE */
6464 };
6465
6466 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6467                            const struct ixgbe_info *ii)
6468 {
6469 #ifdef CONFIG_PCI_IOV
6470         struct ixgbe_hw *hw = &adapter->hw;
6471         int err;
6472
6473         if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6474                 return;
6475
6476         /* The 82599 supports up to 64 VFs per physical function
6477          * but this implementation limits allocation to 63 so that
6478          * basic networking resources are still available to the
6479          * physical function
6480          */
6481         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6482         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6483         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6484         if (err) {
6485                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
6486                 goto err_novfs;
6487         }
6488         /* If call to enable VFs succeeded then allocate memory
6489          * for per VF control structures.
6490          */
6491         adapter->vfinfo =
6492                 kcalloc(adapter->num_vfs,
6493                         sizeof(struct vf_data_storage), GFP_KERNEL);
6494         if (adapter->vfinfo) {
6495                 /* Now that we're sure SR-IOV is enabled
6496                  * and memory allocated set up the mailbox parameters
6497                  */
6498                 ixgbe_init_mbx_params_pf(hw);
6499                 memcpy(&hw->mbx.ops, ii->mbx_ops,
6500                        sizeof(hw->mbx.ops));
6501
6502                 /* Disable RSC when in SR-IOV mode */
6503                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6504                                      IXGBE_FLAG2_RSC_ENABLED);
6505                 return;
6506         }
6507
6508         /* Oh oh */
6509         e_err(probe, "Unable to allocate memory for VF Data Storage - "
6510               "SRIOV disabled\n");
6511         pci_disable_sriov(adapter->pdev);
6512
6513 err_novfs:
6514         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6515         adapter->num_vfs = 0;
6516 #endif /* CONFIG_PCI_IOV */
6517 }
6518
6519 /**
6520  * ixgbe_probe - Device Initialization Routine
6521  * @pdev: PCI device information struct
6522  * @ent: entry in ixgbe_pci_tbl
6523  *
6524  * Returns 0 on success, negative on failure
6525  *
6526  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6527  * The OS initialization, configuring of the adapter private structure,
6528  * and a hardware reset occur.
6529  **/
6530 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6531                                  const struct pci_device_id *ent)
6532 {
6533         struct net_device *netdev;
6534         struct ixgbe_adapter *adapter = NULL;
6535         struct ixgbe_hw *hw;
6536         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6537         static int cards_found;
6538         int i, err, pci_using_dac;
6539         unsigned int indices = num_possible_cpus();
6540 #ifdef IXGBE_FCOE
6541         u16 device_caps;
6542 #endif
6543         u32 part_num, eec;
6544
6545         /* Catch broken hardware that put the wrong VF device ID in
6546          * the PCIe SR-IOV capability.
6547          */
6548         if (pdev->is_virtfn) {
6549                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6550                      pci_name(pdev), pdev->vendor, pdev->device);
6551                 return -EINVAL;
6552         }
6553
6554         err = pci_enable_device_mem(pdev);
6555         if (err)
6556                 return err;
6557
6558         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6559             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6560                 pci_using_dac = 1;
6561         } else {
6562                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6563                 if (err) {
6564                         err = dma_set_coherent_mask(&pdev->dev,
6565                                                     DMA_BIT_MASK(32));
6566                         if (err) {
6567                                 dev_err(&pdev->dev,
6568                                         "No usable DMA configuration, aborting\n");
6569                                 goto err_dma;
6570                         }
6571                 }
6572                 pci_using_dac = 0;
6573         }
6574
6575         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6576                                            IORESOURCE_MEM), ixgbe_driver_name);
6577         if (err) {
6578                 dev_err(&pdev->dev,
6579                         "pci_request_selected_regions failed 0x%x\n", err);
6580                 goto err_pci_reg;
6581         }
6582
6583         pci_enable_pcie_error_reporting(pdev);
6584
6585         pci_set_master(pdev);
6586         pci_save_state(pdev);
6587
6588         if (ii->mac == ixgbe_mac_82598EB)
6589                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6590         else
6591                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6592
6593         indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6594 #ifdef IXGBE_FCOE
6595         indices += min_t(unsigned int, num_possible_cpus(),
6596                          IXGBE_MAX_FCOE_INDICES);
6597 #endif
6598         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6599         if (!netdev) {
6600                 err = -ENOMEM;
6601                 goto err_alloc_etherdev;
6602         }
6603
6604         SET_NETDEV_DEV(netdev, &pdev->dev);
6605
6606         pci_set_drvdata(pdev, netdev);
6607         adapter = netdev_priv(netdev);
6608
6609         adapter->netdev = netdev;
6610         adapter->pdev = pdev;
6611         hw = &adapter->hw;
6612         hw->back = adapter;
6613         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6614
6615         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6616                               pci_resource_len(pdev, 0));
6617         if (!hw->hw_addr) {
6618                 err = -EIO;
6619                 goto err_ioremap;
6620         }
6621
6622         for (i = 1; i <= 5; i++) {
6623                 if (pci_resource_len(pdev, i) == 0)
6624                         continue;
6625         }
6626
6627         netdev->netdev_ops = &ixgbe_netdev_ops;
6628         ixgbe_set_ethtool_ops(netdev);
6629         netdev->watchdog_timeo = 5 * HZ;
6630         strcpy(netdev->name, pci_name(pdev));
6631
6632         adapter->bd_number = cards_found;
6633
6634         /* Setup hw api */
6635         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6636         hw->mac.type  = ii->mac;
6637
6638         /* EEPROM */
6639         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6640         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6641         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6642         if (!(eec & (1 << 8)))
6643                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6644
6645         /* PHY */
6646         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6647         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6648         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6649         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6650         hw->phy.mdio.mmds = 0;
6651         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6652         hw->phy.mdio.dev = netdev;
6653         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6654         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6655
6656         /* set up this timer and work struct before calling get_invariants
6657          * which might start the timer
6658          */
6659         init_timer(&adapter->sfp_timer);
6660         adapter->sfp_timer.function = &ixgbe_sfp_timer;
6661         adapter->sfp_timer.data = (unsigned long) adapter;
6662
6663         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6664
6665         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6666         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6667
6668         /* a new SFP+ module arrival, called from GPI SDP2 context */
6669         INIT_WORK(&adapter->sfp_config_module_task,
6670                   ixgbe_sfp_config_module_task);
6671
6672         ii->get_invariants(hw);
6673
6674         /* setup the private structure */
6675         err = ixgbe_sw_init(adapter);
6676         if (err)
6677                 goto err_sw_init;
6678
6679         /* Make it possible the adapter to be woken up via WOL */
6680         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6681                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6682
6683         /*
6684          * If there is a fan on this device and it has failed log the
6685          * failure.
6686          */
6687         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6688                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6689                 if (esdp & IXGBE_ESDP_SDP1)
6690                         e_crit(probe, "Fan has stopped, replace the adapter\n");
6691         }
6692
6693         /* reset_hw fills in the perm_addr as well */
6694         hw->phy.reset_if_overtemp = true;
6695         err = hw->mac.ops.reset_hw(hw);
6696         hw->phy.reset_if_overtemp = false;
6697         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6698             hw->mac.type == ixgbe_mac_82598EB) {
6699                 /*
6700                  * Start a kernel thread to watch for a module to arrive.
6701                  * Only do this for 82598, since 82599 will generate
6702                  * interrupts on module arrival.
6703                  */
6704                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6705                 mod_timer(&adapter->sfp_timer,
6706                           round_jiffies(jiffies + (2 * HZ)));
6707                 err = 0;
6708         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6709                 e_dev_err("failed to initialize because an unsupported SFP+ "
6710                           "module type was detected.\n");
6711                 e_dev_err("Reload the driver after installing a supported "
6712                           "module.\n");
6713                 goto err_sw_init;
6714         } else if (err) {
6715                 e_dev_err("HW Init failed: %d\n", err);
6716                 goto err_sw_init;
6717         }
6718
6719         ixgbe_probe_vf(adapter, ii);
6720
6721         netdev->features = NETIF_F_SG |
6722                            NETIF_F_IP_CSUM |
6723                            NETIF_F_HW_VLAN_TX |
6724                            NETIF_F_HW_VLAN_RX |
6725                            NETIF_F_HW_VLAN_FILTER;
6726
6727         netdev->features |= NETIF_F_IPV6_CSUM;
6728         netdev->features |= NETIF_F_TSO;
6729         netdev->features |= NETIF_F_TSO6;
6730         netdev->features |= NETIF_F_GRO;
6731
6732         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6733                 netdev->features |= NETIF_F_SCTP_CSUM;
6734
6735         netdev->vlan_features |= NETIF_F_TSO;
6736         netdev->vlan_features |= NETIF_F_TSO6;
6737         netdev->vlan_features |= NETIF_F_IP_CSUM;
6738         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6739         netdev->vlan_features |= NETIF_F_SG;
6740
6741         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6742                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6743                                     IXGBE_FLAG_DCB_ENABLED);
6744         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6745                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6746
6747 #ifdef CONFIG_IXGBE_DCB
6748         netdev->dcbnl_ops = &dcbnl_ops;
6749 #endif
6750
6751 #ifdef IXGBE_FCOE
6752         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6753                 if (hw->mac.ops.get_device_caps) {
6754                         hw->mac.ops.get_device_caps(hw, &device_caps);
6755                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6756                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6757                 }
6758         }
6759         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6760                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6761                 netdev->vlan_features |= NETIF_F_FSO;
6762                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6763         }
6764 #endif /* IXGBE_FCOE */
6765         if (pci_using_dac)
6766                 netdev->features |= NETIF_F_HIGHDMA;
6767
6768         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6769                 netdev->features |= NETIF_F_LRO;
6770
6771         /* make sure the EEPROM is good */
6772         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
6773                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
6774                 err = -EIO;
6775                 goto err_eeprom;
6776         }
6777
6778         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6779         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6780
6781         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6782                 e_dev_err("invalid MAC address\n");
6783                 err = -EIO;
6784                 goto err_eeprom;
6785         }
6786
6787         /* power down the optics */
6788         if (hw->phy.multispeed_fiber)
6789                 hw->mac.ops.disable_tx_laser(hw);
6790
6791         init_timer(&adapter->watchdog_timer);
6792         adapter->watchdog_timer.function = &ixgbe_watchdog;
6793         adapter->watchdog_timer.data = (unsigned long)adapter;
6794
6795         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
6796         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
6797
6798         err = ixgbe_init_interrupt_scheme(adapter);
6799         if (err)
6800                 goto err_sw_init;
6801
6802         switch (pdev->device) {
6803         case IXGBE_DEV_ID_82599_KX4:
6804                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6805                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
6806                 break;
6807         default:
6808                 adapter->wol = 0;
6809                 break;
6810         }
6811         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6812
6813         /* pick up the PCI bus settings for reporting later */
6814         hw->mac.ops.get_bus_info(hw);
6815
6816         /* print bus type/speed/width info */
6817         e_dev_info("(PCI Express:%s:%s) %pM\n",
6818                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6819                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6820                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6821                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6822                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
6823                  "Unknown"),
6824                 netdev->dev_addr);
6825         ixgbe_read_pba_num_generic(hw, &part_num);
6826         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6827                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
6828                            "PBA No: %06x-%03x\n",
6829                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6830                            (part_num >> 8), (part_num & 0xff));
6831         else
6832                 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6833                            hw->mac.type, hw->phy.type,
6834                            (part_num >> 8), (part_num & 0xff));
6835
6836         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
6837                 e_dev_warn("PCI-Express bandwidth available for this card is "
6838                            "not sufficient for optimal performance.\n");
6839                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
6840                            "is required.\n");
6841         }
6842
6843         /* save off EEPROM version number */
6844         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6845
6846         /* reset the hardware with the new settings */
6847         err = hw->mac.ops.start_hw(hw);
6848
6849         if (err == IXGBE_ERR_EEPROM_VERSION) {
6850                 /* We are running on a pre-production device, log a warning */
6851                 e_dev_warn("This device is a pre-production adapter/LOM. "
6852                            "Please be aware there may be issues associated "
6853                            "with your hardware.  If you are experiencing "
6854                            "problems please contact your Intel or hardware "
6855                            "representative who provided you with this "
6856                            "hardware.\n");
6857         }
6858         strcpy(netdev->name, "eth%d");
6859         err = register_netdev(netdev);
6860         if (err)
6861                 goto err_register;
6862
6863         /* carrier off reporting is important to ethtool even BEFORE open */
6864         netif_carrier_off(netdev);
6865
6866         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6867             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6868                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6869
6870         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
6871                 INIT_WORK(&adapter->check_overtemp_task, ixgbe_check_overtemp_task);
6872 #ifdef CONFIG_IXGBE_DCA
6873         if (dca_add_requester(&pdev->dev) == 0) {
6874                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
6875                 ixgbe_setup_dca(adapter);
6876         }
6877 #endif
6878         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6879                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
6880                 for (i = 0; i < adapter->num_vfs; i++)
6881                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
6882         }
6883
6884         /* add san mac addr to netdev */
6885         ixgbe_add_sanmac_netdev(netdev);
6886
6887         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
6888         cards_found++;
6889         return 0;
6890
6891 err_register:
6892         ixgbe_release_hw_control(adapter);
6893         ixgbe_clear_interrupt_scheme(adapter);
6894 err_sw_init:
6895 err_eeprom:
6896         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6897                 ixgbe_disable_sriov(adapter);
6898         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6899         del_timer_sync(&adapter->sfp_timer);
6900         cancel_work_sync(&adapter->sfp_task);
6901         cancel_work_sync(&adapter->multispeed_fiber_task);
6902         cancel_work_sync(&adapter->sfp_config_module_task);
6903         iounmap(hw->hw_addr);
6904 err_ioremap:
6905         free_netdev(netdev);
6906 err_alloc_etherdev:
6907         pci_release_selected_regions(pdev, pci_select_bars(pdev,
6908                                      IORESOURCE_MEM));
6909 err_pci_reg:
6910 err_dma:
6911         pci_disable_device(pdev);
6912         return err;
6913 }
6914
6915 /**
6916  * ixgbe_remove - Device Removal Routine
6917  * @pdev: PCI device information struct
6918  *
6919  * ixgbe_remove is called by the PCI subsystem to alert the driver
6920  * that it should release a PCI device.  The could be caused by a
6921  * Hot-Plug event, or because the driver is going to be removed from
6922  * memory.
6923  **/
6924 static void __devexit ixgbe_remove(struct pci_dev *pdev)
6925 {
6926         struct net_device *netdev = pci_get_drvdata(pdev);
6927         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6928
6929         set_bit(__IXGBE_DOWN, &adapter->state);
6930         /* clear the module not found bit to make sure the worker won't
6931          * reschedule
6932          */
6933         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6934         del_timer_sync(&adapter->watchdog_timer);
6935
6936         del_timer_sync(&adapter->sfp_timer);
6937         cancel_work_sync(&adapter->watchdog_task);
6938         cancel_work_sync(&adapter->sfp_task);
6939         cancel_work_sync(&adapter->multispeed_fiber_task);
6940         cancel_work_sync(&adapter->sfp_config_module_task);
6941         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6942             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6943                 cancel_work_sync(&adapter->fdir_reinit_task);
6944         flush_scheduled_work();
6945
6946 #ifdef CONFIG_IXGBE_DCA
6947         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6948                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6949                 dca_remove_requester(&pdev->dev);
6950                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6951         }
6952
6953 #endif
6954 #ifdef IXGBE_FCOE
6955         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6956                 ixgbe_cleanup_fcoe(adapter);
6957
6958 #endif /* IXGBE_FCOE */
6959
6960         /* remove the added san mac */
6961         ixgbe_del_sanmac_netdev(netdev);
6962
6963         if (netdev->reg_state == NETREG_REGISTERED)
6964                 unregister_netdev(netdev);
6965
6966         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6967                 ixgbe_disable_sriov(adapter);
6968
6969         ixgbe_clear_interrupt_scheme(adapter);
6970
6971         ixgbe_release_hw_control(adapter);
6972
6973         iounmap(adapter->hw.hw_addr);
6974         pci_release_selected_regions(pdev, pci_select_bars(pdev,
6975                                      IORESOURCE_MEM));
6976
6977         e_dev_info("complete\n");
6978
6979         free_netdev(netdev);
6980
6981         pci_disable_pcie_error_reporting(pdev);
6982
6983         pci_disable_device(pdev);
6984 }
6985
6986 /**
6987  * ixgbe_io_error_detected - called when PCI error is detected
6988  * @pdev: Pointer to PCI device
6989  * @state: The current pci connection state
6990  *
6991  * This function is called after a PCI bus error affecting
6992  * this device has been detected.
6993  */
6994 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
6995                                                 pci_channel_state_t state)
6996 {
6997         struct net_device *netdev = pci_get_drvdata(pdev);
6998         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6999
7000         netif_device_detach(netdev);
7001
7002         if (state == pci_channel_io_perm_failure)
7003                 return PCI_ERS_RESULT_DISCONNECT;
7004
7005         if (netif_running(netdev))
7006                 ixgbe_down(adapter);
7007         pci_disable_device(pdev);
7008
7009         /* Request a slot reset. */
7010         return PCI_ERS_RESULT_NEED_RESET;
7011 }
7012
7013 /**
7014  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7015  * @pdev: Pointer to PCI device
7016  *
7017  * Restart the card from scratch, as if from a cold-boot.
7018  */
7019 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7020 {
7021         struct net_device *netdev = pci_get_drvdata(pdev);
7022         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7023         pci_ers_result_t result;
7024         int err;
7025
7026         if (pci_enable_device_mem(pdev)) {
7027                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7028                 result = PCI_ERS_RESULT_DISCONNECT;
7029         } else {
7030                 pci_set_master(pdev);
7031                 pci_restore_state(pdev);
7032                 pci_save_state(pdev);
7033
7034                 pci_wake_from_d3(pdev, false);
7035
7036                 ixgbe_reset(adapter);
7037                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7038                 result = PCI_ERS_RESULT_RECOVERED;
7039         }
7040
7041         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7042         if (err) {
7043                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7044                           "failed 0x%0x\n", err);
7045                 /* non-fatal, continue */
7046         }
7047
7048         return result;
7049 }
7050
7051 /**
7052  * ixgbe_io_resume - called when traffic can start flowing again.
7053  * @pdev: Pointer to PCI device
7054  *
7055  * This callback is called when the error recovery driver tells us that
7056  * its OK to resume normal operation.
7057  */
7058 static void ixgbe_io_resume(struct pci_dev *pdev)
7059 {
7060         struct net_device *netdev = pci_get_drvdata(pdev);
7061         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7062
7063         if (netif_running(netdev)) {
7064                 if (ixgbe_up(adapter)) {
7065                         e_info(probe, "ixgbe_up failed after reset\n");
7066                         return;
7067                 }
7068         }
7069
7070         netif_device_attach(netdev);
7071 }
7072
7073 static struct pci_error_handlers ixgbe_err_handler = {
7074         .error_detected = ixgbe_io_error_detected,
7075         .slot_reset = ixgbe_io_slot_reset,
7076         .resume = ixgbe_io_resume,
7077 };
7078
7079 static struct pci_driver ixgbe_driver = {
7080         .name     = ixgbe_driver_name,
7081         .id_table = ixgbe_pci_tbl,
7082         .probe    = ixgbe_probe,
7083         .remove   = __devexit_p(ixgbe_remove),
7084 #ifdef CONFIG_PM
7085         .suspend  = ixgbe_suspend,
7086         .resume   = ixgbe_resume,
7087 #endif
7088         .shutdown = ixgbe_shutdown,
7089         .err_handler = &ixgbe_err_handler
7090 };
7091
7092 /**
7093  * ixgbe_init_module - Driver Registration Routine
7094  *
7095  * ixgbe_init_module is the first routine called when the driver is
7096  * loaded. All it does is register with the PCI subsystem.
7097  **/
7098 static int __init ixgbe_init_module(void)
7099 {
7100         int ret;
7101         pr_info("%s - version %s\n", ixgbe_driver_string,
7102                    ixgbe_driver_version);
7103         pr_info("%s\n", ixgbe_copyright);
7104
7105 #ifdef CONFIG_IXGBE_DCA
7106         dca_register_notify(&dca_notifier);
7107 #endif
7108
7109         ret = pci_register_driver(&ixgbe_driver);
7110         return ret;
7111 }
7112
7113 module_init(ixgbe_init_module);
7114
7115 /**
7116  * ixgbe_exit_module - Driver Exit Cleanup Routine
7117  *
7118  * ixgbe_exit_module is called just before the driver is removed
7119  * from memory.
7120  **/
7121 static void __exit ixgbe_exit_module(void)
7122 {
7123 #ifdef CONFIG_IXGBE_DCA
7124         dca_unregister_notify(&dca_notifier);
7125 #endif
7126         pci_unregister_driver(&ixgbe_driver);
7127 }
7128
7129 #ifdef CONFIG_IXGBE_DCA
7130 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7131                             void *p)
7132 {
7133         int ret_val;
7134
7135         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7136                                          __ixgbe_notify_dca);
7137
7138         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7139 }
7140
7141 #endif /* CONFIG_IXGBE_DCA */
7142
7143 /**
7144  * ixgbe_get_hw_dev return device
7145  * used by hardware layer to print debugging information
7146  **/
7147 struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7148 {
7149         struct ixgbe_adapter *adapter = hw->back;
7150         return adapter->netdev;
7151 }
7152
7153 module_exit(ixgbe_exit_module);
7154
7155 /* ixgbe_main.c */