drivers/net/phy/broadcom.c

   1 /*
   2  *      drivers/net/phy/broadcom.c
   3  *
   4  *      Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet
   5  *      transceivers.
   6  *
   7  *      Copyright (c) 2006  Maciej W. Rozycki
   8  *
   9  *      Inspired by code written by Amy Fong.
  10  *
  11  *      This program is free software; you can redistribute it and/or
  12  *      modify it under the terms of the GNU General Public License
  13  *      as published by the Free Software Foundation; either version
  14  *      2 of the License, or (at your option) any later version.
  15  */
  16
  17 #include "bcm-phy-lib.h"
  18 #include <linux/module.h>
  19 #include <linux/phy.h>
  20 #include <linux/brcmphy.h>
  21 #include <linux/of.h>
  22
  23 #define BRCM_PHY_MODEL(phydev) \
  24         ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
  25
  26 #define BRCM_PHY_REV(phydev) \
  27         ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
  28
  29 MODULE_DESCRIPTION("Broadcom PHY driver");
  30 MODULE_AUTHOR("Maciej W. Rozycki");
  31 MODULE_LICENSE("GPL");
  32
  33 static int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum)
  34 {
  35         /* The register must be written to both the Shadow Register Select and
  36          * the Shadow Read Register Selector
  37          */
  38         phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum |
  39                   regnum << MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT);
  40         return phy_read(phydev, MII_BCM54XX_AUX_CTL);
  41 }
  42
  43 static int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
  44 {
  45         return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
  46 }
  47
  48 static int bcm54810_config(struct phy_device *phydev)
  49 {
  50         int rc, val;
  51
  52         val = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
  53         val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
  54         rc = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
  55                                val);
  56         if (rc < 0)
  57                 return rc;
  58
  59         val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
  60         val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
  61         val |= MII_BCM54XX_AUXCTL_MISC_WREN;
  62         rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
  63                                   val);
  64         if (rc < 0)
  65                 return rc;
  66
  67         val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
  68         val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
  69         rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
  70         if (rc < 0)
  71                 return rc;
  72
  73         return 0;
  74 }
  75
  76 /* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
  77 static int bcm50610_a0_workaround(struct phy_device *phydev)
  78 {
  79         int err;
  80
  81         err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH0,
  82                                 MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN |
  83                                 MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF);
  84         if (err < 0)
  85                 return err;
  86
  87         err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH3,
  88                                 MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ);
  89         if (err < 0)
  90                 return err;
  91
  92         err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75,
  93                                 MII_BCM54XX_EXP_EXP75_VDACCTRL);
  94         if (err < 0)
  95                 return err;
  96
  97         err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP96,
  98                                 MII_BCM54XX_EXP_EXP96_MYST);
  99         if (err < 0)
 100                 return err;
 101
 102         err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP97,
 103                                 MII_BCM54XX_EXP_EXP97_MYST);
 104
 105         return err;
 106 }
 107
 108 static int bcm54xx_phydsp_config(struct phy_device *phydev)
 109 {
 110         int err, err2;
 111
 112         /* Enable the SMDSP clock */
 113         err = bcm54xx_auxctl_write(phydev,
 114                                    MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
 115                                    MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA |
 116                                    MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
 117         if (err < 0)
 118                 return err;
 119
 120         if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
 121             BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) {
 122                 /* Clear bit 9 to fix a phy interop issue. */
 123                 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08,
 124                                         MII_BCM54XX_EXP_EXP08_RJCT_2MHZ);
 125                 if (err < 0)
 126                         goto error;
 127
 128                 if (phydev->drv->phy_id == PHY_ID_BCM50610) {
 129                         err = bcm50610_a0_workaround(phydev);
 130                         if (err < 0)
 131                                 goto error;
 132                 }
 133         }
 134
 135         if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {
 136                 int val;
 137
 138                 val = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP75);
 139                 if (val < 0)
 140                         goto error;
 141
 142                 val |= MII_BCM54XX_EXP_EXP75_CM_OSC;
 143                 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, val);
 144         }
 145
 146 error:
 147         /* Disable the SMDSP clock */
 148         err2 = bcm54xx_auxctl_write(phydev,
 149                                     MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
 150                                     MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
 151
 152         /* Return the first error reported. */
 153         return err ? err : err2;
 154 }
 155
 156 static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)
 157 {
 158         u32 orig;
 159         int val;
 160         bool clk125en = true;
 161
 162         /* Abort if we are using an untested phy. */
 163         if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM57780 &&
 164             BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 &&
 165             BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M)
 166                 return;
 167
 168         val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
 169         if (val < 0)
 170                 return;
 171
 172         orig = val;
 173
 174         if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
 175              BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
 176             BRCM_PHY_REV(phydev) >= 0x3) {
 177                 /*
 178                  * Here, bit 0 _disables_ CLK125 when set.
 179                  * This bit is set by default.
 180                  */
 181                 clk125en = false;
 182         } else {
 183                 if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) {
 184                         /* Here, bit 0 _enables_ CLK125 when set */
 185                         val &= ~BCM54XX_SHD_SCR3_DEF_CLK125;
 186                         clk125en = false;
 187                 }
 188         }
 189
 190         if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
 191                 val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS;
 192         else
 193                 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
 194
 195         if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY)
 196                 val |= BCM54XX_SHD_SCR3_TRDDAPD;
 197
 198         if (orig != val)
 199                 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
 200
 201         val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);
 202         if (val < 0)
 203                 return;
 204
 205         orig = val;
 206
 207         if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
 208                 val |= BCM54XX_SHD_APD_EN;
 209         else
 210                 val &= ~BCM54XX_SHD_APD_EN;
 211
 212         if (orig != val)
 213                 bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);
 214 }
 215
 216 static int bcm54xx_config_init(struct phy_device *phydev)
 217 {
 218         int reg, err;
 219
 220         reg = phy_read(phydev, MII_BCM54XX_ECR);
 221         if (reg < 0)
 222                 return reg;
 223
 224         /* Mask interrupts globally.  */
 225         reg |= MII_BCM54XX_ECR_IM;
 226         err = phy_write(phydev, MII_BCM54XX_ECR, reg);
 227         if (err < 0)
 228                 return err;
 229
 230         /* Unmask events we are interested in.  */
 231         reg = ~(MII_BCM54XX_INT_DUPLEX |
 232                 MII_BCM54XX_INT_SPEED |
 233                 MII_BCM54XX_INT_LINK);
 234         err = phy_write(phydev, MII_BCM54XX_IMR, reg);
 235         if (err < 0)
 236                 return err;
 237
 238         if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
 239              BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
 240             (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))
 241                 bcm_phy_write_shadow(phydev, BCM54XX_SHD_RGMII_MODE, 0);
 242
 243         if ((phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) ||
 244             (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) ||
 245             (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
 246                 bcm54xx_adjust_rxrefclk(phydev);
 247
 248         if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
 249                 err = bcm54810_config(phydev);
 250                 if (err)
 251                         return err;
 252         }
 253
 254         bcm54xx_phydsp_config(phydev);
 255
 256         return 0;
 257 }
 258
 259 static int bcm5482_config_init(struct phy_device *phydev)
 260 {
 261         int err, reg;
 262
 263         err = bcm54xx_config_init(phydev);
 264
 265         if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
 266                 /*
 267                  * Enable secondary SerDes and its use as an LED source
 268                  */
 269                 reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_SSD);
 270                 bcm_phy_write_shadow(phydev, BCM5482_SHD_SSD,
 271                                      reg |
 272                                      BCM5482_SHD_SSD_LEDM |
 273                                      BCM5482_SHD_SSD_EN);
 274
 275                 /*
 276                  * Enable SGMII slave mode and auto-detection
 277                  */
 278                 reg = BCM5482_SSD_SGMII_SLAVE | MII_BCM54XX_EXP_SEL_SSD;
 279                 err = bcm_phy_read_exp(phydev, reg);
 280                 if (err < 0)
 281                         return err;
 282                 err = bcm_phy_write_exp(phydev, reg, err |
 283                                         BCM5482_SSD_SGMII_SLAVE_EN |
 284                                         BCM5482_SSD_SGMII_SLAVE_AD);
 285                 if (err < 0)
 286                         return err;
 287
 288                 /*
 289                  * Disable secondary SerDes powerdown
 290                  */
 291                 reg = BCM5482_SSD_1000BX_CTL | MII_BCM54XX_EXP_SEL_SSD;
 292                 err = bcm_phy_read_exp(phydev, reg);
 293                 if (err < 0)
 294                         return err;
 295                 err = bcm_phy_write_exp(phydev, reg,
 296                                         err & ~BCM5482_SSD_1000BX_CTL_PWRDOWN);
 297                 if (err < 0)
 298                         return err;
 299
 300                 /*
 301                  * Select 1000BASE-X register set (primary SerDes)
 302                  */
 303                 reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_MODE);
 304                 bcm_phy_write_shadow(phydev, BCM5482_SHD_MODE,
 305                                      reg | BCM5482_SHD_MODE_1000BX);
 306
 307                 /*
 308                  * LED1=ACTIVITYLED, LED3=LINKSPD[2]
 309                  * (Use LED1 as secondary SerDes ACTIVITY LED)
 310                  */
 311                 bcm_phy_write_shadow(phydev, BCM5482_SHD_LEDS1,
 312                         BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_ACTIVITYLED) |
 313                         BCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_LINKSPD2));
 314
 315                 /*
 316                  * Auto-negotiation doesn't seem to work quite right
 317                  * in this mode, so we disable it and force it to the
 318                  * right speed/duplex setting.  Only 'link status'
 319                  * is important.
 320                  */
 321                 phydev->autoneg = AUTONEG_DISABLE;
 322                 phydev->speed = SPEED_1000;
 323                 phydev->duplex = DUPLEX_FULL;
 324         }
 325
 326         return err;
 327 }
 328
 329 static int bcm5482_read_status(struct phy_device *phydev)
 330 {
 331         int err;
 332
 333         err = genphy_read_status(phydev);
 334
 335         if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
 336                 /*
 337                  * Only link status matters for 1000Base-X mode, so force
 338                  * 1000 Mbit/s full-duplex status
 339                  */
 340                 if (phydev->link) {
 341                         phydev->speed = SPEED_1000;
 342                         phydev->duplex = DUPLEX_FULL;
 343                 }
 344         }
 345
 346         return err;
 347 }
 348
 349 static int bcm5481_config_aneg(struct phy_device *phydev)
 350 {
 351         struct device_node *np = phydev->mdio.dev.of_node;
 352         int ret;
 353
 354         /* Aneg firsly. */
 355         ret = genphy_config_aneg(phydev);
 356
 357         /* Then we can set up the delay. */
 358         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
 359                 u16 reg;
 360
 361                 /*
 362                  * There is no BCM5481 specification available, so down
 363                  * here is everything we know about "register 0x18". This
 364                  * at least helps BCM5481 to successfully receive packets
 365                  * on MPC8360E-RDK board. Peter Barada <peterb@logicpd.com>
 366                  * says: "This sets delay between the RXD and RXC signals
 367                  * instead of using trace lengths to achieve timing".
 368                  */
 369
 370                 /* Set RDX clk delay. */
 371                 reg = 0x7 | (0x7 << 12);
 372                 phy_write(phydev, 0x18, reg);
 373
 374                 reg = phy_read(phydev, 0x18);
 375                 /* Set RDX-RXC skew. */
 376                 reg |= (1 << 8);
 377                 /* Write bits 14:0. */
 378                 reg |= (1 << 15);
 379                 phy_write(phydev, 0x18, reg);
 380         }
 381
 382         if (of_property_read_bool(np, "enet-phy-lane-swap")) {
 383                 /* Lane Swap - Undocumented register...magic! */
 384                 ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
 385                                         0x11B);
 386                 if (ret < 0)
 387                         return ret;
 388         }
 389
 390         return ret;
 391 }
 392
 393 static int bcm54612e_config_aneg(struct phy_device *phydev)
 394 {
 395         int ret;
 396
 397         /* First, auto-negotiate. */
 398         ret = genphy_config_aneg(phydev);
 399
 400         /* Clear TX internal delay unless requested. */
 401         if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
 402             (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
 403                 /* Disable TXD to GTXCLK clock delay (default set) */
 404                 /* Bit 9 is the only field in shadow register 00011 */
 405                 bcm_phy_write_shadow(phydev, 0x03, 0);
 406         }
 407
 408         /* Clear RX internal delay unless requested. */
 409         if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
 410             (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
 411                 u16 reg;
 412
 413                 /* Errata: reads require filling in the write selector field */
 414                 bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
 415                                      MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC);
 416                 reg = phy_read(phydev, MII_BCM54XX_AUX_CTL);
 417                 /* Disable RXD to RXC delay (default set) */
 418                 reg &= ~MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW;
 419                 /* Clear shadow selector field */
 420                 reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
 421                 bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
 422                                      MII_BCM54XX_AUXCTL_MISC_WREN | reg);
 423         }
 424
 425         return ret;
 426 }
 427
 428 static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
 429 {
 430         int val;
 431
 432         val = phy_read(phydev, reg);
 433         if (val < 0)
 434                 return val;
 435
 436         return phy_write(phydev, reg, val | set);
 437 }
 438
 439 static int brcm_fet_config_init(struct phy_device *phydev)
 440 {
 441         int reg, err, err2, brcmtest;
 442
 443         /* Reset the PHY to bring it to a known state. */
 444         err = phy_write(phydev, MII_BMCR, BMCR_RESET);
 445         if (err < 0)
 446                 return err;
 447
 448         reg = phy_read(phydev, MII_BRCM_FET_INTREG);
 449         if (reg < 0)
 450                 return reg;
 451
 452         /* Unmask events we are interested in and mask interrupts globally. */
 453         reg = MII_BRCM_FET_IR_DUPLEX_EN |
 454               MII_BRCM_FET_IR_SPEED_EN |
 455               MII_BRCM_FET_IR_LINK_EN |
 456               MII_BRCM_FET_IR_ENABLE |
 457               MII_BRCM_FET_IR_MASK;
 458
 459         err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
 460         if (err < 0)
 461                 return err;
 462
 463         /* Enable shadow register access */
 464         brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
 465         if (brcmtest < 0)
 466                 return brcmtest;
 467
 468         reg = brcmtest | MII_BRCM_FET_BT_SRE;
 469
 470         err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
 471         if (err < 0)
 472                 return err;
 473
 474         /* Set the LED mode */
 475         reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);
 476         if (reg < 0) {
 477                 err = reg;
 478                 goto done;
 479         }
 480
 481         reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK;
 482         reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1;
 483
 484         err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);
 485         if (err < 0)
 486                 goto done;
 487
 488         /* Enable auto MDIX */
 489         err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_MISCCTRL,
 490                                        MII_BRCM_FET_SHDW_MC_FAME);
 491         if (err < 0)
 492                 goto done;
 493
 494         if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) {
 495                 /* Enable auto power down */
 496                 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
 497                                                MII_BRCM_FET_SHDW_AS2_APDE);
 498         }
 499
 500 done:
 501         /* Disable shadow register access */
 502         err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
 503         if (!err)
 504                 err = err2;
 505
 506         return err;
 507 }
 508
 509 static int brcm_fet_ack_interrupt(struct phy_device *phydev)
 510 {
 511         int reg;
 512
 513         /* Clear pending interrupts.  */
 514         reg = phy_read(phydev, MII_BRCM_FET_INTREG);
 515         if (reg < 0)
 516                 return reg;
 517
 518         return 0;
 519 }
 520
 521 static int brcm_fet_config_intr(struct phy_device *phydev)
 522 {
 523         int reg, err;
 524
 525         reg = phy_read(phydev, MII_BRCM_FET_INTREG);
 526         if (reg < 0)
 527                 return reg;
 528
 529         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 530                 reg &= ~MII_BRCM_FET_IR_MASK;
 531         else
 532                 reg |= MII_BRCM_FET_IR_MASK;
 533
 534         err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
 535         return err;
 536 }
 537
 538 static struct phy_driver broadcom_drivers[] = {
 539 {
 540         .phy_id         = PHY_ID_BCM5411,
 541         .phy_id_mask    = 0xfffffff0,
 542         .name           = "Broadcom BCM5411",
 543         .features       = PHY_GBIT_FEATURES |
 544                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 545         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 546         .config_init    = bcm54xx_config_init,
 547         .config_aneg    = genphy_config_aneg,
 548         .read_status    = genphy_read_status,
 549         .ack_interrupt  = bcm_phy_ack_intr,
 550         .config_intr    = bcm_phy_config_intr,
 551 }, {
 552         .phy_id         = PHY_ID_BCM5421,
 553         .phy_id_mask    = 0xfffffff0,
 554         .name           = "Broadcom BCM5421",
 555         .features       = PHY_GBIT_FEATURES |
 556                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 557         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 558         .config_init    = bcm54xx_config_init,
 559         .config_aneg    = genphy_config_aneg,
 560         .read_status    = genphy_read_status,
 561         .ack_interrupt  = bcm_phy_ack_intr,
 562         .config_intr    = bcm_phy_config_intr,
 563 }, {
 564         .phy_id         = PHY_ID_BCM5461,
 565         .phy_id_mask    = 0xfffffff0,
 566         .name           = "Broadcom BCM5461",
 567         .features       = PHY_GBIT_FEATURES |
 568                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 569         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 570         .config_init    = bcm54xx_config_init,
 571         .config_aneg    = genphy_config_aneg,
 572         .read_status    = genphy_read_status,
 573         .ack_interrupt  = bcm_phy_ack_intr,
 574         .config_intr    = bcm_phy_config_intr,
 575 }, {
 576         .phy_id         = PHY_ID_BCM54612E,
 577         .phy_id_mask    = 0xfffffff0,
 578         .name           = "Broadcom BCM54612E",
 579         .features       = PHY_GBIT_FEATURES |
 580                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 581         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 582         .config_init    = bcm54xx_config_init,
 583         .config_aneg    = bcm54612e_config_aneg,
 584         .read_status    = genphy_read_status,
 585         .ack_interrupt  = bcm_phy_ack_intr,
 586         .config_intr    = bcm_phy_config_intr,
 587 }, {
 588         .phy_id         = PHY_ID_BCM54616S,
 589         .phy_id_mask    = 0xfffffff0,
 590         .name           = "Broadcom BCM54616S",
 591         .features       = PHY_GBIT_FEATURES |
 592                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 593         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 594         .config_init    = bcm54xx_config_init,
 595         .config_aneg    = genphy_config_aneg,
 596         .read_status    = genphy_read_status,
 597         .ack_interrupt  = bcm_phy_ack_intr,
 598         .config_intr    = bcm_phy_config_intr,
 599 }, {
 600         .phy_id         = PHY_ID_BCM5464,
 601         .phy_id_mask    = 0xfffffff0,
 602         .name           = "Broadcom BCM5464",
 603         .features       = PHY_GBIT_FEATURES |
 604                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 605         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 606         .config_init    = bcm54xx_config_init,
 607         .config_aneg    = genphy_config_aneg,
 608         .read_status    = genphy_read_status,
 609         .ack_interrupt  = bcm_phy_ack_intr,
 610         .config_intr    = bcm_phy_config_intr,
 611 }, {
 612         .phy_id         = PHY_ID_BCM5481,
 613         .phy_id_mask    = 0xfffffff0,
 614         .name           = "Broadcom BCM5481",
 615         .features       = PHY_GBIT_FEATURES |
 616                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 617         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 618         .config_init    = bcm54xx_config_init,
 619         .config_aneg    = bcm5481_config_aneg,
 620         .read_status    = genphy_read_status,
 621         .ack_interrupt  = bcm_phy_ack_intr,
 622         .config_intr    = bcm_phy_config_intr,
 623 }, {
 624         .phy_id         = PHY_ID_BCM54810,
 625         .phy_id_mask    = 0xfffffff0,
 626         .name           = "Broadcom BCM54810",
 627         .features       = PHY_GBIT_FEATURES |
 628                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 629         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 630         .config_init    = bcm54xx_config_init,
 631         .config_aneg    = bcm5481_config_aneg,
 632         .read_status    = genphy_read_status,
 633         .ack_interrupt  = bcm_phy_ack_intr,
 634         .config_intr    = bcm_phy_config_intr,
 635 }, {
 636         .phy_id         = PHY_ID_BCM5482,
 637         .phy_id_mask    = 0xfffffff0,
 638         .name           = "Broadcom BCM5482",
 639         .features       = PHY_GBIT_FEATURES |
 640                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 641         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 642         .config_init    = bcm5482_config_init,
 643         .config_aneg    = genphy_config_aneg,
 644         .read_status    = bcm5482_read_status,
 645         .ack_interrupt  = bcm_phy_ack_intr,
 646         .config_intr    = bcm_phy_config_intr,
 647 }, {
 648         .phy_id         = PHY_ID_BCM50610,
 649         .phy_id_mask    = 0xfffffff0,
 650         .name           = "Broadcom BCM50610",
 651         .features       = PHY_GBIT_FEATURES |
 652                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 653         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 654         .config_init    = bcm54xx_config_init,
 655         .config_aneg    = genphy_config_aneg,
 656         .read_status    = genphy_read_status,
 657         .ack_interrupt  = bcm_phy_ack_intr,
 658         .config_intr    = bcm_phy_config_intr,
 659 }, {
 660         .phy_id         = PHY_ID_BCM50610M,
 661         .phy_id_mask    = 0xfffffff0,
 662         .name           = "Broadcom BCM50610M",
 663         .features       = PHY_GBIT_FEATURES |
 664                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 665         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 666         .config_init    = bcm54xx_config_init,
 667         .config_aneg    = genphy_config_aneg,
 668         .read_status    = genphy_read_status,
 669         .ack_interrupt  = bcm_phy_ack_intr,
 670         .config_intr    = bcm_phy_config_intr,
 671 }, {
 672         .phy_id         = PHY_ID_BCM57780,
 673         .phy_id_mask    = 0xfffffff0,
 674         .name           = "Broadcom BCM57780",
 675         .features       = PHY_GBIT_FEATURES |
 676                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 677         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 678         .config_init    = bcm54xx_config_init,
 679         .config_aneg    = genphy_config_aneg,
 680         .read_status    = genphy_read_status,
 681         .ack_interrupt  = bcm_phy_ack_intr,
 682         .config_intr    = bcm_phy_config_intr,
 683 }, {
 684         .phy_id         = PHY_ID_BCMAC131,
 685         .phy_id_mask    = 0xfffffff0,
 686         .name           = "Broadcom BCMAC131",
 687         .features       = PHY_BASIC_FEATURES |
 688                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 689         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 690         .config_init    = brcm_fet_config_init,
 691         .config_aneg    = genphy_config_aneg,
 692         .read_status    = genphy_read_status,
 693         .ack_interrupt  = brcm_fet_ack_interrupt,
 694         .config_intr    = brcm_fet_config_intr,
 695 }, {
 696         .phy_id         = PHY_ID_BCM5241,
 697         .phy_id_mask    = 0xfffffff0,
 698         .name           = "Broadcom BCM5241",
 699         .features       = PHY_BASIC_FEATURES |
 700                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 701         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 702         .config_init    = brcm_fet_config_init,
 703         .config_aneg    = genphy_config_aneg,
 704         .read_status    = genphy_read_status,
 705         .ack_interrupt  = brcm_fet_ack_interrupt,
 706         .config_intr    = brcm_fet_config_intr,
 707 } };
 708
 709 module_phy_driver(broadcom_drivers);
 710
 711 static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
 712         { PHY_ID_BCM5411, 0xfffffff0 },
 713         { PHY_ID_BCM5421, 0xfffffff0 },
 714         { PHY_ID_BCM5461, 0xfffffff0 },
 715         { PHY_ID_BCM54612E, 0xfffffff0 },
 716         { PHY_ID_BCM54616S, 0xfffffff0 },
 717         { PHY_ID_BCM5464, 0xfffffff0 },
 718         { PHY_ID_BCM5481, 0xfffffff0 },
 719         { PHY_ID_BCM54810, 0xfffffff0 },
 720         { PHY_ID_BCM5482, 0xfffffff0 },
 721         { PHY_ID_BCM50610, 0xfffffff0 },
 722         { PHY_ID_BCM50610M, 0xfffffff0 },
 723         { PHY_ID_BCM57780, 0xfffffff0 },
 724         { PHY_ID_BCMAC131, 0xfffffff0 },
 725         { PHY_ID_BCM5241, 0xfffffff0 },
 726         { }
 727 };
 728
 729 MODULE_DEVICE_TABLE(mdio, broadcom_tbl);