drivers/net/phy/micrel.c

   1 /*
   2  * drivers/net/phy/micrel.c
   3  *
   4  * Driver for Micrel PHYs
   5  *
   6  * Author: David J. Choi
   7  *
   8  * Copyright (c) 2010-2013 Micrel, Inc.
   9  * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General  Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  *
  16  * Support : Micrel Phys:
  17  *              Giga phys: ksz9021, ksz9031
  18  *              100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
  19  *                         ksz8021, ksz8031, ksz8051,
  20  *                         ksz8081, ksz8091,
  21  *                         ksz8061,
  22  *              Switch : ksz8873, ksz886x
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/phy.h>
  28 #include <linux/micrel_phy.h>
  29 #include <linux/of.h>
  30 #include <linux/clk.h>
  31
  32 /* Operation Mode Strap Override */
  33 #define MII_KSZPHY_OMSO                         0x16
  34 #define KSZPHY_OMSO_B_CAST_OFF                  BIT(9)
  35 #define KSZPHY_OMSO_NAND_TREE_ON                BIT(5)
  36 #define KSZPHY_OMSO_RMII_OVERRIDE               BIT(1)
  37 #define KSZPHY_OMSO_MII_OVERRIDE                BIT(0)
  38
  39 /* general Interrupt control/status reg in vendor specific block. */
  40 #define MII_KSZPHY_INTCS                        0x1B
  41 #define KSZPHY_INTCS_JABBER                     BIT(15)
  42 #define KSZPHY_INTCS_RECEIVE_ERR                BIT(14)
  43 #define KSZPHY_INTCS_PAGE_RECEIVE               BIT(13)
  44 #define KSZPHY_INTCS_PARELLEL                   BIT(12)
  45 #define KSZPHY_INTCS_LINK_PARTNER_ACK           BIT(11)
  46 #define KSZPHY_INTCS_LINK_DOWN                  BIT(10)
  47 #define KSZPHY_INTCS_REMOTE_FAULT               BIT(9)
  48 #define KSZPHY_INTCS_LINK_UP                    BIT(8)
  49 #define KSZPHY_INTCS_ALL                        (KSZPHY_INTCS_LINK_UP |\
  50                                                 KSZPHY_INTCS_LINK_DOWN)
  51
  52 /* PHY Control 1 */
  53 #define MII_KSZPHY_CTRL_1                       0x1e
  54
  55 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
  56 #define MII_KSZPHY_CTRL_2                       0x1f
  57 #define MII_KSZPHY_CTRL                         MII_KSZPHY_CTRL_2
  58 /* bitmap of PHY register to set interrupt mode */
  59 #define KSZPHY_CTRL_INT_ACTIVE_HIGH             BIT(9)
  60 #define KSZPHY_RMII_REF_CLK_SEL                 BIT(7)
  61
  62 /* Write/read to/from extended registers */
  63 #define MII_KSZPHY_EXTREG                       0x0b
  64 #define KSZPHY_EXTREG_WRITE                     0x8000
  65
  66 #define MII_KSZPHY_EXTREG_WRITE                 0x0c
  67 #define MII_KSZPHY_EXTREG_READ                  0x0d
  68
  69 /* Extended registers */
  70 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW         0x104
  71 #define MII_KSZPHY_RX_DATA_PAD_SKEW             0x105
  72 #define MII_KSZPHY_TX_DATA_PAD_SKEW             0x106
  73
  74 #define PS_TO_REG                               200
  75
  76 struct kszphy_hw_stat {
  77         const char *string;
  78         u8 reg;
  79         u8 bits;
  80 };
  81
  82 static struct kszphy_hw_stat kszphy_hw_stats[] = {
  83         { "phy_receive_errors", 21, 16},
  84         { "phy_idle_errors", 10, 8 },
  85 };
  86
  87 struct kszphy_type {
  88         u32 led_mode_reg;
  89         u16 interrupt_level_mask;
  90         bool has_broadcast_disable;
  91         bool has_nand_tree_disable;
  92         bool has_rmii_ref_clk_sel;
  93 };
  94
  95 struct kszphy_priv {
  96         const struct kszphy_type *type;
  97         int led_mode;
  98         bool rmii_ref_clk_sel;
  99         bool rmii_ref_clk_sel_val;
 100         u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
 101 };
 102
 103 static const struct kszphy_type ksz8021_type = {
 104         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 105         .has_broadcast_disable  = true,
 106         .has_nand_tree_disable  = true,
 107         .has_rmii_ref_clk_sel   = true,
 108 };
 109
 110 static const struct kszphy_type ksz8041_type = {
 111         .led_mode_reg           = MII_KSZPHY_CTRL_1,
 112 };
 113
 114 static const struct kszphy_type ksz8051_type = {
 115         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 116         .has_nand_tree_disable  = true,
 117 };
 118
 119 static const struct kszphy_type ksz8081_type = {
 120         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 121         .has_broadcast_disable  = true,
 122         .has_nand_tree_disable  = true,
 123         .has_rmii_ref_clk_sel   = true,
 124 };
 125
 126 static const struct kszphy_type ks8737_type = {
 127         .interrupt_level_mask   = BIT(14),
 128 };
 129
 130 static const struct kszphy_type ksz9021_type = {
 131         .interrupt_level_mask   = BIT(14),
 132 };
 133
 134 static int kszphy_extended_write(struct phy_device *phydev,
 135                                 u32 regnum, u16 val)
 136 {
 137         phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
 138         return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
 139 }
 140
 141 static int kszphy_extended_read(struct phy_device *phydev,
 142                                 u32 regnum)
 143 {
 144         phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
 145         return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
 146 }
 147
 148 static int kszphy_ack_interrupt(struct phy_device *phydev)
 149 {
 150         /* bit[7..0] int status, which is a read and clear register. */
 151         int rc;
 152
 153         rc = phy_read(phydev, MII_KSZPHY_INTCS);
 154
 155         return (rc < 0) ? rc : 0;
 156 }
 157
 158 static int kszphy_config_intr(struct phy_device *phydev)
 159 {
 160         const struct kszphy_type *type = phydev->drv->driver_data;
 161         int temp;
 162         u16 mask;
 163
 164         if (type && type->interrupt_level_mask)
 165                 mask = type->interrupt_level_mask;
 166         else
 167                 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
 168
 169         /* set the interrupt pin active low */
 170         temp = phy_read(phydev, MII_KSZPHY_CTRL);
 171         if (temp < 0)
 172                 return temp;
 173         temp &= ~mask;
 174         phy_write(phydev, MII_KSZPHY_CTRL, temp);
 175
 176         /* enable / disable interrupts */
 177         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 178                 temp = KSZPHY_INTCS_ALL;
 179         else
 180                 temp = 0;
 181
 182         return phy_write(phydev, MII_KSZPHY_INTCS, temp);
 183 }
 184
 185 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
 186 {
 187         int ctrl;
 188
 189         ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
 190         if (ctrl < 0)
 191                 return ctrl;
 192
 193         if (val)
 194                 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
 195         else
 196                 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
 197
 198         return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
 199 }
 200
 201 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
 202 {
 203         int rc, temp, shift;
 204
 205         switch (reg) {
 206         case MII_KSZPHY_CTRL_1:
 207                 shift = 14;
 208                 break;
 209         case MII_KSZPHY_CTRL_2:
 210                 shift = 4;
 211                 break;
 212         default:
 213                 return -EINVAL;
 214         }
 215
 216         temp = phy_read(phydev, reg);
 217         if (temp < 0) {
 218                 rc = temp;
 219                 goto out;
 220         }
 221
 222         temp &= ~(3 << shift);
 223         temp |= val << shift;
 224         rc = phy_write(phydev, reg, temp);
 225 out:
 226         if (rc < 0)
 227                 phydev_err(phydev, "failed to set led mode\n");
 228
 229         return rc;
 230 }
 231
 232 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
 233  * unique (non-broadcast) address on a shared bus.
 234  */
 235 static int kszphy_broadcast_disable(struct phy_device *phydev)
 236 {
 237         int ret;
 238
 239         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 240         if (ret < 0)
 241                 goto out;
 242
 243         ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
 244 out:
 245         if (ret)
 246                 phydev_err(phydev, "failed to disable broadcast address\n");
 247
 248         return ret;
 249 }
 250
 251 static int kszphy_nand_tree_disable(struct phy_device *phydev)
 252 {
 253         int ret;
 254
 255         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 256         if (ret < 0)
 257                 goto out;
 258
 259         if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
 260                 return 0;
 261
 262         ret = phy_write(phydev, MII_KSZPHY_OMSO,
 263                         ret & ~KSZPHY_OMSO_NAND_TREE_ON);
 264 out:
 265         if (ret)
 266                 phydev_err(phydev, "failed to disable NAND tree mode\n");
 267
 268         return ret;
 269 }
 270
 271 /* Some config bits need to be set again on resume, handle them here. */
 272 static int kszphy_config_reset(struct phy_device *phydev)
 273 {
 274         struct kszphy_priv *priv = phydev->priv;
 275         int ret;
 276
 277         if (priv->rmii_ref_clk_sel) {
 278                 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
 279                 if (ret) {
 280                         phydev_err(phydev,
 281                                    "failed to set rmii reference clock\n");
 282                         return ret;
 283                 }
 284         }
 285
 286         if (priv->led_mode >= 0)
 287                 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
 288
 289         return 0;
 290 }
 291
 292 static int kszphy_config_init(struct phy_device *phydev)
 293 {
 294         struct kszphy_priv *priv = phydev->priv;
 295         const struct kszphy_type *type;
 296
 297         if (!priv)
 298                 return 0;
 299
 300         type = priv->type;
 301
 302         if (type->has_broadcast_disable)
 303                 kszphy_broadcast_disable(phydev);
 304
 305         if (type->has_nand_tree_disable)
 306                 kszphy_nand_tree_disable(phydev);
 307
 308         return kszphy_config_reset(phydev);
 309 }
 310
 311 static int ksz8041_config_init(struct phy_device *phydev)
 312 {
 313         struct device_node *of_node = phydev->mdio.dev.of_node;
 314
 315         /* Limit supported and advertised modes in fiber mode */
 316         if (of_property_read_bool(of_node, "micrel,fiber-mode")) {
 317                 phydev->dev_flags |= MICREL_PHY_FXEN;
 318                 phydev->supported &= SUPPORTED_100baseT_Full |
 319                                      SUPPORTED_100baseT_Half;
 320                 phydev->supported |= SUPPORTED_FIBRE;
 321                 phydev->advertising &= ADVERTISED_100baseT_Full |
 322                                        ADVERTISED_100baseT_Half;
 323                 phydev->advertising |= ADVERTISED_FIBRE;
 324                 phydev->autoneg = AUTONEG_DISABLE;
 325         }
 326
 327         return kszphy_config_init(phydev);
 328 }
 329
 330 static int ksz8041_config_aneg(struct phy_device *phydev)
 331 {
 332         /* Skip auto-negotiation in fiber mode */
 333         if (phydev->dev_flags & MICREL_PHY_FXEN) {
 334                 phydev->speed = SPEED_100;
 335                 return 0;
 336         }
 337
 338         return genphy_config_aneg(phydev);
 339 }
 340
 341 static int ksz9021_load_values_from_of(struct phy_device *phydev,
 342                                        const struct device_node *of_node,
 343                                        u16 reg,
 344                                        const char *field1, const char *field2,
 345                                        const char *field3, const char *field4)
 346 {
 347         int val1 = -1;
 348         int val2 = -2;
 349         int val3 = -3;
 350         int val4 = -4;
 351         int newval;
 352         int matches = 0;
 353
 354         if (!of_property_read_u32(of_node, field1, &val1))
 355                 matches++;
 356
 357         if (!of_property_read_u32(of_node, field2, &val2))
 358                 matches++;
 359
 360         if (!of_property_read_u32(of_node, field3, &val3))
 361                 matches++;
 362
 363         if (!of_property_read_u32(of_node, field4, &val4))
 364                 matches++;
 365
 366         if (!matches)
 367                 return 0;
 368
 369         if (matches < 4)
 370                 newval = kszphy_extended_read(phydev, reg);
 371         else
 372                 newval = 0;
 373
 374         if (val1 != -1)
 375                 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
 376
 377         if (val2 != -2)
 378                 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
 379
 380         if (val3 != -3)
 381                 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
 382
 383         if (val4 != -4)
 384                 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
 385
 386         return kszphy_extended_write(phydev, reg, newval);
 387 }
 388
 389 static int ksz9021_config_init(struct phy_device *phydev)
 390 {
 391         const struct device *dev = &phydev->mdio.dev;
 392         const struct device_node *of_node = dev->of_node;
 393         const struct device *dev_walker;
 394
 395         /* The Micrel driver has a deprecated option to place phy OF
 396          * properties in the MAC node. Walk up the tree of devices to
 397          * find a device with an OF node.
 398          */
 399         dev_walker = &phydev->mdio.dev;
 400         do {
 401                 of_node = dev_walker->of_node;
 402                 dev_walker = dev_walker->parent;
 403
 404         } while (!of_node && dev_walker);
 405
 406         if (of_node) {
 407                 ksz9021_load_values_from_of(phydev, of_node,
 408                                     MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
 409                                     "txen-skew-ps", "txc-skew-ps",
 410                                     "rxdv-skew-ps", "rxc-skew-ps");
 411                 ksz9021_load_values_from_of(phydev, of_node,
 412                                     MII_KSZPHY_RX_DATA_PAD_SKEW,
 413                                     "rxd0-skew-ps", "rxd1-skew-ps",
 414                                     "rxd2-skew-ps", "rxd3-skew-ps");
 415                 ksz9021_load_values_from_of(phydev, of_node,
 416                                     MII_KSZPHY_TX_DATA_PAD_SKEW,
 417                                     "txd0-skew-ps", "txd1-skew-ps",
 418                                     "txd2-skew-ps", "txd3-skew-ps");
 419         }
 420         return 0;
 421 }
 422
 423 #define MII_KSZ9031RN_MMD_CTRL_REG      0x0d
 424 #define MII_KSZ9031RN_MMD_REGDATA_REG   0x0e
 425 #define OP_DATA                         1
 426 #define KSZ9031_PS_TO_REG               60
 427
 428 /* Extended registers */
 429 /* MMD Address 0x0 */
 430 #define MII_KSZ9031RN_FLP_BURST_TX_LO   3
 431 #define MII_KSZ9031RN_FLP_BURST_TX_HI   4
 432
 433 /* MMD Address 0x2 */
 434 #define MII_KSZ9031RN_CONTROL_PAD_SKEW  4
 435 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW  5
 436 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW  6
 437 #define MII_KSZ9031RN_CLK_PAD_SKEW      8
 438
 439 /* MMD Address 0x1C */
 440 #define MII_KSZ9031RN_EDPD              0x23
 441 #define MII_KSZ9031RN_EDPD_ENABLE       BIT(0)
 442
 443 static int ksz9031_extended_write(struct phy_device *phydev,
 444                                   u8 mode, u32 dev_addr, u32 regnum, u16 val)
 445 {
 446         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
 447         phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
 448         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
 449         return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
 450 }
 451
 452 static int ksz9031_extended_read(struct phy_device *phydev,
 453                                  u8 mode, u32 dev_addr, u32 regnum)
 454 {
 455         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
 456         phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
 457         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
 458         return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
 459 }
 460
 461 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
 462                                        const struct device_node *of_node,
 463                                        u16 reg, size_t field_sz,
 464                                        const char *field[], u8 numfields)
 465 {
 466         int val[4] = {-1, -2, -3, -4};
 467         int matches = 0;
 468         u16 mask;
 469         u16 maxval;
 470         u16 newval;
 471         int i;
 472
 473         for (i = 0; i < numfields; i++)
 474                 if (!of_property_read_u32(of_node, field[i], val + i))
 475                         matches++;
 476
 477         if (!matches)
 478                 return 0;
 479
 480         if (matches < numfields)
 481                 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
 482         else
 483                 newval = 0;
 484
 485         maxval = (field_sz == 4) ? 0xf : 0x1f;
 486         for (i = 0; i < numfields; i++)
 487                 if (val[i] != -(i + 1)) {
 488                         mask = 0xffff;
 489                         mask ^= maxval << (field_sz * i);
 490                         newval = (newval & mask) |
 491                                 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
 492                                         << (field_sz * i));
 493                 }
 494
 495         return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
 496 }
 497
 498 static int ksz9031_center_flp_timing(struct phy_device *phydev)
 499 {
 500         int result;
 501
 502         /* Center KSZ9031RNX FLP timing at 16ms. */
 503         result = ksz9031_extended_write(phydev, OP_DATA, 0,
 504                                         MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
 505         result = ksz9031_extended_write(phydev, OP_DATA, 0,
 506                                         MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
 507
 508         if (result)
 509                 return result;
 510
 511         return genphy_restart_aneg(phydev);
 512 }
 513
 514 /* Enable energy-detect power-down mode */
 515 static int ksz9031_enable_edpd(struct phy_device *phydev)
 516 {
 517         int reg;
 518
 519         reg = ksz9031_extended_read(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD);
 520         if (reg < 0)
 521                 return reg;
 522         return ksz9031_extended_write(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD,
 523                                       reg | MII_KSZ9031RN_EDPD_ENABLE);
 524 }
 525
 526 static int ksz9031_config_init(struct phy_device *phydev)
 527 {
 528         const struct device *dev = &phydev->mdio.dev;
 529         const struct device_node *of_node = dev->of_node;
 530         static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
 531         static const char *rx_data_skews[4] = {
 532                 "rxd0-skew-ps", "rxd1-skew-ps",
 533                 "rxd2-skew-ps", "rxd3-skew-ps"
 534         };
 535         static const char *tx_data_skews[4] = {
 536                 "txd0-skew-ps", "txd1-skew-ps",
 537                 "txd2-skew-ps", "txd3-skew-ps"
 538         };
 539         static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
 540         const struct device *dev_walker;
 541         int result;
 542
 543         result = ksz9031_enable_edpd(phydev);
 544         if (result < 0)
 545                 return result;
 546
 547         /* The Micrel driver has a deprecated option to place phy OF
 548          * properties in the MAC node. Walk up the tree of devices to
 549          * find a device with an OF node.
 550          */
 551         dev_walker = &phydev->mdio.dev;
 552         do {
 553                 of_node = dev_walker->of_node;
 554                 dev_walker = dev_walker->parent;
 555         } while (!of_node && dev_walker);
 556
 557         if (of_node) {
 558                 ksz9031_of_load_skew_values(phydev, of_node,
 559                                 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
 560                                 clk_skews, 2);
 561
 562                 ksz9031_of_load_skew_values(phydev, of_node,
 563                                 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
 564                                 control_skews, 2);
 565
 566                 ksz9031_of_load_skew_values(phydev, of_node,
 567                                 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
 568                                 rx_data_skews, 4);
 569
 570                 ksz9031_of_load_skew_values(phydev, of_node,
 571                                 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
 572                                 tx_data_skews, 4);
 573         }
 574
 575         return ksz9031_center_flp_timing(phydev);
 576 }
 577
 578 #define KSZ8873MLL_GLOBAL_CONTROL_4     0x06
 579 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX      BIT(6)
 580 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED       BIT(4)
 581 static int ksz8873mll_read_status(struct phy_device *phydev)
 582 {
 583         int regval;
 584
 585         /* dummy read */
 586         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
 587
 588         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
 589
 590         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
 591                 phydev->duplex = DUPLEX_HALF;
 592         else
 593                 phydev->duplex = DUPLEX_FULL;
 594
 595         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
 596                 phydev->speed = SPEED_10;
 597         else
 598                 phydev->speed = SPEED_100;
 599
 600         phydev->link = 1;
 601         phydev->pause = phydev->asym_pause = 0;
 602
 603         return 0;
 604 }
 605
 606 static int ksz9031_read_status(struct phy_device *phydev)
 607 {
 608         int err;
 609         int regval;
 610
 611         err = genphy_read_status(phydev);
 612         if (err)
 613                 return err;
 614
 615         /* Make sure the PHY is not broken. Read idle error count,
 616          * and reset the PHY if it is maxed out.
 617          */
 618         regval = phy_read(phydev, MII_STAT1000);
 619         if ((regval & 0xFF) == 0xFF) {
 620                 phy_init_hw(phydev);
 621                 phydev->link = 0;
 622                 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
 623                         phydev->drv->config_intr(phydev);
 624         }
 625
 626         return 0;
 627 }
 628
 629 static int ksz8873mll_config_aneg(struct phy_device *phydev)
 630 {
 631         return 0;
 632 }
 633
 634 /* This routine returns -1 as an indication to the caller that the
 635  * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE
 636  * MMD extended PHY registers.
 637  */
 638 static int
 639 ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int devad, u16 regnum)
 640 {
 641         return -1;
 642 }
 643
 644 /* This routine does nothing since the Micrel ksz9021 does not support
 645  * standard IEEE MMD extended PHY registers.
 646  */
 647 static int
 648 ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int devad, u16 regnum, u16 val)
 649 {
 650         return -1;
 651 }
 652
 653 static int kszphy_get_sset_count(struct phy_device *phydev)
 654 {
 655         return ARRAY_SIZE(kszphy_hw_stats);
 656 }
 657
 658 static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
 659 {
 660         int i;
 661
 662         for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
 663                 memcpy(data + i * ETH_GSTRING_LEN,
 664                        kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
 665         }
 666 }
 667
 668 #ifndef UINT64_MAX
 669 #define UINT64_MAX              (u64)(~((u64)0))
 670 #endif
 671 static u64 kszphy_get_stat(struct phy_device *phydev, int i)
 672 {
 673         struct kszphy_hw_stat stat = kszphy_hw_stats[i];
 674         struct kszphy_priv *priv = phydev->priv;
 675         int val;
 676         u64 ret;
 677
 678         val = phy_read(phydev, stat.reg);
 679         if (val < 0) {
 680                 ret = UINT64_MAX;
 681         } else {
 682                 val = val & ((1 << stat.bits) - 1);
 683                 priv->stats[i] += val;
 684                 ret = priv->stats[i];
 685         }
 686
 687         return ret;
 688 }
 689
 690 static void kszphy_get_stats(struct phy_device *phydev,
 691                              struct ethtool_stats *stats, u64 *data)
 692 {
 693         int i;
 694
 695         for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
 696                 data[i] = kszphy_get_stat(phydev, i);
 697 }
 698
 699 static int kszphy_suspend(struct phy_device *phydev)
 700 {
 701         /* Disable PHY Interrupts */
 702         if (phy_interrupt_is_valid(phydev)) {
 703                 phydev->interrupts = PHY_INTERRUPT_DISABLED;
 704                 if (phydev->drv->config_intr)
 705                         phydev->drv->config_intr(phydev);
 706         }
 707
 708         return genphy_suspend(phydev);
 709 }
 710
 711 static int kszphy_resume(struct phy_device *phydev)
 712 {
 713         int ret;
 714
 715         genphy_resume(phydev);
 716
 717         ret = kszphy_config_reset(phydev);
 718         if (ret)
 719                 return ret;
 720
 721         /* Enable PHY Interrupts */
 722         if (phy_interrupt_is_valid(phydev)) {
 723                 phydev->interrupts = PHY_INTERRUPT_ENABLED;
 724                 if (phydev->drv->config_intr)
 725                         phydev->drv->config_intr(phydev);
 726         }
 727
 728         return 0;
 729 }
 730
 731 static int kszphy_probe(struct phy_device *phydev)
 732 {
 733         const struct kszphy_type *type = phydev->drv->driver_data;
 734         const struct device_node *np = phydev->mdio.dev.of_node;
 735         struct kszphy_priv *priv;
 736         struct clk *clk;
 737         int ret;
 738
 739         priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
 740         if (!priv)
 741                 return -ENOMEM;
 742
 743         phydev->priv = priv;
 744
 745         priv->type = type;
 746
 747         if (type->led_mode_reg) {
 748                 ret = of_property_read_u32(np, "micrel,led-mode",
 749                                 &priv->led_mode);
 750                 if (ret)
 751                         priv->led_mode = -1;
 752
 753                 if (priv->led_mode > 3) {
 754                         phydev_err(phydev, "invalid led mode: 0x%02x\n",
 755                                    priv->led_mode);
 756                         priv->led_mode = -1;
 757                 }
 758         } else {
 759                 priv->led_mode = -1;
 760         }
 761
 762         clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
 763         /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
 764         if (!IS_ERR_OR_NULL(clk)) {
 765                 unsigned long rate = clk_get_rate(clk);
 766                 bool rmii_ref_clk_sel_25_mhz;
 767
 768                 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
 769                 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
 770                                 "micrel,rmii-reference-clock-select-25-mhz");
 771
 772                 if (rate > 24500000 && rate < 25500000) {
 773                         priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
 774                 } else if (rate > 49500000 && rate < 50500000) {
 775                         priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
 776                 } else {
 777                         phydev_err(phydev, "Clock rate out of range: %ld\n",
 778                                    rate);
 779                         return -EINVAL;
 780                 }
 781         }
 782
 783         /* Support legacy board-file configuration */
 784         if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
 785                 priv->rmii_ref_clk_sel = true;
 786                 priv->rmii_ref_clk_sel_val = true;
 787         }
 788
 789         return 0;
 790 }
 791
 792 static struct phy_driver ksphy_driver[] = {
 793 {
 794         .phy_id         = PHY_ID_KS8737,
 795         .phy_id_mask    = MICREL_PHY_ID_MASK,
 796         .name           = "Micrel KS8737",
 797         .features       = PHY_BASIC_FEATURES,
 798         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 799         .driver_data    = &ks8737_type,
 800         .config_init    = kszphy_config_init,
 801         .config_aneg    = genphy_config_aneg,
 802         .read_status    = genphy_read_status,
 803         .ack_interrupt  = kszphy_ack_interrupt,
 804         .config_intr    = kszphy_config_intr,
 805         .suspend        = genphy_suspend,
 806         .resume         = genphy_resume,
 807 }, {
 808         .phy_id         = PHY_ID_KSZ8021,
 809         .phy_id_mask    = 0x00ffffff,
 810         .name           = "Micrel KSZ8021 or KSZ8031",
 811         .features       = PHY_BASIC_FEATURES,
 812         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 813         .driver_data    = &ksz8021_type,
 814         .probe          = kszphy_probe,
 815         .config_init    = kszphy_config_init,
 816         .config_aneg    = genphy_config_aneg,
 817         .read_status    = genphy_read_status,
 818         .ack_interrupt  = kszphy_ack_interrupt,
 819         .config_intr    = kszphy_config_intr,
 820         .get_sset_count = kszphy_get_sset_count,
 821         .get_strings    = kszphy_get_strings,
 822         .get_stats      = kszphy_get_stats,
 823         .suspend        = genphy_suspend,
 824         .resume         = genphy_resume,
 825 }, {
 826         .phy_id         = PHY_ID_KSZ8031,
 827         .phy_id_mask    = 0x00ffffff,
 828         .name           = "Micrel KSZ8031",
 829         .features       = PHY_BASIC_FEATURES,
 830         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 831         .driver_data    = &ksz8021_type,
 832         .probe          = kszphy_probe,
 833         .config_init    = kszphy_config_init,
 834         .config_aneg    = genphy_config_aneg,
 835         .read_status    = genphy_read_status,
 836         .ack_interrupt  = kszphy_ack_interrupt,
 837         .config_intr    = kszphy_config_intr,
 838         .get_sset_count = kszphy_get_sset_count,
 839         .get_strings    = kszphy_get_strings,
 840         .get_stats      = kszphy_get_stats,
 841         .suspend        = genphy_suspend,
 842         .resume         = genphy_resume,
 843 }, {
 844         .phy_id         = PHY_ID_KSZ8041,
 845         .phy_id_mask    = MICREL_PHY_ID_MASK,
 846         .name           = "Micrel KSZ8041",
 847         .features       = PHY_BASIC_FEATURES,
 848         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 849         .driver_data    = &ksz8041_type,
 850         .probe          = kszphy_probe,
 851         .config_init    = ksz8041_config_init,
 852         .config_aneg    = ksz8041_config_aneg,
 853         .read_status    = genphy_read_status,
 854         .ack_interrupt  = kszphy_ack_interrupt,
 855         .config_intr    = kszphy_config_intr,
 856         .get_sset_count = kszphy_get_sset_count,
 857         .get_strings    = kszphy_get_strings,
 858         .get_stats      = kszphy_get_stats,
 859         .suspend        = genphy_suspend,
 860         .resume         = genphy_resume,
 861 }, {
 862         .phy_id         = PHY_ID_KSZ8041RNLI,
 863         .phy_id_mask    = MICREL_PHY_ID_MASK,
 864         .name           = "Micrel KSZ8041RNLI",
 865         .features       = PHY_BASIC_FEATURES,
 866         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 867         .driver_data    = &ksz8041_type,
 868         .probe          = kszphy_probe,
 869         .config_init    = kszphy_config_init,
 870         .config_aneg    = genphy_config_aneg,
 871         .read_status    = genphy_read_status,
 872         .ack_interrupt  = kszphy_ack_interrupt,
 873         .config_intr    = kszphy_config_intr,
 874         .get_sset_count = kszphy_get_sset_count,
 875         .get_strings    = kszphy_get_strings,
 876         .get_stats      = kszphy_get_stats,
 877         .suspend        = genphy_suspend,
 878         .resume         = genphy_resume,
 879 }, {
 880         .phy_id         = PHY_ID_KSZ8051,
 881         .phy_id_mask    = MICREL_PHY_ID_MASK,
 882         .name           = "Micrel KSZ8051",
 883         .features       = PHY_BASIC_FEATURES,
 884         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 885         .driver_data    = &ksz8051_type,
 886         .probe          = kszphy_probe,
 887         .config_init    = kszphy_config_init,
 888         .config_aneg    = genphy_config_aneg,
 889         .read_status    = genphy_read_status,
 890         .ack_interrupt  = kszphy_ack_interrupt,
 891         .config_intr    = kszphy_config_intr,
 892         .get_sset_count = kszphy_get_sset_count,
 893         .get_strings    = kszphy_get_strings,
 894         .get_stats      = kszphy_get_stats,
 895         .suspend        = genphy_suspend,
 896         .resume         = genphy_resume,
 897 }, {
 898         .phy_id         = PHY_ID_KSZ8001,
 899         .name           = "Micrel KSZ8001 or KS8721",
 900         .phy_id_mask    = 0x00fffffc,
 901         .features       = PHY_BASIC_FEATURES,
 902         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 903         .driver_data    = &ksz8041_type,
 904         .probe          = kszphy_probe,
 905         .config_init    = kszphy_config_init,
 906         .config_aneg    = genphy_config_aneg,
 907         .read_status    = genphy_read_status,
 908         .ack_interrupt  = kszphy_ack_interrupt,
 909         .config_intr    = kszphy_config_intr,
 910         .get_sset_count = kszphy_get_sset_count,
 911         .get_strings    = kszphy_get_strings,
 912         .get_stats      = kszphy_get_stats,
 913         .suspend        = genphy_suspend,
 914         .resume         = genphy_resume,
 915 }, {
 916         .phy_id         = PHY_ID_KSZ8081,
 917         .name           = "Micrel KSZ8081 or KSZ8091",
 918         .phy_id_mask    = MICREL_PHY_ID_MASK,
 919         .features       = PHY_BASIC_FEATURES,
 920         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 921         .driver_data    = &ksz8081_type,
 922         .probe          = kszphy_probe,
 923         .config_init    = kszphy_config_init,
 924         .config_aneg    = genphy_config_aneg,
 925         .read_status    = genphy_read_status,
 926         .ack_interrupt  = kszphy_ack_interrupt,
 927         .config_intr    = kszphy_config_intr,
 928         .get_sset_count = kszphy_get_sset_count,
 929         .get_strings    = kszphy_get_strings,
 930         .get_stats      = kszphy_get_stats,
 931         .suspend        = kszphy_suspend,
 932         .resume         = kszphy_resume,
 933 }, {
 934         .phy_id         = PHY_ID_KSZ8061,
 935         .name           = "Micrel KSZ8061",
 936         .phy_id_mask    = MICREL_PHY_ID_MASK,
 937         .features       = PHY_BASIC_FEATURES,
 938         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 939         .config_init    = kszphy_config_init,
 940         .config_aneg    = genphy_config_aneg,
 941         .read_status    = genphy_read_status,
 942         .ack_interrupt  = kszphy_ack_interrupt,
 943         .config_intr    = kszphy_config_intr,
 944         .suspend        = genphy_suspend,
 945         .resume         = genphy_resume,
 946 }, {
 947         .phy_id         = PHY_ID_KSZ9021,
 948         .phy_id_mask    = 0x000ffffe,
 949         .name           = "Micrel KSZ9021 Gigabit PHY",
 950         .features       = PHY_GBIT_FEATURES,
 951         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 952         .driver_data    = &ksz9021_type,
 953         .probe          = kszphy_probe,
 954         .config_init    = ksz9021_config_init,
 955         .config_aneg    = genphy_config_aneg,
 956         .read_status    = genphy_read_status,
 957         .ack_interrupt  = kszphy_ack_interrupt,
 958         .config_intr    = kszphy_config_intr,
 959         .get_sset_count = kszphy_get_sset_count,
 960         .get_strings    = kszphy_get_strings,
 961         .get_stats      = kszphy_get_stats,
 962         .suspend        = genphy_suspend,
 963         .resume         = genphy_resume,
 964         .read_mmd       = ksz9021_rd_mmd_phyreg,
 965         .write_mmd      = ksz9021_wr_mmd_phyreg,
 966 }, {
 967         .phy_id         = PHY_ID_KSZ9031,
 968         .phy_id_mask    = MICREL_PHY_ID_MASK,
 969         .name           = "Micrel KSZ9031 Gigabit PHY",
 970         .features       = PHY_GBIT_FEATURES,
 971         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 972         .driver_data    = &ksz9021_type,
 973         .probe          = kszphy_probe,
 974         .config_init    = ksz9031_config_init,
 975         .config_aneg    = genphy_config_aneg,
 976         .read_status    = ksz9031_read_status,
 977         .ack_interrupt  = kszphy_ack_interrupt,
 978         .config_intr    = kszphy_config_intr,
 979         .get_sset_count = kszphy_get_sset_count,
 980         .get_strings    = kszphy_get_strings,
 981         .get_stats      = kszphy_get_stats,
 982         .suspend        = genphy_suspend,
 983         .resume         = kszphy_resume,
 984 }, {
 985         .phy_id         = PHY_ID_KSZ8873MLL,
 986         .phy_id_mask    = MICREL_PHY_ID_MASK,
 987         .name           = "Micrel KSZ8873MLL Switch",
 988         .flags          = PHY_HAS_MAGICANEG,
 989         .config_init    = kszphy_config_init,
 990         .config_aneg    = ksz8873mll_config_aneg,
 991         .read_status    = ksz8873mll_read_status,
 992         .suspend        = genphy_suspend,
 993         .resume         = genphy_resume,
 994 }, {
 995         .phy_id         = PHY_ID_KSZ886X,
 996         .phy_id_mask    = MICREL_PHY_ID_MASK,
 997         .name           = "Micrel KSZ886X Switch",
 998         .features       = PHY_BASIC_FEATURES,
 999         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
1000         .config_init    = kszphy_config_init,
1001         .config_aneg    = genphy_config_aneg,
1002         .read_status    = genphy_read_status,
1003         .suspend        = genphy_suspend,
1004         .resume         = genphy_resume,
1005 }, {
1006         .phy_id         = PHY_ID_KSZ8795,
1007         .phy_id_mask    = MICREL_PHY_ID_MASK,
1008         .name           = "Micrel KSZ8795",
1009         .features       = PHY_BASIC_FEATURES,
1010         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
1011         .config_init    = kszphy_config_init,
1012         .config_aneg    = ksz8873mll_config_aneg,
1013         .read_status    = ksz8873mll_read_status,
1014         .suspend        = genphy_suspend,
1015         .resume         = genphy_resume,
1016 } };
1017
1018 module_phy_driver(ksphy_driver);
1019
1020 MODULE_DESCRIPTION("Micrel PHY driver");
1021 MODULE_AUTHOR("David J. Choi");
1022 MODULE_LICENSE("GPL");
1023
1024 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
1025         { PHY_ID_KSZ9021, 0x000ffffe },
1026         { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
1027         { PHY_ID_KSZ8001, 0x00fffffc },
1028         { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
1029         { PHY_ID_KSZ8021, 0x00ffffff },
1030         { PHY_ID_KSZ8031, 0x00ffffff },
1031         { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
1032         { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
1033         { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
1034         { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
1035         { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
1036         { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
1037         { }
1038 };
1039
1040 MODULE_DEVICE_TABLE(mdio, micrel_tbl);