drivers/net/wan/pc300_drv.c

   1 #define USE_PCI_CLOCK
   2 static char rcsid[] =
   3 "Revision: 3.4.5 Date: 2002/03/07 ";
   4
   5 /*
   6  * pc300.c      Cyclades-PC300(tm) Driver.
   7  *
   8  * Author:      Ivan Passos <ivan@cyclades.com>
   9  * Maintainer:  PC300 Maintainer <pc300@cyclades.com>
  10  *
  11  * Copyright:   (c) 1999-2003 Cyclades Corp.
  12  *
  13  *      This program is free software; you can redistribute it and/or
  14  *      modify it under the terms of the GNU General Public License
  15  *      as published by the Free Software Foundation; either version
  16  *      2 of the License, or (at your option) any later version.
  17  *
  18  *      Using tabstop = 4.
  19  *
  20  * $Log: pc300_drv.c,v $
  21  * Revision 3.23  2002/03/20 13:58:40  henrique
  22  * Fixed ortographic mistakes
  23  *
  24  * Revision 3.22  2002/03/13 16:56:56  henrique
  25  * Take out the debug messages
  26  *
  27  * Revision 3.21  2002/03/07 14:17:09  henrique
  28  * License data fixed
  29  *
  30  * Revision 3.20  2002/01/17 17:58:52  ivan
  31  * Support for PC300-TE/M (PMC).
  32  *
  33  * Revision 3.19  2002/01/03 17:08:47  daniela
  34  * Enables DMA reception when the SCA-II disables it improperly.
  35  *
  36  * Revision 3.18  2001/12/03 18:47:50  daniela
  37  * Esthetic changes.
  38  *
  39  * Revision 3.17  2001/10/19 16:50:13  henrique
  40  * Patch to kernel 2.4.12 and new generic hdlc.
  41  *
  42  * Revision 3.16  2001/10/16 15:12:31  regina
  43  * clear statistics
  44  *
  45  * Revision 3.11 to 3.15  2001/10/11 20:26:04  daniela
  46  * More DMA fixes for noisy lines.
  47  * Return the size of bad frames in dma_get_rx_frame_size, so that the Rx buffer
  48  * descriptors can be cleaned by dma_buf_read (called in cpc_net_rx).
  49  * Renamed dma_start routine to rx_dma_start. Improved Rx statistics.
  50  * Fixed BOF interrupt treatment. Created dma_start routine.
  51  * Changed min and max to cpc_min and cpc_max.
  52  *
  53  * Revision 3.10  2001/08/06 12:01:51  regina
  54  * Fixed problem in DSR_DE bit.
  55  *
  56  * Revision 3.9  2001/07/18 19:27:26  daniela
  57  * Added some history comments.
  58  *
  59  * Revision 3.8  2001/07/12 13:11:19  regina
  60  * bug fix - DCD-OFF in pc300 tty driver
  61  *
  62  * Revision 3.3 to 3.7  2001/07/06 15:00:20  daniela
  63  * Removing kernel 2.4.3 and previous support.
  64  * DMA transmission bug fix.
  65  * MTU check in cpc_net_rx fixed.
  66  * Boot messages reviewed.
  67  * New configuration parameters (line code, CRC calculation and clock).
  68  *
  69  * Revision 3.2 2001/06/22 13:13:02  regina
  70  * MLPPP implementation. Changed the header of message trace to include
  71  * the device name. New format : "hdlcX[R/T]: ".
  72  * Default configuration changed.
  73  *
  74  * Revision 3.1 2001/06/15 regina
  75  * in cpc_queue_xmit, netif_stop_queue is called if don't have free descriptor
  76  * upping major version number
  77  *
  78  * Revision 1.1.1.1  2001/06/13 20:25:04  daniela
  79  * PC300 initial CVS version (3.4.0-pre1)
  80  *
  81  * Revision 3.0.1.2 2001/06/08 daniela
  82  * Did some changes in the DMA programming implementation to avoid the
  83  * occurrence of a SCA-II bug when CDA is accessed during a DMA transfer.
  84  *
  85  * Revision 3.0.1.1 2001/05/02 daniela
  86  * Added kernel 2.4.3 support.
  87  *
  88  * Revision 3.0.1.0 2001/03/13 daniela, henrique
  89  * Added Frame Relay Support.
  90  * Driver now uses HDLC generic driver to provide protocol support.
  91  *
  92  * Revision 3.0.0.8 2001/03/02 daniela
  93  * Fixed ram size detection.
  94  * Changed SIOCGPC300CONF ioctl, to give hw information to pc300util.
  95  *
  96  * Revision 3.0.0.7 2001/02/23 daniela
  97  * netif_stop_queue called before the SCA-II transmition commands in
  98  * cpc_queue_xmit, and with interrupts disabled to avoid race conditions with
  99  * transmition interrupts.
 100  * Fixed falc_check_status for Unframed E1.
 101  *
 102  * Revision 3.0.0.6 2000/12/13 daniela
 103  * Implemented pc300util support: trace, statistics, status and loopback
 104  * tests for the PC300 TE boards.
 105  *
 106  * Revision 3.0.0.5 2000/12/12 ivan
 107  * Added support for Unframed E1.
 108  * Implemented monitor mode.
 109  * Fixed DCD sensitivity on the second channel.
 110  * Driver now complies with new PCI kernel architecture.
 111  *
 112  * Revision 3.0.0.4 2000/09/28 ivan
 113  * Implemented DCD sensitivity.
 114  * Moved hardware-specific open to the end of cpc_open, to avoid race
 115  * conditions with early reception interrupts.
 116  * Included code for [request|release]_mem_region().
 117  * Changed location of pc300.h .
 118  * Minor code revision (contrib. of Jeff Garzik).
 119  *
 120  * Revision 3.0.0.3 2000/07/03 ivan
 121  * Previous bugfix for the framing errors with external clock made X21
 122  * boards stop working. This version fixes it.
 123  *
 124  * Revision 3.0.0.2 2000/06/23 ivan
 125  * Revisited cpc_queue_xmit to prevent race conditions on Tx DMA buffer
 126  * handling when Tx timeouts occur.
 127  * Revisited Rx statistics.
 128  * Fixed a bug in the SCA-II programming that would cause framing errors
 129  * when external clock was configured.
 130  *
 131  * Revision 3.0.0.1 2000/05/26 ivan
 132  * Added logic in the SCA interrupt handler so that no board can monopolize
 133  * the driver.
 134  * Request PLX I/O region, although driver doesn't use it, to avoid
 135  * problems with other drivers accessing it.
 136  *
 137  * Revision 3.0.0.0 2000/05/15 ivan
 138  * Did some changes in the DMA programming implementation to avoid the
 139  * occurrence of a SCA-II bug in the second channel.
 140  * Implemented workaround for PLX9050 bug that would cause a system lockup
 141  * in certain systems, depending on the MMIO addresses allocated to the
 142  * board.
 143  * Fixed the FALC chip programming to avoid synchronization problems in the
 144  * second channel (TE only).
 145  * Implemented a cleaner and faster Tx DMA descriptor cleanup procedure in
 146  * cpc_queue_xmit().
 147  * Changed the built-in driver implementation so that the driver can use the
 148  * general 'hdlcN' naming convention instead of proprietary device names.
 149  * Driver load messages are now device-centric, instead of board-centric.
 150  * Dynamic allocation of net_device structures.
 151  * Code is now compliant with the new module interface (module_[init|exit]).
 152  * Make use of the PCI helper functions to access PCI resources.
 153  *
 154  * Revision 2.0.0.0 2000/04/15 ivan
 155  * Added support for the PC300/TE boards (T1/FT1/E1/FE1).
 156  *
 157  * Revision 1.1.0.0 2000/02/28 ivan
 158  * Major changes in the driver architecture.
 159  * Softnet compliancy implemented.
 160  * Driver now reports physical instead of virtual memory addresses.
 161  * Added cpc_change_mtu function.
 162  *
 163  * Revision 1.0.0.0 1999/12/16 ivan
 164  * First official release.
 165  * Support for 1- and 2-channel boards (which use distinct PCI Device ID's).
 166  * Support for monolythic installation (i.e., drv built into the kernel).
 167  * X.25 additional checking when lapb_[dis]connect_request returns an error.
 168  * SCA programming now covers X.21 as well.
 169  *
 170  * Revision 0.3.1.0 1999/11/18 ivan
 171  * Made X.25 support configuration-dependent (as it depends on external
 172  * modules to work).
 173  * Changed X.25-specific function names to comply with adopted convention.
 174  * Fixed typos in X.25 functions that would cause compile errors (Daniela).
 175  * Fixed bug in ch_config that would disable interrupts on a previously
 176  * enabled channel if the other channel on the same board was enabled later.
 177  *
 178  * Revision 0.3.0.0 1999/11/16 daniela
 179  * X.25 support.
 180  *
 181  * Revision 0.2.3.0 1999/11/15 ivan
 182  * Function cpc_ch_status now provides more detailed information.
 183  * Added support for X.21 clock configuration.
 184  * Changed TNR1 setting in order to prevent Tx FIFO overaccesses by the SCA.
 185  * Now using PCI clock instead of internal oscillator clock for the SCA.
 186  *
 187  * Revision 0.2.2.0 1999/11/10 ivan
 188  * Changed the *_dma_buf_check functions so that they would print only
 189  * the useful info instead of the whole buffer descriptor bank.
 190  * Fixed bug in cpc_queue_xmit that would eventually crash the system
 191  * in case of a packet drop.
 192  * Implemented TX underrun handling.
 193  * Improved SCA fine tuning to boost up its performance.
 194  *
 195  * Revision 0.2.1.0 1999/11/03 ivan
 196  * Added functions *dma_buf_pt_init to allow independent initialization
 197  * of the next-descr. and DMA buffer pointers on the DMA descriptors.
 198  * Kernel buffer release and tbusy clearing is now done in the interrupt
 199  * handler.
 200  * Fixed bug in cpc_open that would cause an interface reopen to fail.
 201  * Added a protocol-specific code section in cpc_net_rx.
 202  * Removed printk level defs (they might be added back after the beta phase).
 203  *
 204  * Revision 0.2.0.0 1999/10/28 ivan
 205  * Revisited the code so that new protocols can be easily added / supported.
 206  *
 207  * Revision 0.1.0.1 1999/10/20 ivan
 208  * Mostly "esthetic" changes.
 209  *
 210  * Revision 0.1.0.0 1999/10/11 ivan
 211  * Initial version.
 212  *
 213  */
 214
 215 #include <linux/module.h>
 216 #include <linux/kernel.h>
 217 #include <linux/mm.h>
 218 #include <linux/ioport.h>
 219 #include <linux/pci.h>
 220 #include <linux/errno.h>
 221 #include <linux/string.h>
 222 #include <linux/init.h>
 223 #include <linux/delay.h>
 224 #include <linux/net.h>
 225 #include <linux/skbuff.h>
 226 #include <linux/if_arp.h>
 227 #include <linux/netdevice.h>
 228 #include <linux/spinlock.h>
 229 #include <linux/if.h>
 230 #include <net/arp.h>
 231
 232 #include <asm/io.h>
 233 #include <asm/uaccess.h>
 234
 235 #include "pc300.h"
 236
 237 #define CPC_LOCK(card,flags)            \
 238                 do {                                            \
 239                 spin_lock_irqsave(&card->card_lock, flags);     \
 240                 } while (0)
 241
 242 #define CPC_UNLOCK(card,flags)                  \
 243                 do {                                                    \
 244                 spin_unlock_irqrestore(&card->card_lock, flags);        \
 245                 } while (0)
 246
 247 #undef  PC300_DEBUG_PCI
 248 #undef  PC300_DEBUG_INTR
 249 #undef  PC300_DEBUG_TX
 250 #undef  PC300_DEBUG_RX
 251 #undef  PC300_DEBUG_OTHER
 252
 253 static struct pci_device_id cpc_pci_dev_id[] __devinitdata = {
 254         /* PC300/RSV or PC300/X21, 2 chan */
 255         {0x120e, 0x300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x300},
 256         /* PC300/RSV or PC300/X21, 1 chan */
 257         {0x120e, 0x301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x301},
 258         /* PC300/TE, 2 chan */
 259         {0x120e, 0x310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x310},
 260         /* PC300/TE, 1 chan */
 261         {0x120e, 0x311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x311},
 262         /* PC300/TE-M, 2 chan */
 263         {0x120e, 0x320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x320},
 264         /* PC300/TE-M, 1 chan */
 265         {0x120e, 0x321, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x321},
 266         /* End of table */
 267         {0,},
 268 };
 269 MODULE_DEVICE_TABLE(pci, cpc_pci_dev_id);
 270
 271 #ifndef cpc_min
 272 #define cpc_min(a,b)    (((a)<(b))?(a):(b))
 273 #endif
 274 #ifndef cpc_max
 275 #define cpc_max(a,b)    (((a)>(b))?(a):(b))
 276 #endif
 277
 278 /* prototypes */
 279 static void tx_dma_buf_pt_init(pc300_t *, int);
 280 static void tx_dma_buf_init(pc300_t *, int);
 281 static void rx_dma_buf_pt_init(pc300_t *, int);
 282 static void rx_dma_buf_init(pc300_t *, int);
 283 static void tx_dma_buf_check(pc300_t *, int);
 284 static void rx_dma_buf_check(pc300_t *, int);
 285 static irqreturn_t cpc_intr(int, void *);
 286 static int clock_rate_calc(uclong, uclong, int *);
 287 static uclong detect_ram(pc300_t *);
 288 static void plx_init(pc300_t *);
 289 static void cpc_trace(struct net_device *, struct sk_buff *, char);
 290 static int cpc_attach(struct net_device *, unsigned short, unsigned short);
 291 static int cpc_close(struct net_device *dev);
 292
 293 #ifdef CONFIG_PC300_MLPPP
 294 void cpc_tty_init(pc300dev_t * dev);
 295 void cpc_tty_unregister_service(pc300dev_t * pc300dev);
 296 void cpc_tty_receive(pc300dev_t * pc300dev);
 297 void cpc_tty_trigger_poll(pc300dev_t * pc300dev);
 298 void cpc_tty_reset_var(void);
 299 #endif
 300
 301 /************************/
 302 /***   DMA Routines   ***/
 303 /************************/
 304 static void tx_dma_buf_pt_init(pc300_t * card, int ch)
 305 {
 306         int i;
 307         int ch_factor = ch * N_DMA_TX_BUF;
 308         volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
 309                                        + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
 310
 311         for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) {
 312                 cpc_writel(&ptdescr->next, (uclong) (DMA_TX_BD_BASE +
 313                         (ch_factor + ((i + 1) & (N_DMA_TX_BUF - 1))) * sizeof(pcsca_bd_t)));
 314                 cpc_writel(&ptdescr->ptbuf,
 315                                                 (uclong) (DMA_TX_BASE + (ch_factor + i) * BD_DEF_LEN));
 316         }
 317 }
 318
 319 static void tx_dma_buf_init(pc300_t * card, int ch)
 320 {
 321         int i;
 322         int ch_factor = ch * N_DMA_TX_BUF;
 323         volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
 324                                + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
 325
 326         for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) {
 327                 memset_io(ptdescr, 0, sizeof(pcsca_bd_t));
 328                 cpc_writew(&ptdescr->len, 0);
 329                 cpc_writeb(&ptdescr->status, DST_OSB);
 330         }
 331         tx_dma_buf_pt_init(card, ch);
 332 }
 333
 334 static void rx_dma_buf_pt_init(pc300_t * card, int ch)
 335 {
 336         int i;
 337         int ch_factor = ch * N_DMA_RX_BUF;
 338         volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
 339                                        + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
 340
 341         for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) {
 342                 cpc_writel(&ptdescr->next, (uclong) (DMA_RX_BD_BASE +
 343                 (ch_factor + ((i + 1) & (N_DMA_RX_BUF - 1))) * sizeof(pcsca_bd_t)));
 344                 cpc_writel(&ptdescr->ptbuf,
 345                            (uclong) (DMA_RX_BASE + (ch_factor + i) * BD_DEF_LEN));
 346         }
 347 }
 348
 349 static void rx_dma_buf_init(pc300_t * card, int ch)
 350 {
 351         int i;
 352         int ch_factor = ch * N_DMA_RX_BUF;
 353         volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
 354                                        + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
 355
 356         for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) {
 357                 memset_io(ptdescr, 0, sizeof(pcsca_bd_t));
 358                 cpc_writew(&ptdescr->len, 0);
 359                 cpc_writeb(&ptdescr->status, 0);
 360         }
 361         rx_dma_buf_pt_init(card, ch);
 362 }
 363
 364 static void tx_dma_buf_check(pc300_t * card, int ch)
 365 {
 366         volatile pcsca_bd_t __iomem *ptdescr;
 367         int i;
 368         ucshort first_bd = card->chan[ch].tx_first_bd;
 369         ucshort next_bd = card->chan[ch].tx_next_bd;
 370
 371         printk("#CH%d: f_bd = %d(0x%08zx), n_bd = %d(0x%08zx)\n", ch,
 372                first_bd, TX_BD_ADDR(ch, first_bd),
 373                next_bd, TX_BD_ADDR(ch, next_bd));
 374         for (i = first_bd,
 375              ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, first_bd));
 376              i != ((next_bd + 1) & (N_DMA_TX_BUF - 1));
 377              i = (i + 1) & (N_DMA_TX_BUF - 1),
 378                  ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, i))) {
 379                 printk("\n CH%d TX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
 380                        ch, i, cpc_readl(&ptdescr->next),
 381                        cpc_readl(&ptdescr->ptbuf),
 382                        cpc_readb(&ptdescr->status), cpc_readw(&ptdescr->len));
 383         }
 384         printk("\n");
 385 }
 386
 387 #ifdef  PC300_DEBUG_OTHER
 388 /* Show all TX buffer descriptors */
 389 static void tx1_dma_buf_check(pc300_t * card, int ch)
 390 {
 391         volatile pcsca_bd_t __iomem *ptdescr;
 392         int i;
 393         ucshort first_bd = card->chan[ch].tx_first_bd;
 394         ucshort next_bd = card->chan[ch].tx_next_bd;
 395         uclong scabase = card->hw.scabase;
 396
 397         printk ("\nnfree_tx_bd = %d \n", card->chan[ch].nfree_tx_bd);
 398         printk("#CH%d: f_bd = %d(0x%08x), n_bd = %d(0x%08x)\n", ch,
 399                first_bd, TX_BD_ADDR(ch, first_bd),
 400                next_bd, TX_BD_ADDR(ch, next_bd));
 401         printk("TX_CDA=0x%08x, TX_EDA=0x%08x\n",
 402                cpc_readl(scabase + DTX_REG(CDAL, ch)),
 403                cpc_readl(scabase + DTX_REG(EDAL, ch)));
 404         for (i = 0; i < N_DMA_TX_BUF; i++) {
 405                 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, i));
 406                 printk("\n CH%d TX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
 407                        ch, i, cpc_readl(&ptdescr->next),
 408                        cpc_readl(&ptdescr->ptbuf),
 409                        cpc_readb(&ptdescr->status), cpc_readw(&ptdescr->len));
 410         }
 411         printk("\n");
 412 }
 413 #endif
 414
 415 static void rx_dma_buf_check(pc300_t * card, int ch)
 416 {
 417         volatile pcsca_bd_t __iomem *ptdescr;
 418         int i;
 419         ucshort first_bd = card->chan[ch].rx_first_bd;
 420         ucshort last_bd = card->chan[ch].rx_last_bd;
 421         int ch_factor;
 422
 423         ch_factor = ch * N_DMA_RX_BUF;
 424         printk("#CH%d: f_bd = %d, l_bd = %d\n", ch, first_bd, last_bd);
 425         for (i = 0, ptdescr = (card->hw.rambase +
 426                                               DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
 427              i < N_DMA_RX_BUF; i++, ptdescr++) {
 428                 if (cpc_readb(&ptdescr->status) & DST_OSB)
 429                         printk ("\n CH%d RX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
 430                                  ch, i, cpc_readl(&ptdescr->next),
 431                                  cpc_readl(&ptdescr->ptbuf),
 432                                  cpc_readb(&ptdescr->status),
 433                                  cpc_readw(&ptdescr->len));
 434         }
 435         printk("\n");
 436 }
 437
 438 static int dma_get_rx_frame_size(pc300_t * card, int ch)
 439 {
 440         volatile pcsca_bd_t __iomem *ptdescr;
 441         ucshort first_bd = card->chan[ch].rx_first_bd;
 442         int rcvd = 0;
 443         volatile ucchar status;
 444
 445         ptdescr = (card->hw.rambase + RX_BD_ADDR(ch, first_bd));
 446         while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) {
 447                 rcvd += cpc_readw(&ptdescr->len);
 448                 first_bd = (first_bd + 1) & (N_DMA_RX_BUF - 1);
 449                 if ((status & DST_EOM) || (first_bd == card->chan[ch].rx_last_bd)) {
 450                         /* Return the size of a good frame or incomplete bad frame
 451                         * (dma_buf_read will clean the buffer descriptors in this case). */
 452                         return (rcvd);
 453                 }
 454                 ptdescr = (card->hw.rambase + cpc_readl(&ptdescr->next));
 455         }
 456         return (-1);
 457 }
 458
 459 /*
 460  * dma_buf_write: writes a frame to the Tx DMA buffers
 461  * NOTE: this function writes one frame at a time.
 462  */
 463 static int dma_buf_write(pc300_t * card, int ch, ucchar * ptdata, int len)
 464 {
 465         int i, nchar;
 466         volatile pcsca_bd_t __iomem *ptdescr;
 467         int tosend = len;
 468         ucchar nbuf = ((len - 1) / BD_DEF_LEN) + 1;
 469
 470         if (nbuf >= card->chan[ch].nfree_tx_bd) {
 471                 return -ENOMEM;
 472         }
 473
 474         for (i = 0; i < nbuf; i++) {
 475                 ptdescr = (card->hw.rambase +
 476                                           TX_BD_ADDR(ch, card->chan[ch].tx_next_bd));
 477                 nchar = cpc_min(BD_DEF_LEN, tosend);
 478                 if (cpc_readb(&ptdescr->status) & DST_OSB) {
 479                         memcpy_toio((card->hw.rambase + cpc_readl(&ptdescr->ptbuf)),
 480                                     &ptdata[len - tosend], nchar);
 481                         cpc_writew(&ptdescr->len, nchar);
 482                         card->chan[ch].nfree_tx_bd--;
 483                         if ((i + 1) == nbuf) {
 484                                 /* This must be the last BD to be used */
 485                                 cpc_writeb(&ptdescr->status, DST_EOM);
 486                         } else {
 487                                 cpc_writeb(&ptdescr->status, 0);
 488                         }
 489                 } else {
 490                         return -ENOMEM;
 491                 }
 492                 tosend -= nchar;
 493                 card->chan[ch].tx_next_bd =
 494                         (card->chan[ch].tx_next_bd + 1) & (N_DMA_TX_BUF - 1);
 495         }
 496         /* If it gets to here, it means we have sent the whole frame */
 497         return 0;
 498 }
 499
 500 /*
 501  * dma_buf_read: reads a frame from the Rx DMA buffers
 502  * NOTE: this function reads one frame at a time.
 503  */
 504 static int dma_buf_read(pc300_t * card, int ch, struct sk_buff *skb)
 505 {
 506         int nchar;
 507         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 508         volatile pcsca_bd_t __iomem *ptdescr;
 509         int rcvd = 0;
 510         volatile ucchar status;
 511
 512         ptdescr = (card->hw.rambase +
 513                                   RX_BD_ADDR(ch, chan->rx_first_bd));
 514         while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) {
 515                 nchar = cpc_readw(&ptdescr->len);
 516                 if ((status & (DST_OVR | DST_CRC | DST_RBIT | DST_SHRT | DST_ABT))
 517                     || (nchar > BD_DEF_LEN)) {
 518
 519                         if (nchar > BD_DEF_LEN)
 520                                 status |= DST_RBIT;
 521                         rcvd = -status;
 522                         /* Discard remaining descriptors used by the bad frame */
 523                         while (chan->rx_first_bd != chan->rx_last_bd) {
 524                                 cpc_writeb(&ptdescr->status, 0);
 525                                 chan->rx_first_bd = (chan->rx_first_bd+1) & (N_DMA_RX_BUF-1);
 526                                 if (status & DST_EOM)
 527                                         break;
 528                                 ptdescr = (card->hw.rambase +
 529                                                           cpc_readl(&ptdescr->next));
 530                                 status = cpc_readb(&ptdescr->status);
 531                         }
 532                         break;
 533                 }
 534                 if (nchar != 0) {
 535                         if (skb) {
 536                                 memcpy_fromio(skb_put(skb, nchar),
 537                                  (card->hw.rambase+cpc_readl(&ptdescr->ptbuf)),nchar);
 538                         }
 539                         rcvd += nchar;
 540                 }
 541                 cpc_writeb(&ptdescr->status, 0);
 542                 cpc_writeb(&ptdescr->len, 0);
 543                 chan->rx_first_bd = (chan->rx_first_bd + 1) & (N_DMA_RX_BUF - 1);
 544
 545                 if (status & DST_EOM)
 546                         break;
 547
 548                 ptdescr = (card->hw.rambase + cpc_readl(&ptdescr->next));
 549         }
 550
 551         if (rcvd != 0) {
 552                 /* Update pointer */
 553                 chan->rx_last_bd = (chan->rx_first_bd - 1) & (N_DMA_RX_BUF - 1);
 554                 /* Update EDA */
 555                 cpc_writel(card->hw.scabase + DRX_REG(EDAL, ch),
 556                            RX_BD_ADDR(ch, chan->rx_last_bd));
 557         }
 558         return (rcvd);
 559 }
 560
 561 static void tx_dma_stop(pc300_t * card, int ch)
 562 {
 563         void __iomem *scabase = card->hw.scabase;
 564         ucchar drr_ena_bit = 1 << (5 + 2 * ch);
 565         ucchar drr_rst_bit = 1 << (1 + 2 * ch);
 566
 567         /* Disable DMA */
 568         cpc_writeb(scabase + DRR, drr_ena_bit);
 569         cpc_writeb(scabase + DRR, drr_rst_bit & ~drr_ena_bit);
 570 }
 571
 572 static void rx_dma_stop(pc300_t * card, int ch)
 573 {
 574         void __iomem *scabase = card->hw.scabase;
 575         ucchar drr_ena_bit = 1 << (4 + 2 * ch);
 576         ucchar drr_rst_bit = 1 << (2 * ch);
 577
 578         /* Disable DMA */
 579         cpc_writeb(scabase + DRR, drr_ena_bit);
 580         cpc_writeb(scabase + DRR, drr_rst_bit & ~drr_ena_bit);
 581 }
 582
 583 static void rx_dma_start(pc300_t * card, int ch)
 584 {
 585         void __iomem *scabase = card->hw.scabase;
 586         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 587
 588         /* Start DMA */
 589         cpc_writel(scabase + DRX_REG(CDAL, ch),
 590                    RX_BD_ADDR(ch, chan->rx_first_bd));
 591         if (cpc_readl(scabase + DRX_REG(CDAL,ch)) !=
 592                                   RX_BD_ADDR(ch, chan->rx_first_bd)) {
 593                 cpc_writel(scabase + DRX_REG(CDAL, ch),
 594                                    RX_BD_ADDR(ch, chan->rx_first_bd));
 595         }
 596         cpc_writel(scabase + DRX_REG(EDAL, ch),
 597                    RX_BD_ADDR(ch, chan->rx_last_bd));
 598         cpc_writew(scabase + DRX_REG(BFLL, ch), BD_DEF_LEN);
 599         cpc_writeb(scabase + DSR_RX(ch), DSR_DE);
 600         if (!(cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
 601         cpc_writeb(scabase + DSR_RX(ch), DSR_DE);
 602         }
 603 }
 604
 605 /*************************/
 606 /***   FALC Routines   ***/
 607 /*************************/
 608 static void falc_issue_cmd(pc300_t * card, int ch, ucchar cmd)
 609 {
 610         void __iomem *falcbase = card->hw.falcbase;
 611         unsigned long i = 0;
 612
 613         while (cpc_readb(falcbase + F_REG(SIS, ch)) & SIS_CEC) {
 614                 if (i++ >= PC300_FALC_MAXLOOP) {
 615                         printk("%s: FALC command locked(cmd=0x%x).\n",
 616                                card->chan[ch].d.name, cmd);
 617                         break;
 618                 }
 619         }
 620         cpc_writeb(falcbase + F_REG(CMDR, ch), cmd);
 621 }
 622
 623 static void falc_intr_enable(pc300_t * card, int ch)
 624 {
 625         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 626         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
 627         falc_t *pfalc = (falc_t *) & chan->falc;
 628         void __iomem *falcbase = card->hw.falcbase;
 629
 630         /* Interrupt pins are open-drain */
 631         cpc_writeb(falcbase + F_REG(IPC, ch),
 632                    cpc_readb(falcbase + F_REG(IPC, ch)) & ~IPC_IC0);
 633         /* Conters updated each second */
 634         cpc_writeb(falcbase + F_REG(FMR1, ch),
 635                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_ECM);
 636         /* Enable SEC and ES interrupts  */
 637         cpc_writeb(falcbase + F_REG(IMR3, ch),
 638                    cpc_readb(falcbase + F_REG(IMR3, ch)) & ~(IMR3_SEC | IMR3_ES));
 639         if (conf->fr_mode == PC300_FR_UNFRAMED) {
 640                 cpc_writeb(falcbase + F_REG(IMR4, ch),
 641                            cpc_readb(falcbase + F_REG(IMR4, ch)) & ~(IMR4_LOS));
 642         } else {
 643                 cpc_writeb(falcbase + F_REG(IMR4, ch),
 644                            cpc_readb(falcbase + F_REG(IMR4, ch)) &
 645                            ~(IMR4_LFA | IMR4_AIS | IMR4_LOS | IMR4_SLIP));
 646         }
 647         if (conf->media == IF_IFACE_T1) {
 648                 cpc_writeb(falcbase + F_REG(IMR3, ch),
 649                            cpc_readb(falcbase + F_REG(IMR3, ch)) & ~IMR3_LLBSC);
 650         } else {
 651                 cpc_writeb(falcbase + F_REG(IPC, ch),
 652                            cpc_readb(falcbase + F_REG(IPC, ch)) | IPC_SCI);
 653                 if (conf->fr_mode == PC300_FR_UNFRAMED) {
 654                         cpc_writeb(falcbase + F_REG(IMR2, ch),
 655                                    cpc_readb(falcbase + F_REG(IMR2, ch)) & ~(IMR2_LOS));
 656                 } else {
 657                         cpc_writeb(falcbase + F_REG(IMR2, ch),
 658                                    cpc_readb(falcbase + F_REG(IMR2, ch)) &
 659                                    ~(IMR2_FAR | IMR2_LFA | IMR2_AIS | IMR2_LOS));
 660                         if (pfalc->multiframe_mode) {
 661                                 cpc_writeb(falcbase + F_REG(IMR2, ch),
 662                                            cpc_readb(falcbase + F_REG(IMR2, ch)) &
 663                                            ~(IMR2_T400MS | IMR2_MFAR));
 664                         } else {
 665                                 cpc_writeb(falcbase + F_REG(IMR2, ch),
 666                                            cpc_readb(falcbase + F_REG(IMR2, ch)) |
 667                                            IMR2_T400MS | IMR2_MFAR);
 668                         }
 669                 }
 670         }
 671 }
 672
 673 static void falc_open_timeslot(pc300_t * card, int ch, int timeslot)
 674 {
 675         void __iomem *falcbase = card->hw.falcbase;
 676         ucchar tshf = card->chan[ch].falc.offset;
 677
 678         cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch),
 679                    cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) &
 680                         ~(0x80 >> ((timeslot - tshf) & 0x07)));
 681         cpc_writeb(falcbase + F_REG((TTR1 + timeslot / 8), ch),
 682                    cpc_readb(falcbase + F_REG((TTR1 + timeslot / 8), ch)) |
 683                         (0x80 >> (timeslot & 0x07)));
 684         cpc_writeb(falcbase + F_REG((RTR1 + timeslot / 8), ch),
 685                    cpc_readb(falcbase + F_REG((RTR1 + timeslot / 8), ch)) |
 686                         (0x80 >> (timeslot & 0x07)));
 687 }
 688
 689 static void falc_close_timeslot(pc300_t * card, int ch, int timeslot)
 690 {
 691         void __iomem *falcbase = card->hw.falcbase;
 692         ucchar tshf = card->chan[ch].falc.offset;
 693
 694         cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch),
 695                    cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) |
 696                    (0x80 >> ((timeslot - tshf) & 0x07)));
 697         cpc_writeb(falcbase + F_REG((TTR1 + timeslot / 8), ch),
 698                    cpc_readb(falcbase + F_REG((TTR1 + timeslot / 8), ch)) &
 699                    ~(0x80 >> (timeslot & 0x07)));
 700         cpc_writeb(falcbase + F_REG((RTR1 + timeslot / 8), ch),
 701                    cpc_readb(falcbase + F_REG((RTR1 + timeslot / 8), ch)) &
 702                    ~(0x80 >> (timeslot & 0x07)));
 703 }
 704
 705 static void falc_close_all_timeslots(pc300_t * card, int ch)
 706 {
 707         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 708         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
 709         void __iomem *falcbase = card->hw.falcbase;
 710
 711         cpc_writeb(falcbase + F_REG(ICB1, ch), 0xff);
 712         cpc_writeb(falcbase + F_REG(TTR1, ch), 0);
 713         cpc_writeb(falcbase + F_REG(RTR1, ch), 0);
 714         cpc_writeb(falcbase + F_REG(ICB2, ch), 0xff);
 715         cpc_writeb(falcbase + F_REG(TTR2, ch), 0);
 716         cpc_writeb(falcbase + F_REG(RTR2, ch), 0);
 717         cpc_writeb(falcbase + F_REG(ICB3, ch), 0xff);
 718         cpc_writeb(falcbase + F_REG(TTR3, ch), 0);
 719         cpc_writeb(falcbase + F_REG(RTR3, ch), 0);
 720         if (conf->media == IF_IFACE_E1) {
 721                 cpc_writeb(falcbase + F_REG(ICB4, ch), 0xff);
 722                 cpc_writeb(falcbase + F_REG(TTR4, ch), 0);
 723                 cpc_writeb(falcbase + F_REG(RTR4, ch), 0);
 724         }
 725 }
 726
 727 static void falc_open_all_timeslots(pc300_t * card, int ch)
 728 {
 729         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 730         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
 731         void __iomem *falcbase = card->hw.falcbase;
 732
 733         cpc_writeb(falcbase + F_REG(ICB1, ch), 0);
 734         if (conf->fr_mode == PC300_FR_UNFRAMED) {
 735                 cpc_writeb(falcbase + F_REG(TTR1, ch), 0xff);
 736                 cpc_writeb(falcbase + F_REG(RTR1, ch), 0xff);
 737         } else {
 738                 /* Timeslot 0 is never enabled */
 739                 cpc_writeb(falcbase + F_REG(TTR1, ch), 0x7f);
 740                 cpc_writeb(falcbase + F_REG(RTR1, ch), 0x7f);
 741         }
 742         cpc_writeb(falcbase + F_REG(ICB2, ch), 0);
 743         cpc_writeb(falcbase + F_REG(TTR2, ch), 0xff);
 744         cpc_writeb(falcbase + F_REG(RTR2, ch), 0xff);
 745         cpc_writeb(falcbase + F_REG(ICB3, ch), 0);
 746         cpc_writeb(falcbase + F_REG(TTR3, ch), 0xff);
 747         cpc_writeb(falcbase + F_REG(RTR3, ch), 0xff);
 748         if (conf->media == IF_IFACE_E1) {
 749                 cpc_writeb(falcbase + F_REG(ICB4, ch), 0);
 750                 cpc_writeb(falcbase + F_REG(TTR4, ch), 0xff);
 751                 cpc_writeb(falcbase + F_REG(RTR4, ch), 0xff);
 752         } else {
 753                 cpc_writeb(falcbase + F_REG(ICB4, ch), 0xff);
 754                 cpc_writeb(falcbase + F_REG(TTR4, ch), 0x80);
 755                 cpc_writeb(falcbase + F_REG(RTR4, ch), 0x80);
 756         }
 757 }
 758
 759 static void falc_init_timeslot(pc300_t * card, int ch)
 760 {
 761         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 762         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
 763         falc_t *pfalc = (falc_t *) & chan->falc;
 764         int tslot;
 765
 766         for (tslot = 0; tslot < pfalc->num_channels; tslot++) {
 767                 if (conf->tslot_bitmap & (1 << tslot)) {
 768                         // Channel enabled
 769                         falc_open_timeslot(card, ch, tslot + 1);
 770                 } else {
 771                         // Channel disabled
 772                         falc_close_timeslot(card, ch, tslot + 1);
 773                 }
 774         }
 775 }
 776
 777 static void falc_enable_comm(pc300_t * card, int ch)
 778 {
 779         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 780         falc_t *pfalc = (falc_t *) & chan->falc;
 781
 782         if (pfalc->full_bandwidth) {
 783                 falc_open_all_timeslots(card, ch);
 784         } else {
 785                 falc_init_timeslot(card, ch);
 786         }
 787         // CTS/DCD ON
 788         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
 789                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
 790                    ~((CPLD_REG1_FALC_DCD | CPLD_REG1_FALC_CTS) << (2 * ch)));
 791 }
 792
 793 static void falc_disable_comm(pc300_t * card, int ch)
 794 {
 795         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 796         falc_t *pfalc = (falc_t *) & chan->falc;
 797
 798         if (pfalc->loop_active != 2) {
 799                 falc_close_all_timeslots(card, ch);
 800         }
 801         // CTS/DCD OFF
 802         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
 803                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
 804                    ((CPLD_REG1_FALC_DCD | CPLD_REG1_FALC_CTS) << (2 * ch)));
 805 }
 806
 807 static void falc_init_t1(pc300_t * card, int ch)
 808 {
 809         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 810         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
 811         falc_t *pfalc = (falc_t *) & chan->falc;
 812         void __iomem *falcbase = card->hw.falcbase;
 813         ucchar dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);
 814
 815         /* Switch to T1 mode (PCM 24) */
 816         cpc_writeb(falcbase + F_REG(FMR1, ch), FMR1_PMOD);
 817
 818         /* Wait 20 us for setup */
 819         udelay(20);
 820
 821         /* Transmit Buffer Size (1 frame) */
 822         cpc_writeb(falcbase + F_REG(SIC1, ch), SIC1_XBS0);
 823
 824         /* Clock mode */
 825         if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */
 826                 cpc_writeb(falcbase + F_REG(LIM0, ch),
 827                            cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS);
 828         } else { /* Slave mode */
 829                 cpc_writeb(falcbase + F_REG(LIM0, ch),
 830                            cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS);
 831                 cpc_writeb(falcbase + F_REG(LOOP, ch),
 832                            cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_RTM);
 833         }
 834
 835         cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI);
 836         cpc_writeb(falcbase + F_REG(FMR0, ch),
 837                    cpc_readb(falcbase + F_REG(FMR0, ch)) &
 838                    ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1));
 839
 840         switch (conf->lcode) {
 841                 case PC300_LC_AMI:
 842                         cpc_writeb(falcbase + F_REG(FMR0, ch),
 843                                    cpc_readb(falcbase + F_REG(FMR0, ch)) |
 844                                    FMR0_XC1 | FMR0_RC1);
 845                         /* Clear Channel register to ON for all channels */
 846                         cpc_writeb(falcbase + F_REG(CCB1, ch), 0xff);
 847                         cpc_writeb(falcbase + F_REG(CCB2, ch), 0xff);
 848                         cpc_writeb(falcbase + F_REG(CCB3, ch), 0xff);
 849                         break;
 850
 851                 case PC300_LC_B8ZS:
 852                         cpc_writeb(falcbase + F_REG(FMR0, ch),
 853                                    cpc_readb(falcbase + F_REG(FMR0, ch)) |
 854                                    FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1);
 855                         break;
 856
 857                 case PC300_LC_NRZ:
 858                         cpc_writeb(falcbase + F_REG(FMR0, ch),
 859                                    cpc_readb(falcbase + F_REG(FMR0, ch)) | 0x00);
 860                         break;
 861         }
 862
 863         cpc_writeb(falcbase + F_REG(LIM0, ch),
 864                    cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_ELOS);
 865         cpc_writeb(falcbase + F_REG(LIM0, ch),
 866                    cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0));
 867         /* Set interface mode to 2 MBPS */
 868         cpc_writeb(falcbase + F_REG(FMR1, ch),
 869                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD);
 870
 871         switch (conf->fr_mode) {
 872                 case PC300_FR_ESF:
 873                         pfalc->multiframe_mode = 0;
 874                         cpc_writeb(falcbase + F_REG(FMR4, ch),
 875                                    cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_FM1);
 876                         cpc_writeb(falcbase + F_REG(FMR1, ch),
 877                                    cpc_readb(falcbase + F_REG(FMR1, ch)) |
 878                                    FMR1_CRC | FMR1_EDL);
 879                         cpc_writeb(falcbase + F_REG(XDL1, ch), 0);
 880                         cpc_writeb(falcbase + F_REG(XDL2, ch), 0);
 881                         cpc_writeb(falcbase + F_REG(XDL3, ch), 0);
 882                         cpc_writeb(falcbase + F_REG(FMR0, ch),
 883                                    cpc_readb(falcbase + F_REG(FMR0, ch)) & ~FMR0_SRAF);
 884                         cpc_writeb(falcbase + F_REG(FMR2, ch),
 885                                    cpc_readb(falcbase + F_REG(FMR2,ch)) | FMR2_MCSP | FMR2_SSP);
 886                         break;
 887
 888                 case PC300_FR_D4:
 889                         pfalc->multiframe_mode = 1;
 890                         cpc_writeb(falcbase + F_REG(FMR4, ch),
 891                                    cpc_readb(falcbase + F_REG(FMR4, ch)) &
 892                                    ~(FMR4_FM1 | FMR4_FM0));
 893                         cpc_writeb(falcbase + F_REG(FMR0, ch),
 894                                    cpc_readb(falcbase + F_REG(FMR0, ch)) | FMR0_SRAF);
 895                         cpc_writeb(falcbase + F_REG(FMR2, ch),
 896                                    cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_SSP);
 897                         break;
 898         }
 899
 900         /* Enable Automatic Resynchronization */
 901         cpc_writeb(falcbase + F_REG(FMR4, ch),
 902                    cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_AUTO);
 903
 904         /* Transmit Automatic Remote Alarm */
 905         cpc_writeb(falcbase + F_REG(FMR2, ch),
 906                    cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
 907
 908         /* Channel translation mode 1 : one to one */
 909         cpc_writeb(falcbase + F_REG(FMR1, ch),
 910                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_CTM);
 911
 912         /* No signaling */
 913         cpc_writeb(falcbase + F_REG(FMR1, ch),
 914                    cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_SIGM);
 915         cpc_writeb(falcbase + F_REG(FMR5, ch),
 916                    cpc_readb(falcbase + F_REG(FMR5, ch)) &
 917                    ~(FMR5_EIBR | FMR5_SRS));
 918         cpc_writeb(falcbase + F_REG(CCR1, ch), 0);
 919
 920         cpc_writeb(falcbase + F_REG(LIM1, ch),
 921                    cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1);
 922
 923         switch (conf->lbo) {
 924                         /* Provides proper Line Build Out */
 925                 case PC300_LBO_0_DB:
 926                         cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja));
 927                         cpc_writeb(falcbase + F_REG(XPM0, ch), 0x5a);
 928                         cpc_writeb(falcbase + F_REG(XPM1, ch), 0x8f);
 929                         cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
 930                         break;
 931                 case PC300_LBO_7_5_DB:
 932                         cpc_writeb(falcbase + F_REG(LIM2, ch), (0x40 | LIM2_LOS1 | dja));
 933                         cpc_writeb(falcbase + F_REG(XPM0, ch), 0x11);
 934                         cpc_writeb(falcbase + F_REG(XPM1, ch), 0x02);
 935                         cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
 936                         break;
 937                 case PC300_LBO_15_DB:
 938                         cpc_writeb(falcbase + F_REG(LIM2, ch), (0x80 | LIM2_LOS1 | dja));
 939                         cpc_writeb(falcbase + F_REG(XPM0, ch), 0x8e);
 940                         cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01);
 941                         cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
 942                         break;
 943                 case PC300_LBO_22_5_DB:
 944                         cpc_writeb(falcbase + F_REG(LIM2, ch), (0xc0 | LIM2_LOS1 | dja));
 945                         cpc_writeb(falcbase + F_REG(XPM0, ch), 0x09);
 946                         cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01);
 947                         cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
 948                         break;
 949         }
 950
 951         /* Transmit Clock-Slot Offset */
 952         cpc_writeb(falcbase + F_REG(XC0, ch),
 953                    cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01);
 954         /* Transmit Time-slot Offset */
 955         cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e);
 956         /* Receive  Clock-Slot offset */
 957         cpc_writeb(falcbase + F_REG(RC0, ch), 0x05);
 958         /* Receive  Time-slot offset */
 959         cpc_writeb(falcbase + F_REG(RC1, ch), 0x00);
 960
 961         /* LOS Detection after 176 consecutive 0s */
 962         cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a);
 963         /* LOS Recovery after 22 ones in the time window of PCD */
 964         cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15);
 965
 966         cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f);
 967
 968         if (conf->fr_mode == PC300_FR_ESF_JAPAN) {
 969                 cpc_writeb(falcbase + F_REG(RC1, ch),
 970                            cpc_readb(falcbase + F_REG(RC1, ch)) | 0x80);
 971         }
 972
 973         falc_close_all_timeslots(card, ch);
 974 }
 975
 976 static void falc_init_e1(pc300_t * card, int ch)
 977 {
 978         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 979         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
 980         falc_t *pfalc = (falc_t *) & chan->falc;
 981         void __iomem *falcbase = card->hw.falcbase;
 982         ucchar dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);
 983
 984         /* Switch to E1 mode (PCM 30) */
 985         cpc_writeb(falcbase + F_REG(FMR1, ch),
 986                    cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_PMOD);
 987
 988         /* Clock mode */
 989         if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */
 990                 cpc_writeb(falcbase + F_REG(LIM0, ch),
 991                            cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS);
 992         } else { /* Slave mode */
 993                 cpc_writeb(falcbase + F_REG(LIM0, ch),
 994                            cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS);
 995         }
 996         cpc_writeb(falcbase + F_REG(LOOP, ch),
 997                    cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_SFM);
 998
 999         cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI);
1000         cpc_writeb(falcbase + F_REG(FMR0, ch),
1001                    cpc_readb(falcbase + F_REG(FMR0, ch)) &
1002                    ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1));
1003
1004         switch (conf->lcode) {
1005                 case PC300_LC_AMI:
1006                         cpc_writeb(falcbase + F_REG(FMR0, ch),
1007                                    cpc_readb(falcbase + F_REG(FMR0, ch)) |
1008                                    FMR0_XC1 | FMR0_RC1);
1009                         break;
1010
1011                 case PC300_LC_HDB3:
1012                         cpc_writeb(falcbase + F_REG(FMR0, ch),
1013                                    cpc_readb(falcbase + F_REG(FMR0, ch)) |
1014                                    FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1);
1015                         break;
1016
1017                 case PC300_LC_NRZ:
1018                         break;
1019         }
1020
1021         cpc_writeb(falcbase + F_REG(LIM0, ch),
1022                    cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0));
1023         /* Set interface mode to 2 MBPS */
1024         cpc_writeb(falcbase + F_REG(FMR1, ch),
1025                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD);
1026
1027         cpc_writeb(falcbase + F_REG(XPM0, ch), 0x18);
1028         cpc_writeb(falcbase + F_REG(XPM1, ch), 0x03);
1029         cpc_writeb(falcbase + F_REG(XPM2, ch), 0x00);
1030
1031         switch (conf->fr_mode) {
1032                 case PC300_FR_MF_CRC4:
1033                         pfalc->multiframe_mode = 1;
1034                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1035                                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_XFS);
1036                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1037                                    cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_RFS1);
1038                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1039                                    cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_RFS0);
1040                         cpc_writeb(falcbase + F_REG(FMR3, ch),
1041                                    cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_EXTIW);
1042
1043                         /* MultiFrame Resynchronization */
1044                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1045                                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_MFCS);
1046
1047                         /* Automatic Loss of Multiframe > 914 CRC errors */
1048                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1049                                    cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_ALMF);
1050
1051                         /* S1 and SI1/SI2 spare Bits set to 1 */
1052                         cpc_writeb(falcbase + F_REG(XSP, ch),
1053                                    cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_AXS);
1054                         cpc_writeb(falcbase + F_REG(XSP, ch),
1055                                    cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_EBP);
1056                         cpc_writeb(falcbase + F_REG(XSP, ch),
1057                                    cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XS13 | XSP_XS15);
1058
1059                         /* Automatic Force Resynchronization */
1060                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1061                                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR);
1062
1063                         /* Transmit Automatic Remote Alarm */
1064                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1065                                    cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
1066
1067                         /* Transmit Spare Bits for National Use (Y, Sn, Sa) */
1068                         cpc_writeb(falcbase + F_REG(XSW, ch),
1069                                    cpc_readb(falcbase + F_REG(XSW, ch)) |
1070                                    XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4);
1071                         break;
1072
1073                 case PC300_FR_MF_NON_CRC4:
1074                 case PC300_FR_D4:
1075                         pfalc->multiframe_mode = 0;
1076                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1077                                    cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS);
1078                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1079                                    cpc_readb(falcbase + F_REG(FMR2, ch)) &
1080                                    ~(FMR2_RFS1 | FMR2_RFS0));
1081                         cpc_writeb(falcbase + F_REG(XSW, ch),
1082                                    cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XSIS);
1083                         cpc_writeb(falcbase + F_REG(XSP, ch),
1084                                    cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XSIF);
1085
1086                         /* Automatic Force Resynchronization */
1087                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1088                                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR);
1089
1090                         /* Transmit Automatic Remote Alarm */
1091                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1092                                    cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
1093
1094                         /* Transmit Spare Bits for National Use (Y, Sn, Sa) */
1095                         cpc_writeb(falcbase + F_REG(XSW, ch),
1096                                    cpc_readb(falcbase + F_REG(XSW, ch)) |
1097                                    XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4);
1098                         break;
1099
1100                 case PC300_FR_UNFRAMED:
1101                         pfalc->multiframe_mode = 0;
1102                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1103                                    cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS);
1104                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1105                                    cpc_readb(falcbase + F_REG(FMR2, ch)) &
1106                                    ~(FMR2_RFS1 | FMR2_RFS0));
1107                         cpc_writeb(falcbase + F_REG(XSP, ch),
1108                                    cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_TT0);
1109                         cpc_writeb(falcbase + F_REG(XSW, ch),
1110                                    cpc_readb(falcbase + F_REG(XSW, ch)) &
1111                                    ~(XSW_XTM|XSW_XY0|XSW_XY1|XSW_XY2|XSW_XY3|XSW_XY4));
1112                         cpc_writeb(falcbase + F_REG(TSWM, ch), 0xff);
1113                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1114                                    cpc_readb(falcbase + F_REG(FMR2, ch)) |
1115                                    (FMR2_RTM | FMR2_DAIS));
1116                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1117                                    cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_AXRA);
1118                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1119                                    cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_AFR);
1120                         pfalc->sync = 1;
1121                         cpc_writeb(falcbase + card->hw.cpld_reg2,
1122                                    cpc_readb(falcbase + card->hw.cpld_reg2) |
1123                                    (CPLD_REG2_FALC_LED2 << (2 * ch)));
1124                         break;
1125         }
1126
1127         /* No signaling */
1128         cpc_writeb(falcbase + F_REG(XSP, ch),
1129                    cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_CASEN);
1130         cpc_writeb(falcbase + F_REG(CCR1, ch), 0);
1131
1132         cpc_writeb(falcbase + F_REG(LIM1, ch),
1133                    cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1);
1134         cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja));
1135
1136         /* Transmit Clock-Slot Offset */
1137         cpc_writeb(falcbase + F_REG(XC0, ch),
1138                    cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01);
1139         /* Transmit Time-slot Offset */
1140         cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e);
1141         /* Receive  Clock-Slot offset */
1142         cpc_writeb(falcbase + F_REG(RC0, ch), 0x05);
1143         /* Receive  Time-slot offset */
1144         cpc_writeb(falcbase + F_REG(RC1, ch), 0x00);
1145
1146         /* LOS Detection after 176 consecutive 0s */
1147         cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a);
1148         /* LOS Recovery after 22 ones in the time window of PCD */
1149         cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15);
1150
1151         cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f);
1152
1153         falc_close_all_timeslots(card, ch);
1154 }
1155
1156 static void falc_init_hdlc(pc300_t * card, int ch)
1157 {
1158         void __iomem *falcbase = card->hw.falcbase;
1159         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1160         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1161
1162         /* Enable transparent data transfer */
1163         if (conf->fr_mode == PC300_FR_UNFRAMED) {
1164                 cpc_writeb(falcbase + F_REG(MODE, ch), 0);
1165         } else {
1166                 cpc_writeb(falcbase + F_REG(MODE, ch),
1167                            cpc_readb(falcbase + F_REG(MODE, ch)) |
1168                            (MODE_HRAC | MODE_MDS2));
1169                 cpc_writeb(falcbase + F_REG(RAH2, ch), 0xff);
1170                 cpc_writeb(falcbase + F_REG(RAH1, ch), 0xff);
1171                 cpc_writeb(falcbase + F_REG(RAL2, ch), 0xff);
1172                 cpc_writeb(falcbase + F_REG(RAL1, ch), 0xff);
1173         }
1174
1175         /* Tx/Rx reset  */
1176         falc_issue_cmd(card, ch, CMDR_RRES | CMDR_XRES | CMDR_SRES);
1177
1178         /* Enable interrupt sources */
1179         falc_intr_enable(card, ch);
1180 }
1181
1182 static void te_config(pc300_t * card, int ch)
1183 {
1184         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1185         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1186         falc_t *pfalc = (falc_t *) & chan->falc;
1187         void __iomem *falcbase = card->hw.falcbase;
1188         ucchar dummy;
1189         unsigned long flags;
1190
1191         memset(pfalc, 0, sizeof(falc_t));
1192         switch (conf->media) {
1193                 case IF_IFACE_T1:
1194                         pfalc->num_channels = NUM_OF_T1_CHANNELS;
1195                         pfalc->offset = 1;
1196                         break;
1197                 case IF_IFACE_E1:
1198                         pfalc->num_channels = NUM_OF_E1_CHANNELS;
1199                         pfalc->offset = 0;
1200                         break;
1201         }
1202         if (conf->tslot_bitmap == 0xffffffffUL)
1203                 pfalc->full_bandwidth = 1;
1204         else
1205                 pfalc->full_bandwidth = 0;
1206
1207         CPC_LOCK(card, flags);
1208         /* Reset the FALC chip */
1209         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
1210                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
1211                    (CPLD_REG1_FALC_RESET << (2 * ch)));
1212         udelay(10000);
1213         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
1214                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
1215                    ~(CPLD_REG1_FALC_RESET << (2 * ch)));
1216
1217         if (conf->media == IF_IFACE_T1) {
1218                 falc_init_t1(card, ch);
1219         } else {
1220                 falc_init_e1(card, ch);
1221         }
1222         falc_init_hdlc(card, ch);
1223         if (conf->rx_sens == PC300_RX_SENS_SH) {
1224                 cpc_writeb(falcbase + F_REG(LIM0, ch),
1225                            cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_EQON);
1226         } else {
1227                 cpc_writeb(falcbase + F_REG(LIM0, ch),
1228                            cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_EQON);
1229         }
1230         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1231                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) |
1232                    ((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK) << (2 * ch)));
1233
1234         /* Clear all interrupt registers */
1235         dummy = cpc_readb(falcbase + F_REG(FISR0, ch)) +
1236                 cpc_readb(falcbase + F_REG(FISR1, ch)) +
1237                 cpc_readb(falcbase + F_REG(FISR2, ch)) +
1238                 cpc_readb(falcbase + F_REG(FISR3, ch));
1239         CPC_UNLOCK(card, flags);
1240 }
1241
1242 static void falc_check_status(pc300_t * card, int ch, unsigned char frs0)
1243 {
1244         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1245         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1246         falc_t *pfalc = (falc_t *) & chan->falc;
1247         void __iomem *falcbase = card->hw.falcbase;
1248
1249         /* Verify LOS */
1250         if (frs0 & FRS0_LOS) {
1251                 if (!pfalc->red_alarm) {
1252                         pfalc->red_alarm = 1;
1253                         pfalc->los++;
1254                         if (!pfalc->blue_alarm) {
1255                                 // EVENT_FALC_ABNORMAL
1256                                 if (conf->media == IF_IFACE_T1) {
1257                                         /* Disable this interrupt as it may otherwise interfere
1258                                          * with other working boards. */
1259                                         cpc_writeb(falcbase + F_REG(IMR0, ch),
1260                                                    cpc_readb(falcbase + F_REG(IMR0, ch))
1261                                                    | IMR0_PDEN);
1262                                 }
1263                                 falc_disable_comm(card, ch);
1264                                 // EVENT_FALC_ABNORMAL
1265                         }
1266                 }
1267         } else {
1268                 if (pfalc->red_alarm) {
1269                         pfalc->red_alarm = 0;
1270                         pfalc->losr++;
1271                 }
1272         }
1273
1274         if (conf->fr_mode != PC300_FR_UNFRAMED) {
1275                 /* Verify AIS alarm */
1276                 if (frs0 & FRS0_AIS) {
1277                         if (!pfalc->blue_alarm) {
1278                                 pfalc->blue_alarm = 1;
1279                                 pfalc->ais++;
1280                                 // EVENT_AIS
1281                                 if (conf->media == IF_IFACE_T1) {
1282                                         /* Disable this interrupt as it may otherwise interfere with                       other working boards. */
1283                                         cpc_writeb(falcbase + F_REG(IMR0, ch),
1284                                                    cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1285                                 }
1286                                 falc_disable_comm(card, ch);
1287                                 // EVENT_AIS
1288                         }
1289                 } else {
1290                         pfalc->blue_alarm = 0;
1291                 }
1292
1293                 /* Verify LFA */
1294                 if (frs0 & FRS0_LFA) {
1295                         if (!pfalc->loss_fa) {
1296                                 pfalc->loss_fa = 1;
1297                                 pfalc->lfa++;
1298                                 if (!pfalc->blue_alarm && !pfalc->red_alarm) {
1299                                         // EVENT_FALC_ABNORMAL
1300                                         if (conf->media == IF_IFACE_T1) {
1301                                                 /* Disable this interrupt as it may otherwise
1302                                                  * interfere with other working boards. */
1303                                                 cpc_writeb(falcbase + F_REG(IMR0, ch),
1304                                                            cpc_readb(falcbase + F_REG(IMR0, ch))
1305                                                            | IMR0_PDEN);
1306                                         }
1307                                         falc_disable_comm(card, ch);
1308                                         // EVENT_FALC_ABNORMAL
1309                                 }
1310                         }
1311                 } else {
1312                         if (pfalc->loss_fa) {
1313                                 pfalc->loss_fa = 0;
1314                                 pfalc->farec++;
1315                         }
1316                 }
1317
1318                 /* Verify LMFA */
1319                 if (pfalc->multiframe_mode && (frs0 & FRS0_LMFA)) {
1320                         /* D4 or CRC4 frame mode */
1321                         if (!pfalc->loss_mfa) {
1322                                 pfalc->loss_mfa = 1;
1323                                 pfalc->lmfa++;
1324                                 if (!pfalc->blue_alarm && !pfalc->red_alarm &&
1325                                     !pfalc->loss_fa) {
1326                                         // EVENT_FALC_ABNORMAL
1327                                         if (conf->media == IF_IFACE_T1) {
1328                                                 /* Disable this interrupt as it may otherwise
1329                                                  * interfere with other working boards. */
1330                                                 cpc_writeb(falcbase + F_REG(IMR0, ch),
1331                                                            cpc_readb(falcbase + F_REG(IMR0, ch))
1332                                                            | IMR0_PDEN);
1333                                         }
1334                                         falc_disable_comm(card, ch);
1335                                         // EVENT_FALC_ABNORMAL
1336                                 }
1337                         }
1338                 } else {
1339                         pfalc->loss_mfa = 0;
1340                 }
1341
1342                 /* Verify Remote Alarm */
1343                 if (frs0 & FRS0_RRA) {
1344                         if (!pfalc->yellow_alarm) {
1345                                 pfalc->yellow_alarm = 1;
1346                                 pfalc->rai++;
1347                                 if (pfalc->sync) {
1348                                         // EVENT_RAI
1349                                         falc_disable_comm(card, ch);
1350                                         // EVENT_RAI
1351                                 }
1352                         }
1353                 } else {
1354                         pfalc->yellow_alarm = 0;
1355                 }
1356         } /* if !PC300_UNFRAMED */
1357
1358         if (pfalc->red_alarm || pfalc->loss_fa ||
1359             pfalc->loss_mfa || pfalc->blue_alarm) {
1360                 if (pfalc->sync) {
1361                         pfalc->sync = 0;
1362                         chan->d.line_off++;
1363                         cpc_writeb(falcbase + card->hw.cpld_reg2,
1364                                    cpc_readb(falcbase + card->hw.cpld_reg2) &
1365                                    ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1366                 }
1367         } else {
1368                 if (!pfalc->sync) {
1369                         pfalc->sync = 1;
1370                         chan->d.line_on++;
1371                         cpc_writeb(falcbase + card->hw.cpld_reg2,
1372                                    cpc_readb(falcbase + card->hw.cpld_reg2) |
1373                                    (CPLD_REG2_FALC_LED2 << (2 * ch)));
1374                 }
1375         }
1376
1377         if (pfalc->sync && !pfalc->yellow_alarm) {
1378                 if (!pfalc->active) {
1379                         // EVENT_FALC_NORMAL
1380                         if (pfalc->loop_active) {
1381                                 return;
1382                         }
1383                         if (conf->media == IF_IFACE_T1) {
1384                                 cpc_writeb(falcbase + F_REG(IMR0, ch),
1385                                            cpc_readb(falcbase + F_REG(IMR0, ch)) & ~IMR0_PDEN);
1386                         }
1387                         falc_enable_comm(card, ch);
1388                         // EVENT_FALC_NORMAL
1389                         pfalc->active = 1;
1390                 }
1391         } else {
1392                 if (pfalc->active) {
1393                         pfalc->active = 0;
1394                 }
1395         }
1396 }
1397
1398 static void falc_update_stats(pc300_t * card, int ch)
1399 {
1400         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1401         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1402         falc_t *pfalc = (falc_t *) & chan->falc;
1403         void __iomem *falcbase = card->hw.falcbase;
1404         ucshort counter;
1405
1406         counter = cpc_readb(falcbase + F_REG(FECL, ch));
1407         counter |= cpc_readb(falcbase + F_REG(FECH, ch)) << 8;
1408         pfalc->fec += counter;
1409
1410         counter = cpc_readb(falcbase + F_REG(CVCL, ch));
1411         counter |= cpc_readb(falcbase + F_REG(CVCH, ch)) << 8;
1412         pfalc->cvc += counter;
1413
1414         counter = cpc_readb(falcbase + F_REG(CECL, ch));
1415         counter |= cpc_readb(falcbase + F_REG(CECH, ch)) << 8;
1416         pfalc->cec += counter;
1417
1418         counter = cpc_readb(falcbase + F_REG(EBCL, ch));
1419         counter |= cpc_readb(falcbase + F_REG(EBCH, ch)) << 8;
1420         pfalc->ebc += counter;
1421
1422         if (cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) {
1423                 mdelay(10);
1424                 counter = cpc_readb(falcbase + F_REG(BECL, ch));
1425                 counter |= cpc_readb(falcbase + F_REG(BECH, ch)) << 8;
1426                 pfalc->bec += counter;
1427
1428                 if (((conf->media == IF_IFACE_T1) &&
1429                      (cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_LLBAD) &&
1430                      (!(cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_PDEN)))
1431                     ||
1432                     ((conf->media == IF_IFACE_E1) &&
1433                      (cpc_readb(falcbase + F_REG(RSP, ch)) & RSP_LLBAD))) {
1434                         pfalc->prbs = 2;
1435                 } else {
1436                         pfalc->prbs = 1;
1437                 }
1438         }
1439 }
1440
1441 /*----------------------------------------------------------------------------
1442  * falc_remote_loop
1443  *----------------------------------------------------------------------------
1444  * Description: In the remote loopback mode the clock and data recovered
1445  *              from the line inputs RL1/2 or RDIP/RDIN are routed back
1446  *              to the line outputs XL1/2 or XDOP/XDON via the analog
1447  *              transmitter. As in normal mode they are processsed by
1448  *              the synchronizer and then sent to the system interface.
1449  *----------------------------------------------------------------------------
1450  */
1451 static void falc_remote_loop(pc300_t * card, int ch, int loop_on)
1452 {
1453         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1454         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1455         falc_t *pfalc = (falc_t *) & chan->falc;
1456         void __iomem *falcbase = card->hw.falcbase;
1457
1458         if (loop_on) {
1459                 // EVENT_FALC_ABNORMAL
1460                 if (conf->media == IF_IFACE_T1) {
1461                         /* Disable this interrupt as it may otherwise interfere with
1462                          * other working boards. */
1463                         cpc_writeb(falcbase + F_REG(IMR0, ch),
1464                                    cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1465                 }
1466                 falc_disable_comm(card, ch);
1467                 // EVENT_FALC_ABNORMAL
1468                 cpc_writeb(falcbase + F_REG(LIM1, ch),
1469                            cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RL);
1470                 pfalc->loop_active = 1;
1471         } else {
1472                 cpc_writeb(falcbase + F_REG(LIM1, ch),
1473                            cpc_readb(falcbase + F_REG(LIM1, ch)) & ~LIM1_RL);
1474                 pfalc->sync = 0;
1475                 cpc_writeb(falcbase + card->hw.cpld_reg2,
1476                            cpc_readb(falcbase + card->hw.cpld_reg2) &
1477                            ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1478                 pfalc->active = 0;
1479                 falc_issue_cmd(card, ch, CMDR_XRES);
1480                 pfalc->loop_active = 0;
1481         }
1482 }
1483
1484 /*----------------------------------------------------------------------------
1485  * falc_local_loop
1486  *----------------------------------------------------------------------------
1487  * Description: The local loopback mode disconnects the receive lines
1488  *              RL1/RL2 resp. RDIP/RDIN from the receiver. Instead of the
1489  *              signals coming from the line the data provided by system
1490  *              interface are routed through the analog receiver back to
1491  *              the system interface. The unipolar bit stream will be
1492  *              undisturbed transmitted on the line. Receiver and transmitter
1493  *              coding must be identical.
1494  *----------------------------------------------------------------------------
1495  */
1496 static void falc_local_loop(pc300_t * card, int ch, int loop_on)
1497 {
1498         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1499         falc_t *pfalc = (falc_t *) & chan->falc;
1500         void __iomem *falcbase = card->hw.falcbase;
1501
1502         if (loop_on) {
1503                 cpc_writeb(falcbase + F_REG(LIM0, ch),
1504                            cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_LL);
1505                 pfalc->loop_active = 1;
1506         } else {
1507                 cpc_writeb(falcbase + F_REG(LIM0, ch),
1508                            cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_LL);
1509                 pfalc->loop_active = 0;
1510         }
1511 }
1512
1513 /*----------------------------------------------------------------------------
1514  * falc_payload_loop
1515  *----------------------------------------------------------------------------
1516  * Description: This routine allows to enable/disable payload loopback.
1517  *              When the payload loop is activated, the received 192 bits
1518  *              of payload data will be looped back to the transmit
1519  *              direction. The framing bits, CRC6 and DL bits are not
1520  *              looped. They are originated by the FALC-LH transmitter.
1521  *----------------------------------------------------------------------------
1522  */
1523 static void falc_payload_loop(pc300_t * card, int ch, int loop_on)
1524 {
1525         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1526         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1527         falc_t *pfalc = (falc_t *) & chan->falc;
1528         void __iomem *falcbase = card->hw.falcbase;
1529
1530         if (loop_on) {
1531                 // EVENT_FALC_ABNORMAL
1532                 if (conf->media == IF_IFACE_T1) {
1533                         /* Disable this interrupt as it may otherwise interfere with
1534                          * other working boards. */
1535                         cpc_writeb(falcbase + F_REG(IMR0, ch),
1536                                    cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1537                 }
1538                 falc_disable_comm(card, ch);
1539                 // EVENT_FALC_ABNORMAL
1540                 cpc_writeb(falcbase + F_REG(FMR2, ch),
1541                            cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_PLB);
1542                 if (conf->media == IF_IFACE_T1) {
1543                         cpc_writeb(falcbase + F_REG(FMR4, ch),
1544                                    cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_TM);
1545                 } else {
1546                         cpc_writeb(falcbase + F_REG(FMR5, ch),
1547                                    cpc_readb(falcbase + F_REG(FMR5, ch)) | XSP_TT0);
1548                 }
1549                 falc_open_all_timeslots(card, ch);
1550                 pfalc->loop_active = 2;
1551         } else {
1552                 cpc_writeb(falcbase + F_REG(FMR2, ch),
1553                            cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_PLB);
1554                 if (conf->media == IF_IFACE_T1) {
1555                         cpc_writeb(falcbase + F_REG(FMR4, ch),
1556                                    cpc_readb(falcbase + F_REG(FMR4, ch)) & ~FMR4_TM);
1557                 } else {
1558                         cpc_writeb(falcbase + F_REG(FMR5, ch),
1559                                    cpc_readb(falcbase + F_REG(FMR5, ch)) & ~XSP_TT0);
1560                 }
1561                 pfalc->sync = 0;
1562                 cpc_writeb(falcbase + card->hw.cpld_reg2,
1563                            cpc_readb(falcbase + card->hw.cpld_reg2) &
1564                            ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1565                 pfalc->active = 0;
1566                 falc_issue_cmd(card, ch, CMDR_XRES);
1567                 pfalc->loop_active = 0;
1568         }
1569 }
1570
1571 /*----------------------------------------------------------------------------
1572  * turn_off_xlu
1573  *----------------------------------------------------------------------------
1574  * Description: Turns XLU bit off in the proper register
1575  *----------------------------------------------------------------------------
1576  */
1577 static void turn_off_xlu(pc300_t * card, int ch)
1578 {
1579         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1580         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1581         void __iomem *falcbase = card->hw.falcbase;
1582
1583         if (conf->media == IF_IFACE_T1) {
1584                 cpc_writeb(falcbase + F_REG(FMR5, ch),
1585                            cpc_readb(falcbase + F_REG(FMR5, ch)) & ~FMR5_XLU);
1586         } else {
1587                 cpc_writeb(falcbase + F_REG(FMR3, ch),
1588                            cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_XLU);
1589         }
1590 }
1591
1592 /*----------------------------------------------------------------------------
1593  * turn_off_xld
1594  *----------------------------------------------------------------------------
1595  * Description: Turns XLD bit off in the proper register
1596  *----------------------------------------------------------------------------
1597  */
1598 static void turn_off_xld(pc300_t * card, int ch)
1599 {
1600         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1601         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1602         void __iomem *falcbase = card->hw.falcbase;
1603
1604         if (conf->media == IF_IFACE_T1) {
1605                 cpc_writeb(falcbase + F_REG(FMR5, ch),
1606                            cpc_readb(falcbase + F_REG(FMR5, ch)) & ~FMR5_XLD);
1607         } else {
1608                 cpc_writeb(falcbase + F_REG(FMR3, ch),
1609                            cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_XLD);
1610         }
1611 }
1612
1613 /*----------------------------------------------------------------------------
1614  * falc_generate_loop_up_code
1615  *----------------------------------------------------------------------------
1616  * Description: This routine writes the proper FALC chip register in order
1617  *              to generate a LOOP activation code over a T1/E1 line.
1618  *----------------------------------------------------------------------------
1619  */
1620 static void falc_generate_loop_up_code(pc300_t * card, int ch)
1621 {
1622         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1623         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1624         falc_t *pfalc = (falc_t *) & chan->falc;
1625         void __iomem *falcbase = card->hw.falcbase;
1626
1627         if (conf->media == IF_IFACE_T1) {
1628                 cpc_writeb(falcbase + F_REG(FMR5, ch),
1629                            cpc_readb(falcbase + F_REG(FMR5, ch)) | FMR5_XLU);
1630         } else {
1631                 cpc_writeb(falcbase + F_REG(FMR3, ch),
1632                            cpc_readb(falcbase + F_REG(FMR3, ch)) | FMR3_XLU);
1633         }
1634         // EVENT_FALC_ABNORMAL
1635         if (conf->media == IF_IFACE_T1) {
1636                 /* Disable this interrupt as it may otherwise interfere with
1637                  * other working boards. */
1638                 cpc_writeb(falcbase + F_REG(IMR0, ch),
1639                            cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1640         }
1641         falc_disable_comm(card, ch);
1642         // EVENT_FALC_ABNORMAL
1643         pfalc->loop_gen = 1;
1644 }
1645
1646 /*----------------------------------------------------------------------------
1647  * falc_generate_loop_down_code
1648  *----------------------------------------------------------------------------
1649  * Description: This routine writes the proper FALC chip register in order
1650  *              to generate a LOOP deactivation code over a T1/E1 line.
1651  *----------------------------------------------------------------------------
1652  */
1653 static void falc_generate_loop_down_code(pc300_t * card, int ch)
1654 {
1655         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1656         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1657         falc_t *pfalc = (falc_t *) & chan->falc;
1658         void __iomem *falcbase = card->hw.falcbase;
1659
1660         if (conf->media == IF_IFACE_T1) {
1661                 cpc_writeb(falcbase + F_REG(FMR5, ch),
1662                            cpc_readb(falcbase + F_REG(FMR5, ch)) | FMR5_XLD);
1663         } else {
1664                 cpc_writeb(falcbase + F_REG(FMR3, ch),
1665                            cpc_readb(falcbase + F_REG(FMR3, ch)) | FMR3_XLD);
1666         }
1667         pfalc->sync = 0;
1668         cpc_writeb(falcbase + card->hw.cpld_reg2,
1669                    cpc_readb(falcbase + card->hw.cpld_reg2) &
1670                    ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1671         pfalc->active = 0;
1672 //?    falc_issue_cmd(card, ch, CMDR_XRES);
1673         pfalc->loop_gen = 0;
1674 }
1675
1676 /*----------------------------------------------------------------------------
1677  * falc_pattern_test
1678  *----------------------------------------------------------------------------
1679  * Description: This routine generates a pattern code and checks
1680  *              it on the reception side.
1681  *----------------------------------------------------------------------------
1682  */
1683 static void falc_pattern_test(pc300_t * card, int ch, unsigned int activate)
1684 {
1685         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1686         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1687         falc_t *pfalc = (falc_t *) & chan->falc;
1688         void __iomem *falcbase = card->hw.falcbase;
1689
1690         if (activate) {
1691                 pfalc->prbs = 1;
1692                 pfalc->bec = 0;
1693                 if (conf->media == IF_IFACE_T1) {
1694                         /* Disable local loop activation/deactivation detect */
1695                         cpc_writeb(falcbase + F_REG(IMR3, ch),
1696                                    cpc_readb(falcbase + F_REG(IMR3, ch)) | IMR3_LLBSC);
1697                 } else {
1698                         /* Disable local loop activation/deactivation detect */
1699                         cpc_writeb(falcbase + F_REG(IMR1, ch),
1700                                    cpc_readb(falcbase + F_REG(IMR1, ch)) | IMR1_LLBSC);
1701                 }
1702                 /* Activates generation and monitoring of PRBS
1703                  * (Pseudo Random Bit Sequence) */
1704                 cpc_writeb(falcbase + F_REG(LCR1, ch),
1705                            cpc_readb(falcbase + F_REG(LCR1, ch)) | LCR1_EPRM | LCR1_XPRBS);
1706         } else {
1707                 pfalc->prbs = 0;
1708                 /* Deactivates generation and monitoring of PRBS
1709                  * (Pseudo Random Bit Sequence) */
1710                 cpc_writeb(falcbase + F_REG(LCR1, ch),
1711                            cpc_readb(falcbase+F_REG(LCR1,ch)) & ~(LCR1_EPRM | LCR1_XPRBS));
1712                 if (conf->media == IF_IFACE_T1) {
1713                         /* Enable local loop activation/deactivation detect */
1714                         cpc_writeb(falcbase + F_REG(IMR3, ch),
1715                                    cpc_readb(falcbase + F_REG(IMR3, ch)) & ~IMR3_LLBSC);
1716                 } else {
1717                         /* Enable local loop activation/deactivation detect */
1718                         cpc_writeb(falcbase + F_REG(IMR1, ch),
1719                                    cpc_readb(falcbase + F_REG(IMR1, ch)) & ~IMR1_LLBSC);
1720                 }
1721         }
1722 }
1723
1724 /*----------------------------------------------------------------------------
1725  * falc_pattern_test_error
1726  *----------------------------------------------------------------------------
1727  * Description: This routine returns the bit error counter value
1728  *----------------------------------------------------------------------------
1729  */
1730 static ucshort falc_pattern_test_error(pc300_t * card, int ch)
1731 {
1732         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1733         falc_t *pfalc = (falc_t *) & chan->falc;
1734
1735         return (pfalc->bec);
1736 }
1737
1738 /**********************************/
1739 /***   Net Interface Routines   ***/
1740 /**********************************/
1741
1742 static void
1743 cpc_trace(struct net_device *dev, struct sk_buff *skb_main, char rx_tx)
1744 {
1745         struct sk_buff *skb;
1746
1747         if ((skb = dev_alloc_skb(10 + skb_main->len)) == NULL) {
1748                 printk("%s: out of memory\n", dev->name);
1749                 return;
1750         }
1751         skb_put(skb, 10 + skb_main->len);
1752
1753         skb->dev = dev;
1754         skb->protocol = htons(ETH_P_CUST);
1755         skb_reset_mac_header(skb);
1756         skb->pkt_type = PACKET_HOST;
1757         skb->len = 10 + skb_main->len;
1758
1759         skb_copy_to_linear_data(skb, dev->name, 5);
1760         skb->data[5] = '[';
1761         skb->data[6] = rx_tx;
1762         skb->data[7] = ']';
1763         skb->data[8] = ':';
1764         skb->data[9] = ' ';
1765         skb_copy_from_linear_data(skb_main, &skb->data[10], skb_main->len);
1766
1767         netif_rx(skb);
1768 }
1769
1770 static void cpc_tx_timeout(struct net_device *dev)
1771 {
1772         pc300dev_t *d = (pc300dev_t *) dev->priv;
1773         pc300ch_t *chan = (pc300ch_t *) d->chan;
1774         pc300_t *card = (pc300_t *) chan->card;
1775         int ch = chan->channel;
1776         unsigned long flags;
1777         ucchar ilar;
1778
1779         dev->stats.tx_errors++;
1780         dev->stats.tx_aborted_errors++;
1781         CPC_LOCK(card, flags);
1782         if ((ilar = cpc_readb(card->hw.scabase + ILAR)) != 0) {
1783                 printk("%s: ILAR=0x%x\n", dev->name, ilar);
1784                 cpc_writeb(card->hw.scabase + ILAR, ilar);
1785                 cpc_writeb(card->hw.scabase + DMER, 0x80);
1786         }
1787         if (card->hw.type == PC300_TE) {
1788                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1789                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
1790                            ~(CPLD_REG2_FALC_LED1 << (2 * ch)));
1791         }
1792         dev->trans_start = jiffies;
1793         CPC_UNLOCK(card, flags);
1794         netif_wake_queue(dev);
1795 }
1796
1797 static int cpc_queue_xmit(struct sk_buff *skb, struct net_device *dev)
1798 {
1799         pc300dev_t *d = (pc300dev_t *) dev->priv;
1800         pc300ch_t *chan = (pc300ch_t *) d->chan;
1801         pc300_t *card = (pc300_t *) chan->card;
1802         int ch = chan->channel;
1803         unsigned long flags;
1804 #ifdef PC300_DEBUG_TX
1805         int i;
1806 #endif
1807
1808         if (chan->conf.monitor) {
1809                 /* In monitor mode no Tx is done: ignore packet */
1810                 dev_kfree_skb(skb);
1811                 return 0;
1812         } else if (!netif_carrier_ok(dev)) {
1813                 /* DCD must be OFF: drop packet */
1814                 dev_kfree_skb(skb);
1815                 dev->stats.tx_errors++;
1816                 dev->stats.tx_carrier_errors++;
1817                 return 0;
1818         } else if (cpc_readb(card->hw.scabase + M_REG(ST3, ch)) & ST3_DCD) {
1819                 printk("%s: DCD is OFF. Going administrative down.\n", dev->name);
1820                 dev->stats.tx_errors++;
1821                 dev->stats.tx_carrier_errors++;
1822                 dev_kfree_skb(skb);
1823                 netif_carrier_off(dev);
1824                 CPC_LOCK(card, flags);
1825                 cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_TX_BUF_CLR);
1826                 if (card->hw.type == PC300_TE) {
1827                         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1828                                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
1829                                                         ~(CPLD_REG2_FALC_LED1 << (2 * ch)));
1830                 }
1831                 CPC_UNLOCK(card, flags);
1832                 netif_wake_queue(dev);
1833                 return 0;
1834         }
1835
1836         /* Write buffer to DMA buffers */
1837         if (dma_buf_write(card, ch, (ucchar *) skb->data, skb->len) != 0) {
1838 //              printk("%s: write error. Dropping TX packet.\n", dev->name);
1839                 netif_stop_queue(dev);
1840                 dev_kfree_skb(skb);
1841                 dev->stats.tx_errors++;
1842                 dev->stats.tx_dropped++;
1843                 return 0;
1844         }
1845 #ifdef PC300_DEBUG_TX
1846         printk("%s T:", dev->name);
1847         for (i = 0; i < skb->len; i++)
1848                 printk(" %02x", *(skb->data + i));
1849         printk("\n");
1850 #endif
1851
1852         if (d->trace_on) {
1853                 cpc_trace(dev, skb, 'T');
1854         }
1855         dev->trans_start = jiffies;
1856
1857         /* Start transmission */
1858         CPC_LOCK(card, flags);
1859         /* verify if it has more than one free descriptor */
1860         if (card->chan[ch].nfree_tx_bd <= 1) {
1861                 /* don't have so stop the queue */
1862                 netif_stop_queue(dev);
1863         }
1864         cpc_writel(card->hw.scabase + DTX_REG(EDAL, ch),
1865                    TX_BD_ADDR(ch, chan->tx_next_bd));
1866         cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_TX_ENA);
1867         cpc_writeb(card->hw.scabase + DSR_TX(ch), DSR_DE);
1868         if (card->hw.type == PC300_TE) {
1869                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1870                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) |
1871                            (CPLD_REG2_FALC_LED1 << (2 * ch)));
1872         }
1873         CPC_UNLOCK(card, flags);
1874         dev_kfree_skb(skb);
1875
1876         return 0;
1877 }
1878
1879 static void cpc_net_rx(struct net_device *dev)
1880 {
1881         pc300dev_t *d = (pc300dev_t *) dev->priv;
1882         pc300ch_t *chan = (pc300ch_t *) d->chan;
1883         pc300_t *card = (pc300_t *) chan->card;
1884         int ch = chan->channel;
1885 #ifdef PC300_DEBUG_RX
1886         int i;
1887 #endif
1888         int rxb;
1889         struct sk_buff *skb;
1890
1891         while (1) {
1892                 if ((rxb = dma_get_rx_frame_size(card, ch)) == -1)
1893                         return;
1894
1895                 if (!netif_carrier_ok(dev)) {
1896                         /* DCD must be OFF: drop packet */
1897                     printk("%s : DCD is OFF - drop %d rx bytes\n", dev->name, rxb);
1898                         skb = NULL;
1899                 } else {
1900                         if (rxb > (dev->mtu + 40)) { /* add headers */
1901                                 printk("%s : MTU exceeded %d\n", dev->name, rxb);
1902                                 skb = NULL;
1903                         } else {
1904                                 skb = dev_alloc_skb(rxb);
1905                                 if (skb == NULL) {
1906                                         printk("%s: Memory squeeze!!\n", dev->name);
1907                                         return;
1908                                 }
1909                                 skb->dev = dev;
1910                         }
1911                 }
1912
1913                 if (((rxb = dma_buf_read(card, ch, skb)) <= 0) || (skb == NULL)) {
1914 #ifdef PC300_DEBUG_RX
1915                         printk("%s: rxb = %x\n", dev->name, rxb);
1916 #endif
1917                         if ((skb == NULL) && (rxb > 0)) {
1918                                 /* rxb > dev->mtu */
1919                                 dev->stats.rx_errors++;
1920                                 dev->stats.rx_length_errors++;
1921                                 continue;
1922                         }
1923
1924                         if (rxb < 0) {  /* Invalid frame */
1925                                 rxb = -rxb;
1926                                 if (rxb & DST_OVR) {
1927                                         dev->stats.rx_errors++;
1928                                         dev->stats.rx_fifo_errors++;
1929                                 }
1930                                 if (rxb & DST_CRC) {
1931                                         dev->stats.rx_errors++;
1932                                         dev->stats.rx_crc_errors++;
1933                                 }
1934                                 if (rxb & (DST_RBIT | DST_SHRT | DST_ABT)) {
1935                                         dev->stats.rx_errors++;
1936                                         dev->stats.rx_frame_errors++;
1937                                 }
1938                         }
1939                         if (skb) {
1940                                 dev_kfree_skb_irq(skb);
1941                         }
1942                         continue;
1943                 }
1944
1945                 dev->stats.rx_bytes += rxb;
1946
1947 #ifdef PC300_DEBUG_RX
1948                 printk("%s R:", dev->name);
1949                 for (i = 0; i < skb->len; i++)
1950                         printk(" %02x", *(skb->data + i));
1951                 printk("\n");
1952 #endif
1953                 if (d->trace_on) {
1954                         cpc_trace(dev, skb, 'R');
1955                 }
1956                 dev->stats.rx_packets++;
1957                 skb->protocol = hdlc_type_trans(skb, dev);
1958                 netif_rx(skb);
1959         }
1960 }
1961
1962 /************************************/
1963 /***   PC300 Interrupt Routines   ***/
1964 /************************************/
1965 static void sca_tx_intr(pc300dev_t *dev)
1966 {
1967         pc300ch_t *chan = (pc300ch_t *)dev->chan;
1968         pc300_t *card = (pc300_t *)chan->card;
1969         int ch = chan->channel;
1970         volatile pcsca_bd_t __iomem * ptdescr;
1971
1972     /* Clean up descriptors from previous transmission */
1973         ptdescr = (card->hw.rambase +
1974                                                 TX_BD_ADDR(ch,chan->tx_first_bd));
1975         while ((cpc_readl(card->hw.scabase + DTX_REG(CDAL,ch)) !=
1976                 TX_BD_ADDR(ch,chan->tx_first_bd)) &&
1977                (cpc_readb(&ptdescr->status) & DST_OSB)) {
1978                 dev->dev->stats.tx_packets++;
1979                 dev->dev->stats.tx_bytes += cpc_readw(&ptdescr->len);
1980                 cpc_writeb(&ptdescr->status, DST_OSB);
1981                 cpc_writew(&ptdescr->len, 0);
1982                 chan->nfree_tx_bd++;
1983                 chan->tx_first_bd = (chan->tx_first_bd + 1) & (N_DMA_TX_BUF - 1);
1984                 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch,chan->tx_first_bd));
1985     }
1986
1987 #ifdef CONFIG_PC300_MLPPP
1988         if (chan->conf.proto == PC300_PROTO_MLPPP) {
1989                         cpc_tty_trigger_poll(dev);
1990         } else {
1991 #endif
1992         /* Tell the upper layer we are ready to transmit more packets */
1993                 netif_wake_queue(dev->dev);
1994 #ifdef CONFIG_PC300_MLPPP
1995         }
1996 #endif
1997 }
1998
1999 static void sca_intr(pc300_t * card)
2000 {
2001         void __iomem *scabase = card->hw.scabase;
2002         volatile uclong status;
2003         int ch;
2004         int intr_count = 0;
2005         unsigned char dsr_rx;
2006
2007         while ((status = cpc_readl(scabase + ISR0)) != 0) {
2008                 for (ch = 0; ch < card->hw.nchan; ch++) {
2009                         pc300ch_t *chan = &card->chan[ch];
2010                         pc300dev_t *d = &chan->d;
2011                         struct net_device *dev = d->dev;
2012
2013                         spin_lock(&card->card_lock);
2014
2015             /**** Reception ****/
2016                         if (status & IR0_DRX((IR0_DMIA | IR0_DMIB), ch)) {
2017                                 ucchar drx_stat = cpc_readb(scabase + DSR_RX(ch));
2018
2019                                 /* Clear RX interrupts */
2020                                 cpc_writeb(scabase + DSR_RX(ch), drx_stat | DSR_DWE);
2021
2022 #ifdef PC300_DEBUG_INTR
2023                                 printk ("sca_intr: RX intr chan[%d] (st=0x%08lx, dsr=0x%02x)\n",
2024                                          ch, status, drx_stat);
2025 #endif
2026                                 if (status & IR0_DRX(IR0_DMIA, ch)) {
2027                                         if (drx_stat & DSR_BOF) {
2028 #ifdef CONFIG_PC300_MLPPP
2029                                                 if (chan->conf.proto == PC300_PROTO_MLPPP) {
2030                                                         /* verify if driver is TTY */
2031                                                         if ((cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2032                                                                 rx_dma_stop(card, ch);
2033                                                         }
2034                                                         cpc_tty_receive(d);
2035                                                         rx_dma_start(card, ch);
2036                                                 } else
2037 #endif
2038                                                 {
2039                                                         if ((cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2040                                                                 rx_dma_stop(card, ch);
2041                                                         }
2042                                                         cpc_net_rx(dev);
2043                                                         /* Discard invalid frames */
2044                                                         dev->stats.rx_errors++;
2045                                                         dev->stats.rx_over_errors++;
2046                                                         chan->rx_first_bd = 0;
2047                                                         chan->rx_last_bd = N_DMA_RX_BUF - 1;
2048                                                         rx_dma_start(card, ch);
2049                                                 }
2050                                         }
2051                                 }
2052                                 if (status & IR0_DRX(IR0_DMIB, ch)) {
2053                                         if (drx_stat & DSR_EOM) {
2054                                                 if (card->hw.type == PC300_TE) {
2055                                                         cpc_writeb(card->hw.falcbase +
2056                                                                    card->hw.cpld_reg2,
2057                                                                    cpc_readb (card->hw.falcbase +
2058                                                                         card->hw.cpld_reg2) |
2059                                                                    (CPLD_REG2_FALC_LED1 << (2 * ch)));
2060                                                 }
2061 #ifdef CONFIG_PC300_MLPPP
2062                                                 if (chan->conf.proto == PC300_PROTO_MLPPP) {
2063                                                         /* verify if driver is TTY */
2064                                                         cpc_tty_receive(d);
2065                                                 } else {
2066                                                         cpc_net_rx(dev);
2067                                                 }
2068 #else
2069                                                 cpc_net_rx(dev);
2070 #endif
2071                                                 if (card->hw.type == PC300_TE) {
2072                                                         cpc_writeb(card->hw.falcbase +
2073                                                                    card->hw.cpld_reg2,
2074                                                                    cpc_readb (card->hw.falcbase +
2075                                                                                 card->hw.cpld_reg2) &
2076                                                                    ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2077                                                 }
2078                                         }
2079                                 }
2080                                 if (!(dsr_rx = cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2081 #ifdef PC300_DEBUG_INTR
2082                 printk("%s: RX intr chan[%d] (st=0x%08lx, dsr=0x%02x, dsr2=0x%02x)\n",
2083                         dev->name, ch, status, drx_stat, dsr_rx);
2084 #endif
2085                                         cpc_writeb(scabase + DSR_RX(ch), (dsr_rx | DSR_DE) & 0xfe);
2086                                 }
2087                         }
2088
2089             /**** Transmission ****/
2090                         if (status & IR0_DTX((IR0_EFT | IR0_DMIA | IR0_DMIB), ch)) {
2091                                 ucchar dtx_stat = cpc_readb(scabase + DSR_TX(ch));
2092
2093                                 /* Clear TX interrupts */
2094                                 cpc_writeb(scabase + DSR_TX(ch), dtx_stat | DSR_DWE);
2095
2096 #ifdef PC300_DEBUG_INTR
2097                                 printk ("sca_intr: TX intr chan[%d] (st=0x%08lx, dsr=0x%02x)\n",
2098                                          ch, status, dtx_stat);
2099 #endif
2100                                 if (status & IR0_DTX(IR0_EFT, ch)) {
2101                                         if (dtx_stat & DSR_UDRF) {
2102                                                 if (cpc_readb (scabase + M_REG(TBN, ch)) != 0) {
2103                                                         cpc_writeb(scabase + M_REG(CMD,ch), CMD_TX_BUF_CLR);
2104                                                 }
2105                                                 if (card->hw.type == PC300_TE) {
2106                                                         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
2107                                                                    cpc_readb (card->hw.falcbase +
2108                                                                                    card->hw.cpld_reg2) &
2109                                                                    ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2110                                                 }
2111                                                 dev->stats.tx_errors++;
2112                                                 dev->stats.tx_fifo_errors++;
2113                                                 sca_tx_intr(d);
2114                                         }
2115                                 }
2116                                 if (status & IR0_DTX(IR0_DMIA, ch)) {
2117                                         if (dtx_stat & DSR_BOF) {
2118                                         }
2119                                 }
2120                                 if (status & IR0_DTX(IR0_DMIB, ch)) {
2121                                         if (dtx_stat & DSR_EOM) {
2122                                                 if (card->hw.type == PC300_TE) {
2123                                                         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
2124                                                                    cpc_readb (card->hw.falcbase +
2125                                                                                         card->hw.cpld_reg2) &
2126                                                                    ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2127                                                 }
2128                                                 sca_tx_intr(d);
2129                                         }
2130                                 }
2131                         }
2132
2133             /**** MSCI ****/
2134                         if (status & IR0_M(IR0_RXINTA, ch)) {
2135                                 ucchar st1 = cpc_readb(scabase + M_REG(ST1, ch));
2136
2137                                 /* Clear MSCI interrupts */
2138                                 cpc_writeb(scabase + M_REG(ST1, ch), st1);
2139
2140 #ifdef PC300_DEBUG_INTR
2141                                 printk("sca_intr: MSCI intr chan[%d] (st=0x%08lx, st1=0x%02x)\n",
2142                                          ch, status, st1);
2143 #endif
2144                                 if (st1 & ST1_CDCD) {   /* DCD changed */
2145                                         if (cpc_readb(scabase + M_REG(ST3, ch)) & ST3_DCD) {
2146                                                 printk ("%s: DCD is OFF. Going administrative down.\n",
2147                                                          dev->name);
2148 #ifdef CONFIG_PC300_MLPPP
2149                                                 if (chan->conf.proto != PC300_PROTO_MLPPP) {
2150                                                         netif_carrier_off(dev);
2151                                                 }
2152 #else
2153                                                 netif_carrier_off(dev);
2154
2155 #endif
2156                                                 card->chan[ch].d.line_off++;
2157                                         } else {        /* DCD = 1 */
2158                                                 printk ("%s: DCD is ON. Going administrative up.\n",
2159                                                          dev->name);
2160 #ifdef CONFIG_PC300_MLPPP
2161                                                 if (chan->conf.proto != PC300_PROTO_MLPPP)
2162                                                         /* verify if driver is not TTY */
2163 #endif
2164                                                         netif_carrier_on(dev);
2165                                                 card->chan[ch].d.line_on++;
2166                                         }
2167                                 }
2168                         }
2169                         spin_unlock(&card->card_lock);
2170                 }
2171                 if (++intr_count == 10)
2172                         /* Too much work at this board. Force exit */
2173                         break;
2174         }
2175 }
2176
2177 static void falc_t1_loop_detection(pc300_t * card, int ch, ucchar frs1)
2178 {
2179         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2180         falc_t *pfalc = (falc_t *) & chan->falc;
2181         void __iomem *falcbase = card->hw.falcbase;
2182
2183         if (((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_XPRBS) == 0) &&
2184             !pfalc->loop_gen) {
2185                 if (frs1 & FRS1_LLBDD) {
2186                         // A Line Loop Back Deactivation signal detected
2187                         if (pfalc->loop_active) {
2188                                 falc_remote_loop(card, ch, 0);
2189                         }
2190                 } else {
2191                         if ((frs1 & FRS1_LLBAD) &&
2192                             ((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) == 0)) {
2193                                 // A Line Loop Back Activation signal detected
2194                                 if (!pfalc->loop_active) {
2195                                         falc_remote_loop(card, ch, 1);
2196                                 }
2197                         }
2198                 }
2199         }
2200 }
2201
2202 static void falc_e1_loop_detection(pc300_t * card, int ch, ucchar rsp)
2203 {
2204         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2205         falc_t *pfalc = (falc_t *) & chan->falc;
2206         void __iomem *falcbase = card->hw.falcbase;
2207
2208         if (((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_XPRBS) == 0) &&
2209             !pfalc->loop_gen) {
2210                 if (rsp & RSP_LLBDD) {
2211                         // A Line Loop Back Deactivation signal detected
2212                         if (pfalc->loop_active) {
2213                                 falc_remote_loop(card, ch, 0);
2214                         }
2215                 } else {
2216                         if ((rsp & RSP_LLBAD) &&
2217                             ((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) == 0)) {
2218                                 // A Line Loop Back Activation signal detected
2219                                 if (!pfalc->loop_active) {
2220                                         falc_remote_loop(card, ch, 1);
2221                                 }
2222                         }
2223                 }
2224         }
2225 }
2226
2227 static void falc_t1_intr(pc300_t * card, int ch)
2228 {
2229         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2230         falc_t *pfalc = (falc_t *) & chan->falc;
2231         void __iomem *falcbase = card->hw.falcbase;
2232         ucchar isr0, isr3, gis;
2233         ucchar dummy;
2234
2235         while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) {
2236                 if (gis & GIS_ISR0) {
2237                         isr0 = cpc_readb(falcbase + F_REG(FISR0, ch));
2238                         if (isr0 & FISR0_PDEN) {
2239                                 /* Read the bit to clear the situation */
2240                                 if (cpc_readb(falcbase + F_REG(FRS1, ch)) &
2241                                     FRS1_PDEN) {
2242                                         pfalc->pden++;
2243                                 }
2244                         }
2245                 }
2246
2247                 if (gis & GIS_ISR1) {
2248                         dummy = cpc_readb(falcbase + F_REG(FISR1, ch));
2249                 }
2250
2251                 if (gis & GIS_ISR2) {
2252                         dummy = cpc_readb(falcbase + F_REG(FISR2, ch));
2253                 }
2254
2255                 if (gis & GIS_ISR3) {
2256                         isr3 = cpc_readb(falcbase + F_REG(FISR3, ch));
2257                         if (isr3 & FISR3_SEC) {
2258                                 pfalc->sec++;
2259                                 falc_update_stats(card, ch);
2260                                 falc_check_status(card, ch,
2261                                                   cpc_readb(falcbase + F_REG(FRS0, ch)));
2262                         }
2263                         if (isr3 & FISR3_ES) {
2264                                 pfalc->es++;
2265                         }
2266                         if (isr3 & FISR3_LLBSC) {
2267                                 falc_t1_loop_detection(card, ch,
2268                                                        cpc_readb(falcbase + F_REG(FRS1, ch)));
2269                         }
2270                 }
2271         }
2272 }
2273
2274 static void falc_e1_intr(pc300_t * card, int ch)
2275 {
2276         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2277         falc_t *pfalc = (falc_t *) & chan->falc;
2278         void __iomem *falcbase = card->hw.falcbase;
2279         ucchar isr1, isr2, isr3, gis, rsp;
2280         ucchar dummy;
2281
2282         while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) {
2283                 rsp = cpc_readb(falcbase + F_REG(RSP, ch));
2284
2285                 if (gis & GIS_ISR0) {
2286                         dummy = cpc_readb(falcbase + F_REG(FISR0, ch));
2287                 }
2288                 if (gis & GIS_ISR1) {
2289                         isr1 = cpc_readb(falcbase + F_REG(FISR1, ch));
2290                         if (isr1 & FISR1_XMB) {
2291                                 if ((pfalc->xmb_cause & 2)
2292                                     && pfalc->multiframe_mode) {
2293                                         if (cpc_readb (falcbase + F_REG(FRS0, ch)) &
2294                                                                         (FRS0_LOS | FRS0_AIS | FRS0_LFA)) {
2295                                                 cpc_writeb(falcbase + F_REG(XSP, ch),
2296                                                            cpc_readb(falcbase + F_REG(XSP, ch))
2297                                                            & ~XSP_AXS);
2298                                         } else {
2299                                                 cpc_writeb(falcbase + F_REG(XSP, ch),
2300                                                            cpc_readb(falcbase + F_REG(XSP, ch))
2301                                                            | XSP_AXS);
2302                                         }
2303                                 }
2304                                 pfalc->xmb_cause = 0;
2305                                 cpc_writeb(falcbase + F_REG(IMR1, ch),
2306                                            cpc_readb(falcbase + F_REG(IMR1, ch)) | IMR1_XMB);
2307                         }
2308                         if (isr1 & FISR1_LLBSC) {
2309                                 falc_e1_loop_detection(card, ch, rsp);
2310                         }
2311                 }
2312                 if (gis & GIS_ISR2) {
2313                         isr2 = cpc_readb(falcbase + F_REG(FISR2, ch));
2314                         if (isr2 & FISR2_T400MS) {
2315                                 cpc_writeb(falcbase + F_REG(XSW, ch),
2316                                            cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XRA);
2317                         }
2318                         if (isr2 & FISR2_MFAR) {
2319                                 cpc_writeb(falcbase + F_REG(XSW, ch),
2320                                            cpc_readb(falcbase + F_REG(XSW, ch)) & ~XSW_XRA);
2321                         }
2322                         if (isr2 & (FISR2_FAR | FISR2_LFA | FISR2_AIS | FISR2_LOS)) {
2323                                 pfalc->xmb_cause |= 2;
2324                                 cpc_writeb(falcbase + F_REG(IMR1, ch),
2325                                            cpc_readb(falcbase + F_REG(IMR1, ch)) & ~IMR1_XMB);
2326                         }
2327                 }
2328                 if (gis & GIS_ISR3) {
2329                         isr3 = cpc_readb(falcbase + F_REG(FISR3, ch));
2330                         if (isr3 & FISR3_SEC) {
2331                                 pfalc->sec++;
2332                                 falc_update_stats(card, ch);
2333                                 falc_check_status(card, ch,
2334                                                   cpc_readb(falcbase + F_REG(FRS0, ch)));
2335                         }
2336                         if (isr3 & FISR3_ES) {
2337                                 pfalc->es++;
2338                         }
2339                 }
2340         }
2341 }
2342
2343 static void falc_intr(pc300_t * card)
2344 {
2345         int ch;
2346
2347         for (ch = 0; ch < card->hw.nchan; ch++) {
2348                 pc300ch_t *chan = &card->chan[ch];
2349                 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2350
2351                 if (conf->media == IF_IFACE_T1) {
2352                         falc_t1_intr(card, ch);
2353                 } else {
2354                         falc_e1_intr(card, ch);
2355                 }
2356         }
2357 }
2358
2359 static irqreturn_t cpc_intr(int irq, void *dev_id)
2360 {
2361         pc300_t *card = dev_id;
2362         volatile ucchar plx_status;
2363
2364         if (!card) {
2365 #ifdef PC300_DEBUG_INTR
2366                 printk("cpc_intr: spurious intr %d\n", irq);
2367 #endif
2368                 return IRQ_NONE;                /* spurious intr */
2369         }
2370
2371         if (!card->hw.rambase) {
2372 #ifdef PC300_DEBUG_INTR
2373                 printk("cpc_intr: spurious intr2 %d\n", irq);
2374 #endif
2375                 return IRQ_NONE;                /* spurious intr */
2376         }
2377
2378         switch (card->hw.type) {
2379                 case PC300_RSV:
2380                 case PC300_X21:
2381                         sca_intr(card);
2382                         break;
2383
2384                 case PC300_TE:
2385                         while ( (plx_status = (cpc_readb(card->hw.plxbase + card->hw.intctl_reg) &
2386                                  (PLX_9050_LINT1_STATUS | PLX_9050_LINT2_STATUS))) != 0) {
2387                                 if (plx_status & PLX_9050_LINT1_STATUS) {       /* SCA Interrupt */
2388                                         sca_intr(card);
2389                                 }
2390                                 if (plx_status & PLX_9050_LINT2_STATUS) {       /* FALC Interrupt */
2391                                         falc_intr(card);
2392                                 }
2393                         }
2394                         break;
2395         }
2396         return IRQ_HANDLED;
2397 }
2398
2399 static void cpc_sca_status(pc300_t * card, int ch)
2400 {
2401         ucchar ilar;
2402         void __iomem *scabase = card->hw.scabase;
2403         unsigned long flags;
2404
2405         tx_dma_buf_check(card, ch);
2406         rx_dma_buf_check(card, ch);
2407         ilar = cpc_readb(scabase + ILAR);
2408         printk ("ILAR=0x%02x, WCRL=0x%02x, PCR=0x%02x, BTCR=0x%02x, BOLR=0x%02x\n",
2409                  ilar, cpc_readb(scabase + WCRL), cpc_readb(scabase + PCR),
2410                  cpc_readb(scabase + BTCR), cpc_readb(scabase + BOLR));
2411         printk("TX_CDA=0x%08x, TX_EDA=0x%08x\n",
2412                cpc_readl(scabase + DTX_REG(CDAL, ch)),
2413                cpc_readl(scabase + DTX_REG(EDAL, ch)));
2414         printk("RX_CDA=0x%08x, RX_EDA=0x%08x, BFL=0x%04x\n",
2415                cpc_readl(scabase + DRX_REG(CDAL, ch)),
2416                cpc_readl(scabase + DRX_REG(EDAL, ch)),
2417                cpc_readw(scabase + DRX_REG(BFLL, ch)));
2418         printk("DMER=0x%02x, DSR_TX=0x%02x, DSR_RX=0x%02x\n",
2419                cpc_readb(scabase + DMER), cpc_readb(scabase + DSR_TX(ch)),
2420                cpc_readb(scabase + DSR_RX(ch)));
2421         printk("DMR_TX=0x%02x, DMR_RX=0x%02x, DIR_TX=0x%02x, DIR_RX=0x%02x\n",
2422                cpc_readb(scabase + DMR_TX(ch)), cpc_readb(scabase + DMR_RX(ch)),
2423                cpc_readb(scabase + DIR_TX(ch)),
2424                cpc_readb(scabase + DIR_RX(ch)));
2425         printk("DCR_TX=0x%02x, DCR_RX=0x%02x, FCT_TX=0x%02x, FCT_RX=0x%02x\n",
2426                cpc_readb(scabase + DCR_TX(ch)), cpc_readb(scabase + DCR_RX(ch)),
2427                cpc_readb(scabase + FCT_TX(ch)),
2428                cpc_readb(scabase + FCT_RX(ch)));
2429         printk("MD0=0x%02x, MD1=0x%02x, MD2=0x%02x, MD3=0x%02x, IDL=0x%02x\n",
2430                cpc_readb(scabase + M_REG(MD0, ch)),
2431                cpc_readb(scabase + M_REG(MD1, ch)),
2432                cpc_readb(scabase + M_REG(MD2, ch)),
2433                cpc_readb(scabase + M_REG(MD3, ch)),
2434                cpc_readb(scabase + M_REG(IDL, ch)));
2435         printk("CMD=0x%02x, SA0=0x%02x, SA1=0x%02x, TFN=0x%02x, CTL=0x%02x\n",
2436                cpc_readb(scabase + M_REG(CMD, ch)),
2437                cpc_readb(scabase + M_REG(SA0, ch)),
2438                cpc_readb(scabase + M_REG(SA1, ch)),
2439                cpc_readb(scabase + M_REG(TFN, ch)),
2440                cpc_readb(scabase + M_REG(CTL, ch)));
2441         printk("ST0=0x%02x, ST1=0x%02x, ST2=0x%02x, ST3=0x%02x, ST4=0x%02x\n",
2442                cpc_readb(scabase + M_REG(ST0, ch)),
2443                cpc_readb(scabase + M_REG(ST1, ch)),
2444                cpc_readb(scabase + M_REG(ST2, ch)),
2445                cpc_readb(scabase + M_REG(ST3, ch)),
2446                cpc_readb(scabase + M_REG(ST4, ch)));
2447         printk ("CST0=0x%02x, CST1=0x%02x, CST2=0x%02x, CST3=0x%02x, FST=0x%02x\n",
2448                  cpc_readb(scabase + M_REG(CST0, ch)),
2449                  cpc_readb(scabase + M_REG(CST1, ch)),
2450                  cpc_readb(scabase + M_REG(CST2, ch)),
2451                  cpc_readb(scabase + M_REG(CST3, ch)),
2452                  cpc_readb(scabase + M_REG(FST, ch)));
2453         printk("TRC0=0x%02x, TRC1=0x%02x, RRC=0x%02x, TBN=0x%02x, RBN=0x%02x\n",
2454                cpc_readb(scabase + M_REG(TRC0, ch)),
2455                cpc_readb(scabase + M_REG(TRC1, ch)),
2456                cpc_readb(scabase + M_REG(RRC, ch)),
2457                cpc_readb(scabase + M_REG(TBN, ch)),
2458                cpc_readb(scabase + M_REG(RBN, ch)));
2459         printk("TFS=0x%02x, TNR0=0x%02x, TNR1=0x%02x, RNR=0x%02x\n",
2460                cpc_readb(scabase + M_REG(TFS, ch)),
2461                cpc_readb(scabase + M_REG(TNR0, ch)),
2462                cpc_readb(scabase + M_REG(TNR1, ch)),
2463                cpc_readb(scabase + M_REG(RNR, ch)));
2464         printk("TCR=0x%02x, RCR=0x%02x, TNR1=0x%02x, RNR=0x%02x\n",
2465                cpc_readb(scabase + M_REG(TCR, ch)),
2466                cpc_readb(scabase + M_REG(RCR, ch)),
2467                cpc_readb(scabase + M_REG(TNR1, ch)),
2468                cpc_readb(scabase + M_REG(RNR, ch)));
2469         printk("TXS=0x%02x, RXS=0x%02x, EXS=0x%02x, TMCT=0x%02x, TMCR=0x%02x\n",
2470                cpc_readb(scabase + M_REG(TXS, ch)),
2471                cpc_readb(scabase + M_REG(RXS, ch)),
2472                cpc_readb(scabase + M_REG(EXS, ch)),
2473                cpc_readb(scabase + M_REG(TMCT, ch)),
2474                cpc_readb(scabase + M_REG(TMCR, ch)));
2475         printk("IE0=0x%02x, IE1=0x%02x, IE2=0x%02x, IE4=0x%02x, FIE=0x%02x\n",
2476                cpc_readb(scabase + M_REG(IE0, ch)),
2477                cpc_readb(scabase + M_REG(IE1, ch)),
2478                cpc_readb(scabase + M_REG(IE2, ch)),
2479                cpc_readb(scabase + M_REG(IE4, ch)),
2480                cpc_readb(scabase + M_REG(FIE, ch)));
2481         printk("IER0=0x%08x\n", cpc_readl(scabase + IER0));
2482
2483         if (ilar != 0) {
2484                 CPC_LOCK(card, flags);
2485                 cpc_writeb(scabase + ILAR, ilar);
2486                 cpc_writeb(scabase + DMER, 0x80);
2487                 CPC_UNLOCK(card, flags);
2488         }
2489 }
2490
2491 static void cpc_falc_status(pc300_t * card, int ch)
2492 {
2493         pc300ch_t *chan = &card->chan[ch];
2494         falc_t *pfalc = (falc_t *) & chan->falc;
2495         unsigned long flags;
2496
2497         CPC_LOCK(card, flags);
2498         printk("CH%d:   %s %s  %d channels\n",
2499                ch, (pfalc->sync ? "SYNC" : ""), (pfalc->active ? "ACTIVE" : ""),
2500                pfalc->num_channels);
2501
2502         printk("        pden=%d,  los=%d,  losr=%d,  lfa=%d,  farec=%d\n",
2503                pfalc->pden, pfalc->los, pfalc->losr, pfalc->lfa, pfalc->farec);
2504         printk("        lmfa=%d,  ais=%d,  sec=%d,  es=%d,  rai=%d\n",
2505                pfalc->lmfa, pfalc->ais, pfalc->sec, pfalc->es, pfalc->rai);
2506         printk("        bec=%d,  fec=%d,  cvc=%d,  cec=%d,  ebc=%d\n",
2507                pfalc->bec, pfalc->fec, pfalc->cvc, pfalc->cec, pfalc->ebc);
2508
2509         printk("\n");
2510         printk("        STATUS: %s  %s  %s  %s  %s  %s\n",
2511                (pfalc->red_alarm ? "RED" : ""),
2512                (pfalc->blue_alarm ? "BLU" : ""),
2513                (pfalc->yellow_alarm ? "YEL" : ""),
2514                (pfalc->loss_fa ? "LFA" : ""),
2515                (pfalc->loss_mfa ? "LMF" : ""), (pfalc->prbs ? "PRB" : ""));
2516         CPC_UNLOCK(card, flags);
2517 }
2518
2519 static int cpc_change_mtu(struct net_device *dev, int new_mtu)
2520 {
2521         if ((new_mtu < 128) || (new_mtu > PC300_DEF_MTU))
2522                 return -EINVAL;
2523         dev->mtu = new_mtu;
2524         return 0;
2525 }
2526
2527 static int cpc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2528 {
2529         pc300dev_t *d = (pc300dev_t *) dev->priv;
2530         pc300ch_t *chan = (pc300ch_t *) d->chan;
2531         pc300_t *card = (pc300_t *) chan->card;
2532         pc300conf_t conf_aux;
2533         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2534         int ch = chan->channel;
2535         void __user *arg = ifr->ifr_data;
2536         struct if_settings *settings = &ifr->ifr_settings;
2537         void __iomem *scabase = card->hw.scabase;
2538
2539         if (!capable(CAP_NET_ADMIN))
2540                 return -EPERM;
2541
2542         switch (cmd) {
2543                 case SIOCGPC300CONF:
2544 #ifdef CONFIG_PC300_MLPPP
2545                         if (conf->proto != PC300_PROTO_MLPPP) {
2546                                 conf->proto = /* FIXME hdlc->proto.id */ 0;
2547                         }
2548 #else
2549                         conf->proto = /* FIXME hdlc->proto.id */ 0;
2550 #endif
2551                         memcpy(&conf_aux.conf, conf, sizeof(pc300chconf_t));
2552                         memcpy(&conf_aux.hw, &card->hw, sizeof(pc300hw_t));
2553                         if (!arg ||
2554                                 copy_to_user(arg, &conf_aux, sizeof(pc300conf_t)))
2555                                 return -EINVAL;
2556                         return 0;
2557                 case SIOCSPC300CONF:
2558                         if (!capable(CAP_NET_ADMIN))
2559                                 return -EPERM;
2560                         if (!arg ||
2561                                 copy_from_user(&conf_aux.conf, arg, sizeof(pc300chconf_t)))
2562                                 return -EINVAL;
2563                         if (card->hw.cpld_id < 0x02 &&
2564                             conf_aux.conf.fr_mode == PC300_FR_UNFRAMED) {
2565                                 /* CPLD_ID < 0x02 doesn't support Unframed E1 */
2566                                 return -EINVAL;
2567                         }
2568 #ifdef CONFIG_PC300_MLPPP
2569                         if (conf_aux.conf.proto == PC300_PROTO_MLPPP) {
2570                                 if (conf->proto != PC300_PROTO_MLPPP) {
2571                                         memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2572                                         cpc_tty_init(d);        /* init TTY driver */
2573                                 }
2574                         } else {
2575                                 if (conf_aux.conf.proto == 0xffff) {
2576                                         if (conf->proto == PC300_PROTO_MLPPP){
2577                                                 /* ifdown interface */
2578                                                 cpc_close(dev);
2579                                         }
2580                                 } else {
2581                                         memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2582                                         /* FIXME hdlc->proto.id = conf->proto; */
2583                                 }
2584                         }
2585 #else
2586                         memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2587                         /* FIXME hdlc->proto.id = conf->proto; */
2588 #endif
2589                         return 0;
2590                 case SIOCGPC300STATUS:
2591                         cpc_sca_status(card, ch);
2592                         return 0;
2593                 case SIOCGPC300FALCSTATUS:
2594                         cpc_falc_status(card, ch);
2595                         return 0;
2596
2597                 case SIOCGPC300UTILSTATS:
2598                         {
2599                                 if (!arg) {     /* clear statistics */
2600                                         memset(&dev->stats, 0, sizeof(dev->stats));
2601                                         if (card->hw.type == PC300_TE) {
2602                                                 memset(&chan->falc, 0, sizeof(falc_t));
2603                                         }
2604                                 } else {
2605                                         pc300stats_t pc300stats;
2606
2607                                         memset(&pc300stats, 0, sizeof(pc300stats_t));
2608                                         pc300stats.hw_type = card->hw.type;
2609                                         pc300stats.line_on = card->chan[ch].d.line_on;
2610                                         pc300stats.line_off = card->chan[ch].d.line_off;
2611                                         memcpy(&pc300stats.gen_stats, &dev->stats,
2612                                                sizeof(dev->stats));
2613                                         if (card->hw.type == PC300_TE)
2614                                                 memcpy(&pc300stats.te_stats,&chan->falc,sizeof(falc_t));
2615                                         if (copy_to_user(arg, &pc300stats, sizeof(pc300stats_t)))
2616                                                 return -EFAULT;
2617                                 }
2618                                 return 0;
2619                         }
2620
2621                 case SIOCGPC300UTILSTATUS:
2622                         {
2623                                 struct pc300status pc300status;
2624
2625                                 pc300status.hw_type = card->hw.type;
2626                                 if (card->hw.type == PC300_TE) {
2627                                         pc300status.te_status.sync = chan->falc.sync;
2628                                         pc300status.te_status.red_alarm = chan->falc.red_alarm;
2629                                         pc300status.te_status.blue_alarm = chan->falc.blue_alarm;
2630                                         pc300status.te_status.loss_fa = chan->falc.loss_fa;
2631                                         pc300status.te_status.yellow_alarm =chan->falc.yellow_alarm;
2632                                         pc300status.te_status.loss_mfa = chan->falc.loss_mfa;
2633                                         pc300status.te_status.prbs = chan->falc.prbs;
2634                                 } else {
2635                                         pc300status.gen_status.dcd =
2636                                                 !(cpc_readb (scabase + M_REG(ST3, ch)) & ST3_DCD);
2637                                         pc300status.gen_status.cts =
2638                                                 !(cpc_readb (scabase + M_REG(ST3, ch)) & ST3_CTS);
2639                                         pc300status.gen_status.rts =
2640                                                 !(cpc_readb (scabase + M_REG(CTL, ch)) & CTL_RTS);
2641                                         pc300status.gen_status.dtr =
2642                                                 !(cpc_readb (scabase + M_REG(CTL, ch)) & CTL_DTR);
2643                                         /* There is no DSR in HD64572 */
2644                                 }
2645                                 if (!arg
2646                                     || copy_to_user(arg, &pc300status, sizeof(pc300status_t)))
2647                                                 return -EINVAL;
2648                                 return 0;
2649                         }
2650
2651                 case SIOCSPC300TRACE:
2652                         /* Sets/resets a trace_flag for the respective device */
2653                         if (!arg || copy_from_user(&d->trace_on, arg,sizeof(unsigned char)))
2654                                         return -EINVAL;
2655                         return 0;
2656
2657                 case SIOCSPC300LOOPBACK:
2658                         {
2659                                 struct pc300loopback pc300loop;
2660
2661                                 /* TE boards only */
2662                                 if (card->hw.type != PC300_TE)
2663                                         return -EINVAL;
2664
2665                                 if (!arg ||
2666                                         copy_from_user(&pc300loop, arg, sizeof(pc300loopback_t)))
2667                                                 return -EINVAL;
2668                                 switch (pc300loop.loop_type) {
2669                                         case PC300LOCLOOP:      /* Turn the local loop on/off */
2670                                                 falc_local_loop(card, ch, pc300loop.loop_on);
2671                                                 return 0;
2672
2673                                         case PC300REMLOOP:      /* Turn the remote loop on/off */
2674                                                 falc_remote_loop(card, ch, pc300loop.loop_on);
2675                                                 return 0;
2676
2677                                         case PC300PAYLOADLOOP:  /* Turn the payload loop on/off */
2678                                                 falc_payload_loop(card, ch, pc300loop.loop_on);
2679                                                 return 0;
2680
2681                                         case PC300GENLOOPUP:    /* Generate loop UP */
2682                                                 if (pc300loop.loop_on) {
2683                                                         falc_generate_loop_up_code (card, ch);
2684                                                 } else {
2685                                                         turn_off_xlu(card, ch);
2686                                                 }
2687                                                 return 0;
2688
2689                                         case PC300GENLOOPDOWN:  /* Generate loop DOWN */
2690                                                 if (pc300loop.loop_on) {
2691                                                         falc_generate_loop_down_code (card, ch);
2692                                                 } else {
2693                                                         turn_off_xld(card, ch);
2694                                                 }
2695                                                 return 0;
2696
2697                                         default:
2698                                                 return -EINVAL;
2699                                 }
2700                         }
2701
2702                 case SIOCSPC300PATTERNTEST:
2703                         /* Turn the pattern test on/off and show the errors counter */
2704                         {
2705                                 struct pc300patterntst pc300patrntst;
2706
2707                                 /* TE boards only */
2708                                 if (card->hw.type != PC300_TE)
2709                                         return -EINVAL;
2710
2711                                 if (card->hw.cpld_id < 0x02) {
2712                                         /* CPLD_ID < 0x02 doesn't support pattern test */
2713                                         return -EINVAL;
2714                                 }
2715
2716                                 if (!arg ||
2717                                         copy_from_user(&pc300patrntst,arg,sizeof(pc300patterntst_t)))
2718                                                 return -EINVAL;
2719                                 if (pc300patrntst.patrntst_on == 2) {
2720                                         if (chan->falc.prbs == 0) {
2721                                                 falc_pattern_test(card, ch, 1);
2722                                         }
2723                                         pc300patrntst.num_errors =
2724                                                 falc_pattern_test_error(card, ch);
2725                                         if (!arg
2726                                             || copy_to_user(arg, &pc300patrntst,
2727                                                             sizeof (pc300patterntst_t)))
2728                                                         return -EINVAL;
2729                                 } else {
2730                                         falc_pattern_test(card, ch, pc300patrntst.patrntst_on);
2731                                 }
2732                                 return 0;
2733                         }
2734
2735                 case SIOCWANDEV:
2736                         switch (ifr->ifr_settings.type) {
2737                                 case IF_GET_IFACE:
2738                                 {
2739                                         const size_t size = sizeof(sync_serial_settings);
2740                                         ifr->ifr_settings.type = conf->media;
2741                                         if (ifr->ifr_settings.size < size) {
2742                                                 /* data size wanted */
2743                                                 ifr->ifr_settings.size = size;
2744                                                 return -ENOBUFS;
2745                                         }
2746
2747                                         if (copy_to_user(settings->ifs_ifsu.sync,
2748                                                          &conf->phys_settings, size)) {
2749                                                 return -EFAULT;
2750                                         }
2751                                         return 0;
2752                                 }
2753
2754                                 case IF_IFACE_V35:
2755                                 case IF_IFACE_V24:
2756                                 case IF_IFACE_X21:
2757                                 {
2758                                         const size_t size = sizeof(sync_serial_settings);
2759
2760                                         if (!capable(CAP_NET_ADMIN)) {
2761                                                 return -EPERM;
2762                                         }
2763                                         /* incorrect data len? */
2764                                         if (ifr->ifr_settings.size != size) {
2765                                                 return -ENOBUFS;
2766                                         }
2767
2768                                         if (copy_from_user(&conf->phys_settings,
2769                                                            settings->ifs_ifsu.sync, size)) {
2770                                                 return -EFAULT;
2771                                         }
2772
2773                                         if (conf->phys_settings.loopback) {
2774                                                 cpc_writeb(card->hw.scabase + M_REG(MD2, ch),
2775                                                         cpc_readb(card->hw.scabase + M_REG(MD2, ch)) |
2776                                                         MD2_LOOP_MIR);
2777                                         }
2778                                         conf->media = ifr->ifr_settings.type;
2779                                         return 0;
2780                                 }
2781
2782                                 case IF_IFACE_T1:
2783                                 case IF_IFACE_E1:
2784                                 {
2785                                         const size_t te_size = sizeof(te1_settings);
2786                                         const size_t size = sizeof(sync_serial_settings);
2787
2788                                         if (!capable(CAP_NET_ADMIN)) {
2789                                                 return -EPERM;
2790                                         }
2791
2792                                         /* incorrect data len? */
2793                                         if (ifr->ifr_settings.size != te_size) {
2794                                                 return -ENOBUFS;
2795                                         }
2796
2797                                         if (copy_from_user(&conf->phys_settings,
2798                                                            settings->ifs_ifsu.te1, size)) {
2799                                                 return -EFAULT;
2800                                         }/* Ignoring HDLC slot_map for a while */
2801
2802                                         if (conf->phys_settings.loopback) {
2803                                                 cpc_writeb(card->hw.scabase + M_REG(MD2, ch),
2804                                                         cpc_readb(card->hw.scabase + M_REG(MD2, ch)) |
2805                                                         MD2_LOOP_MIR);
2806                                         }
2807                                         conf->media = ifr->ifr_settings.type;
2808                                         return 0;
2809                                 }
2810                                 default:
2811                                         return hdlc_ioctl(dev, ifr, cmd);
2812                         }
2813
2814                 default:
2815                         return hdlc_ioctl(dev, ifr, cmd);
2816         }
2817 }
2818
2819 static int clock_rate_calc(uclong rate, uclong clock, int *br_io)
2820 {
2821         int br, tc;
2822         int br_pwr, error;
2823
2824         *br_io = 0;
2825
2826         if (rate == 0)
2827                 return (0);
2828
2829         for (br = 0, br_pwr = 1; br <= 9; br++, br_pwr <<= 1) {
2830                 if ((tc = clock / br_pwr / rate) <= 0xff) {
2831                         *br_io = br;
2832                         break;
2833                 }
2834         }
2835
2836         if (tc <= 0xff) {
2837                 error = ((rate - (clock / br_pwr / rate)) / rate) * 1000;
2838                 /* Errors bigger than +/- 1% won't be tolerated */
2839                 if (error < -10 || error > 10)
2840                         return (-1);
2841                 else
2842                         return (tc);
2843         } else {
2844                 return (-1);
2845         }
2846 }
2847
2848 static int ch_config(pc300dev_t * d)
2849 {
2850         pc300ch_t *chan = (pc300ch_t *) d->chan;
2851         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2852         pc300_t *card = (pc300_t *) chan->card;
2853         void __iomem *scabase = card->hw.scabase;
2854         void __iomem *plxbase = card->hw.plxbase;
2855         int ch = chan->channel;
2856         uclong clkrate = chan->conf.phys_settings.clock_rate;
2857         uclong clktype = chan->conf.phys_settings.clock_type;
2858         ucshort encoding = chan->conf.proto_settings.encoding;
2859         ucshort parity = chan->conf.proto_settings.parity;
2860         ucchar md0, md2;
2861
2862         /* Reset the channel */
2863         cpc_writeb(scabase + M_REG(CMD, ch), CMD_CH_RST);
2864
2865         /* Configure the SCA registers */
2866         switch (parity) {
2867                 case PARITY_NONE:
2868                         md0 = MD0_BIT_SYNC;
2869                         break;
2870                 case PARITY_CRC16_PR0:
2871                         md0 = MD0_CRC16_0|MD0_CRCC0|MD0_BIT_SYNC;
2872                         break;
2873                 case PARITY_CRC16_PR1:
2874                         md0 = MD0_CRC16_1|MD0_CRCC0|MD0_BIT_SYNC;
2875                         break;
2876                 case PARITY_CRC32_PR1_CCITT:
2877                         md0 = MD0_CRC32|MD0_CRCC0|MD0_BIT_SYNC;
2878                         break;
2879                 case PARITY_CRC16_PR1_CCITT:
2880                 default:
2881                         md0 = MD0_CRC_CCITT|MD0_CRCC0|MD0_BIT_SYNC;
2882                         break;
2883         }
2884         switch (encoding) {
2885                 case ENCODING_NRZI:
2886                         md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_NRZI;
2887                         break;
2888                 case ENCODING_FM_MARK:  /* FM1 */
2889                         md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_FM1;
2890                         break;
2891                 case ENCODING_FM_SPACE: /* FM0 */
2892                         md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_FM0;
2893                         break;
2894                 case ENCODING_MANCHESTER: /* It's not working... */
2895                         md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_MANCH;
2896                         break;
2897                 case ENCODING_NRZ:
2898                 default:
2899                         md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_NRZ;
2900                         break;
2901         }
2902         cpc_writeb(scabase + M_REG(MD0, ch), md0);
2903         cpc_writeb(scabase + M_REG(MD1, ch), 0);
2904         cpc_writeb(scabase + M_REG(MD2, ch), md2);
2905         cpc_writeb(scabase + M_REG(IDL, ch), 0x7e);
2906         cpc_writeb(scabase + M_REG(CTL, ch), CTL_URSKP | CTL_IDLC);
2907
2908         /* Configure HW media */
2909         switch (card->hw.type) {
2910                 case PC300_RSV:
2911                         if (conf->media == IF_IFACE_V35) {
2912                                 cpc_writel((plxbase + card->hw.gpioc_reg),
2913                                            cpc_readl(plxbase + card->hw.gpioc_reg) | PC300_CHMEDIA_MASK(ch));
2914                         } else {
2915                                 cpc_writel((plxbase + card->hw.gpioc_reg),
2916                                            cpc_readl(plxbase + card->hw.gpioc_reg) & ~PC300_CHMEDIA_MASK(ch));
2917                         }
2918                         break;
2919
2920                 case PC300_X21:
2921                         break;
2922
2923                 case PC300_TE:
2924                         te_config(card, ch);
2925                         break;
2926         }
2927
2928         switch (card->hw.type) {
2929                 case PC300_RSV:
2930                 case PC300_X21:
2931                         if (clktype == CLOCK_INT || clktype == CLOCK_TXINT) {
2932                                 int tmc, br;
2933
2934                                 /* Calculate the clkrate parameters */
2935                                 tmc = clock_rate_calc(clkrate, card->hw.clock, &br);
2936                                 if (tmc < 0)
2937                                         return -EIO;
2938                                 cpc_writeb(scabase + M_REG(TMCT, ch), tmc);
2939                                 cpc_writeb(scabase + M_REG(TXS, ch),
2940                                            (TXS_DTRXC | TXS_IBRG | br));
2941                                 if (clktype == CLOCK_INT) {
2942                                         cpc_writeb(scabase + M_REG(TMCR, ch), tmc);
2943                                         cpc_writeb(scabase + M_REG(RXS, ch),
2944                                                    (RXS_IBRG | br));
2945                                 } else {
2946                                         cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2947                                         cpc_writeb(scabase + M_REG(RXS, ch), 0);
2948                                 }
2949                                 if (card->hw.type == PC300_X21) {
2950                                         cpc_writeb(scabase + M_REG(GPO, ch), 1);
2951                                         cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1 | EXS_RES1);
2952                                 } else {
2953                                         cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1);
2954                                 }
2955                         } else {
2956                                 cpc_writeb(scabase + M_REG(TMCT, ch), 1);
2957                                 if (clktype == CLOCK_EXT) {
2958                                         cpc_writeb(scabase + M_REG(TXS, ch),
2959                                                    TXS_DTRXC);
2960                                 } else {
2961                                         cpc_writeb(scabase + M_REG(TXS, ch),
2962                                                    TXS_DTRXC|TXS_RCLK);
2963                                 }
2964                                 cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2965                                 cpc_writeb(scabase + M_REG(RXS, ch), 0);
2966                                 if (card->hw.type == PC300_X21) {
2967                                         cpc_writeb(scabase + M_REG(GPO, ch), 0);
2968                                         cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1 | EXS_RES1);
2969                                 } else {
2970                                         cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1);
2971                                 }
2972                         }
2973                         break;
2974
2975                 case PC300_TE:
2976                         /* SCA always receives clock from the FALC chip */
2977                         cpc_writeb(scabase + M_REG(TMCT, ch), 1);
2978                         cpc_writeb(scabase + M_REG(TXS, ch), 0);
2979                         cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2980                         cpc_writeb(scabase + M_REG(RXS, ch), 0);
2981                         cpc_writeb(scabase + M_REG(EXS, ch), 0);
2982                         break;
2983         }
2984
2985         /* Enable Interrupts */
2986         cpc_writel(scabase + IER0,
2987                    cpc_readl(scabase + IER0) |
2988                    IR0_M(IR0_RXINTA, ch) |
2989                    IR0_DRX(IR0_EFT | IR0_DMIA | IR0_DMIB, ch) |
2990                    IR0_DTX(IR0_EFT | IR0_DMIA | IR0_DMIB, ch));
2991         cpc_writeb(scabase + M_REG(IE0, ch),
2992                    cpc_readl(scabase + M_REG(IE0, ch)) | IE0_RXINTA);
2993         cpc_writeb(scabase + M_REG(IE1, ch),
2994                    cpc_readl(scabase + M_REG(IE1, ch)) | IE1_CDCD);
2995
2996         return 0;
2997 }
2998
2999 static int rx_config(pc300dev_t * d)
3000 {
3001         pc300ch_t *chan = (pc300ch_t *) d->chan;
3002         pc300_t *card = (pc300_t *) chan->card;
3003         void __iomem *scabase = card->hw.scabase;
3004         int ch = chan->channel;
3005
3006         cpc_writeb(scabase + DSR_RX(ch), 0);
3007
3008         /* General RX settings */
3009         cpc_writeb(scabase + M_REG(RRC, ch), 0);
3010         cpc_writeb(scabase + M_REG(RNR, ch), 16);
3011
3012         /* Enable reception */
3013         cpc_writeb(scabase + M_REG(CMD, ch), CMD_RX_CRC_INIT);
3014         cpc_writeb(scabase + M_REG(CMD, ch), CMD_RX_ENA);
3015
3016         /* Initialize DMA stuff */
3017         chan->rx_first_bd = 0;
3018         chan->rx_last_bd = N_DMA_RX_BUF - 1;
3019         rx_dma_buf_init(card, ch);
3020         cpc_writeb(scabase + DCR_RX(ch), DCR_FCT_CLR);
3021         cpc_writeb(scabase + DMR_RX(ch), (DMR_TMOD | DMR_NF));
3022         cpc_writeb(scabase + DIR_RX(ch), (DIR_EOM | DIR_BOF));
3023
3024         /* Start DMA */
3025         rx_dma_start(card, ch);
3026
3027         return 0;
3028 }
3029
3030 static int tx_config(pc300dev_t * d)
3031 {
3032         pc300ch_t *chan = (pc300ch_t *) d->chan;
3033         pc300_t *card = (pc300_t *) chan->card;
3034         void __iomem *scabase = card->hw.scabase;
3035         int ch = chan->channel;
3036
3037         cpc_writeb(scabase + DSR_TX(ch), 0);
3038
3039         /* General TX settings */
3040         cpc_writeb(scabase + M_REG(TRC0, ch), 0);
3041         cpc_writeb(scabase + M_REG(TFS, ch), 32);
3042         cpc_writeb(scabase + M_REG(TNR0, ch), 20);
3043         cpc_writeb(scabase + M_REG(TNR1, ch), 48);
3044         cpc_writeb(scabase + M_REG(TCR, ch), 8);
3045
3046         /* Enable transmission */
3047         cpc_writeb(scabase + M_REG(CMD, ch), CMD_TX_CRC_INIT);
3048
3049         /* Initialize DMA stuff */
3050         chan->tx_first_bd = 0;
3051         chan->tx_next_bd = 0;
3052         tx_dma_buf_init(card, ch);
3053         cpc_writeb(scabase + DCR_TX(ch), DCR_FCT_CLR);
3054         cpc_writeb(scabase + DMR_TX(ch), (DMR_TMOD | DMR_NF));
3055         cpc_writeb(scabase + DIR_TX(ch), (DIR_EOM | DIR_BOF | DIR_UDRF));
3056         cpc_writel(scabase + DTX_REG(CDAL, ch), TX_BD_ADDR(ch, chan->tx_first_bd));
3057         cpc_writel(scabase + DTX_REG(EDAL, ch), TX_BD_ADDR(ch, chan->tx_next_bd));
3058
3059         return 0;
3060 }
3061
3062 static int cpc_attach(struct net_device *dev, unsigned short encoding,
3063                       unsigned short parity)
3064 {
3065         pc300dev_t *d = (pc300dev_t *)dev->priv;
3066         pc300ch_t *chan = (pc300ch_t *)d->chan;
3067         pc300_t *card = (pc300_t *)chan->card;
3068         pc300chconf_t *conf = (pc300chconf_t *)&chan->conf;
3069
3070         if (card->hw.type == PC300_TE) {
3071                 if (encoding != ENCODING_NRZ && encoding != ENCODING_NRZI) {
3072                         return -EINVAL;
3073                 }
3074         } else {
3075                 if (encoding != ENCODING_NRZ && encoding != ENCODING_NRZI &&
3076                     encoding != ENCODING_FM_MARK && encoding != ENCODING_FM_SPACE) {
3077                         /* Driver doesn't support ENCODING_MANCHESTER yet */
3078                         return -EINVAL;
3079                 }
3080         }
3081
3082         if (parity != PARITY_NONE && parity != PARITY_CRC16_PR0 &&
3083             parity != PARITY_CRC16_PR1 && parity != PARITY_CRC32_PR1_CCITT &&
3084             parity != PARITY_CRC16_PR1_CCITT) {
3085                 return -EINVAL;
3086         }
3087
3088         conf->proto_settings.encoding = encoding;
3089         conf->proto_settings.parity = parity;
3090         return 0;
3091 }
3092
3093 static int cpc_opench(pc300dev_t * d)
3094 {
3095         pc300ch_t *chan = (pc300ch_t *) d->chan;
3096         pc300_t *card = (pc300_t *) chan->card;
3097         int ch = chan->channel, rc;
3098         void __iomem *scabase = card->hw.scabase;
3099
3100         rc = ch_config(d);
3101         if (rc)
3102                 return rc;
3103
3104         rx_config(d);
3105
3106         tx_config(d);
3107
3108         /* Assert RTS and DTR */
3109         cpc_writeb(scabase + M_REG(CTL, ch),
3110                    cpc_readb(scabase + M_REG(CTL, ch)) & ~(CTL_RTS | CTL_DTR));
3111
3112         return 0;
3113 }
3114
3115 static void cpc_closech(pc300dev_t * d)
3116 {
3117         pc300ch_t *chan = (pc300ch_t *) d->chan;
3118         pc300_t *card = (pc300_t *) chan->card;
3119         falc_t *pfalc = (falc_t *) & chan->falc;
3120         int ch = chan->channel;
3121
3122         cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_CH_RST);
3123         rx_dma_stop(card, ch);
3124         tx_dma_stop(card, ch);
3125
3126         if (card->hw.type == PC300_TE) {
3127                 memset(pfalc, 0, sizeof(falc_t));
3128                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
3129                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
3130                            ~((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK |
3131                               CPLD_REG2_FALC_LED2) << (2 * ch)));
3132                 /* Reset the FALC chip */
3133                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3134                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
3135                            (CPLD_REG1_FALC_RESET << (2 * ch)));
3136                 udelay(10000);
3137                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3138                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
3139                            ~(CPLD_REG1_FALC_RESET << (2 * ch)));
3140         }
3141 }
3142
3143 int cpc_open(struct net_device *dev)
3144 {
3145         pc300dev_t *d = (pc300dev_t *) dev->priv;
3146         struct ifreq ifr;
3147         int result;
3148
3149 #ifdef  PC300_DEBUG_OTHER
3150         printk("pc300: cpc_open");
3151 #endif
3152
3153 #ifdef FIXME
3154         if (hdlc->proto.id == IF_PROTO_PPP) {
3155                 d->if_ptr = &hdlc->state.ppp.pppdev;
3156         }
3157 #endif
3158
3159         result = hdlc_open(dev);
3160         if (/* FIXME hdlc->proto.id == IF_PROTO_PPP*/ 0) {
3161                 dev->priv = d;
3162         }
3163         if (result) {
3164                 return result;
3165         }
3166
3167         sprintf(ifr.ifr_name, "%s", dev->name);
3168         result = cpc_opench(d);
3169         if (result)
3170                 goto err_out;
3171
3172         netif_start_queue(dev);
3173         return 0;
3174
3175 err_out:
3176         hdlc_close(dev);
3177         return result;
3178 }
3179
3180 static int cpc_close(struct net_device *dev)
3181 {
3182         pc300dev_t *d = (pc300dev_t *) dev->priv;
3183         pc300ch_t *chan = (pc300ch_t *) d->chan;
3184         pc300_t *card = (pc300_t *) chan->card;
3185         unsigned long flags;
3186
3187 #ifdef  PC300_DEBUG_OTHER
3188         printk("pc300: cpc_close");
3189 #endif
3190
3191         netif_stop_queue(dev);
3192
3193         CPC_LOCK(card, flags);
3194         cpc_closech(d);
3195         CPC_UNLOCK(card, flags);
3196
3197         hdlc_close(dev);
3198         if (/* FIXME hdlc->proto.id == IF_PROTO_PPP*/ 0) {
3199                 d->if_ptr = NULL;
3200         }
3201 #ifdef CONFIG_PC300_MLPPP
3202         if (chan->conf.proto == PC300_PROTO_MLPPP) {
3203                 cpc_tty_unregister_service(d);
3204                 chan->conf.proto = 0xffff;
3205         }
3206 #endif
3207
3208         return 0;
3209 }
3210
3211 static uclong detect_ram(pc300_t * card)
3212 {
3213         uclong i;
3214         ucchar data;
3215         void __iomem *rambase = card->hw.rambase;
3216
3217         card->hw.ramsize = PC300_RAMSIZE;
3218         /* Let's find out how much RAM is present on this board */
3219         for (i = 0; i < card->hw.ramsize; i++) {
3220                 data = (ucchar) (i & 0xff);
3221                 cpc_writeb(rambase + i, data);
3222                 if (cpc_readb(rambase + i) != data) {
3223                         break;
3224                 }
3225         }
3226         return (i);
3227 }
3228
3229 static void plx_init(pc300_t * card)
3230 {
3231         struct RUNTIME_9050 __iomem *plx_ctl = card->hw.plxbase;
3232
3233         /* Reset PLX */
3234         cpc_writel(&plx_ctl->init_ctrl,
3235                    cpc_readl(&plx_ctl->init_ctrl) | 0x40000000);
3236         udelay(10000L);
3237         cpc_writel(&plx_ctl->init_ctrl,
3238                    cpc_readl(&plx_ctl->init_ctrl) & ~0x40000000);
3239
3240         /* Reload Config. Registers from EEPROM */
3241         cpc_writel(&plx_ctl->init_ctrl,
3242                    cpc_readl(&plx_ctl->init_ctrl) | 0x20000000);
3243         udelay(10000L);
3244         cpc_writel(&plx_ctl->init_ctrl,
3245                    cpc_readl(&plx_ctl->init_ctrl) & ~0x20000000);
3246
3247 }
3248
3249 static inline void show_version(void)
3250 {
3251         char *rcsvers, *rcsdate, *tmp;
3252
3253         rcsvers = strchr(rcsid, ' ');
3254         rcsvers++;
3255         tmp = strchr(rcsvers, ' ');
3256         *tmp++ = '\0';
3257         rcsdate = strchr(tmp, ' ');
3258         rcsdate++;
3259         tmp = strrchr(rcsdate, ' ');
3260         *tmp = '\0';
3261         printk(KERN_INFO "Cyclades-PC300 driver %s %s (built %s %s)\n",
3262                 rcsvers, rcsdate, __DATE__, __TIME__);
3263 }                               /* show_version */
3264
3265 static void cpc_init_card(pc300_t * card)
3266 {
3267         int i, devcount = 0;
3268         static int board_nbr = 1;
3269
3270         /* Enable interrupts on the PCI bridge */
3271         plx_init(card);
3272         cpc_writew(card->hw.plxbase + card->hw.intctl_reg,
3273                    cpc_readw(card->hw.plxbase + card->hw.intctl_reg) | 0x0040);
3274
3275 #ifdef USE_PCI_CLOCK
3276         /* Set board clock to PCI clock */
3277         cpc_writel(card->hw.plxbase + card->hw.gpioc_reg,
3278                    cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) | 0x00000004UL);
3279         card->hw.clock = PC300_PCI_CLOCK;
3280 #else
3281         /* Set board clock to internal oscillator clock */
3282         cpc_writel(card->hw.plxbase + card->hw.gpioc_reg,
3283                    cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) & ~0x00000004UL);
3284         card->hw.clock = PC300_OSC_CLOCK;
3285 #endif
3286
3287         /* Detect actual on-board RAM size */
3288         card->hw.ramsize = detect_ram(card);
3289
3290         /* Set Global SCA-II registers */
3291         cpc_writeb(card->hw.scabase + PCR, PCR_PR2);
3292         cpc_writeb(card->hw.scabase + BTCR, 0x10);
3293         cpc_writeb(card->hw.scabase + WCRL, 0);
3294         cpc_writeb(card->hw.scabase + DMER, 0x80);
3295
3296         if (card->hw.type == PC300_TE) {
3297                 ucchar reg1;
3298
3299                 /* Check CPLD version */
3300                 reg1 = cpc_readb(card->hw.falcbase + CPLD_REG1);
3301                 cpc_writeb(card->hw.falcbase + CPLD_REG1, (reg1 + 0x5a));
3302                 if (cpc_readb(card->hw.falcbase + CPLD_REG1) == reg1) {
3303                         /* New CPLD */
3304                         card->hw.cpld_id = cpc_readb(card->hw.falcbase + CPLD_ID_REG);
3305                         card->hw.cpld_reg1 = CPLD_V2_REG1;
3306                         card->hw.cpld_reg2 = CPLD_V2_REG2;
3307                 } else {
3308                         /* old CPLD */
3309                         card->hw.cpld_id = 0;
3310                         card->hw.cpld_reg1 = CPLD_REG1;
3311                         card->hw.cpld_reg2 = CPLD_REG2;
3312                         cpc_writeb(card->hw.falcbase + CPLD_REG1, reg1);
3313                 }
3314
3315                 /* Enable the board's global clock */
3316                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3317                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
3318                            CPLD_REG1_GLOBAL_CLK);
3319
3320         }
3321
3322         for (i = 0; i < card->hw.nchan; i++) {
3323                 pc300ch_t *chan = &card->chan[i];
3324                 pc300dev_t *d = &chan->d;
3325                 hdlc_device *hdlc;
3326                 struct net_device *dev;
3327
3328                 chan->card = card;
3329                 chan->channel = i;
3330                 chan->conf.phys_settings.clock_rate = 0;
3331                 chan->conf.phys_settings.clock_type = CLOCK_EXT;
3332                 chan->conf.proto_settings.encoding = ENCODING_NRZ;
3333                 chan->conf.proto_settings.parity = PARITY_CRC16_PR1_CCITT;
3334                 switch (card->hw.type) {
3335                         case PC300_TE:
3336                                 chan->conf.media = IF_IFACE_T1;
3337                                 chan->conf.lcode = PC300_LC_B8ZS;
3338                                 chan->conf.fr_mode = PC300_FR_ESF;
3339                                 chan->conf.lbo = PC300_LBO_0_DB;
3340                                 chan->conf.rx_sens = PC300_RX_SENS_SH;
3341                                 chan->conf.tslot_bitmap = 0xffffffffUL;
3342                                 break;
3343
3344                         case PC300_X21:
3345                                 chan->conf.media = IF_IFACE_X21;
3346                                 break;
3347
3348                         case PC300_RSV:
3349                         default:
3350                                 chan->conf.media = IF_IFACE_V35;
3351                                 break;
3352                 }
3353                 chan->conf.proto = IF_PROTO_PPP;
3354                 chan->tx_first_bd = 0;
3355                 chan->tx_next_bd = 0;
3356                 chan->rx_first_bd = 0;
3357                 chan->rx_last_bd = N_DMA_RX_BUF - 1;
3358                 chan->nfree_tx_bd = N_DMA_TX_BUF;
3359
3360                 d->chan = chan;
3361                 d->tx_skb = NULL;
3362                 d->trace_on = 0;
3363                 d->line_on = 0;
3364                 d->line_off = 0;
3365
3366                 dev = alloc_hdlcdev(NULL);
3367                 if (dev == NULL)
3368                         continue;
3369
3370                 hdlc = dev_to_hdlc(dev);
3371                 hdlc->xmit = cpc_queue_xmit;
3372                 hdlc->attach = cpc_attach;
3373                 d->dev = dev;
3374                 dev->mem_start = card->hw.ramphys;
3375                 dev->mem_end = card->hw.ramphys + card->hw.ramsize - 1;
3376                 dev->irq = card->hw.irq;
3377                 dev->init = NULL;
3378                 dev->tx_queue_len = PC300_TX_QUEUE_LEN;
3379                 dev->mtu = PC300_DEF_MTU;
3380
3381                 dev->open = cpc_open;
3382                 dev->stop = cpc_close;
3383                 dev->tx_timeout = cpc_tx_timeout;
3384                 dev->watchdog_timeo = PC300_TX_TIMEOUT;
3385                 dev->set_multicast_list = NULL;
3386                 dev->set_mac_address = NULL;
3387                 dev->change_mtu = cpc_change_mtu;
3388                 dev->do_ioctl = cpc_ioctl;
3389
3390                 if (register_hdlc_device(dev) == 0) {
3391                         dev->priv = d;  /* We need 'priv', hdlc doesn't */
3392                         printk("%s: Cyclades-PC300/", dev->name);
3393                         switch (card->hw.type) {
3394                                 case PC300_TE:
3395                                         if (card->hw.bus == PC300_PMC) {
3396                                                 printk("TE-M");
3397                                         } else {
3398                                                 printk("TE  ");
3399                                         }
3400                                         break;
3401
3402                                 case PC300_X21:
3403                                         printk("X21 ");
3404                                         break;
3405
3406                                 case PC300_RSV:
3407                                 default:
3408                                         printk("RSV ");
3409                                         break;
3410                         }
3411                         printk (" #%d, %dKB of RAM at 0x%08x, IRQ%d, channel %d.\n",
3412                                  board_nbr, card->hw.ramsize / 1024,
3413                                  card->hw.ramphys, card->hw.irq, i + 1);
3414                         devcount++;
3415                 } else {
3416                         printk ("Dev%d on card(0x%08x): unable to allocate i/f name.\n",
3417                                  i + 1, card->hw.ramphys);
3418                         free_netdev(dev);
3419                         continue;
3420                 }
3421         }
3422         spin_lock_init(&card->card_lock);
3423
3424         board_nbr++;
3425 }
3426
3427 static int __devinit
3428 cpc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3429 {
3430         static int first_time = 1;
3431         int err, eeprom_outdated = 0;
3432         ucshort device_id;
3433         pc300_t *card;
3434
3435         if (first_time) {
3436                 first_time = 0;
3437                 show_version();
3438 #ifdef CONFIG_PC300_MLPPP
3439                 cpc_tty_reset_var();
3440 #endif
3441         }
3442
3443         if ((err = pci_enable_device(pdev)) < 0)
3444                 return err;
3445
3446         card = kzalloc(sizeof(pc300_t), GFP_KERNEL);
3447         if (card == NULL) {
3448                 printk("PC300 found at RAM 0x%016llx, "
3449                        "but could not allocate card structure.\n",
3450                        (unsigned long long)pci_resource_start(pdev, 3));
3451                 err = -ENOMEM;
3452                 goto err_disable_dev;
3453         }
3454
3455         err = -ENODEV;
3456
3457         /* read PCI configuration area */
3458         device_id = ent->device;
3459         card->hw.irq = pdev->irq;
3460         card->hw.iophys = pci_resource_start(pdev, 1);
3461         card->hw.iosize = pci_resource_len(pdev, 1);
3462         card->hw.scaphys = pci_resource_start(pdev, 2);
3463         card->hw.scasize = pci_resource_len(pdev, 2);
3464         card->hw.ramphys = pci_resource_start(pdev, 3);
3465         card->hw.alloc_ramsize = pci_resource_len(pdev, 3);
3466         card->hw.falcphys = pci_resource_start(pdev, 4);
3467         card->hw.falcsize = pci_resource_len(pdev, 4);
3468         card->hw.plxphys = pci_resource_start(pdev, 5);
3469         card->hw.plxsize = pci_resource_len(pdev, 5);
3470
3471         switch (device_id) {
3472                 case PCI_DEVICE_ID_PC300_RX_1:
3473                 case PCI_DEVICE_ID_PC300_TE_1:
3474                 case PCI_DEVICE_ID_PC300_TE_M_1:
3475                         card->hw.nchan = 1;
3476                         break;
3477
3478                 case PCI_DEVICE_ID_PC300_RX_2:
3479                 case PCI_DEVICE_ID_PC300_TE_2:
3480                 case PCI_DEVICE_ID_PC300_TE_M_2:
3481                 default:
3482                         card->hw.nchan = PC300_MAXCHAN;
3483                         break;
3484         }
3485 #ifdef PC300_DEBUG_PCI
3486         printk("cpc (bus=0x0%x,pci_id=0x%x,", pdev->bus->number, pdev->devfn);
3487         printk("rev_id=%d) IRQ%d\n", pdev->revision, card->hw.irq);
3488         printk("cpc:found  ramaddr=0x%08lx plxaddr=0x%08lx "
3489                "ctladdr=0x%08lx falcaddr=0x%08lx\n",
3490                card->hw.ramphys, card->hw.plxphys, card->hw.scaphys,
3491                card->hw.falcphys);
3492 #endif
3493         /* Although we don't use this I/O region, we should
3494          * request it from the kernel anyway, to avoid problems
3495          * with other drivers accessing it. */
3496         if (!request_region(card->hw.iophys, card->hw.iosize, "PLX Registers")) {
3497                 /* In case we can't allocate it, warn user */
3498                 printk("WARNING: couldn't allocate I/O region for PC300 board "
3499                        "at 0x%08x!\n", card->hw.ramphys);
3500         }
3501
3502         if (card->hw.plxphys) {
3503                 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, card->hw.plxphys);
3504         } else {
3505                 eeprom_outdated = 1;
3506                 card->hw.plxphys = pci_resource_start(pdev, 0);
3507                 card->hw.plxsize = pci_resource_len(pdev, 0);
3508         }
3509
3510         if (!request_mem_region(card->hw.plxphys, card->hw.plxsize,
3511                                 "PLX Registers")) {
3512                 printk("PC300 found at RAM 0x%08x, "
3513                        "but could not allocate PLX mem region.\n",
3514                        card->hw.ramphys);
3515                 goto err_release_io;
3516         }
3517         if (!request_mem_region(card->hw.ramphys, card->hw.alloc_ramsize,
3518                                 "On-board RAM")) {
3519                 printk("PC300 found at RAM 0x%08x, "
3520                        "but could not allocate RAM mem region.\n",
3521                        card->hw.ramphys);
3522                 goto err_release_plx;
3523         }
3524         if (!request_mem_region(card->hw.scaphys, card->hw.scasize,
3525                                 "SCA-II Registers")) {
3526                 printk("PC300 found at RAM 0x%08x, "
3527                        "but could not allocate SCA mem region.\n",
3528                        card->hw.ramphys);
3529                 goto err_release_ram;
3530         }
3531
3532         card->hw.plxbase = ioremap(card->hw.plxphys, card->hw.plxsize);
3533         card->hw.rambase = ioremap(card->hw.ramphys, card->hw.alloc_ramsize);
3534         card->hw.scabase = ioremap(card->hw.scaphys, card->hw.scasize);
3535         switch (device_id) {
3536                 case PCI_DEVICE_ID_PC300_TE_1:
3537                 case PCI_DEVICE_ID_PC300_TE_2:
3538                 case PCI_DEVICE_ID_PC300_TE_M_1:
3539                 case PCI_DEVICE_ID_PC300_TE_M_2:
3540                         request_mem_region(card->hw.falcphys, card->hw.falcsize,
3541                                            "FALC Registers");
3542                         card->hw.falcbase = ioremap(card->hw.falcphys, card->hw.falcsize);
3543                         break;
3544
3545                 case PCI_DEVICE_ID_PC300_RX_1:
3546                 case PCI_DEVICE_ID_PC300_RX_2:
3547                 default:
3548                         card->hw.falcbase = NULL;
3549                         break;
3550         }
3551
3552 #ifdef PC300_DEBUG_PCI
3553         printk("cpc: relocate ramaddr=0x%08lx plxaddr=0x%08lx "
3554                "ctladdr=0x%08lx falcaddr=0x%08lx\n",
3555                card->hw.rambase, card->hw.plxbase, card->hw.scabase,
3556                card->hw.falcbase);
3557 #endif
3558
3559         /* Set PCI drv pointer to the card structure */
3560         pci_set_drvdata(pdev, card);
3561
3562         /* Set board type */
3563         switch (device_id) {
3564                 case PCI_DEVICE_ID_PC300_TE_1:
3565                 case PCI_DEVICE_ID_PC300_TE_2:
3566                 case PCI_DEVICE_ID_PC300_TE_M_1:
3567                 case PCI_DEVICE_ID_PC300_TE_M_2:
3568                         card->hw.type = PC300_TE;
3569
3570                         if ((device_id == PCI_DEVICE_ID_PC300_TE_M_1) ||
3571                             (device_id == PCI_DEVICE_ID_PC300_TE_M_2)) {
3572                                 card->hw.bus = PC300_PMC;
3573                                 /* Set PLX register offsets */
3574                                 card->hw.gpioc_reg = 0x54;
3575                                 card->hw.intctl_reg = 0x4c;
3576                         } else {
3577                                 card->hw.bus = PC300_PCI;
3578                                 /* Set PLX register offsets */
3579                                 card->hw.gpioc_reg = 0x50;
3580                                 card->hw.intctl_reg = 0x4c;
3581                         }
3582                         break;
3583
3584                 case PCI_DEVICE_ID_PC300_RX_1:
3585                 case PCI_DEVICE_ID_PC300_RX_2:
3586                 default:
3587                         card->hw.bus = PC300_PCI;
3588                         /* Set PLX register offsets */
3589                         card->hw.gpioc_reg = 0x50;
3590                         card->hw.intctl_reg = 0x4c;
3591
3592                         if ((cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) & PC300_CTYPE_MASK)) {
3593                                 card->hw.type = PC300_X21;
3594                         } else {
3595                                 card->hw.type = PC300_RSV;
3596                         }
3597                         break;
3598         }
3599
3600         /* Allocate IRQ */
3601         if (request_irq(card->hw.irq, cpc_intr, IRQF_SHARED, "Cyclades-PC300", card)) {
3602                 printk ("PC300 found at RAM 0x%08x, but could not allocate IRQ%d.\n",
3603                          card->hw.ramphys, card->hw.irq);
3604                 goto err_io_unmap;
3605         }
3606
3607         cpc_init_card(card);
3608
3609         if (eeprom_outdated)
3610                 printk("WARNING: PC300 with outdated EEPROM.\n");
3611         return 0;
3612
3613 err_io_unmap:
3614         iounmap(card->hw.plxbase);
3615         iounmap(card->hw.scabase);
3616         iounmap(card->hw.rambase);
3617         if (card->hw.type == PC300_TE) {
3618                 iounmap(card->hw.falcbase);
3619                 release_mem_region(card->hw.falcphys, card->hw.falcsize);
3620         }
3621         release_mem_region(card->hw.scaphys, card->hw.scasize);
3622 err_release_ram:
3623         release_mem_region(card->hw.ramphys, card->hw.alloc_ramsize);
3624 err_release_plx:
3625         release_mem_region(card->hw.plxphys, card->hw.plxsize);
3626 err_release_io:
3627         release_region(card->hw.iophys, card->hw.iosize);
3628         kfree(card);
3629 err_disable_dev:
3630         pci_disable_device(pdev);
3631         return err;
3632 }
3633
3634 static void __devexit cpc_remove_one(struct pci_dev *pdev)
3635 {
3636         pc300_t *card = pci_get_drvdata(pdev);
3637
3638         if (card->hw.rambase) {
3639                 int i;
3640
3641                 /* Disable interrupts on the PCI bridge */
3642                 cpc_writew(card->hw.plxbase + card->hw.intctl_reg,
3643                            cpc_readw(card->hw.plxbase + card->hw.intctl_reg) & ~(0x0040));
3644
3645                 for (i = 0; i < card->hw.nchan; i++) {
3646                         unregister_hdlc_device(card->chan[i].d.dev);
3647                 }
3648                 iounmap(card->hw.plxbase);
3649                 iounmap(card->hw.scabase);
3650                 iounmap(card->hw.rambase);
3651                 release_mem_region(card->hw.plxphys, card->hw.plxsize);
3652                 release_mem_region(card->hw.ramphys, card->hw.alloc_ramsize);
3653                 release_mem_region(card->hw.scaphys, card->hw.scasize);
3654                 release_region(card->hw.iophys, card->hw.iosize);
3655                 if (card->hw.type == PC300_TE) {
3656                         iounmap(card->hw.falcbase);
3657                         release_mem_region(card->hw.falcphys, card->hw.falcsize);
3658                 }
3659                 for (i = 0; i < card->hw.nchan; i++)
3660                         if (card->chan[i].d.dev)
3661                                 free_netdev(card->chan[i].d.dev);
3662                 if (card->hw.irq)
3663                         free_irq(card->hw.irq, card);
3664                 kfree(card);
3665                 pci_disable_device(pdev);
3666         }
3667 }
3668
3669 static struct pci_driver cpc_driver = {
3670         .name           = "pc300",
3671         .id_table       = cpc_pci_dev_id,
3672         .probe          = cpc_init_one,
3673         .remove         = __devexit_p(cpc_remove_one),
3674 };
3675
3676 static int __init cpc_init(void)
3677 {
3678         return pci_register_driver(&cpc_driver);
3679 }
3680
3681 static void __exit cpc_cleanup_module(void)
3682 {
3683         pci_unregister_driver(&cpc_driver);
3684 }
3685
3686 module_init(cpc_init);
3687 module_exit(cpc_cleanup_module);
3688
3689 MODULE_DESCRIPTION("Cyclades-PC300 cards driver");
3690 MODULE_AUTHOR(  "Author: Ivan Passos <ivan@cyclades.com>\r\n"
3691                 "Maintainer: PC300 Maintainer <pc300@cyclades.com");
3692 MODULE_LICENSE("GPL");
3693