drivers/net/wireless/ath/ath9k/ar9002_hw.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/moduleparam.h>
  18 #include "hw.h"
  19 #include "ar5008_initvals.h"
  20 #include "ar9001_initvals.h"
  21 #include "ar9002_initvals.h"
  22 #include "ar9002_phy.h"
  23
  24 /* General hardware code for the A5008/AR9001/AR9002 hadware families */
  25
  26 static int ar9002_hw_init_mode_regs(struct ath_hw *ah)
  27 {
  28         if (AR_SREV_9271(ah)) {
  29                 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271);
  30                 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271);
  31                 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg);
  32                 return 0;
  33         }
  34
  35         if (ah->config.pcie_clock_req)
  36                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
  37                            ar9280PciePhy_clkreq_off_L1_9280);
  38         else
  39                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
  40                            ar9280PciePhy_clkreq_always_on_L1_9280);
  41
  42         if (AR_SREV_9287_11_OR_LATER(ah)) {
  43                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1);
  44                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1);
  45         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
  46                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2);
  47                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2);
  48         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
  49                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2);
  50                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2);
  51
  52                 INIT_INI_ARRAY(&ah->iniModesFastClock,
  53                                ar9280Modes_fast_clock_9280_2);
  54         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
  55                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160);
  56                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160);
  57                 if (AR_SREV_9160_11(ah)) {
  58                         INIT_INI_ARRAY(&ah->iniAddac,
  59                                        ar5416Addac_9160_1_1);
  60                 } else {
  61                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160);
  62                 }
  63         } else if (AR_SREV_9100_OR_LATER(ah)) {
  64                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100);
  65                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100);
  66                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100);
  67         } else {
  68                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes);
  69                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common);
  70                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac);
  71         }
  72
  73         if (!AR_SREV_9280_20_OR_LATER(ah)) {
  74                 /* Common for AR5416, AR913x, AR9160 */
  75                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain);
  76
  77                 /* Common for AR913x, AR9160 */
  78                 if (!AR_SREV_5416(ah))
  79                         INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6TPC_9100);
  80                 else
  81                         INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6TPC);
  82         }
  83
  84         /* iniAddac needs to be modified for these chips */
  85         if (AR_SREV_9160(ah) || !AR_SREV_5416_22_OR_LATER(ah)) {
  86                 struct ar5416IniArray *addac = &ah->iniAddac;
  87                 u32 size = sizeof(u32) * addac->ia_rows * addac->ia_columns;
  88                 u32 *data;
  89
  90                 data = devm_kzalloc(ah->dev, size, GFP_KERNEL);
  91                 if (!data)
  92                         return -ENOMEM;
  93
  94                 memcpy(data, addac->ia_array, size);
  95                 addac->ia_array = data;
  96
  97                 if (!AR_SREV_5416_22_OR_LATER(ah)) {
  98                         /* override CLKDRV value */
  99                         INI_RA(addac, 31,1) = 0;
 100                 }
 101         }
 102         if (AR_SREV_9287_11_OR_LATER(ah)) {
 103                 INIT_INI_ARRAY(&ah->iniCckfirNormal,
 104                        ar9287Common_normal_cck_fir_coeff_9287_1_1);
 105                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 106                        ar9287Common_japan_2484_cck_fir_coeff_9287_1_1);
 107         }
 108         return 0;
 109 }
 110
 111 static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah)
 112 {
 113         u32 rxgain_type;
 114
 115         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >=
 116             AR5416_EEP_MINOR_VER_17) {
 117                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 118
 119                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 120                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 121                                        ar9280Modes_backoff_13db_rxgain_9280_2);
 122                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 123                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 124                                        ar9280Modes_backoff_23db_rxgain_9280_2);
 125                 else
 126                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 127                                        ar9280Modes_original_rxgain_9280_2);
 128         } else {
 129                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 130                                ar9280Modes_original_rxgain_9280_2);
 131         }
 132 }
 133
 134 static void ar9280_20_hw_init_txgain_ini(struct ath_hw *ah, u32 txgain_type)
 135 {
 136         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >=
 137             AR5416_EEP_MINOR_VER_19) {
 138                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 139                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 140                                        ar9280Modes_high_power_tx_gain_9280_2);
 141                 else
 142                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 143                                        ar9280Modes_original_tx_gain_9280_2);
 144         } else {
 145                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 146                                ar9280Modes_original_tx_gain_9280_2);
 147         }
 148 }
 149
 150 static void ar9271_hw_init_txgain_ini(struct ath_hw *ah, u32 txgain_type)
 151 {
 152         if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 153                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 154                                ar9271Modes_high_power_tx_gain_9271);
 155         else
 156                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 157                                ar9271Modes_normal_power_tx_gain_9271);
 158 }
 159
 160 static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
 161 {
 162         u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 163
 164         if (AR_SREV_9287_11_OR_LATER(ah))
 165                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 166                                ar9287Modes_rx_gain_9287_1_1);
 167         else if (AR_SREV_9280_20(ah))
 168                 ar9280_20_hw_init_rxgain_ini(ah);
 169
 170         if (AR_SREV_9271(ah)) {
 171                 ar9271_hw_init_txgain_ini(ah, txgain_type);
 172         } else if (AR_SREV_9287_11_OR_LATER(ah)) {
 173                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 174                                ar9287Modes_tx_gain_9287_1_1);
 175         } else if (AR_SREV_9280_20(ah)) {
 176                 ar9280_20_hw_init_txgain_ini(ah, txgain_type);
 177         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 178                 /* txgain table */
 179                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 180                         if (AR_SREV_9285E_20(ah)) {
 181                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 182                                                ar9285Modes_XE2_0_high_power);
 183                         } else {
 184                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 185                                         ar9285Modes_high_power_tx_gain_9285_1_2);
 186                         }
 187                 } else {
 188                         if (AR_SREV_9285E_20(ah)) {
 189                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 190                                                ar9285Modes_XE2_0_normal_power);
 191                         } else {
 192                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 193                                         ar9285Modes_original_tx_gain_9285_1_2);
 194                         }
 195                 }
 196         }
 197 }
 198
 199 /*
 200  * Helper for ASPM support.
 201  *
 202  * Disable PLL when in L0s as well as receiver clock when in L1.
 203  * This power saving option must be enabled through the SerDes.
 204  *
 205  * Programming the SerDes must go through the same 288 bit serial shift
 206  * register as the other analog registers.  Hence the 9 writes.
 207  */
 208 static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
 209                                          bool power_off)
 210 {
 211         u8 i;
 212         u32 val;
 213
 214         /* Nothing to do on restore for 11N */
 215         if (!power_off /* !restore */) {
 216                 if (AR_SREV_9280_20_OR_LATER(ah)) {
 217                         /*
 218                          * AR9280 2.0 or later chips use SerDes values from the
 219                          * initvals.h initialized depending on chipset during
 220                          * __ath9k_hw_init()
 221                          */
 222                         for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
 223                                 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
 224                                           INI_RA(&ah->iniPcieSerdes, i, 1));
 225                         }
 226                 } else {
 227                         ENABLE_REGWRITE_BUFFER(ah);
 228
 229                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 230                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 231
 232                         /* RX shut off when elecidle is asserted */
 233                         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
 234                         REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
 235                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
 236
 237                         /*
 238                          * Ignore ah->ah_config.pcie_clock_req setting for
 239                          * pre-AR9280 11n
 240                          */
 241                         REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
 242
 243                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 244                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 245                         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
 246
 247                         /* Load the new settings */
 248                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 249
 250                         REGWRITE_BUFFER_FLUSH(ah);
 251                 }
 252
 253                 udelay(1000);
 254         }
 255
 256         if (power_off) {
 257                 /* clear bit 19 to disable L1 */
 258                 REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
 259
 260                 val = REG_READ(ah, AR_WA);
 261
 262                 /*
 263                  * Set PCIe workaround bits
 264                  * In AR9280 and AR9285, bit 14 in WA register (disable L1)
 265                  * should only  be set when device enters D3 and be
 266                  * cleared when device comes back to D0.
 267                  */
 268                 if (ah->config.pcie_waen) {
 269                         if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
 270                                 val |= AR_WA_D3_L1_DISABLE;
 271                 } else {
 272                         if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || AR_SREV_9287(ah)) {
 273                                 if (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)
 274                                         val |= AR_WA_D3_L1_DISABLE;
 275                         } else if (AR_SREV_9280(ah)) {
 276                                 if (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE)
 277                                         val |= AR_WA_D3_L1_DISABLE;
 278                         }
 279                 }
 280
 281                 if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) {
 282                         /*
 283                          * Disable bit 6 and 7 before entering D3 to
 284                          * prevent system hang.
 285                          */
 286                         val &= ~(AR_WA_BIT6 | AR_WA_BIT7);
 287                 }
 288
 289                 if (AR_SREV_9280(ah))
 290                         val |= AR_WA_BIT22;
 291
 292                 if (AR_SREV_9285E_20(ah))
 293                         val |= AR_WA_BIT23;
 294
 295                 REG_WRITE(ah, AR_WA, val);
 296         } else {
 297                 if (ah->config.pcie_waen) {
 298                         val = ah->config.pcie_waen;
 299                         val &= (~AR_WA_D3_L1_DISABLE);
 300                 } else {
 301                         if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || AR_SREV_9287(ah)) {
 302                                 val = AR9285_WA_DEFAULT;
 303                                 val &= (~AR_WA_D3_L1_DISABLE);
 304                         } else if (AR_SREV_9280(ah)) {
 305                                 /*
 306                                  * For AR9280 chips, bit 22 of 0x4004
 307                                  * needs to be set.
 308                                  */
 309                                 val = AR9280_WA_DEFAULT;
 310                                 val &= (~AR_WA_D3_L1_DISABLE);
 311                         } else {
 312                                 val = AR_WA_DEFAULT;
 313                         }
 314                 }
 315
 316                 /* WAR for ASPM system hang */
 317                 if (AR_SREV_9285(ah) || AR_SREV_9287(ah))
 318                         val |= (AR_WA_BIT6 | AR_WA_BIT7);
 319
 320                 if (AR_SREV_9285E_20(ah))
 321                         val |= AR_WA_BIT23;
 322
 323                 REG_WRITE(ah, AR_WA, val);
 324
 325                 /* set bit 19 to allow forcing of pcie core into L1 state */
 326                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
 327         }
 328 }
 329
 330 static int ar9002_hw_get_radiorev(struct ath_hw *ah)
 331 {
 332         u32 val;
 333         int i;
 334
 335         ENABLE_REGWRITE_BUFFER(ah);
 336
 337         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 338         for (i = 0; i < 8; i++)
 339                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 340
 341         REGWRITE_BUFFER_FLUSH(ah);
 342
 343         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 344         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 345
 346         return ath9k_hw_reverse_bits(val, 8);
 347 }
 348
 349 int ar9002_hw_rf_claim(struct ath_hw *ah)
 350 {
 351         u32 val;
 352
 353         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 354
 355         val = ar9002_hw_get_radiorev(ah);
 356         switch (val & AR_RADIO_SREV_MAJOR) {
 357         case 0:
 358                 val = AR_RAD5133_SREV_MAJOR;
 359                 break;
 360         case AR_RAD5133_SREV_MAJOR:
 361         case AR_RAD5122_SREV_MAJOR:
 362         case AR_RAD2133_SREV_MAJOR:
 363         case AR_RAD2122_SREV_MAJOR:
 364                 break;
 365         default:
 366                 ath_err(ath9k_hw_common(ah),
 367                         "Radio Chip Rev 0x%02X not supported\n",
 368                         val & AR_RADIO_SREV_MAJOR);
 369                 return -EOPNOTSUPP;
 370         }
 371
 372         ah->hw_version.analog5GhzRev = val;
 373
 374         return 0;
 375 }
 376
 377 void ar9002_hw_enable_async_fifo(struct ath_hw *ah)
 378 {
 379         if (AR_SREV_9287_13_OR_LATER(ah)) {
 380                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
 381                                 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
 382                 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
 383                 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
 384                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
 385                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
 386                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
 387         }
 388 }
 389
 390 /* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
 391 int ar9002_hw_attach_ops(struct ath_hw *ah)
 392 {
 393         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
 394         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
 395         int ret;
 396
 397         ret = ar9002_hw_init_mode_regs(ah);
 398         if (ret)
 399                 return ret;
 400
 401         priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs;
 402
 403         ops->config_pci_powersave = ar9002_hw_configpcipowersave;
 404
 405         ret = ar5008_hw_attach_phy_ops(ah);
 406         if (ret)
 407                 return ret;
 408
 409         if (AR_SREV_9280_20_OR_LATER(ah))
 410                 ar9002_hw_attach_phy_ops(ah);
 411
 412         ar9002_hw_attach_calib_ops(ah);
 413         ar9002_hw_attach_mac_ops(ah);
 414         return 0;
 415 }
 416
 417 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan)
 418 {
 419         u32 modesIndex;
 420         int i;
 421
 422         if (IS_CHAN_5GHZ(chan))
 423                 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
 424         else
 425                 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
 426
 427         ENABLE_REGWRITE_BUFFER(ah);
 428
 429         for (i = 0; i < ah->iniModes_9271_ANI_reg.ia_rows; i++) {
 430                 u32 reg = INI_RA(&ah->iniModes_9271_ANI_reg, i, 0);
 431                 u32 val = INI_RA(&ah->iniModes_9271_ANI_reg, i, modesIndex);
 432                 u32 val_orig;
 433
 434                 if (reg == AR_PHY_CCK_DETECT) {
 435                         val_orig = REG_READ(ah, reg);
 436                         val &= AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK;
 437                         val_orig &= ~AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK;
 438
 439                         REG_WRITE(ah, reg, val|val_orig);
 440                 } else
 441                         REG_WRITE(ah, reg, val);
 442         }
 443
 444         REGWRITE_BUFFER_FLUSH(ah);
 445 }