3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
42 #include <linux/dma-mapping.h>
43 #include <asm/unaligned.h>
57 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
58 MODULE_AUTHOR("Martin Langer");
59 MODULE_AUTHOR("Stefano Brivio");
60 MODULE_AUTHOR("Michael Buesch");
61 MODULE_LICENSE("GPL");
63 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
66 static int modparam_bad_frames_preempt;
67 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
68 MODULE_PARM_DESC(bad_frames_preempt,
69 "enable(1) / disable(0) Bad Frames Preemption");
71 static char modparam_fwpostfix[16];
72 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
73 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
75 static int modparam_hwpctl;
76 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
77 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
79 static int modparam_nohwcrypt;
80 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
81 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
83 int b43_modparam_qos = 1;
84 module_param_named(qos, b43_modparam_qos, int, 0444);
85 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
88 static const struct ssb_device_id b43_ssb_tbl[] = {
89 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
90 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
91 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
92 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
93 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
94 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
95 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
99 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
101 /* Channel and ratetables are shared for all devices.
102 * They can't be const, because ieee80211 puts some precalculated
103 * data in there. This data is the same for all devices, so we don't
104 * get concurrency issues */
105 #define RATETAB_ENT(_rateid, _flags) \
107 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
108 .hw_value = (_rateid), \
113 * NOTE: When changing this, sync with xmit.c's
114 * b43_plcp_get_bitrate_idx_* functions!
116 static struct ieee80211_rate __b43_ratetable[] = {
117 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
118 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
119 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
120 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
121 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
122 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
123 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
124 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
125 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
126 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
127 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
128 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
131 #define b43_a_ratetable (__b43_ratetable + 4)
132 #define b43_a_ratetable_size 8
133 #define b43_b_ratetable (__b43_ratetable + 0)
134 #define b43_b_ratetable_size 4
135 #define b43_g_ratetable (__b43_ratetable + 0)
136 #define b43_g_ratetable_size 12
138 #define CHAN4G(_channel, _freq, _flags) { \
139 .band = IEEE80211_BAND_2GHZ, \
140 .center_freq = (_freq), \
141 .hw_value = (_channel), \
143 .max_antenna_gain = 0, \
146 static struct ieee80211_channel b43_2ghz_chantable[] = {
164 #define CHAN5G(_channel, _flags) { \
165 .band = IEEE80211_BAND_5GHZ, \
166 .center_freq = 5000 + (5 * (_channel)), \
167 .hw_value = (_channel), \
169 .max_antenna_gain = 0, \
172 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
173 CHAN5G(32, 0), CHAN5G(34, 0),
174 CHAN5G(36, 0), CHAN5G(38, 0),
175 CHAN5G(40, 0), CHAN5G(42, 0),
176 CHAN5G(44, 0), CHAN5G(46, 0),
177 CHAN5G(48, 0), CHAN5G(50, 0),
178 CHAN5G(52, 0), CHAN5G(54, 0),
179 CHAN5G(56, 0), CHAN5G(58, 0),
180 CHAN5G(60, 0), CHAN5G(62, 0),
181 CHAN5G(64, 0), CHAN5G(66, 0),
182 CHAN5G(68, 0), CHAN5G(70, 0),
183 CHAN5G(72, 0), CHAN5G(74, 0),
184 CHAN5G(76, 0), CHAN5G(78, 0),
185 CHAN5G(80, 0), CHAN5G(82, 0),
186 CHAN5G(84, 0), CHAN5G(86, 0),
187 CHAN5G(88, 0), CHAN5G(90, 0),
188 CHAN5G(92, 0), CHAN5G(94, 0),
189 CHAN5G(96, 0), CHAN5G(98, 0),
190 CHAN5G(100, 0), CHAN5G(102, 0),
191 CHAN5G(104, 0), CHAN5G(106, 0),
192 CHAN5G(108, 0), CHAN5G(110, 0),
193 CHAN5G(112, 0), CHAN5G(114, 0),
194 CHAN5G(116, 0), CHAN5G(118, 0),
195 CHAN5G(120, 0), CHAN5G(122, 0),
196 CHAN5G(124, 0), CHAN5G(126, 0),
197 CHAN5G(128, 0), CHAN5G(130, 0),
198 CHAN5G(132, 0), CHAN5G(134, 0),
199 CHAN5G(136, 0), CHAN5G(138, 0),
200 CHAN5G(140, 0), CHAN5G(142, 0),
201 CHAN5G(144, 0), CHAN5G(145, 0),
202 CHAN5G(146, 0), CHAN5G(147, 0),
203 CHAN5G(148, 0), CHAN5G(149, 0),
204 CHAN5G(150, 0), CHAN5G(151, 0),
205 CHAN5G(152, 0), CHAN5G(153, 0),
206 CHAN5G(154, 0), CHAN5G(155, 0),
207 CHAN5G(156, 0), CHAN5G(157, 0),
208 CHAN5G(158, 0), CHAN5G(159, 0),
209 CHAN5G(160, 0), CHAN5G(161, 0),
210 CHAN5G(162, 0), CHAN5G(163, 0),
211 CHAN5G(164, 0), CHAN5G(165, 0),
212 CHAN5G(166, 0), CHAN5G(168, 0),
213 CHAN5G(170, 0), CHAN5G(172, 0),
214 CHAN5G(174, 0), CHAN5G(176, 0),
215 CHAN5G(178, 0), CHAN5G(180, 0),
216 CHAN5G(182, 0), CHAN5G(184, 0),
217 CHAN5G(186, 0), CHAN5G(188, 0),
218 CHAN5G(190, 0), CHAN5G(192, 0),
219 CHAN5G(194, 0), CHAN5G(196, 0),
220 CHAN5G(198, 0), CHAN5G(200, 0),
221 CHAN5G(202, 0), CHAN5G(204, 0),
222 CHAN5G(206, 0), CHAN5G(208, 0),
223 CHAN5G(210, 0), CHAN5G(212, 0),
224 CHAN5G(214, 0), CHAN5G(216, 0),
225 CHAN5G(218, 0), CHAN5G(220, 0),
226 CHAN5G(222, 0), CHAN5G(224, 0),
227 CHAN5G(226, 0), CHAN5G(228, 0),
230 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
231 CHAN5G(34, 0), CHAN5G(36, 0),
232 CHAN5G(38, 0), CHAN5G(40, 0),
233 CHAN5G(42, 0), CHAN5G(44, 0),
234 CHAN5G(46, 0), CHAN5G(48, 0),
235 CHAN5G(52, 0), CHAN5G(56, 0),
236 CHAN5G(60, 0), CHAN5G(64, 0),
237 CHAN5G(100, 0), CHAN5G(104, 0),
238 CHAN5G(108, 0), CHAN5G(112, 0),
239 CHAN5G(116, 0), CHAN5G(120, 0),
240 CHAN5G(124, 0), CHAN5G(128, 0),
241 CHAN5G(132, 0), CHAN5G(136, 0),
242 CHAN5G(140, 0), CHAN5G(149, 0),
243 CHAN5G(153, 0), CHAN5G(157, 0),
244 CHAN5G(161, 0), CHAN5G(165, 0),
245 CHAN5G(184, 0), CHAN5G(188, 0),
246 CHAN5G(192, 0), CHAN5G(196, 0),
247 CHAN5G(200, 0), CHAN5G(204, 0),
248 CHAN5G(208, 0), CHAN5G(212, 0),
253 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
254 .band = IEEE80211_BAND_5GHZ,
255 .channels = b43_5ghz_nphy_chantable,
256 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
257 .bitrates = b43_a_ratetable,
258 .n_bitrates = b43_a_ratetable_size,
261 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
262 .band = IEEE80211_BAND_5GHZ,
263 .channels = b43_5ghz_aphy_chantable,
264 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
265 .bitrates = b43_a_ratetable,
266 .n_bitrates = b43_a_ratetable_size,
269 static struct ieee80211_supported_band b43_band_2GHz = {
270 .band = IEEE80211_BAND_2GHZ,
271 .channels = b43_2ghz_chantable,
272 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
273 .bitrates = b43_g_ratetable,
274 .n_bitrates = b43_g_ratetable_size,
277 static void b43_wireless_core_exit(struct b43_wldev *dev);
278 static int b43_wireless_core_init(struct b43_wldev *dev);
279 static void b43_wireless_core_stop(struct b43_wldev *dev);
280 static int b43_wireless_core_start(struct b43_wldev *dev);
282 static int b43_ratelimit(struct b43_wl *wl)
284 if (!wl || !wl->current_dev)
286 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
288 /* We are up and running.
289 * Ratelimit the messages to avoid DoS over the net. */
290 return net_ratelimit();
293 void b43info(struct b43_wl *wl, const char *fmt, ...)
297 if (!b43_ratelimit(wl))
300 printk(KERN_INFO "b43-%s: ",
301 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
306 void b43err(struct b43_wl *wl, const char *fmt, ...)
310 if (!b43_ratelimit(wl))
313 printk(KERN_ERR "b43-%s ERROR: ",
314 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
319 void b43warn(struct b43_wl *wl, const char *fmt, ...)
323 if (!b43_ratelimit(wl))
326 printk(KERN_WARNING "b43-%s warning: ",
327 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
333 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
338 printk(KERN_DEBUG "b43-%s debug: ",
339 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
345 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
349 B43_WARN_ON(offset % 4 != 0);
351 macctl = b43_read32(dev, B43_MMIO_MACCTL);
352 if (macctl & B43_MACCTL_BE)
355 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
357 b43_write32(dev, B43_MMIO_RAM_DATA, val);
360 static inline void b43_shm_control_word(struct b43_wldev *dev,
361 u16 routing, u16 offset)
365 /* "offset" is the WORD offset. */
369 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
372 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
374 struct b43_wl *wl = dev->wl;
378 spin_lock_irqsave(&wl->shm_lock, flags);
379 if (routing == B43_SHM_SHARED) {
380 B43_WARN_ON(offset & 0x0001);
381 if (offset & 0x0003) {
382 /* Unaligned access */
383 b43_shm_control_word(dev, routing, offset >> 2);
384 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
386 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
387 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
393 b43_shm_control_word(dev, routing, offset);
394 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
396 spin_unlock_irqrestore(&wl->shm_lock, flags);
401 u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
403 struct b43_wl *wl = dev->wl;
407 spin_lock_irqsave(&wl->shm_lock, flags);
408 if (routing == B43_SHM_SHARED) {
409 B43_WARN_ON(offset & 0x0001);
410 if (offset & 0x0003) {
411 /* Unaligned access */
412 b43_shm_control_word(dev, routing, offset >> 2);
413 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
419 b43_shm_control_word(dev, routing, offset);
420 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
422 spin_unlock_irqrestore(&wl->shm_lock, flags);
427 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
429 struct b43_wl *wl = dev->wl;
432 spin_lock_irqsave(&wl->shm_lock, flags);
433 if (routing == B43_SHM_SHARED) {
434 B43_WARN_ON(offset & 0x0001);
435 if (offset & 0x0003) {
436 /* Unaligned access */
437 b43_shm_control_word(dev, routing, offset >> 2);
438 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
439 (value >> 16) & 0xffff);
440 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
441 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
446 b43_shm_control_word(dev, routing, offset);
447 b43_write32(dev, B43_MMIO_SHM_DATA, value);
449 spin_unlock_irqrestore(&wl->shm_lock, flags);
452 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
454 struct b43_wl *wl = dev->wl;
457 spin_lock_irqsave(&wl->shm_lock, flags);
458 if (routing == B43_SHM_SHARED) {
459 B43_WARN_ON(offset & 0x0001);
460 if (offset & 0x0003) {
461 /* Unaligned access */
462 b43_shm_control_word(dev, routing, offset >> 2);
463 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
468 b43_shm_control_word(dev, routing, offset);
469 b43_write16(dev, B43_MMIO_SHM_DATA, value);
471 spin_unlock_irqrestore(&wl->shm_lock, flags);
475 u64 b43_hf_read(struct b43_wldev * dev)
479 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
481 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
483 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
488 /* Write HostFlags */
489 void b43_hf_write(struct b43_wldev *dev, u64 value)
493 lo = (value & 0x00000000FFFFULL);
494 mi = (value & 0x0000FFFF0000ULL) >> 16;
495 hi = (value & 0xFFFF00000000ULL) >> 32;
496 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
497 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
498 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
501 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
503 /* We need to be careful. As we read the TSF from multiple
504 * registers, we should take care of register overflows.
505 * In theory, the whole tsf read process should be atomic.
506 * We try to be atomic here, by restaring the read process,
507 * if any of the high registers changed (overflew).
509 if (dev->dev->id.revision >= 3) {
510 u32 low, high, high2;
513 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
514 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
515 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
516 } while (unlikely(high != high2));
524 u16 test1, test2, test3;
527 v3 = b43_read16(dev, B43_MMIO_TSF_3);
528 v2 = b43_read16(dev, B43_MMIO_TSF_2);
529 v1 = b43_read16(dev, B43_MMIO_TSF_1);
530 v0 = b43_read16(dev, B43_MMIO_TSF_0);
532 test3 = b43_read16(dev, B43_MMIO_TSF_3);
533 test2 = b43_read16(dev, B43_MMIO_TSF_2);
534 test1 = b43_read16(dev, B43_MMIO_TSF_1);
535 } while (v3 != test3 || v2 != test2 || v1 != test1);
549 static void b43_time_lock(struct b43_wldev *dev)
553 macctl = b43_read32(dev, B43_MMIO_MACCTL);
554 macctl |= B43_MACCTL_TBTTHOLD;
555 b43_write32(dev, B43_MMIO_MACCTL, macctl);
556 /* Commit the write */
557 b43_read32(dev, B43_MMIO_MACCTL);
560 static void b43_time_unlock(struct b43_wldev *dev)
564 macctl = b43_read32(dev, B43_MMIO_MACCTL);
565 macctl &= ~B43_MACCTL_TBTTHOLD;
566 b43_write32(dev, B43_MMIO_MACCTL, macctl);
567 /* Commit the write */
568 b43_read32(dev, B43_MMIO_MACCTL);
571 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
573 /* Be careful with the in-progress timer.
574 * First zero out the low register, so we have a full
575 * register-overflow duration to complete the operation.
577 if (dev->dev->id.revision >= 3) {
578 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
579 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
581 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
583 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
585 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
587 u16 v0 = (tsf & 0x000000000000FFFFULL);
588 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
589 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
590 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
592 b43_write16(dev, B43_MMIO_TSF_0, 0);
594 b43_write16(dev, B43_MMIO_TSF_3, v3);
596 b43_write16(dev, B43_MMIO_TSF_2, v2);
598 b43_write16(dev, B43_MMIO_TSF_1, v1);
600 b43_write16(dev, B43_MMIO_TSF_0, v0);
604 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
607 b43_tsf_write_locked(dev, tsf);
608 b43_time_unlock(dev);
612 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
614 static const u8 zero_addr[ETH_ALEN] = { 0 };
621 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
625 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
628 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
631 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
634 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
638 u8 mac_bssid[ETH_ALEN * 2];
642 bssid = dev->wl->bssid;
643 mac = dev->wl->mac_addr;
645 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
647 memcpy(mac_bssid, mac, ETH_ALEN);
648 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
650 /* Write our MAC address and BSSID to template ram */
651 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
652 tmp = (u32) (mac_bssid[i + 0]);
653 tmp |= (u32) (mac_bssid[i + 1]) << 8;
654 tmp |= (u32) (mac_bssid[i + 2]) << 16;
655 tmp |= (u32) (mac_bssid[i + 3]) << 24;
656 b43_ram_write(dev, 0x20 + i, tmp);
660 static void b43_upload_card_macaddress(struct b43_wldev *dev)
662 b43_write_mac_bssid_templates(dev);
663 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
666 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
668 /* slot_time is in usec. */
669 if (dev->phy.type != B43_PHYTYPE_G)
671 b43_write16(dev, 0x684, 510 + slot_time);
672 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
675 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
677 b43_set_slot_time(dev, 9);
681 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
683 b43_set_slot_time(dev, 20);
687 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
688 * Returns the _previously_ enabled IRQ mask.
690 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
694 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
695 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
700 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
701 * Returns the _previously_ enabled IRQ mask.
703 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
707 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
708 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
713 /* Synchronize IRQ top- and bottom-half.
714 * IRQs must be masked before calling this.
715 * This must not be called with the irq_lock held.
717 static void b43_synchronize_irq(struct b43_wldev *dev)
719 synchronize_irq(dev->dev->irq);
720 tasklet_kill(&dev->isr_tasklet);
723 /* DummyTransmission function, as documented on
724 * http://bcm-specs.sipsolutions.net/DummyTransmission
726 void b43_dummy_transmission(struct b43_wldev *dev)
728 struct b43_phy *phy = &dev->phy;
729 unsigned int i, max_loop;
742 buffer[0] = 0x000201CC;
747 buffer[0] = 0x000B846E;
754 for (i = 0; i < 5; i++)
755 b43_ram_write(dev, i * 4, buffer[i]);
758 b43_read32(dev, B43_MMIO_MACCTL);
760 b43_write16(dev, 0x0568, 0x0000);
761 b43_write16(dev, 0x07C0, 0x0000);
762 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
763 b43_write16(dev, 0x050C, value);
764 b43_write16(dev, 0x0508, 0x0000);
765 b43_write16(dev, 0x050A, 0x0000);
766 b43_write16(dev, 0x054C, 0x0000);
767 b43_write16(dev, 0x056A, 0x0014);
768 b43_write16(dev, 0x0568, 0x0826);
769 b43_write16(dev, 0x0500, 0x0000);
770 b43_write16(dev, 0x0502, 0x0030);
772 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
773 b43_radio_write16(dev, 0x0051, 0x0017);
774 for (i = 0x00; i < max_loop; i++) {
775 value = b43_read16(dev, 0x050E);
780 for (i = 0x00; i < 0x0A; i++) {
781 value = b43_read16(dev, 0x050E);
786 for (i = 0x00; i < 0x0A; i++) {
787 value = b43_read16(dev, 0x0690);
788 if (!(value & 0x0100))
792 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
793 b43_radio_write16(dev, 0x0051, 0x0037);
796 static void key_write(struct b43_wldev *dev,
797 u8 index, u8 algorithm, const u8 * key)
804 /* Key index/algo block */
805 kidx = b43_kidx_to_fw(dev, index);
806 value = ((kidx << 4) | algorithm);
807 b43_shm_write16(dev, B43_SHM_SHARED,
808 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
810 /* Write the key to the Key Table Pointer offset */
811 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
812 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
814 value |= (u16) (key[i + 1]) << 8;
815 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
819 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
821 u32 addrtmp[2] = { 0, 0, };
822 u8 per_sta_keys_start = 8;
824 if (b43_new_kidx_api(dev))
825 per_sta_keys_start = 4;
827 B43_WARN_ON(index < per_sta_keys_start);
828 /* We have two default TX keys and possibly two default RX keys.
829 * Physical mac 0 is mapped to physical key 4 or 8, depending
830 * on the firmware version.
831 * So we must adjust the index here.
833 index -= per_sta_keys_start;
836 addrtmp[0] = addr[0];
837 addrtmp[0] |= ((u32) (addr[1]) << 8);
838 addrtmp[0] |= ((u32) (addr[2]) << 16);
839 addrtmp[0] |= ((u32) (addr[3]) << 24);
840 addrtmp[1] = addr[4];
841 addrtmp[1] |= ((u32) (addr[5]) << 8);
844 if (dev->dev->id.revision >= 5) {
845 /* Receive match transmitter address mechanism */
846 b43_shm_write32(dev, B43_SHM_RCMTA,
847 (index * 2) + 0, addrtmp[0]);
848 b43_shm_write16(dev, B43_SHM_RCMTA,
849 (index * 2) + 1, addrtmp[1]);
851 /* RXE (Receive Engine) and
852 * PSM (Programmable State Machine) mechanism
855 /* TODO write to RCM 16, 19, 22 and 25 */
857 b43_shm_write32(dev, B43_SHM_SHARED,
858 B43_SHM_SH_PSM + (index * 6) + 0,
860 b43_shm_write16(dev, B43_SHM_SHARED,
861 B43_SHM_SH_PSM + (index * 6) + 4,
867 static void do_key_write(struct b43_wldev *dev,
868 u8 index, u8 algorithm,
869 const u8 * key, size_t key_len, const u8 * mac_addr)
871 u8 buf[B43_SEC_KEYSIZE] = { 0, };
872 u8 per_sta_keys_start = 8;
874 if (b43_new_kidx_api(dev))
875 per_sta_keys_start = 4;
877 B43_WARN_ON(index >= dev->max_nr_keys);
878 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
880 if (index >= per_sta_keys_start)
881 keymac_write(dev, index, NULL); /* First zero out mac. */
883 memcpy(buf, key, key_len);
884 key_write(dev, index, algorithm, buf);
885 if (index >= per_sta_keys_start)
886 keymac_write(dev, index, mac_addr);
888 dev->key[index].algorithm = algorithm;
891 static int b43_key_write(struct b43_wldev *dev,
892 int index, u8 algorithm,
893 const u8 * key, size_t key_len,
895 struct ieee80211_key_conf *keyconf)
900 if (key_len > B43_SEC_KEYSIZE)
902 for (i = 0; i < dev->max_nr_keys; i++) {
903 /* Check that we don't already have this key. */
904 B43_WARN_ON(dev->key[i].keyconf == keyconf);
907 /* Either pairwise key or address is 00:00:00:00:00:00
908 * for transmit-only keys. Search the index. */
909 if (b43_new_kidx_api(dev))
913 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
914 if (!dev->key[i].keyconf) {
921 b43err(dev->wl, "Out of hardware key memory\n");
925 B43_WARN_ON(index > 3);
927 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
928 if ((index <= 3) && !b43_new_kidx_api(dev)) {
930 B43_WARN_ON(mac_addr);
931 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
933 keyconf->hw_key_idx = index;
934 dev->key[index].keyconf = keyconf;
939 static int b43_key_clear(struct b43_wldev *dev, int index)
941 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
943 do_key_write(dev, index, B43_SEC_ALGO_NONE,
944 NULL, B43_SEC_KEYSIZE, NULL);
945 if ((index <= 3) && !b43_new_kidx_api(dev)) {
946 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
947 NULL, B43_SEC_KEYSIZE, NULL);
949 dev->key[index].keyconf = NULL;
954 static void b43_clear_keys(struct b43_wldev *dev)
958 for (i = 0; i < dev->max_nr_keys; i++)
959 b43_key_clear(dev, i);
962 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
970 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
971 (ps_flags & B43_PS_DISABLED));
972 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
974 if (ps_flags & B43_PS_ENABLED) {
976 } else if (ps_flags & B43_PS_DISABLED) {
979 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
980 // and thus is not an AP and we are associated, set bit 25
982 if (ps_flags & B43_PS_AWAKE) {
984 } else if (ps_flags & B43_PS_ASLEEP) {
987 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
988 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
989 // successful, set bit26
992 /* FIXME: For now we force awake-on and hwps-off */
996 macctl = b43_read32(dev, B43_MMIO_MACCTL);
998 macctl |= B43_MACCTL_HWPS;
1000 macctl &= ~B43_MACCTL_HWPS;
1002 macctl |= B43_MACCTL_AWAKE;
1004 macctl &= ~B43_MACCTL_AWAKE;
1005 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1007 b43_read32(dev, B43_MMIO_MACCTL);
1008 if (awake && dev->dev->id.revision >= 5) {
1009 /* Wait for the microcode to wake up. */
1010 for (i = 0; i < 100; i++) {
1011 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1012 B43_SHM_SH_UCODESTAT);
1013 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1020 /* Turn the Analog ON/OFF */
1021 static void b43_switch_analog(struct b43_wldev *dev, int on)
1023 switch (dev->phy.type) {
1026 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
1029 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
1037 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1042 flags |= B43_TMSLOW_PHYCLKEN;
1043 flags |= B43_TMSLOW_PHYRESET;
1044 ssb_device_enable(dev->dev, flags);
1045 msleep(2); /* Wait for the PLL to turn on. */
1047 /* Now take the PHY out of Reset again */
1048 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1049 tmslow |= SSB_TMSLOW_FGC;
1050 tmslow &= ~B43_TMSLOW_PHYRESET;
1051 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1052 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1054 tmslow &= ~SSB_TMSLOW_FGC;
1055 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1056 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1059 /* Turn Analog ON */
1060 b43_switch_analog(dev, 1);
1062 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1063 macctl &= ~B43_MACCTL_GMODE;
1064 if (flags & B43_TMSLOW_GMODE)
1065 macctl |= B43_MACCTL_GMODE;
1066 macctl |= B43_MACCTL_IHR_ENABLED;
1067 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1070 static void handle_irq_transmit_status(struct b43_wldev *dev)
1074 struct b43_txstatus stat;
1077 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1078 if (!(v0 & 0x00000001))
1080 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1082 stat.cookie = (v0 >> 16);
1083 stat.seq = (v1 & 0x0000FFFF);
1084 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1085 tmp = (v0 & 0x0000FFFF);
1086 stat.frame_count = ((tmp & 0xF000) >> 12);
1087 stat.rts_count = ((tmp & 0x0F00) >> 8);
1088 stat.supp_reason = ((tmp & 0x001C) >> 2);
1089 stat.pm_indicated = !!(tmp & 0x0080);
1090 stat.intermediate = !!(tmp & 0x0040);
1091 stat.for_ampdu = !!(tmp & 0x0020);
1092 stat.acked = !!(tmp & 0x0002);
1094 b43_handle_txstatus(dev, &stat);
1098 static void drain_txstatus_queue(struct b43_wldev *dev)
1102 if (dev->dev->id.revision < 5)
1104 /* Read all entries from the microcode TXstatus FIFO
1105 * and throw them away.
1108 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1109 if (!(dummy & 0x00000001))
1111 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1115 static u32 b43_jssi_read(struct b43_wldev *dev)
1119 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1121 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1126 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1128 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1129 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1132 static void b43_generate_noise_sample(struct b43_wldev *dev)
1134 b43_jssi_write(dev, 0x7F7F7F7F);
1135 b43_write32(dev, B43_MMIO_MACCMD,
1136 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1137 B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1140 static void b43_calculate_link_quality(struct b43_wldev *dev)
1142 /* Top half of Link Quality calculation. */
1144 if (dev->noisecalc.calculation_running)
1146 dev->noisecalc.channel_at_start = dev->phy.channel;
1147 dev->noisecalc.calculation_running = 1;
1148 dev->noisecalc.nr_samples = 0;
1150 b43_generate_noise_sample(dev);
1153 static void handle_irq_noise(struct b43_wldev *dev)
1155 struct b43_phy *phy = &dev->phy;
1161 /* Bottom half of Link Quality calculation. */
1163 B43_WARN_ON(!dev->noisecalc.calculation_running);
1164 if (dev->noisecalc.channel_at_start != phy->channel)
1165 goto drop_calculation;
1166 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1167 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1168 noise[2] == 0x7F || noise[3] == 0x7F)
1171 /* Get the noise samples. */
1172 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1173 i = dev->noisecalc.nr_samples;
1174 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1175 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1176 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1177 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1178 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1179 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1180 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1181 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1182 dev->noisecalc.nr_samples++;
1183 if (dev->noisecalc.nr_samples == 8) {
1184 /* Calculate the Link Quality by the noise samples. */
1186 for (i = 0; i < 8; i++) {
1187 for (j = 0; j < 4; j++)
1188 average += dev->noisecalc.samples[i][j];
1194 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1195 tmp = (tmp / 128) & 0x1F;
1205 dev->stats.link_noise = average;
1207 dev->noisecalc.calculation_running = 0;
1211 b43_generate_noise_sample(dev);
1214 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1216 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1219 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1220 b43_power_saving_ctl_bits(dev, 0);
1222 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1226 static void handle_irq_atim_end(struct b43_wldev *dev)
1228 if (dev->dfq_valid) {
1229 b43_write32(dev, B43_MMIO_MACCMD,
1230 b43_read32(dev, B43_MMIO_MACCMD)
1231 | B43_MACCMD_DFQ_VALID);
1236 static void handle_irq_pmq(struct b43_wldev *dev)
1243 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1244 if (!(tmp & 0x00000008))
1247 /* 16bit write is odd, but correct. */
1248 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1251 static void b43_write_template_common(struct b43_wldev *dev,
1252 const u8 * data, u16 size,
1254 u16 shm_size_offset, u8 rate)
1257 struct b43_plcp_hdr4 plcp;
1260 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1261 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1262 ram_offset += sizeof(u32);
1263 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1264 * So leave the first two bytes of the next write blank.
1266 tmp = (u32) (data[0]) << 16;
1267 tmp |= (u32) (data[1]) << 24;
1268 b43_ram_write(dev, ram_offset, tmp);
1269 ram_offset += sizeof(u32);
1270 for (i = 2; i < size; i += sizeof(u32)) {
1271 tmp = (u32) (data[i + 0]);
1273 tmp |= (u32) (data[i + 1]) << 8;
1275 tmp |= (u32) (data[i + 2]) << 16;
1277 tmp |= (u32) (data[i + 3]) << 24;
1278 b43_ram_write(dev, ram_offset + i - 2, tmp);
1280 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1281 size + sizeof(struct b43_plcp_hdr6));
1284 static void b43_write_beacon_template(struct b43_wldev *dev,
1286 u16 shm_size_offset, u8 rate)
1288 unsigned int i, len, variable_len;
1289 const struct ieee80211_mgmt *bcn;
1293 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1294 len = min((size_t) dev->wl->current_beacon->len,
1295 0x200 - sizeof(struct b43_plcp_hdr6));
1297 b43_write_template_common(dev, (const u8 *)bcn,
1298 len, ram_offset, shm_size_offset, rate);
1300 /* Find the position of the TIM and the DTIM_period value
1301 * and write them to SHM. */
1302 ie = bcn->u.beacon.variable;
1303 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1304 for (i = 0; i < variable_len - 2; ) {
1305 uint8_t ie_id, ie_len;
1312 /* This is the TIM Information Element */
1314 /* Check whether the ie_len is in the beacon data range. */
1315 if (variable_len < ie_len + 2 + i)
1317 /* A valid TIM is at least 4 bytes long. */
1322 tim_position = sizeof(struct b43_plcp_hdr6);
1323 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1326 dtim_period = ie[i + 3];
1328 b43_shm_write16(dev, B43_SHM_SHARED,
1329 B43_SHM_SH_TIMBPOS, tim_position);
1330 b43_shm_write16(dev, B43_SHM_SHARED,
1331 B43_SHM_SH_DTIMPER, dtim_period);
1337 b43warn(dev->wl, "Did not find a valid TIM IE in "
1338 "the beacon template packet. AP or IBSS operation "
1339 "may be broken.\n");
1341 b43dbg(dev->wl, "Updated beacon template\n");
1344 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1345 u16 shm_offset, u16 size,
1346 struct ieee80211_rate *rate)
1348 struct b43_plcp_hdr4 plcp;
1353 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
1354 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1357 /* Write PLCP in two parts and timing for packet transfer */
1358 tmp = le32_to_cpu(plcp.data);
1359 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1360 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1361 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1364 /* Instead of using custom probe response template, this function
1365 * just patches custom beacon template by:
1366 * 1) Changing packet type
1367 * 2) Patching duration field
1370 static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
1372 struct ieee80211_rate *rate)
1376 u16 src_size, elem_size, src_pos, dest_pos;
1378 struct ieee80211_hdr *hdr;
1381 src_size = dev->wl->current_beacon->len;
1382 src_data = (const u8 *)dev->wl->current_beacon->data;
1384 /* Get the start offset of the variable IEs in the packet. */
1385 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1386 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
1388 if (B43_WARN_ON(src_size < ie_start))
1391 dest_data = kmalloc(src_size, GFP_ATOMIC);
1392 if (unlikely(!dest_data))
1395 /* Copy the static data and all Information Elements, except the TIM. */
1396 memcpy(dest_data, src_data, ie_start);
1398 dest_pos = ie_start;
1399 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1400 elem_size = src_data[src_pos + 1] + 2;
1401 if (src_data[src_pos] == 5) {
1402 /* This is the TIM. */
1405 memcpy(dest_data + dest_pos, src_data + src_pos,
1407 dest_pos += elem_size;
1409 *dest_size = dest_pos;
1410 hdr = (struct ieee80211_hdr *)dest_data;
1412 /* Set the frame control. */
1413 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1414 IEEE80211_STYPE_PROBE_RESP);
1415 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1416 dev->wl->vif, *dest_size,
1418 hdr->duration_id = dur;
1423 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1425 u16 shm_size_offset,
1426 struct ieee80211_rate *rate)
1428 const u8 *probe_resp_data;
1431 size = dev->wl->current_beacon->len;
1432 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1433 if (unlikely(!probe_resp_data))
1436 /* Looks like PLCP headers plus packet timings are stored for
1437 * all possible basic rates
1439 b43_write_probe_resp_plcp(dev, 0x31A, size, &b43_b_ratetable[0]);
1440 b43_write_probe_resp_plcp(dev, 0x32C, size, &b43_b_ratetable[1]);
1441 b43_write_probe_resp_plcp(dev, 0x33E, size, &b43_b_ratetable[2]);
1442 b43_write_probe_resp_plcp(dev, 0x350, size, &b43_b_ratetable[3]);
1444 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1445 b43_write_template_common(dev, probe_resp_data,
1446 size, ram_offset, shm_size_offset,
1448 kfree(probe_resp_data);
1451 static void handle_irq_beacon(struct b43_wldev *dev)
1453 struct b43_wl *wl = dev->wl;
1454 u32 cmd, beacon0_valid, beacon1_valid;
1456 if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
1459 /* This is the bottom half of the asynchronous beacon update. */
1461 /* Ignore interrupt in the future. */
1462 dev->irq_savedstate &= ~B43_IRQ_BEACON;
1464 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1465 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1466 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1468 /* Schedule interrupt manually, if busy. */
1469 if (beacon0_valid && beacon1_valid) {
1470 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1471 dev->irq_savedstate |= B43_IRQ_BEACON;
1475 if (!beacon0_valid) {
1476 if (!wl->beacon0_uploaded) {
1477 b43_write_beacon_template(dev, 0x68, 0x18,
1479 b43_write_probe_resp_template(dev, 0x268, 0x4A,
1480 &__b43_ratetable[3]);
1481 wl->beacon0_uploaded = 1;
1483 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1484 cmd |= B43_MACCMD_BEACON0_VALID;
1485 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1486 } else if (!beacon1_valid) {
1487 if (!wl->beacon1_uploaded) {
1488 b43_write_beacon_template(dev, 0x468, 0x1A,
1490 wl->beacon1_uploaded = 1;
1492 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1493 cmd |= B43_MACCMD_BEACON1_VALID;
1494 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1498 static void b43_beacon_update_trigger_work(struct work_struct *work)
1500 struct b43_wl *wl = container_of(work, struct b43_wl,
1501 beacon_update_trigger);
1502 struct b43_wldev *dev;
1504 mutex_lock(&wl->mutex);
1505 dev = wl->current_dev;
1506 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1507 spin_lock_irq(&wl->irq_lock);
1508 /* update beacon right away or defer to irq */
1509 dev->irq_savedstate = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1510 handle_irq_beacon(dev);
1511 /* The handler might have updated the IRQ mask. */
1512 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK,
1513 dev->irq_savedstate);
1515 spin_unlock_irq(&wl->irq_lock);
1517 mutex_unlock(&wl->mutex);
1520 /* Asynchronously update the packet templates in template RAM.
1521 * Locking: Requires wl->irq_lock to be locked. */
1522 static void b43_update_templates(struct b43_wl *wl, struct sk_buff *beacon)
1524 /* This is the top half of the ansynchronous beacon update.
1525 * The bottom half is the beacon IRQ.
1526 * Beacon update must be asynchronous to avoid sending an
1527 * invalid beacon. This can happen for example, if the firmware
1528 * transmits a beacon while we are updating it. */
1530 if (wl->current_beacon)
1531 dev_kfree_skb_any(wl->current_beacon);
1532 wl->current_beacon = beacon;
1533 wl->beacon0_uploaded = 0;
1534 wl->beacon1_uploaded = 0;
1535 queue_work(wl->hw->workqueue, &wl->beacon_update_trigger);
1538 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1543 len = min((u16) ssid_len, (u16) 0x100);
1544 for (i = 0; i < len; i += sizeof(u32)) {
1545 tmp = (u32) (ssid[i + 0]);
1547 tmp |= (u32) (ssid[i + 1]) << 8;
1549 tmp |= (u32) (ssid[i + 2]) << 16;
1551 tmp |= (u32) (ssid[i + 3]) << 24;
1552 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1554 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1557 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1560 if (dev->dev->id.revision >= 3) {
1561 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1562 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1564 b43_write16(dev, 0x606, (beacon_int >> 6));
1565 b43_write16(dev, 0x610, beacon_int);
1567 b43_time_unlock(dev);
1568 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1571 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1576 /* Interrupt handler bottom-half */
1577 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1580 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1581 u32 merged_dma_reason = 0;
1583 unsigned long flags;
1585 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1587 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1589 reason = dev->irq_reason;
1590 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1591 dma_reason[i] = dev->dma_reason[i];
1592 merged_dma_reason |= dma_reason[i];
1595 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1596 b43err(dev->wl, "MAC transmission error\n");
1598 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1599 b43err(dev->wl, "PHY transmission error\n");
1601 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1602 atomic_set(&dev->phy.txerr_cnt,
1603 B43_PHY_TX_BADNESS_LIMIT);
1604 b43err(dev->wl, "Too many PHY TX errors, "
1605 "restarting the controller\n");
1606 b43_controller_restart(dev, "PHY TX errors");
1610 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1611 B43_DMAIRQ_NONFATALMASK))) {
1612 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1613 b43err(dev->wl, "Fatal DMA error: "
1614 "0x%08X, 0x%08X, 0x%08X, "
1615 "0x%08X, 0x%08X, 0x%08X\n",
1616 dma_reason[0], dma_reason[1],
1617 dma_reason[2], dma_reason[3],
1618 dma_reason[4], dma_reason[5]);
1619 b43_controller_restart(dev, "DMA error");
1621 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1624 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1625 b43err(dev->wl, "DMA error: "
1626 "0x%08X, 0x%08X, 0x%08X, "
1627 "0x%08X, 0x%08X, 0x%08X\n",
1628 dma_reason[0], dma_reason[1],
1629 dma_reason[2], dma_reason[3],
1630 dma_reason[4], dma_reason[5]);
1634 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1635 handle_irq_ucode_debug(dev);
1636 if (reason & B43_IRQ_TBTT_INDI)
1637 handle_irq_tbtt_indication(dev);
1638 if (reason & B43_IRQ_ATIM_END)
1639 handle_irq_atim_end(dev);
1640 if (reason & B43_IRQ_BEACON)
1641 handle_irq_beacon(dev);
1642 if (reason & B43_IRQ_PMQ)
1643 handle_irq_pmq(dev);
1644 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1646 if (reason & B43_IRQ_NOISESAMPLE_OK)
1647 handle_irq_noise(dev);
1649 /* Check the DMA reason registers for received data. */
1650 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1651 if (b43_using_pio_transfers(dev))
1652 b43_pio_rx(dev->pio.rx_queue);
1654 b43_dma_rx(dev->dma.rx_ring);
1656 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1657 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1658 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1659 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1660 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1662 if (reason & B43_IRQ_TX_OK)
1663 handle_irq_transmit_status(dev);
1665 b43_interrupt_enable(dev, dev->irq_savedstate);
1667 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1670 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1672 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1674 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1675 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1676 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1677 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1678 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1679 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1682 /* Interrupt handler top-half */
1683 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1685 irqreturn_t ret = IRQ_NONE;
1686 struct b43_wldev *dev = dev_id;
1692 spin_lock(&dev->wl->irq_lock);
1694 if (b43_status(dev) < B43_STAT_STARTED)
1696 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1697 if (reason == 0xffffffff) /* shared IRQ */
1700 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1704 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1706 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1708 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1710 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1712 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1714 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1717 b43_interrupt_ack(dev, reason);
1718 /* disable all IRQs. They are enabled again in the bottom half. */
1719 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1720 /* save the reason code and call our bottom half. */
1721 dev->irq_reason = reason;
1722 tasklet_schedule(&dev->isr_tasklet);
1725 spin_unlock(&dev->wl->irq_lock);
1730 static void do_release_fw(struct b43_firmware_file *fw)
1732 release_firmware(fw->data);
1734 fw->filename = NULL;
1737 static void b43_release_firmware(struct b43_wldev *dev)
1739 do_release_fw(&dev->fw.ucode);
1740 do_release_fw(&dev->fw.pcm);
1741 do_release_fw(&dev->fw.initvals);
1742 do_release_fw(&dev->fw.initvals_band);
1745 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
1749 text = "You must go to "
1750 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1751 "and download the latest firmware (version 4).\n";
1758 static int do_request_fw(struct b43_wldev *dev,
1760 struct b43_firmware_file *fw)
1762 char path[sizeof(modparam_fwpostfix) + 32];
1763 const struct firmware *blob;
1764 struct b43_fw_header *hdr;
1769 /* Don't fetch anything. Free possibly cached firmware. */
1774 if (strcmp(fw->filename, name) == 0)
1775 return 0; /* Already have this fw. */
1776 /* Free the cached firmware first. */
1780 snprintf(path, ARRAY_SIZE(path),
1782 modparam_fwpostfix, name);
1783 err = request_firmware(&blob, path, dev->dev->dev);
1785 b43err(dev->wl, "Firmware file \"%s\" not found "
1786 "or load failed.\n", path);
1789 if (blob->size < sizeof(struct b43_fw_header))
1791 hdr = (struct b43_fw_header *)(blob->data);
1792 switch (hdr->type) {
1793 case B43_FW_TYPE_UCODE:
1794 case B43_FW_TYPE_PCM:
1795 size = be32_to_cpu(hdr->size);
1796 if (size != blob->size - sizeof(struct b43_fw_header))
1799 case B43_FW_TYPE_IV:
1808 fw->filename = name;
1813 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1814 release_firmware(blob);
1819 static int b43_request_firmware(struct b43_wldev *dev)
1821 struct b43_firmware *fw = &dev->fw;
1822 const u8 rev = dev->dev->id.revision;
1823 const char *filename;
1828 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1829 if ((rev >= 5) && (rev <= 10))
1830 filename = "ucode5";
1831 else if ((rev >= 11) && (rev <= 12))
1832 filename = "ucode11";
1834 filename = "ucode13";
1837 err = do_request_fw(dev, filename, &fw->ucode);
1842 if ((rev >= 5) && (rev <= 10))
1848 err = do_request_fw(dev, filename, &fw->pcm);
1853 switch (dev->phy.type) {
1855 if ((rev >= 5) && (rev <= 10)) {
1856 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1857 filename = "a0g1initvals5";
1859 filename = "a0g0initvals5";
1861 goto err_no_initvals;
1864 if ((rev >= 5) && (rev <= 10))
1865 filename = "b0g0initvals5";
1867 filename = "lp0initvals13";
1869 goto err_no_initvals;
1872 if ((rev >= 11) && (rev <= 12))
1873 filename = "n0initvals11";
1875 goto err_no_initvals;
1878 goto err_no_initvals;
1880 err = do_request_fw(dev, filename, &fw->initvals);
1884 /* Get bandswitch initvals */
1885 switch (dev->phy.type) {
1887 if ((rev >= 5) && (rev <= 10)) {
1888 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1889 filename = "a0g1bsinitvals5";
1891 filename = "a0g0bsinitvals5";
1892 } else if (rev >= 11)
1895 goto err_no_initvals;
1898 if ((rev >= 5) && (rev <= 10))
1899 filename = "b0g0bsinitvals5";
1903 goto err_no_initvals;
1906 if ((rev >= 11) && (rev <= 12))
1907 filename = "n0bsinitvals11";
1909 goto err_no_initvals;
1912 goto err_no_initvals;
1914 err = do_request_fw(dev, filename, &fw->initvals_band);
1921 b43_print_fw_helptext(dev->wl, 1);
1926 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1931 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1936 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1937 "core rev %u\n", dev->phy.type, rev);
1941 b43_release_firmware(dev);
1945 static int b43_upload_microcode(struct b43_wldev *dev)
1947 const size_t hdr_len = sizeof(struct b43_fw_header);
1949 unsigned int i, len;
1950 u16 fwrev, fwpatch, fwdate, fwtime;
1954 /* Jump the microcode PSM to offset 0 */
1955 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1956 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
1957 macctl |= B43_MACCTL_PSM_JMP0;
1958 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1959 /* Zero out all microcode PSM registers and shared memory. */
1960 for (i = 0; i < 64; i++)
1961 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
1962 for (i = 0; i < 4096; i += 2)
1963 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
1965 /* Upload Microcode. */
1966 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
1967 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
1968 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1969 for (i = 0; i < len; i++) {
1970 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1974 if (dev->fw.pcm.data) {
1975 /* Upload PCM data. */
1976 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
1977 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
1978 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1979 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1980 /* No need for autoinc bit in SHM_HW */
1981 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1982 for (i = 0; i < len; i++) {
1983 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1988 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1990 /* Start the microcode PSM */
1991 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1992 macctl &= ~B43_MACCTL_PSM_JMP0;
1993 macctl |= B43_MACCTL_PSM_RUN;
1994 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1996 /* Wait for the microcode to load and respond */
1999 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2000 if (tmp == B43_IRQ_MAC_SUSPENDED)
2004 b43err(dev->wl, "Microcode not responding\n");
2005 b43_print_fw_helptext(dev->wl, 1);
2009 msleep_interruptible(50);
2010 if (signal_pending(current)) {
2015 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2017 /* Get and check the revisions. */
2018 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2019 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2020 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2021 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2023 if (fwrev <= 0x128) {
2024 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2025 "binary drivers older than version 4.x is unsupported. "
2026 "You must upgrade your firmware files.\n");
2027 b43_print_fw_helptext(dev->wl, 1);
2031 b43info(dev->wl, "Loading firmware version %u.%u "
2032 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2034 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2035 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2037 dev->fw.rev = fwrev;
2038 dev->fw.patch = fwpatch;
2040 if (b43_is_old_txhdr_format(dev)) {
2041 b43warn(dev->wl, "You are using an old firmware image. "
2042 "Support for old firmware will be removed in July 2008.\n");
2043 b43_print_fw_helptext(dev->wl, 0);
2049 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2050 macctl &= ~B43_MACCTL_PSM_RUN;
2051 macctl |= B43_MACCTL_PSM_JMP0;
2052 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2057 static int b43_write_initvals(struct b43_wldev *dev,
2058 const struct b43_iv *ivals,
2062 const struct b43_iv *iv;
2067 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2069 for (i = 0; i < count; i++) {
2070 if (array_size < sizeof(iv->offset_size))
2072 array_size -= sizeof(iv->offset_size);
2073 offset = be16_to_cpu(iv->offset_size);
2074 bit32 = !!(offset & B43_IV_32BIT);
2075 offset &= B43_IV_OFFSET_MASK;
2076 if (offset >= 0x1000)
2081 if (array_size < sizeof(iv->data.d32))
2083 array_size -= sizeof(iv->data.d32);
2085 value = be32_to_cpu(get_unaligned(&iv->data.d32));
2086 b43_write32(dev, offset, value);
2088 iv = (const struct b43_iv *)((const uint8_t *)iv +
2094 if (array_size < sizeof(iv->data.d16))
2096 array_size -= sizeof(iv->data.d16);
2098 value = be16_to_cpu(iv->data.d16);
2099 b43_write16(dev, offset, value);
2101 iv = (const struct b43_iv *)((const uint8_t *)iv +
2112 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2113 b43_print_fw_helptext(dev->wl, 1);
2118 static int b43_upload_initvals(struct b43_wldev *dev)
2120 const size_t hdr_len = sizeof(struct b43_fw_header);
2121 const struct b43_fw_header *hdr;
2122 struct b43_firmware *fw = &dev->fw;
2123 const struct b43_iv *ivals;
2127 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2128 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2129 count = be32_to_cpu(hdr->size);
2130 err = b43_write_initvals(dev, ivals, count,
2131 fw->initvals.data->size - hdr_len);
2134 if (fw->initvals_band.data) {
2135 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2136 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2137 count = be32_to_cpu(hdr->size);
2138 err = b43_write_initvals(dev, ivals, count,
2139 fw->initvals_band.data->size - hdr_len);
2148 /* Initialize the GPIOs
2149 * http://bcm-specs.sipsolutions.net/GPIO
2151 static int b43_gpio_init(struct b43_wldev *dev)
2153 struct ssb_bus *bus = dev->dev->bus;
2154 struct ssb_device *gpiodev, *pcidev = NULL;
2157 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2158 & ~B43_MACCTL_GPOUTSMSK);
2160 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2165 if (dev->dev->bus->chip_id == 0x4301) {
2169 if (0 /* FIXME: conditional unknown */ ) {
2170 b43_write16(dev, B43_MMIO_GPIO_MASK,
2171 b43_read16(dev, B43_MMIO_GPIO_MASK)
2176 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
2177 b43_write16(dev, B43_MMIO_GPIO_MASK,
2178 b43_read16(dev, B43_MMIO_GPIO_MASK)
2183 if (dev->dev->id.revision >= 2)
2184 mask |= 0x0010; /* FIXME: This is redundant. */
2186 #ifdef CONFIG_SSB_DRIVER_PCICORE
2187 pcidev = bus->pcicore.dev;
2189 gpiodev = bus->chipco.dev ? : pcidev;
2192 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2193 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2199 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2200 static void b43_gpio_cleanup(struct b43_wldev *dev)
2202 struct ssb_bus *bus = dev->dev->bus;
2203 struct ssb_device *gpiodev, *pcidev = NULL;
2205 #ifdef CONFIG_SSB_DRIVER_PCICORE
2206 pcidev = bus->pcicore.dev;
2208 gpiodev = bus->chipco.dev ? : pcidev;
2211 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2214 /* http://bcm-specs.sipsolutions.net/EnableMac */
2215 static void b43_mac_enable(struct b43_wldev *dev)
2217 dev->mac_suspended--;
2218 B43_WARN_ON(dev->mac_suspended < 0);
2219 if (dev->mac_suspended == 0) {
2220 b43_write32(dev, B43_MMIO_MACCTL,
2221 b43_read32(dev, B43_MMIO_MACCTL)
2222 | B43_MACCTL_ENABLED);
2223 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2224 B43_IRQ_MAC_SUSPENDED);
2226 b43_read32(dev, B43_MMIO_MACCTL);
2227 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2228 b43_power_saving_ctl_bits(dev, 0);
2230 /* Re-enable IRQs. */
2231 spin_lock_irq(&dev->wl->irq_lock);
2232 b43_interrupt_enable(dev, dev->irq_savedstate);
2233 spin_unlock_irq(&dev->wl->irq_lock);
2237 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2238 static void b43_mac_suspend(struct b43_wldev *dev)
2244 B43_WARN_ON(dev->mac_suspended < 0);
2246 if (dev->mac_suspended == 0) {
2247 /* Mask IRQs before suspending MAC. Otherwise
2248 * the MAC stays busy and won't suspend. */
2249 spin_lock_irq(&dev->wl->irq_lock);
2250 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
2251 spin_unlock_irq(&dev->wl->irq_lock);
2252 b43_synchronize_irq(dev);
2253 dev->irq_savedstate = tmp;
2255 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2256 b43_write32(dev, B43_MMIO_MACCTL,
2257 b43_read32(dev, B43_MMIO_MACCTL)
2258 & ~B43_MACCTL_ENABLED);
2259 /* force pci to flush the write */
2260 b43_read32(dev, B43_MMIO_MACCTL);
2261 for (i = 40; i; i--) {
2262 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2263 if (tmp & B43_IRQ_MAC_SUSPENDED)
2267 b43err(dev->wl, "MAC suspend failed\n");
2270 dev->mac_suspended++;
2273 static void b43_adjust_opmode(struct b43_wldev *dev)
2275 struct b43_wl *wl = dev->wl;
2279 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2280 /* Reset status to STA infrastructure mode. */
2281 ctl &= ~B43_MACCTL_AP;
2282 ctl &= ~B43_MACCTL_KEEP_CTL;
2283 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2284 ctl &= ~B43_MACCTL_KEEP_BAD;
2285 ctl &= ~B43_MACCTL_PROMISC;
2286 ctl &= ~B43_MACCTL_BEACPROMISC;
2287 ctl |= B43_MACCTL_INFRA;
2289 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2290 ctl |= B43_MACCTL_AP;
2291 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2292 ctl &= ~B43_MACCTL_INFRA;
2294 if (wl->filter_flags & FIF_CONTROL)
2295 ctl |= B43_MACCTL_KEEP_CTL;
2296 if (wl->filter_flags & FIF_FCSFAIL)
2297 ctl |= B43_MACCTL_KEEP_BAD;
2298 if (wl->filter_flags & FIF_PLCPFAIL)
2299 ctl |= B43_MACCTL_KEEP_BADPLCP;
2300 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2301 ctl |= B43_MACCTL_PROMISC;
2302 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2303 ctl |= B43_MACCTL_BEACPROMISC;
2305 /* Workaround: On old hardware the HW-MAC-address-filter
2306 * doesn't work properly, so always run promisc in filter
2307 * it in software. */
2308 if (dev->dev->id.revision <= 4)
2309 ctl |= B43_MACCTL_PROMISC;
2311 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2314 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2315 if (dev->dev->bus->chip_id == 0x4306 &&
2316 dev->dev->bus->chip_rev == 3)
2321 b43_write16(dev, 0x612, cfp_pretbtt);
2324 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2330 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2333 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2335 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2336 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2339 static void b43_rate_memory_init(struct b43_wldev *dev)
2341 switch (dev->phy.type) {
2345 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2346 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2347 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2348 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2349 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2350 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2351 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2352 if (dev->phy.type == B43_PHYTYPE_A)
2356 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2357 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2358 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2359 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2366 /* Set the TX-Antenna for management frames sent by firmware. */
2367 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2374 ant |= B43_TXH_PHY_ANT0;
2377 ant |= B43_TXH_PHY_ANT1;
2380 ant |= B43_TXH_PHY_ANT2;
2383 ant |= B43_TXH_PHY_ANT3;
2385 case B43_ANTENNA_AUTO:
2386 ant |= B43_TXH_PHY_ANT01AUTO;
2392 /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2395 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2396 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2397 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2399 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2400 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2401 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2402 /* For Probe Resposes */
2403 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2404 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2405 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2408 /* This is the opposite of b43_chip_init() */
2409 static void b43_chip_exit(struct b43_wldev *dev)
2411 b43_radio_turn_off(dev, 1);
2412 b43_gpio_cleanup(dev);
2413 /* firmware is released later */
2416 /* Initialize the chip
2417 * http://bcm-specs.sipsolutions.net/ChipInit
2419 static int b43_chip_init(struct b43_wldev *dev)
2421 struct b43_phy *phy = &dev->phy;
2423 u32 value32, macctl;
2426 /* Initialize the MAC control */
2427 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2429 macctl |= B43_MACCTL_GMODE;
2430 macctl |= B43_MACCTL_INFRA;
2431 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2433 err = b43_request_firmware(dev);
2436 err = b43_upload_microcode(dev);
2438 goto out; /* firmware is released later */
2440 err = b43_gpio_init(dev);
2442 goto out; /* firmware is released later */
2444 err = b43_upload_initvals(dev);
2446 goto err_gpio_clean;
2447 b43_radio_turn_on(dev);
2449 b43_write16(dev, 0x03E6, 0x0000);
2450 err = b43_phy_init(dev);
2454 /* Select initial Interference Mitigation. */
2455 tmp = phy->interfmode;
2456 phy->interfmode = B43_INTERFMODE_NONE;
2457 b43_radio_set_interference_mitigation(dev, tmp);
2459 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2460 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2462 if (phy->type == B43_PHYTYPE_B) {
2463 value16 = b43_read16(dev, 0x005E);
2465 b43_write16(dev, 0x005E, value16);
2467 b43_write32(dev, 0x0100, 0x01000000);
2468 if (dev->dev->id.revision < 5)
2469 b43_write32(dev, 0x010C, 0x01000000);
2471 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2472 & ~B43_MACCTL_INFRA);
2473 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2474 | B43_MACCTL_INFRA);
2476 /* Probe Response Timeout value */
2477 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2478 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2480 /* Initially set the wireless operation mode. */
2481 b43_adjust_opmode(dev);
2483 if (dev->dev->id.revision < 3) {
2484 b43_write16(dev, 0x060E, 0x0000);
2485 b43_write16(dev, 0x0610, 0x8000);
2486 b43_write16(dev, 0x0604, 0x0000);
2487 b43_write16(dev, 0x0606, 0x0200);
2489 b43_write32(dev, 0x0188, 0x80000000);
2490 b43_write32(dev, 0x018C, 0x02000000);
2492 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2493 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2494 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2495 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2496 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2497 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2498 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2500 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2501 value32 |= 0x00100000;
2502 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2504 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2505 dev->dev->bus->chipco.fast_pwrup_delay);
2508 b43dbg(dev->wl, "Chip initialized\n");
2513 b43_radio_turn_off(dev, 1);
2515 b43_gpio_cleanup(dev);
2519 static void b43_periodic_every120sec(struct b43_wldev *dev)
2521 struct b43_phy *phy = &dev->phy;
2523 if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2526 b43_mac_suspend(dev);
2527 b43_lo_g_measure(dev);
2528 b43_mac_enable(dev);
2529 if (b43_has_hardware_pctl(phy))
2530 b43_lo_g_ctl_mark_all_unused(dev);
2533 static void b43_periodic_every60sec(struct b43_wldev *dev)
2535 struct b43_phy *phy = &dev->phy;
2537 if (phy->type != B43_PHYTYPE_G)
2539 if (!b43_has_hardware_pctl(phy))
2540 b43_lo_g_ctl_mark_all_unused(dev);
2541 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
2542 b43_mac_suspend(dev);
2543 b43_calc_nrssi_slope(dev);
2544 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2545 u8 old_chan = phy->channel;
2547 /* VCO Calibration */
2549 b43_radio_selectchannel(dev, 1, 0);
2551 b43_radio_selectchannel(dev, 13, 0);
2552 b43_radio_selectchannel(dev, old_chan, 0);
2554 b43_mac_enable(dev);
2558 static void b43_periodic_every30sec(struct b43_wldev *dev)
2560 /* Update device statistics. */
2561 b43_calculate_link_quality(dev);
2564 static void b43_periodic_every15sec(struct b43_wldev *dev)
2566 struct b43_phy *phy = &dev->phy;
2568 if (phy->type == B43_PHYTYPE_G) {
2569 //TODO: update_aci_moving_average
2570 if (phy->aci_enable && phy->aci_wlan_automatic) {
2571 b43_mac_suspend(dev);
2572 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2573 if (0 /*TODO: bunch of conditions */ ) {
2574 b43_radio_set_interference_mitigation
2575 (dev, B43_INTERFMODE_MANUALWLAN);
2577 } else if (1 /*TODO*/) {
2579 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2580 b43_radio_set_interference_mitigation(dev,
2581 B43_INTERFMODE_NONE);
2585 b43_mac_enable(dev);
2586 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2588 //TODO: implement rev1 workaround
2591 b43_phy_xmitpower(dev); //FIXME: unless scanning?
2592 //TODO for APHY (temperature?)
2594 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2598 static void do_periodic_work(struct b43_wldev *dev)
2602 state = dev->periodic_state;
2604 b43_periodic_every120sec(dev);
2606 b43_periodic_every60sec(dev);
2608 b43_periodic_every30sec(dev);
2609 b43_periodic_every15sec(dev);
2612 /* Periodic work locking policy:
2613 * The whole periodic work handler is protected by
2614 * wl->mutex. If another lock is needed somewhere in the
2615 * pwork callchain, it's aquired in-place, where it's needed.
2617 static void b43_periodic_work_handler(struct work_struct *work)
2619 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2620 periodic_work.work);
2621 struct b43_wl *wl = dev->wl;
2622 unsigned long delay;
2624 mutex_lock(&wl->mutex);
2626 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2628 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2631 do_periodic_work(dev);
2633 dev->periodic_state++;
2635 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2636 delay = msecs_to_jiffies(50);
2638 delay = round_jiffies_relative(HZ * 15);
2639 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2641 mutex_unlock(&wl->mutex);
2644 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2646 struct delayed_work *work = &dev->periodic_work;
2648 dev->periodic_state = 0;
2649 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2650 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2653 /* Check if communication with the device works correctly. */
2654 static int b43_validate_chipaccess(struct b43_wldev *dev)
2658 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2660 /* Check for read/write and endianness problems. */
2661 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2662 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2664 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2665 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2668 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2670 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2671 /* The 32bit register shadows the two 16bit registers
2672 * with update sideeffects. Validate this. */
2673 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2674 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2675 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2677 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2680 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2682 v = b43_read32(dev, B43_MMIO_MACCTL);
2683 v |= B43_MACCTL_GMODE;
2684 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2689 b43err(dev->wl, "Failed to validate the chipaccess\n");
2693 static void b43_security_init(struct b43_wldev *dev)
2695 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2696 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2697 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2698 /* KTP is a word address, but we address SHM bytewise.
2699 * So multiply by two.
2702 if (dev->dev->id.revision >= 5) {
2703 /* Number of RCMTA address slots */
2704 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2706 b43_clear_keys(dev);
2709 static int b43_rng_read(struct hwrng *rng, u32 * data)
2711 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2712 unsigned long flags;
2714 /* Don't take wl->mutex here, as it could deadlock with
2715 * hwrng internal locking. It's not needed to take
2716 * wl->mutex here, anyway. */
2718 spin_lock_irqsave(&wl->irq_lock, flags);
2719 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2720 spin_unlock_irqrestore(&wl->irq_lock, flags);
2722 return (sizeof(u16));
2725 static void b43_rng_exit(struct b43_wl *wl, bool suspended)
2727 if (wl->rng_initialized)
2728 __hwrng_unregister(&wl->rng, suspended);
2731 static int b43_rng_init(struct b43_wl *wl)
2735 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2736 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2737 wl->rng.name = wl->rng_name;
2738 wl->rng.data_read = b43_rng_read;
2739 wl->rng.priv = (unsigned long)wl;
2740 wl->rng_initialized = 1;
2741 err = hwrng_register(&wl->rng);
2743 wl->rng_initialized = 0;
2744 b43err(wl, "Failed to register the random "
2745 "number generator (%d)\n", err);
2751 static int b43_op_tx(struct ieee80211_hw *hw,
2752 struct sk_buff *skb,
2753 struct ieee80211_tx_control *ctl)
2755 struct b43_wl *wl = hw_to_b43_wl(hw);
2756 struct b43_wldev *dev = wl->current_dev;
2759 if (unlikely(skb->len < 2 + 2 + 6)) {
2760 /* Too short, this can't be a valid frame. */
2763 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
2767 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2769 /* TX is done without a global lock. */
2770 if (b43_using_pio_transfers(dev))
2771 err = b43_pio_tx(dev, skb, ctl);
2773 err = b43_dma_tx(dev, skb, ctl);
2776 return NETDEV_TX_BUSY;
2777 return NETDEV_TX_OK;
2780 /* Locking: wl->irq_lock */
2781 static void b43_qos_params_upload(struct b43_wldev *dev,
2782 const struct ieee80211_tx_queue_params *p,
2785 u16 params[B43_NR_QOSPARAMS];
2786 int cw_min, cw_max, aifs, bslots, tmp;
2789 const u16 aCWmin = 0x0001;
2790 const u16 aCWmax = 0x03FF;
2792 /* Calculate the default values for the parameters, if needed. */
2793 switch (shm_offset) {
2795 aifs = (p->aifs == -1) ? 2 : p->aifs;
2796 cw_min = (p->cw_min == 0) ? ((aCWmin + 1) / 4 - 1) : p->cw_min;
2797 cw_max = (p->cw_max == 0) ? ((aCWmin + 1) / 2 - 1) : p->cw_max;
2800 aifs = (p->aifs == -1) ? 2 : p->aifs;
2801 cw_min = (p->cw_min == 0) ? ((aCWmin + 1) / 2 - 1) : p->cw_min;
2802 cw_max = (p->cw_max == 0) ? aCWmin : p->cw_max;
2804 case B43_QOS_BESTEFFORT:
2805 aifs = (p->aifs == -1) ? 3 : p->aifs;
2806 cw_min = (p->cw_min == 0) ? aCWmin : p->cw_min;
2807 cw_max = (p->cw_max == 0) ? aCWmax : p->cw_max;
2809 case B43_QOS_BACKGROUND:
2810 aifs = (p->aifs == -1) ? 7 : p->aifs;
2811 cw_min = (p->cw_min == 0) ? aCWmin : p->cw_min;
2812 cw_max = (p->cw_max == 0) ? aCWmax : p->cw_max;
2822 bslots = b43_read16(dev, B43_MMIO_RNG) % cw_min;
2824 memset(¶ms, 0, sizeof(params));
2826 params[B43_QOSPARAM_TXOP] = p->txop * 32;
2827 params[B43_QOSPARAM_CWMIN] = cw_min;
2828 params[B43_QOSPARAM_CWMAX] = cw_max;
2829 params[B43_QOSPARAM_CWCUR] = cw_min;
2830 params[B43_QOSPARAM_AIFS] = aifs;
2831 params[B43_QOSPARAM_BSLOTS] = bslots;
2832 params[B43_QOSPARAM_REGGAP] = bslots + aifs;
2834 for (i = 0; i < ARRAY_SIZE(params); i++) {
2835 if (i == B43_QOSPARAM_STATUS) {
2836 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
2837 shm_offset + (i * 2));
2838 /* Mark the parameters as updated. */
2840 b43_shm_write16(dev, B43_SHM_SHARED,
2841 shm_offset + (i * 2),
2844 b43_shm_write16(dev, B43_SHM_SHARED,
2845 shm_offset + (i * 2),
2851 /* Update the QOS parameters in hardware. */
2852 static void b43_qos_update(struct b43_wldev *dev)
2854 struct b43_wl *wl = dev->wl;
2855 struct b43_qos_params *params;
2856 unsigned long flags;
2859 /* Mapping of mac80211 queues to b43 SHM offsets. */
2860 static const u16 qos_shm_offsets[] = {
2861 [0] = B43_QOS_VOICE,
2862 [1] = B43_QOS_VIDEO,
2863 [2] = B43_QOS_BESTEFFORT,
2864 [3] = B43_QOS_BACKGROUND,
2866 BUILD_BUG_ON(ARRAY_SIZE(qos_shm_offsets) != ARRAY_SIZE(wl->qos_params));
2868 b43_mac_suspend(dev);
2869 spin_lock_irqsave(&wl->irq_lock, flags);
2871 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
2872 params = &(wl->qos_params[i]);
2873 if (params->need_hw_update) {
2874 b43_qos_params_upload(dev, &(params->p),
2875 qos_shm_offsets[i]);
2876 params->need_hw_update = 0;
2880 spin_unlock_irqrestore(&wl->irq_lock, flags);
2881 b43_mac_enable(dev);
2884 static void b43_qos_clear(struct b43_wl *wl)
2886 struct b43_qos_params *params;
2889 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
2890 params = &(wl->qos_params[i]);
2892 memset(&(params->p), 0, sizeof(params->p));
2893 params->p.aifs = -1;
2894 params->need_hw_update = 1;
2898 /* Initialize the core's QOS capabilities */
2899 static void b43_qos_init(struct b43_wldev *dev)
2901 struct b43_wl *wl = dev->wl;
2904 /* Upload the current QOS parameters. */
2905 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++)
2906 wl->qos_params[i].need_hw_update = 1;
2907 b43_qos_update(dev);
2909 /* Enable QOS support. */
2910 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
2911 b43_write16(dev, B43_MMIO_IFSCTL,
2912 b43_read16(dev, B43_MMIO_IFSCTL)
2913 | B43_MMIO_IFSCTL_USE_EDCF);
2916 static void b43_qos_update_work(struct work_struct *work)
2918 struct b43_wl *wl = container_of(work, struct b43_wl, qos_update_work);
2919 struct b43_wldev *dev;
2921 mutex_lock(&wl->mutex);
2922 dev = wl->current_dev;
2923 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED)))
2924 b43_qos_update(dev);
2925 mutex_unlock(&wl->mutex);
2928 static int b43_op_conf_tx(struct ieee80211_hw *hw,
2930 const struct ieee80211_tx_queue_params *params)
2932 struct b43_wl *wl = hw_to_b43_wl(hw);
2933 unsigned long flags;
2934 unsigned int queue = (unsigned int)_queue;
2935 struct b43_qos_params *p;
2937 if (queue >= ARRAY_SIZE(wl->qos_params)) {
2938 /* Queue not available or don't support setting
2939 * params on this queue. Return success to not
2940 * confuse mac80211. */
2944 spin_lock_irqsave(&wl->irq_lock, flags);
2945 p = &(wl->qos_params[queue]);
2946 memcpy(&(p->p), params, sizeof(p->p));
2947 p->need_hw_update = 1;
2948 spin_unlock_irqrestore(&wl->irq_lock, flags);
2950 queue_work(hw->workqueue, &wl->qos_update_work);
2955 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
2956 struct ieee80211_tx_queue_stats *stats)
2958 struct b43_wl *wl = hw_to_b43_wl(hw);
2959 struct b43_wldev *dev = wl->current_dev;
2960 unsigned long flags;
2965 spin_lock_irqsave(&wl->irq_lock, flags);
2966 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2967 if (b43_using_pio_transfers(dev))
2968 b43_pio_get_tx_stats(dev, stats);
2970 b43_dma_get_tx_stats(dev, stats);
2973 spin_unlock_irqrestore(&wl->irq_lock, flags);
2978 static int b43_op_get_stats(struct ieee80211_hw *hw,
2979 struct ieee80211_low_level_stats *stats)
2981 struct b43_wl *wl = hw_to_b43_wl(hw);
2982 unsigned long flags;
2984 spin_lock_irqsave(&wl->irq_lock, flags);
2985 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2986 spin_unlock_irqrestore(&wl->irq_lock, flags);
2991 static void b43_put_phy_into_reset(struct b43_wldev *dev)
2993 struct ssb_device *sdev = dev->dev;
2996 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2997 tmslow &= ~B43_TMSLOW_GMODE;
2998 tmslow |= B43_TMSLOW_PHYRESET;
2999 tmslow |= SSB_TMSLOW_FGC;
3000 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3003 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3004 tmslow &= ~SSB_TMSLOW_FGC;
3005 tmslow |= B43_TMSLOW_PHYRESET;
3006 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3010 static const char * band_to_string(enum ieee80211_band band)
3013 case IEEE80211_BAND_5GHZ:
3015 case IEEE80211_BAND_2GHZ:
3024 /* Expects wl->mutex locked */
3025 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3027 struct b43_wldev *up_dev = NULL;
3028 struct b43_wldev *down_dev;
3029 struct b43_wldev *d;
3034 /* Find a device and PHY which supports the band. */
3035 list_for_each_entry(d, &wl->devlist, list) {
3036 switch (chan->band) {
3037 case IEEE80211_BAND_5GHZ:
3038 if (d->phy.supports_5ghz) {
3043 case IEEE80211_BAND_2GHZ:
3044 if (d->phy.supports_2ghz) {
3057 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3058 band_to_string(chan->band));
3061 if ((up_dev == wl->current_dev) &&
3062 (!!wl->current_dev->phy.gmode == !!gmode)) {
3063 /* This device is already running. */
3066 b43dbg(wl, "Switching to %s-GHz band\n",
3067 band_to_string(chan->band));
3068 down_dev = wl->current_dev;
3070 prev_status = b43_status(down_dev);
3071 /* Shutdown the currently running core. */
3072 if (prev_status >= B43_STAT_STARTED)
3073 b43_wireless_core_stop(down_dev);
3074 if (prev_status >= B43_STAT_INITIALIZED)
3075 b43_wireless_core_exit(down_dev);
3077 if (down_dev != up_dev) {
3078 /* We switch to a different core, so we put PHY into
3079 * RESET on the old core. */
3080 b43_put_phy_into_reset(down_dev);
3083 /* Now start the new core. */
3084 up_dev->phy.gmode = gmode;
3085 if (prev_status >= B43_STAT_INITIALIZED) {
3086 err = b43_wireless_core_init(up_dev);
3088 b43err(wl, "Fatal: Could not initialize device for "
3089 "selected %s-GHz band\n",
3090 band_to_string(chan->band));
3094 if (prev_status >= B43_STAT_STARTED) {
3095 err = b43_wireless_core_start(up_dev);
3097 b43err(wl, "Fatal: Coult not start device for "
3098 "selected %s-GHz band\n",
3099 band_to_string(chan->band));
3100 b43_wireless_core_exit(up_dev);
3104 B43_WARN_ON(b43_status(up_dev) != prev_status);
3106 wl->current_dev = up_dev;
3110 /* Whoops, failed to init the new core. No core is operating now. */
3111 wl->current_dev = NULL;
3115 /* Check if the use of the antenna that ieee80211 told us to
3116 * use is possible. This will fall back to DEFAULT.
3117 * "antenna_nr" is the antenna identifier we got from ieee80211. */
3118 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
3123 if (antenna_nr == 0) {
3124 /* Zero means "use default antenna". That's always OK. */
3128 /* Get the mask of available antennas. */
3130 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
3132 antenna_mask = dev->dev->bus->sprom.ant_available_a;
3134 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
3135 /* This antenna is not available. Fall back to default. */
3142 static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
3144 antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
3146 case 0: /* default/diversity */
3147 return B43_ANTENNA_DEFAULT;
3148 case 1: /* Antenna 0 */
3149 return B43_ANTENNA0;
3150 case 2: /* Antenna 1 */
3151 return B43_ANTENNA1;
3152 case 3: /* Antenna 2 */
3153 return B43_ANTENNA2;
3154 case 4: /* Antenna 3 */
3155 return B43_ANTENNA3;
3157 return B43_ANTENNA_DEFAULT;
3161 static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
3163 struct b43_wl *wl = hw_to_b43_wl(hw);
3164 struct b43_wldev *dev;
3165 struct b43_phy *phy;
3166 unsigned long flags;
3171 mutex_lock(&wl->mutex);
3173 /* Switch the band (if necessary). This might change the active core. */
3174 err = b43_switch_band(wl, conf->channel);
3176 goto out_unlock_mutex;
3177 dev = wl->current_dev;
3180 /* Disable IRQs while reconfiguring the device.
3181 * This makes it possible to drop the spinlock throughout
3182 * the reconfiguration process. */
3183 spin_lock_irqsave(&wl->irq_lock, flags);
3184 if (b43_status(dev) < B43_STAT_STARTED) {
3185 spin_unlock_irqrestore(&wl->irq_lock, flags);
3186 goto out_unlock_mutex;
3188 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
3189 spin_unlock_irqrestore(&wl->irq_lock, flags);
3190 b43_synchronize_irq(dev);
3192 /* Switch to the requested channel.
3193 * The firmware takes care of races with the TX handler. */
3194 if (conf->channel->hw_value != phy->channel)
3195 b43_radio_selectchannel(dev, conf->channel->hw_value, 0);
3197 /* Enable/Disable ShortSlot timing. */
3198 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
3200 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
3201 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
3202 b43_short_slot_timing_enable(dev);
3204 b43_short_slot_timing_disable(dev);
3207 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3209 /* Adjust the desired TX power level. */
3210 if (conf->power_level != 0) {
3211 if (conf->power_level != phy->power_level) {
3212 phy->power_level = conf->power_level;
3213 b43_phy_xmitpower(dev);
3217 /* Antennas for RX and management frame TX. */
3218 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
3219 b43_mgmtframe_txantenna(dev, antenna);
3220 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
3221 b43_set_rx_antenna(dev, antenna);
3223 /* Update templates for AP mode. */
3224 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
3225 b43_set_beacon_int(dev, conf->beacon_int);
3227 if (!!conf->radio_enabled != phy->radio_on) {
3228 if (conf->radio_enabled) {
3229 b43_radio_turn_on(dev);
3230 b43info(dev->wl, "Radio turned on by software\n");
3231 if (!dev->radio_hw_enable) {
3232 b43info(dev->wl, "The hardware RF-kill button "
3233 "still turns the radio physically off. "
3234 "Press the button to turn it on.\n");
3237 b43_radio_turn_off(dev, 0);
3238 b43info(dev->wl, "Radio turned off by software\n");
3242 spin_lock_irqsave(&wl->irq_lock, flags);
3243 b43_interrupt_enable(dev, savedirqs);
3245 spin_unlock_irqrestore(&wl->irq_lock, flags);
3247 mutex_unlock(&wl->mutex);
3252 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3253 const u8 *local_addr, const u8 *addr,
3254 struct ieee80211_key_conf *key)
3256 struct b43_wl *wl = hw_to_b43_wl(hw);
3257 struct b43_wldev *dev;
3258 unsigned long flags;
3262 DECLARE_MAC_BUF(mac);
3264 if (modparam_nohwcrypt)
3265 return -ENOSPC; /* User disabled HW-crypto */
3267 mutex_lock(&wl->mutex);
3268 spin_lock_irqsave(&wl->irq_lock, flags);
3270 dev = wl->current_dev;
3272 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3278 if (key->keylen == 5)
3279 algorithm = B43_SEC_ALGO_WEP40;
3281 algorithm = B43_SEC_ALGO_WEP104;
3284 algorithm = B43_SEC_ALGO_TKIP;
3287 algorithm = B43_SEC_ALGO_AES;
3293 index = (u8) (key->keyidx);
3299 if (algorithm == B43_SEC_ALGO_TKIP) {
3300 /* FIXME: No TKIP hardware encryption for now. */
3305 if (is_broadcast_ether_addr(addr)) {
3306 /* addr is FF:FF:FF:FF:FF:FF for default keys */
3307 err = b43_key_write(dev, index, algorithm,
3308 key->key, key->keylen, NULL, key);
3311 * either pairwise key or address is 00:00:00:00:00:00
3312 * for transmit-only keys
3314 err = b43_key_write(dev, -1, algorithm,
3315 key->key, key->keylen, addr, key);
3320 if (algorithm == B43_SEC_ALGO_WEP40 ||
3321 algorithm == B43_SEC_ALGO_WEP104) {
3322 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3325 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3327 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3330 err = b43_key_clear(dev, key->hw_key_idx);
3339 spin_unlock_irqrestore(&wl->irq_lock, flags);
3340 mutex_unlock(&wl->mutex);
3342 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
3344 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
3345 print_mac(mac, addr));
3350 static void b43_op_configure_filter(struct ieee80211_hw *hw,
3351 unsigned int changed, unsigned int *fflags,
3352 int mc_count, struct dev_addr_list *mc_list)
3354 struct b43_wl *wl = hw_to_b43_wl(hw);
3355 struct b43_wldev *dev = wl->current_dev;
3356 unsigned long flags;
3363 spin_lock_irqsave(&wl->irq_lock, flags);
3364 *fflags &= FIF_PROMISC_IN_BSS |
3370 FIF_BCN_PRBRESP_PROMISC;
3372 changed &= FIF_PROMISC_IN_BSS |
3378 FIF_BCN_PRBRESP_PROMISC;
3380 wl->filter_flags = *fflags;
3382 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3383 b43_adjust_opmode(dev);
3384 spin_unlock_irqrestore(&wl->irq_lock, flags);
3387 static int b43_op_config_interface(struct ieee80211_hw *hw,
3388 struct ieee80211_vif *vif,
3389 struct ieee80211_if_conf *conf)
3391 struct b43_wl *wl = hw_to_b43_wl(hw);
3392 struct b43_wldev *dev = wl->current_dev;
3393 unsigned long flags;
3397 mutex_lock(&wl->mutex);
3398 spin_lock_irqsave(&wl->irq_lock, flags);
3399 B43_WARN_ON(wl->vif != vif);
3401 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3403 memset(wl->bssid, 0, ETH_ALEN);
3404 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3405 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
3406 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
3407 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
3409 b43_update_templates(wl, conf->beacon);
3411 b43_write_mac_bssid_templates(dev);
3413 spin_unlock_irqrestore(&wl->irq_lock, flags);
3414 mutex_unlock(&wl->mutex);
3419 /* Locking: wl->mutex */
3420 static void b43_wireless_core_stop(struct b43_wldev *dev)
3422 struct b43_wl *wl = dev->wl;
3423 unsigned long flags;
3425 if (b43_status(dev) < B43_STAT_STARTED)
3428 /* Disable and sync interrupts. We must do this before than
3429 * setting the status to INITIALIZED, as the interrupt handler
3430 * won't care about IRQs then. */
3431 spin_lock_irqsave(&wl->irq_lock, flags);
3432 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3433 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3434 spin_unlock_irqrestore(&wl->irq_lock, flags);
3435 b43_synchronize_irq(dev);
3437 b43_set_status(dev, B43_STAT_INITIALIZED);
3440 mutex_unlock(&wl->mutex);
3441 /* Must unlock as it would otherwise deadlock. No races here.
3442 * Cancel the possibly running self-rearming periodic work. */
3443 cancel_delayed_work_sync(&dev->periodic_work);
3444 mutex_lock(&wl->mutex);
3446 ieee80211_stop_queues(wl->hw); //FIXME this could cause a deadlock, as mac80211 seems buggy.
3448 b43_mac_suspend(dev);
3449 free_irq(dev->dev->irq, dev);
3450 b43dbg(wl, "Wireless interface stopped\n");
3453 /* Locking: wl->mutex */
3454 static int b43_wireless_core_start(struct b43_wldev *dev)
3458 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3460 drain_txstatus_queue(dev);
3461 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3462 IRQF_SHARED, KBUILD_MODNAME, dev);
3464 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3468 /* We are ready to run. */
3469 b43_set_status(dev, B43_STAT_STARTED);
3471 /* Start data flow (TX/RX). */
3472 b43_mac_enable(dev);
3473 b43_interrupt_enable(dev, dev->irq_savedstate);
3474 ieee80211_start_queues(dev->wl->hw);
3476 /* Start maintainance work */
3477 b43_periodic_tasks_setup(dev);
3479 b43dbg(dev->wl, "Wireless interface started\n");
3484 /* Get PHY and RADIO versioning numbers */
3485 static int b43_phy_versioning(struct b43_wldev *dev)
3487 struct b43_phy *phy = &dev->phy;
3495 int unsupported = 0;
3497 /* Get PHY versioning */
3498 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3499 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3500 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3501 phy_rev = (tmp & B43_PHYVER_VERSION);
3508 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3516 #ifdef CONFIG_B43_NPHY
3526 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3527 "(Analog %u, Type %u, Revision %u)\n",
3528 analog_type, phy_type, phy_rev);
3531 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3532 analog_type, phy_type, phy_rev);
3534 /* Get RADIO versioning */
3535 if (dev->dev->bus->chip_id == 0x4317) {
3536 if (dev->dev->bus->chip_rev == 0)
3538 else if (dev->dev->bus->chip_rev == 1)
3543 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3544 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3545 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3546 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
3548 radio_manuf = (tmp & 0x00000FFF);
3549 radio_ver = (tmp & 0x0FFFF000) >> 12;
3550 radio_rev = (tmp & 0xF0000000) >> 28;
3551 if (radio_manuf != 0x17F /* Broadcom */)
3555 if (radio_ver != 0x2060)
3559 if (radio_manuf != 0x17F)
3563 if ((radio_ver & 0xFFF0) != 0x2050)
3567 if (radio_ver != 0x2050)
3571 if (radio_ver != 0x2055)
3578 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3579 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3580 radio_manuf, radio_ver, radio_rev);
3583 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3584 radio_manuf, radio_ver, radio_rev);
3586 phy->radio_manuf = radio_manuf;
3587 phy->radio_ver = radio_ver;
3588 phy->radio_rev = radio_rev;
3590 phy->analog = analog_type;
3591 phy->type = phy_type;
3597 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3598 struct b43_phy *phy)
3600 struct b43_txpower_lo_control *lo;
3603 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3604 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3606 phy->aci_enable = 0;
3607 phy->aci_wlan_automatic = 0;
3608 phy->aci_hw_rssi = 0;
3610 phy->radio_off_context.valid = 0;
3612 lo = phy->lo_control;
3614 memset(lo, 0, sizeof(*(phy->lo_control)));
3618 phy->max_lb_gain = 0;
3619 phy->trsw_rx_gain = 0;
3620 phy->txpwr_offset = 0;
3623 phy->nrssislope = 0;
3624 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3625 phy->nrssi[i] = -1000;
3626 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3627 phy->nrssi_lt[i] = i;
3629 phy->lofcal = 0xFFFF;
3630 phy->initval = 0xFFFF;
3632 phy->interfmode = B43_INTERFMODE_NONE;
3633 phy->channel = 0xFF;
3635 phy->hardware_power_control = !!modparam_hwpctl;
3637 /* PHY TX errors counter. */
3638 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3640 /* OFDM-table address caching. */
3641 phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
3644 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3648 /* Assume the radio is enabled. If it's not enabled, the state will
3649 * immediately get fixed on the first periodic work run. */
3650 dev->radio_hw_enable = 1;
3653 memset(&dev->stats, 0, sizeof(dev->stats));
3655 setup_struct_phy_for_init(dev, &dev->phy);
3657 /* IRQ related flags */
3658 dev->irq_reason = 0;
3659 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3660 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3662 dev->mac_suspended = 1;
3664 /* Noise calculation context */
3665 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3668 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3670 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3673 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
3675 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3678 hf = b43_hf_read(dev);
3679 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
3680 hf |= B43_HF_BTCOEXALT;
3682 hf |= B43_HF_BTCOEX;
3683 b43_hf_write(dev, hf);
3687 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3691 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3693 #ifdef CONFIG_SSB_DRIVER_PCICORE
3694 struct ssb_bus *bus = dev->dev->bus;
3697 if (bus->pcicore.dev &&
3698 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3699 bus->pcicore.dev->id.revision <= 5) {
3700 /* IMCFGLO timeouts workaround. */
3701 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3702 tmp &= ~SSB_IMCFGLO_REQTO;
3703 tmp &= ~SSB_IMCFGLO_SERTO;
3704 switch (bus->bustype) {
3705 case SSB_BUSTYPE_PCI:
3706 case SSB_BUSTYPE_PCMCIA:
3709 case SSB_BUSTYPE_SSB:
3713 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3715 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3718 /* Write the short and long frame retry limit values. */
3719 static void b43_set_retry_limits(struct b43_wldev *dev,
3720 unsigned int short_retry,
3721 unsigned int long_retry)
3723 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3724 * the chip-internal counter. */
3725 short_retry = min(short_retry, (unsigned int)0xF);
3726 long_retry = min(long_retry, (unsigned int)0xF);
3728 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3730 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3734 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
3738 /* The time value is in microseconds. */
3739 if (dev->phy.type == B43_PHYTYPE_A)
3743 if ((dev->wl->if_type == IEEE80211_IF_TYPE_IBSS) || idle)
3745 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
3746 pu_delay = max(pu_delay, (u16)2400);
3748 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
3751 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
3752 static void b43_set_pretbtt(struct b43_wldev *dev)
3756 /* The time value is in microseconds. */
3757 if (dev->wl->if_type == IEEE80211_IF_TYPE_IBSS) {
3760 if (dev->phy.type == B43_PHYTYPE_A)
3765 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
3766 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
3769 /* Shutdown a wireless core */
3770 /* Locking: wl->mutex */
3771 static void b43_wireless_core_exit(struct b43_wldev *dev)
3773 struct b43_phy *phy = &dev->phy;
3776 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3777 if (b43_status(dev) != B43_STAT_INITIALIZED)
3779 b43_set_status(dev, B43_STAT_UNINIT);
3781 /* Stop the microcode PSM. */
3782 macctl = b43_read32(dev, B43_MMIO_MACCTL);
3783 macctl &= ~B43_MACCTL_PSM_RUN;
3784 macctl |= B43_MACCTL_PSM_JMP0;
3785 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3787 if (!dev->suspend_in_progress) {
3789 b43_rng_exit(dev->wl, false);
3794 b43_radio_turn_off(dev, 1);
3795 b43_switch_analog(dev, 0);
3796 if (phy->dyn_tssi_tbl)
3797 kfree(phy->tssi2dbm);
3798 kfree(phy->lo_control);
3799 phy->lo_control = NULL;
3800 if (dev->wl->current_beacon) {
3801 dev_kfree_skb_any(dev->wl->current_beacon);
3802 dev->wl->current_beacon = NULL;
3805 ssb_device_disable(dev->dev, 0);
3806 ssb_bus_may_powerdown(dev->dev->bus);
3809 /* Initialize a wireless core */
3810 static int b43_wireless_core_init(struct b43_wldev *dev)
3812 struct b43_wl *wl = dev->wl;
3813 struct ssb_bus *bus = dev->dev->bus;
3814 struct ssb_sprom *sprom = &bus->sprom;
3815 struct b43_phy *phy = &dev->phy;
3819 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3821 err = ssb_bus_powerup(bus, 0);
3824 if (!ssb_device_is_enabled(dev->dev)) {
3825 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3826 b43_wireless_core_reset(dev, tmp);
3829 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3831 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3832 if (!phy->lo_control) {
3837 setup_struct_wldev_for_init(dev);
3839 err = b43_phy_init_tssi2dbm_table(dev);
3841 goto err_kfree_lo_control;
3843 /* Enable IRQ routing to this device. */
3844 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3846 b43_imcfglo_timeouts_workaround(dev);
3847 b43_bluetooth_coext_disable(dev);
3848 b43_phy_early_init(dev);
3849 err = b43_chip_init(dev);
3851 goto err_kfree_tssitbl;
3852 b43_shm_write16(dev, B43_SHM_SHARED,
3853 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3854 hf = b43_hf_read(dev);
3855 if (phy->type == B43_PHYTYPE_G) {
3859 if (sprom->boardflags_lo & B43_BFL_PACTRL)
3860 hf |= B43_HF_OFDMPABOOST;
3861 } else if (phy->type == B43_PHYTYPE_B) {
3863 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3866 b43_hf_write(dev, hf);
3868 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
3869 B43_DEFAULT_LONG_RETRY_LIMIT);
3870 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3871 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3873 /* Disable sending probe responses from firmware.
3874 * Setting the MaxTime to one usec will always trigger
3875 * a timeout, so we never send any probe resp.
3876 * A timeout of zero is infinite. */
3877 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3879 b43_rate_memory_init(dev);
3881 /* Minimum Contention Window */
3882 if (phy->type == B43_PHYTYPE_B) {
3883 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3885 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3887 /* Maximum Contention Window */
3888 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3890 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) {
3891 dev->__using_pio_transfers = 1;
3892 err = b43_pio_init(dev);
3894 dev->__using_pio_transfers = 0;
3895 err = b43_dma_init(dev);
3900 b43_set_synth_pu_delay(dev, 1);
3901 b43_bluetooth_coext_enable(dev);
3903 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
3904 b43_upload_card_macaddress(dev);
3905 b43_security_init(dev);
3906 if (!dev->suspend_in_progress)
3909 b43_set_status(dev, B43_STAT_INITIALIZED);
3911 if (!dev->suspend_in_progress)
3919 if (phy->dyn_tssi_tbl)
3920 kfree(phy->tssi2dbm);
3921 err_kfree_lo_control:
3922 kfree(phy->lo_control);
3923 phy->lo_control = NULL;
3925 ssb_bus_may_powerdown(bus);
3926 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3930 static int b43_op_add_interface(struct ieee80211_hw *hw,
3931 struct ieee80211_if_init_conf *conf)
3933 struct b43_wl *wl = hw_to_b43_wl(hw);
3934 struct b43_wldev *dev;
3935 unsigned long flags;
3936 int err = -EOPNOTSUPP;
3938 /* TODO: allow WDS/AP devices to coexist */
3940 if (conf->type != IEEE80211_IF_TYPE_AP &&
3941 conf->type != IEEE80211_IF_TYPE_STA &&
3942 conf->type != IEEE80211_IF_TYPE_WDS &&
3943 conf->type != IEEE80211_IF_TYPE_IBSS)
3946 mutex_lock(&wl->mutex);
3948 goto out_mutex_unlock;
3950 b43dbg(wl, "Adding Interface type %d\n", conf->type);
3952 dev = wl->current_dev;
3954 wl->vif = conf->vif;
3955 wl->if_type = conf->type;
3956 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3958 spin_lock_irqsave(&wl->irq_lock, flags);
3959 b43_adjust_opmode(dev);
3960 b43_set_pretbtt(dev);
3961 b43_set_synth_pu_delay(dev, 0);
3962 b43_upload_card_macaddress(dev);
3963 spin_unlock_irqrestore(&wl->irq_lock, flags);
3967 mutex_unlock(&wl->mutex);
3972 static void b43_op_remove_interface(struct ieee80211_hw *hw,
3973 struct ieee80211_if_init_conf *conf)
3975 struct b43_wl *wl = hw_to_b43_wl(hw);
3976 struct b43_wldev *dev = wl->current_dev;
3977 unsigned long flags;
3979 b43dbg(wl, "Removing Interface type %d\n", conf->type);
3981 mutex_lock(&wl->mutex);
3983 B43_WARN_ON(!wl->operating);
3984 B43_WARN_ON(wl->vif != conf->vif);
3989 spin_lock_irqsave(&wl->irq_lock, flags);
3990 b43_adjust_opmode(dev);
3991 memset(wl->mac_addr, 0, ETH_ALEN);
3992 b43_upload_card_macaddress(dev);
3993 spin_unlock_irqrestore(&wl->irq_lock, flags);
3995 mutex_unlock(&wl->mutex);
3998 static int b43_op_start(struct ieee80211_hw *hw)
4000 struct b43_wl *wl = hw_to_b43_wl(hw);
4001 struct b43_wldev *dev = wl->current_dev;
4004 bool do_rfkill_exit = 0;
4006 /* Kill all old instance specific information to make sure
4007 * the card won't use it in the short timeframe between start
4008 * and mac80211 reconfiguring it. */
4009 memset(wl->bssid, 0, ETH_ALEN);
4010 memset(wl->mac_addr, 0, ETH_ALEN);
4011 wl->filter_flags = 0;
4012 wl->radiotap_enabled = 0;
4015 /* First register RFkill.
4016 * LEDs that are registered later depend on it. */
4017 b43_rfkill_init(dev);
4019 mutex_lock(&wl->mutex);
4021 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4022 err = b43_wireless_core_init(dev);
4025 goto out_mutex_unlock;
4030 if (b43_status(dev) < B43_STAT_STARTED) {
4031 err = b43_wireless_core_start(dev);
4034 b43_wireless_core_exit(dev);
4036 goto out_mutex_unlock;
4041 mutex_unlock(&wl->mutex);
4044 b43_rfkill_exit(dev);
4049 static void b43_op_stop(struct ieee80211_hw *hw)
4051 struct b43_wl *wl = hw_to_b43_wl(hw);
4052 struct b43_wldev *dev = wl->current_dev;
4054 b43_rfkill_exit(dev);
4055 cancel_work_sync(&(wl->qos_update_work));
4056 cancel_work_sync(&(wl->beacon_update_trigger));
4058 mutex_lock(&wl->mutex);
4059 if (b43_status(dev) >= B43_STAT_STARTED)
4060 b43_wireless_core_stop(dev);
4061 b43_wireless_core_exit(dev);
4062 mutex_unlock(&wl->mutex);
4065 static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
4066 u32 short_retry_limit, u32 long_retry_limit)
4068 struct b43_wl *wl = hw_to_b43_wl(hw);
4069 struct b43_wldev *dev;
4072 mutex_lock(&wl->mutex);
4073 dev = wl->current_dev;
4074 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
4078 b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
4080 mutex_unlock(&wl->mutex);
4085 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set)
4087 struct b43_wl *wl = hw_to_b43_wl(hw);
4088 struct sk_buff *beacon;
4089 unsigned long flags;
4091 /* We could modify the existing beacon and set the aid bit in
4092 * the TIM field, but that would probably require resizing and
4093 * moving of data within the beacon template.
4094 * Simply request a new beacon and let mac80211 do the hard work. */
4095 beacon = ieee80211_beacon_get(hw, wl->vif, NULL);
4096 if (unlikely(!beacon))
4098 spin_lock_irqsave(&wl->irq_lock, flags);
4099 b43_update_templates(wl, beacon);
4100 spin_unlock_irqrestore(&wl->irq_lock, flags);
4105 static int b43_op_ibss_beacon_update(struct ieee80211_hw *hw,
4106 struct sk_buff *beacon,
4107 struct ieee80211_tx_control *ctl)
4109 struct b43_wl *wl = hw_to_b43_wl(hw);
4110 unsigned long flags;
4112 spin_lock_irqsave(&wl->irq_lock, flags);
4113 b43_update_templates(wl, beacon);
4114 spin_unlock_irqrestore(&wl->irq_lock, flags);
4119 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4120 struct ieee80211_vif *vif,
4121 enum sta_notify_cmd notify_cmd,
4124 struct b43_wl *wl = hw_to_b43_wl(hw);
4126 B43_WARN_ON(!vif || wl->vif != vif);
4129 static const struct ieee80211_ops b43_hw_ops = {
4131 .conf_tx = b43_op_conf_tx,
4132 .add_interface = b43_op_add_interface,
4133 .remove_interface = b43_op_remove_interface,
4134 .config = b43_op_config,
4135 .config_interface = b43_op_config_interface,
4136 .configure_filter = b43_op_configure_filter,
4137 .set_key = b43_op_set_key,
4138 .get_stats = b43_op_get_stats,
4139 .get_tx_stats = b43_op_get_tx_stats,
4140 .start = b43_op_start,
4141 .stop = b43_op_stop,
4142 .set_retry_limit = b43_op_set_retry_limit,
4143 .set_tim = b43_op_beacon_set_tim,
4144 .beacon_update = b43_op_ibss_beacon_update,
4145 .sta_notify = b43_op_sta_notify,
4148 /* Hard-reset the chip. Do not call this directly.
4149 * Use b43_controller_restart()
4151 static void b43_chip_reset(struct work_struct *work)
4153 struct b43_wldev *dev =
4154 container_of(work, struct b43_wldev, restart_work);
4155 struct b43_wl *wl = dev->wl;
4159 mutex_lock(&wl->mutex);
4161 prev_status = b43_status(dev);
4162 /* Bring the device down... */
4163 if (prev_status >= B43_STAT_STARTED)
4164 b43_wireless_core_stop(dev);
4165 if (prev_status >= B43_STAT_INITIALIZED)
4166 b43_wireless_core_exit(dev);
4168 /* ...and up again. */
4169 if (prev_status >= B43_STAT_INITIALIZED) {
4170 err = b43_wireless_core_init(dev);
4174 if (prev_status >= B43_STAT_STARTED) {
4175 err = b43_wireless_core_start(dev);
4177 b43_wireless_core_exit(dev);
4182 mutex_unlock(&wl->mutex);
4184 b43err(wl, "Controller restart FAILED\n");
4186 b43info(wl, "Controller restarted\n");
4189 static int b43_setup_bands(struct b43_wldev *dev,
4190 bool have_2ghz_phy, bool have_5ghz_phy)
4192 struct ieee80211_hw *hw = dev->wl->hw;
4195 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4196 if (dev->phy.type == B43_PHYTYPE_N) {
4198 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4201 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4204 dev->phy.supports_2ghz = have_2ghz_phy;
4205 dev->phy.supports_5ghz = have_5ghz_phy;
4210 static void b43_wireless_core_detach(struct b43_wldev *dev)
4212 /* We release firmware that late to not be required to re-request
4213 * is all the time when we reinit the core. */
4214 b43_release_firmware(dev);
4217 static int b43_wireless_core_attach(struct b43_wldev *dev)
4219 struct b43_wl *wl = dev->wl;
4220 struct ssb_bus *bus = dev->dev->bus;
4221 struct pci_dev *pdev = bus->host_pci;
4223 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
4226 /* Do NOT do any device initialization here.
4227 * Do it in wireless_core_init() instead.
4228 * This function is for gathering basic information about the HW, only.
4229 * Also some structs may be set up here. But most likely you want to have
4230 * that in core_init(), too.
4233 err = ssb_bus_powerup(bus, 0);
4235 b43err(wl, "Bus powerup failed\n");
4238 /* Get the PHY type. */
4239 if (dev->dev->id.revision >= 5) {
4242 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
4243 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4244 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
4248 dev->phy.gmode = have_2ghz_phy;
4249 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4250 b43_wireless_core_reset(dev, tmp);
4252 err = b43_phy_versioning(dev);
4255 /* Check if this device supports multiband. */
4257 (pdev->device != 0x4312 &&
4258 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4259 /* No multiband support. */
4262 switch (dev->phy.type) {
4274 if (dev->phy.type == B43_PHYTYPE_A) {
4276 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4280 dev->phy.gmode = have_2ghz_phy;
4281 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4282 b43_wireless_core_reset(dev, tmp);
4284 err = b43_validate_chipaccess(dev);
4287 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
4291 /* Now set some default "current_dev" */
4292 if (!wl->current_dev)
4293 wl->current_dev = dev;
4294 INIT_WORK(&dev->restart_work, b43_chip_reset);
4296 b43_radio_turn_off(dev, 1);
4297 b43_switch_analog(dev, 0);
4298 ssb_device_disable(dev->dev, 0);
4299 ssb_bus_may_powerdown(bus);
4305 ssb_bus_may_powerdown(bus);
4309 static void b43_one_core_detach(struct ssb_device *dev)
4311 struct b43_wldev *wldev;
4314 wldev = ssb_get_drvdata(dev);
4316 cancel_work_sync(&wldev->restart_work);
4317 b43_debugfs_remove_device(wldev);
4318 b43_wireless_core_detach(wldev);
4319 list_del(&wldev->list);
4321 ssb_set_drvdata(dev, NULL);
4325 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4327 struct b43_wldev *wldev;
4328 struct pci_dev *pdev;
4331 if (!list_empty(&wl->devlist)) {
4332 /* We are not the first core on this chip. */
4333 pdev = dev->bus->host_pci;
4334 /* Only special chips support more than one wireless
4335 * core, although some of the other chips have more than
4336 * one wireless core as well. Check for this and
4340 ((pdev->device != 0x4321) &&
4341 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4342 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4347 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4353 b43_set_status(wldev, B43_STAT_UNINIT);
4354 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4355 tasklet_init(&wldev->isr_tasklet,
4356 (void (*)(unsigned long))b43_interrupt_tasklet,
4357 (unsigned long)wldev);
4358 INIT_LIST_HEAD(&wldev->list);
4360 err = b43_wireless_core_attach(wldev);
4362 goto err_kfree_wldev;
4364 list_add(&wldev->list, &wl->devlist);
4366 ssb_set_drvdata(dev, wldev);
4367 b43_debugfs_add_device(wldev);
4377 static void b43_sprom_fixup(struct ssb_bus *bus)
4379 /* boardflags workarounds */
4380 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4381 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
4382 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
4383 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4384 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
4385 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
4388 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4390 struct ieee80211_hw *hw = wl->hw;
4392 ssb_set_devtypedata(dev, NULL);
4393 ieee80211_free_hw(hw);
4396 static int b43_wireless_init(struct ssb_device *dev)
4398 struct ssb_sprom *sprom = &dev->bus->sprom;
4399 struct ieee80211_hw *hw;
4403 b43_sprom_fixup(dev->bus);
4405 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4407 b43err(NULL, "Could not allocate ieee80211 device\n");
4412 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4413 IEEE80211_HW_RX_INCLUDES_FCS;
4414 hw->max_signal = 100;
4415 hw->max_rssi = -110;
4416 hw->max_noise = -110;
4417 hw->queues = b43_modparam_qos ? 4 : 1;
4418 SET_IEEE80211_DEV(hw, dev->dev);
4419 if (is_valid_ether_addr(sprom->et1mac))
4420 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
4422 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
4424 /* Get and initialize struct b43_wl */
4425 wl = hw_to_b43_wl(hw);
4426 memset(wl, 0, sizeof(*wl));
4428 spin_lock_init(&wl->irq_lock);
4429 spin_lock_init(&wl->leds_lock);
4430 spin_lock_init(&wl->shm_lock);
4431 mutex_init(&wl->mutex);
4432 INIT_LIST_HEAD(&wl->devlist);
4433 INIT_WORK(&wl->qos_update_work, b43_qos_update_work);
4434 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
4436 ssb_set_devtypedata(dev, wl);
4437 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
4443 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4449 wl = ssb_get_devtypedata(dev);
4451 /* Probing the first core. Must setup common struct b43_wl */
4453 err = b43_wireless_init(dev);
4456 wl = ssb_get_devtypedata(dev);
4459 err = b43_one_core_attach(dev, wl);
4461 goto err_wireless_exit;
4464 err = ieee80211_register_hw(wl->hw);
4466 goto err_one_core_detach;
4472 err_one_core_detach:
4473 b43_one_core_detach(dev);
4476 b43_wireless_exit(dev, wl);
4480 static void b43_remove(struct ssb_device *dev)
4482 struct b43_wl *wl = ssb_get_devtypedata(dev);
4483 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4486 if (wl->current_dev == wldev)
4487 ieee80211_unregister_hw(wl->hw);
4489 b43_one_core_detach(dev);
4491 if (list_empty(&wl->devlist)) {
4492 /* Last core on the chip unregistered.
4493 * We can destroy common struct b43_wl.
4495 b43_wireless_exit(dev, wl);
4499 /* Perform a hardware reset. This can be called from any context. */
4500 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4502 /* Must avoid requeueing, if we are in shutdown. */
4503 if (b43_status(dev) < B43_STAT_INITIALIZED)
4505 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4506 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4511 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4513 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4514 struct b43_wl *wl = wldev->wl;
4516 b43dbg(wl, "Suspending...\n");
4518 mutex_lock(&wl->mutex);
4519 wldev->suspend_in_progress = true;
4520 wldev->suspend_init_status = b43_status(wldev);
4521 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4522 b43_wireless_core_stop(wldev);
4523 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4524 b43_wireless_core_exit(wldev);
4525 mutex_unlock(&wl->mutex);
4527 b43dbg(wl, "Device suspended.\n");
4532 static int b43_resume(struct ssb_device *dev)
4534 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4535 struct b43_wl *wl = wldev->wl;
4538 b43dbg(wl, "Resuming...\n");
4540 mutex_lock(&wl->mutex);
4541 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4542 err = b43_wireless_core_init(wldev);
4544 b43err(wl, "Resume failed at core init\n");
4548 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4549 err = b43_wireless_core_start(wldev);
4551 b43_leds_exit(wldev);
4552 b43_rng_exit(wldev->wl, true);
4553 b43_wireless_core_exit(wldev);
4554 b43err(wl, "Resume failed at core start\n");
4558 b43dbg(wl, "Device resumed.\n");
4560 wldev->suspend_in_progress = false;
4561 mutex_unlock(&wl->mutex);
4565 #else /* CONFIG_PM */
4566 # define b43_suspend NULL
4567 # define b43_resume NULL
4568 #endif /* CONFIG_PM */
4570 static struct ssb_driver b43_ssb_driver = {
4571 .name = KBUILD_MODNAME,
4572 .id_table = b43_ssb_tbl,
4574 .remove = b43_remove,
4575 .suspend = b43_suspend,
4576 .resume = b43_resume,
4579 static void b43_print_driverinfo(void)
4581 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
4582 *feat_leds = "", *feat_rfkill = "";
4584 #ifdef CONFIG_B43_PCI_AUTOSELECT
4587 #ifdef CONFIG_B43_PCMCIA
4590 #ifdef CONFIG_B43_NPHY
4593 #ifdef CONFIG_B43_LEDS
4596 #ifdef CONFIG_B43_RFKILL
4599 printk(KERN_INFO "Broadcom 43xx driver loaded "
4600 "[ Features: %s%s%s%s%s, Firmware-ID: "
4601 B43_SUPPORTED_FIRMWARE_ID " ]\n",
4602 feat_pci, feat_pcmcia, feat_nphy,
4603 feat_leds, feat_rfkill);
4606 static int __init b43_init(void)
4611 err = b43_pcmcia_init();
4614 err = ssb_driver_register(&b43_ssb_driver);
4616 goto err_pcmcia_exit;
4617 b43_print_driverinfo();
4628 static void __exit b43_exit(void)
4630 ssb_driver_unregister(&b43_ssb_driver);
4635 module_init(b43_init)
4636 module_exit(b43_exit)