drivers/net/wireless/iwlwifi/pcie/rx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/sched.h>
  30 #include <linux/wait.h>
  31 #include <linux/gfp.h>
  32
  33 #include "iwl-prph.h"
  34 #include "iwl-io.h"
  35 #include "internal.h"
  36 #include "iwl-op-mode.h"
  37
  38 /******************************************************************************
  39  *
  40  * RX path functions
  41  *
  42  ******************************************************************************/
  43
  44 /*
  45  * Rx theory of operation
  46  *
  47  * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  48  * each of which point to Receive Buffers to be filled by the NIC.  These get
  49  * used not only for Rx frames, but for any command response or notification
  50  * from the NIC.  The driver and NIC manage the Rx buffers by means
  51  * of indexes into the circular buffer.
  52  *
  53  * Rx Queue Indexes
  54  * The host/firmware share two index registers for managing the Rx buffers.
  55  *
  56  * The READ index maps to the first position that the firmware may be writing
  57  * to -- the driver can read up to (but not including) this position and get
  58  * good data.
  59  * The READ index is managed by the firmware once the card is enabled.
  60  *
  61  * The WRITE index maps to the last position the driver has read from -- the
  62  * position preceding WRITE is the last slot the firmware can place a packet.
  63  *
  64  * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  65  * WRITE = READ.
  66  *
  67  * During initialization, the host sets up the READ queue position to the first
  68  * INDEX position, and WRITE to the last (READ - 1 wrapped)
  69  *
  70  * When the firmware places a packet in a buffer, it will advance the READ index
  71  * and fire the RX interrupt.  The driver can then query the READ index and
  72  * process as many packets as possible, moving the WRITE index forward as it
  73  * resets the Rx queue buffers with new memory.
  74  *
  75  * The management in the driver is as follows:
  76  * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free.  When
  77  *   iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  78  *   to replenish the iwl->rxq->rx_free.
  79  * + In iwl_pcie_rx_replenish (scheduled) if 'processed' != 'read' then the
  80  *   iwl->rxq is replenished and the READ INDEX is updated (updating the
  81  *   'processed' and 'read' driver indexes as well)
  82  * + A received packet is processed and handed to the kernel network stack,
  83  *   detached from the iwl->rxq.  The driver 'processed' index is updated.
  84  * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  85  *   list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  86  *   INDEX is not incremented and iwl->status(RX_STALLED) is set.  If there
  87  *   were enough free buffers and RX_STALLED is set it is cleared.
  88  *
  89  *
  90  * Driver sequence:
  91  *
  92  * iwl_rxq_alloc()            Allocates rx_free
  93  * iwl_pcie_rx_replenish()    Replenishes rx_free list from rx_used, and calls
  94  *                            iwl_pcie_rxq_restock
  95  * iwl_pcie_rxq_restock()     Moves available buffers from rx_free into Rx
  96  *                            queue, updates firmware pointers, and updates
  97  *                            the WRITE index.  If insufficient rx_free buffers
  98  *                            are available, schedules iwl_pcie_rx_replenish
  99  *
 100  * -- enable interrupts --
 101  * ISR - iwl_rx()             Detach iwl_rx_mem_buffers from pool up to the
 102  *                            READ INDEX, detaching the SKB from the pool.
 103  *                            Moves the packet buffer from queue to rx_used.
 104  *                            Calls iwl_pcie_rxq_restock to refill any empty
 105  *                            slots.
 106  * ...
 107  *
 108  */
 109
 110 /*
 111  * iwl_rxq_space - Return number of free slots available in queue.
 112  */
 113 static int iwl_rxq_space(const struct iwl_rxq *q)
 114 {
 115         int s = q->read - q->write;
 116         if (s <= 0)
 117                 s += RX_QUEUE_SIZE;
 118         /* keep some buffer to not confuse full and empty queue */
 119         s -= 2;
 120         if (s < 0)
 121                 s = 0;
 122         return s;
 123 }
 124
 125 /*
 126  * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 127  */
 128 static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr)
 129 {
 130         return cpu_to_le32((u32)(dma_addr >> 8));
 131 }
 132
 133 /*
 134  * iwl_pcie_rx_stop - stops the Rx DMA
 135  */
 136 int iwl_pcie_rx_stop(struct iwl_trans *trans)
 137 {
 138         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 139         return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
 140                                    FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 141 }
 142
 143 /*
 144  * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue
 145  */
 146 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_rxq *q)
 147 {
 148         unsigned long flags;
 149         u32 reg;
 150
 151         spin_lock_irqsave(&q->lock, flags);
 152
 153         if (q->need_update == 0)
 154                 goto exit_unlock;
 155
 156         if (trans->cfg->base_params->shadow_reg_enable) {
 157                 /* shadow register enabled */
 158                 /* Device expects a multiple of 8 */
 159                 q->write_actual = (q->write & ~0x7);
 160                 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, q->write_actual);
 161         } else {
 162                 struct iwl_trans_pcie *trans_pcie =
 163                         IWL_TRANS_GET_PCIE_TRANS(trans);
 164
 165                 /* If power-saving is in use, make sure device is awake */
 166                 if (test_bit(STATUS_TPOWER_PMI, &trans_pcie->status)) {
 167                         reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 168
 169                         if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 170                                 IWL_DEBUG_INFO(trans,
 171                                         "Rx queue requesting wakeup,"
 172                                         " GP1 = 0x%x\n", reg);
 173                                 iwl_set_bit(trans, CSR_GP_CNTRL,
 174                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 175                                 goto exit_unlock;
 176                         }
 177
 178                         q->write_actual = (q->write & ~0x7);
 179                         iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
 180                                         q->write_actual);
 181
 182                 /* Else device is assumed to be awake */
 183                 } else {
 184                         /* Device expects a multiple of 8 */
 185                         q->write_actual = (q->write & ~0x7);
 186                         iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
 187                                 q->write_actual);
 188                 }
 189         }
 190         q->need_update = 0;
 191
 192  exit_unlock:
 193         spin_unlock_irqrestore(&q->lock, flags);
 194 }
 195
 196 /*
 197  * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool
 198  *
 199  * If there are slots in the RX queue that need to be restocked,
 200  * and we have free pre-allocated buffers, fill the ranks as much
 201  * as we can, pulling from rx_free.
 202  *
 203  * This moves the 'write' index forward to catch up with 'processed', and
 204  * also updates the memory address in the firmware to reference the new
 205  * target buffer.
 206  */
 207 static void iwl_pcie_rxq_restock(struct iwl_trans *trans)
 208 {
 209         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 210         struct iwl_rxq *rxq = &trans_pcie->rxq;
 211         struct iwl_rx_mem_buffer *rxb;
 212         unsigned long flags;
 213
 214         /*
 215          * If the device isn't enabled - not need to try to add buffers...
 216          * This can happen when we stop the device and still have an interrupt
 217          * pending. We stop the APM before we sync the interrupts / tasklets
 218          * because we have to (see comment there). On the other hand, since
 219          * the APM is stopped, we cannot access the HW (in particular not prph).
 220          * So don't try to restock if the APM has been already stopped.
 221          */
 222         if (!test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status))
 223                 return;
 224
 225         spin_lock_irqsave(&rxq->lock, flags);
 226         while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) {
 227                 /* The overwritten rxb must be a used one */
 228                 rxb = rxq->queue[rxq->write];
 229                 BUG_ON(rxb && rxb->page);
 230
 231                 /* Get next free Rx buffer, remove from free list */
 232                 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
 233                                        list);
 234                 list_del(&rxb->list);
 235
 236                 /* Point to Rx buffer via next RBD in circular buffer */
 237                 rxq->bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma);
 238                 rxq->queue[rxq->write] = rxb;
 239                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 240                 rxq->free_count--;
 241         }
 242         spin_unlock_irqrestore(&rxq->lock, flags);
 243         /* If the pre-allocated buffer pool is dropping low, schedule to
 244          * refill it */
 245         if (rxq->free_count <= RX_LOW_WATERMARK)
 246                 schedule_work(&trans_pcie->rx_replenish);
 247
 248         /* If we've added more space for the firmware to place data, tell it.
 249          * Increment device's write pointer in multiples of 8. */
 250         if (rxq->write_actual != (rxq->write & ~0x7)) {
 251                 spin_lock_irqsave(&rxq->lock, flags);
 252                 rxq->need_update = 1;
 253                 spin_unlock_irqrestore(&rxq->lock, flags);
 254                 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
 255         }
 256 }
 257
 258 /*
 259  * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD
 260  *
 261  * A used RBD is an Rx buffer that has been given to the stack. To use it again
 262  * a page must be allocated and the RBD must point to the page. This function
 263  * doesn't change the HW pointer but handles the list of pages that is used by
 264  * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly
 265  * allocated buffers.
 266  */
 267 static void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority)
 268 {
 269         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 270         struct iwl_rxq *rxq = &trans_pcie->rxq;
 271         struct iwl_rx_mem_buffer *rxb;
 272         struct page *page;
 273         unsigned long flags;
 274         gfp_t gfp_mask = priority;
 275
 276         while (1) {
 277                 spin_lock_irqsave(&rxq->lock, flags);
 278                 if (list_empty(&rxq->rx_used)) {
 279                         spin_unlock_irqrestore(&rxq->lock, flags);
 280                         return;
 281                 }
 282                 spin_unlock_irqrestore(&rxq->lock, flags);
 283
 284                 if (rxq->free_count > RX_LOW_WATERMARK)
 285                         gfp_mask |= __GFP_NOWARN;
 286
 287                 if (trans_pcie->rx_page_order > 0)
 288                         gfp_mask |= __GFP_COMP;
 289
 290                 /* Alloc a new receive buffer */
 291                 page = alloc_pages(gfp_mask, trans_pcie->rx_page_order);
 292                 if (!page) {
 293                         if (net_ratelimit())
 294                                 IWL_DEBUG_INFO(trans, "alloc_pages failed, "
 295                                            "order: %d\n",
 296                                            trans_pcie->rx_page_order);
 297
 298                         if ((rxq->free_count <= RX_LOW_WATERMARK) &&
 299                             net_ratelimit())
 300                                 IWL_CRIT(trans, "Failed to alloc_pages with %s."
 301                                          "Only %u free buffers remaining.\n",
 302                                          priority == GFP_ATOMIC ?
 303                                          "GFP_ATOMIC" : "GFP_KERNEL",
 304                                          rxq->free_count);
 305                         /* We don't reschedule replenish work here -- we will
 306                          * call the restock method and if it still needs
 307                          * more buffers it will schedule replenish */
 308                         return;
 309                 }
 310
 311                 spin_lock_irqsave(&rxq->lock, flags);
 312
 313                 if (list_empty(&rxq->rx_used)) {
 314                         spin_unlock_irqrestore(&rxq->lock, flags);
 315                         __free_pages(page, trans_pcie->rx_page_order);
 316                         return;
 317                 }
 318                 rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer,
 319                                        list);
 320                 list_del(&rxb->list);
 321                 spin_unlock_irqrestore(&rxq->lock, flags);
 322
 323                 BUG_ON(rxb->page);
 324                 rxb->page = page;
 325                 /* Get physical address of the RB */
 326                 rxb->page_dma =
 327                         dma_map_page(trans->dev, page, 0,
 328                                      PAGE_SIZE << trans_pcie->rx_page_order,
 329                                      DMA_FROM_DEVICE);
 330                 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
 331                         rxb->page = NULL;
 332                         spin_lock_irqsave(&rxq->lock, flags);
 333                         list_add(&rxb->list, &rxq->rx_used);
 334                         spin_unlock_irqrestore(&rxq->lock, flags);
 335                         __free_pages(page, trans_pcie->rx_page_order);
 336                         return;
 337                 }
 338                 /* dma address must be no more than 36 bits */
 339                 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
 340                 /* and also 256 byte aligned! */
 341                 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
 342
 343                 spin_lock_irqsave(&rxq->lock, flags);
 344
 345                 list_add_tail(&rxb->list, &rxq->rx_free);
 346                 rxq->free_count++;
 347
 348                 spin_unlock_irqrestore(&rxq->lock, flags);
 349         }
 350 }
 351
 352 static void iwl_pcie_rxq_free_rbs(struct iwl_trans *trans)
 353 {
 354         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 355         struct iwl_rxq *rxq = &trans_pcie->rxq;
 356         int i;
 357
 358         /* Fill the rx_used queue with _all_ of the Rx buffers */
 359         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 360                 /* In the reset function, these buffers may have been allocated
 361                  * to an SKB, so we need to unmap and free potential storage */
 362                 if (rxq->pool[i].page != NULL) {
 363                         dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
 364                                        PAGE_SIZE << trans_pcie->rx_page_order,
 365                                        DMA_FROM_DEVICE);
 366                         __free_pages(rxq->pool[i].page,
 367                                      trans_pcie->rx_page_order);
 368                         rxq->pool[i].page = NULL;
 369                 }
 370                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 371         }
 372 }
 373
 374 /*
 375  * iwl_pcie_rx_replenish - Move all used buffers from rx_used to rx_free
 376  *
 377  * When moving to rx_free an page is allocated for the slot.
 378  *
 379  * Also restock the Rx queue via iwl_pcie_rxq_restock.
 380  * This is called as a scheduled work item (except for during initialization)
 381  */
 382 static void iwl_pcie_rx_replenish(struct iwl_trans *trans)
 383 {
 384         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 385         unsigned long flags;
 386
 387         iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL);
 388
 389         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 390         iwl_pcie_rxq_restock(trans);
 391         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 392 }
 393
 394 static void iwl_pcie_rx_replenish_now(struct iwl_trans *trans)
 395 {
 396         iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC);
 397
 398         iwl_pcie_rxq_restock(trans);
 399 }
 400
 401 static void iwl_pcie_rx_replenish_work(struct work_struct *data)
 402 {
 403         struct iwl_trans_pcie *trans_pcie =
 404             container_of(data, struct iwl_trans_pcie, rx_replenish);
 405
 406         iwl_pcie_rx_replenish(trans_pcie->trans);
 407 }
 408
 409 static int iwl_pcie_rx_alloc(struct iwl_trans *trans)
 410 {
 411         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 412         struct iwl_rxq *rxq = &trans_pcie->rxq;
 413         struct device *dev = trans->dev;
 414
 415         memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
 416
 417         spin_lock_init(&rxq->lock);
 418
 419         if (WARN_ON(rxq->bd || rxq->rb_stts))
 420                 return -EINVAL;
 421
 422         /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
 423         rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 424                                       &rxq->bd_dma, GFP_KERNEL);
 425         if (!rxq->bd)
 426                 goto err_bd;
 427
 428         /*Allocate the driver's pointer to receive buffer status */
 429         rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
 430                                            &rxq->rb_stts_dma, GFP_KERNEL);
 431         if (!rxq->rb_stts)
 432                 goto err_rb_stts;
 433
 434         return 0;
 435
 436 err_rb_stts:
 437         dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 438                           rxq->bd, rxq->bd_dma);
 439         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 440         rxq->bd = NULL;
 441 err_bd:
 442         return -ENOMEM;
 443 }
 444
 445 static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
 446 {
 447         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 448         u32 rb_size;
 449         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 450
 451         if (trans_pcie->rx_buf_size_8k)
 452                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 453         else
 454                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 455
 456         /* Stop Rx DMA */
 457         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 458
 459         /* Reset driver's Rx queue write index */
 460         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 461
 462         /* Tell device where to find RBD circular buffer in DRAM */
 463         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 464                            (u32)(rxq->bd_dma >> 8));
 465
 466         /* Tell device where in DRAM to update its Rx status */
 467         iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 468                            rxq->rb_stts_dma >> 4);
 469
 470         /* Enable Rx DMA
 471          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 472          *      the credit mechanism in 5000 HW RX FIFO
 473          * Direct rx interrupts to hosts
 474          * Rx buffer size 4 or 8k
 475          * RB timeout 0x10
 476          * 256 RBDs
 477          */
 478         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 479                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 480                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 481                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 482                            rb_size|
 483                            (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 484                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 485
 486         /* Set interrupt coalescing timer to default (2048 usecs) */
 487         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 488 }
 489
 490 int iwl_pcie_rx_init(struct iwl_trans *trans)
 491 {
 492         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 493         struct iwl_rxq *rxq = &trans_pcie->rxq;
 494
 495         int i, err;
 496         unsigned long flags;
 497
 498         if (!rxq->bd) {
 499                 err = iwl_pcie_rx_alloc(trans);
 500                 if (err)
 501                         return err;
 502         }
 503
 504         spin_lock_irqsave(&rxq->lock, flags);
 505         INIT_LIST_HEAD(&rxq->rx_free);
 506         INIT_LIST_HEAD(&rxq->rx_used);
 507
 508         INIT_WORK(&trans_pcie->rx_replenish,
 509                   iwl_pcie_rx_replenish_work);
 510
 511         iwl_pcie_rxq_free_rbs(trans);
 512
 513         for (i = 0; i < RX_QUEUE_SIZE; i++)
 514                 rxq->queue[i] = NULL;
 515
 516         /* Set us so that we have processed and used all buffers, but have
 517          * not restocked the Rx queue with fresh buffers */
 518         rxq->read = rxq->write = 0;
 519         rxq->write_actual = 0;
 520         rxq->free_count = 0;
 521         spin_unlock_irqrestore(&rxq->lock, flags);
 522
 523         iwl_pcie_rx_replenish(trans);
 524
 525         iwl_pcie_rx_hw_init(trans, rxq);
 526
 527         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 528         rxq->need_update = 1;
 529         iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
 530         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 531
 532         return 0;
 533 }
 534
 535 void iwl_pcie_rx_free(struct iwl_trans *trans)
 536 {
 537         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 538         struct iwl_rxq *rxq = &trans_pcie->rxq;
 539         unsigned long flags;
 540
 541         /*if rxq->bd is NULL, it means that nothing has been allocated,
 542          * exit now */
 543         if (!rxq->bd) {
 544                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
 545                 return;
 546         }
 547
 548         spin_lock_irqsave(&rxq->lock, flags);
 549         iwl_pcie_rxq_free_rbs(trans);
 550         spin_unlock_irqrestore(&rxq->lock, flags);
 551
 552         dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
 553                           rxq->bd, rxq->bd_dma);
 554         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 555         rxq->bd = NULL;
 556
 557         if (rxq->rb_stts)
 558                 dma_free_coherent(trans->dev,
 559                                   sizeof(struct iwl_rb_status),
 560                                   rxq->rb_stts, rxq->rb_stts_dma);
 561         else
 562                 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
 563         memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
 564         rxq->rb_stts = NULL;
 565 }
 566
 567 static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans,
 568                                 struct iwl_rx_mem_buffer *rxb)
 569 {
 570         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 571         struct iwl_rxq *rxq = &trans_pcie->rxq;
 572         struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
 573         unsigned long flags;
 574         bool page_stolen = false;
 575         int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
 576         u32 offset = 0;
 577
 578         if (WARN_ON(!rxb))
 579                 return;
 580
 581         dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE);
 582
 583         while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) {
 584                 struct iwl_rx_packet *pkt;
 585                 struct iwl_device_cmd *cmd;
 586                 u16 sequence;
 587                 bool reclaim;
 588                 int index, cmd_index, err, len;
 589                 struct iwl_rx_cmd_buffer rxcb = {
 590                         ._offset = offset,
 591                         ._page = rxb->page,
 592                         ._page_stolen = false,
 593                         .truesize = max_len,
 594                 };
 595
 596                 pkt = rxb_addr(&rxcb);
 597
 598                 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID))
 599                         break;
 600
 601                 IWL_DEBUG_RX(trans, "cmd at offset %d: %s (0x%.2x)\n",
 602                         rxcb._offset, get_cmd_string(trans_pcie, pkt->hdr.cmd),
 603                         pkt->hdr.cmd);
 604
 605                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 606                 len += sizeof(u32); /* account for status word */
 607                 trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len);
 608                 trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len);
 609
 610                 /* Reclaim a command buffer only if this packet is a response
 611                  *   to a (driver-originated) command.
 612                  * If the packet (e.g. Rx frame) originated from uCode,
 613                  *   there is no command buffer to reclaim.
 614                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 615                  *   but apparently a few don't get set; catch them here. */
 616                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME);
 617                 if (reclaim) {
 618                         int i;
 619
 620                         for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) {
 621                                 if (trans_pcie->no_reclaim_cmds[i] ==
 622                                                         pkt->hdr.cmd) {
 623                                         reclaim = false;
 624                                         break;
 625                                 }
 626                         }
 627                 }
 628
 629                 sequence = le16_to_cpu(pkt->hdr.sequence);
 630                 index = SEQ_TO_INDEX(sequence);
 631                 cmd_index = get_cmd_index(&txq->q, index);
 632
 633                 if (reclaim) {
 634                         struct iwl_pcie_txq_entry *ent;
 635                         ent = &txq->entries[cmd_index];
 636                         cmd = ent->copy_cmd;
 637                         WARN_ON_ONCE(!cmd && ent->meta.flags & CMD_WANT_HCMD);
 638                 } else {
 639                         cmd = NULL;
 640                 }
 641
 642                 err = iwl_op_mode_rx(trans->op_mode, &rxcb, cmd);
 643
 644                 if (reclaim) {
 645                         /* The original command isn't needed any more */
 646                         kfree(txq->entries[cmd_index].copy_cmd);
 647                         txq->entries[cmd_index].copy_cmd = NULL;
 648                         /* nor is the duplicated part of the command */
 649                         kfree(txq->entries[cmd_index].free_buf);
 650                         txq->entries[cmd_index].free_buf = NULL;
 651                 }
 652
 653                 /*
 654                  * After here, we should always check rxcb._page_stolen,
 655                  * if it is true then one of the handlers took the page.
 656                  */
 657
 658                 if (reclaim) {
 659                         /* Invoke any callbacks, transfer the buffer to caller,
 660                          * and fire off the (possibly) blocking
 661                          * iwl_trans_send_cmd()
 662                          * as we reclaim the driver command queue */
 663                         if (!rxcb._page_stolen)
 664                                 iwl_pcie_hcmd_complete(trans, &rxcb, err);
 665                         else
 666                                 IWL_WARN(trans, "Claim null rxb?\n");
 667                 }
 668
 669                 page_stolen |= rxcb._page_stolen;
 670                 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN);
 671         }
 672
 673         /* page was stolen from us -- free our reference */
 674         if (page_stolen) {
 675                 __free_pages(rxb->page, trans_pcie->rx_page_order);
 676                 rxb->page = NULL;
 677         }
 678
 679         /* Reuse the page if possible. For notification packets and
 680          * SKBs that fail to Rx correctly, add them back into the
 681          * rx_free list for reuse later. */
 682         spin_lock_irqsave(&rxq->lock, flags);
 683         if (rxb->page != NULL) {
 684                 rxb->page_dma =
 685                         dma_map_page(trans->dev, rxb->page, 0,
 686                                      PAGE_SIZE << trans_pcie->rx_page_order,
 687                                      DMA_FROM_DEVICE);
 688                 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
 689                         /*
 690                          * free the page(s) as well to not break
 691                          * the invariant that the items on the used
 692                          * list have no page(s)
 693                          */
 694                         __free_pages(rxb->page, trans_pcie->rx_page_order);
 695                         rxb->page = NULL;
 696                         list_add_tail(&rxb->list, &rxq->rx_used);
 697                 } else {
 698                         list_add_tail(&rxb->list, &rxq->rx_free);
 699                         rxq->free_count++;
 700                 }
 701         } else
 702                 list_add_tail(&rxb->list, &rxq->rx_used);
 703         spin_unlock_irqrestore(&rxq->lock, flags);
 704 }
 705
 706 /*
 707  * iwl_pcie_rx_handle - Main entry function for receiving responses from fw
 708  */
 709 static void iwl_pcie_rx_handle(struct iwl_trans *trans)
 710 {
 711         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 712         struct iwl_rxq *rxq = &trans_pcie->rxq;
 713         u32 r, i;
 714         u8 fill_rx = 0;
 715         u32 count = 8;
 716         int total_empty;
 717
 718         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 719          * buffer that the driver may process (last buffer filled by ucode). */
 720         r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
 721         i = rxq->read;
 722
 723         /* Rx interrupt, but nothing sent from uCode */
 724         if (i == r)
 725                 IWL_DEBUG_RX(trans, "HW = SW = %d\n", r);
 726
 727         /* calculate total frames need to be restock after handling RX */
 728         total_empty = r - rxq->write_actual;
 729         if (total_empty < 0)
 730                 total_empty += RX_QUEUE_SIZE;
 731
 732         if (total_empty > (RX_QUEUE_SIZE / 2))
 733                 fill_rx = 1;
 734
 735         while (i != r) {
 736                 struct iwl_rx_mem_buffer *rxb;
 737
 738                 rxb = rxq->queue[i];
 739                 rxq->queue[i] = NULL;
 740
 741                 IWL_DEBUG_RX(trans, "rxbuf: HW = %d, SW = %d (%p)\n",
 742                              r, i, rxb);
 743                 iwl_pcie_rx_handle_rb(trans, rxb);
 744
 745                 i = (i + 1) & RX_QUEUE_MASK;
 746                 /* If there are a lot of unused frames,
 747                  * restock the Rx queue so ucode wont assert. */
 748                 if (fill_rx) {
 749                         count++;
 750                         if (count >= 8) {
 751                                 rxq->read = i;
 752                                 iwl_pcie_rx_replenish_now(trans);
 753                                 count = 0;
 754                         }
 755                 }
 756         }
 757
 758         /* Backtrack one entry */
 759         rxq->read = i;
 760         if (fill_rx)
 761                 iwl_pcie_rx_replenish_now(trans);
 762         else
 763                 iwl_pcie_rxq_restock(trans);
 764 }
 765
 766 /*
 767  * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card
 768  */
 769 static void iwl_pcie_irq_handle_error(struct iwl_trans *trans)
 770 {
 771         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 772
 773         /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
 774         if (trans->cfg->internal_wimax_coex &&
 775             (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
 776                              APMS_CLK_VAL_MRB_FUNC_MODE) ||
 777              (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
 778                             APMG_PS_CTRL_VAL_RESET_REQ))) {
 779                 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
 780                 iwl_op_mode_wimax_active(trans->op_mode);
 781                 wake_up(&trans_pcie->wait_command_queue);
 782                 return;
 783         }
 784
 785         iwl_pcie_dump_csr(trans);
 786         iwl_pcie_dump_fh(trans, NULL);
 787
 788         set_bit(STATUS_FW_ERROR, &trans_pcie->status);
 789         clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
 790         wake_up(&trans_pcie->wait_command_queue);
 791
 792         iwl_op_mode_nic_error(trans->op_mode);
 793 }
 794
 795 void iwl_pcie_tasklet(struct iwl_trans *trans)
 796 {
 797         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 798         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
 799         u32 inta = 0;
 800         u32 handled = 0;
 801         unsigned long flags;
 802         u32 i;
 803 #ifdef CONFIG_IWLWIFI_DEBUG
 804         u32 inta_mask;
 805 #endif
 806
 807         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 808
 809         /* Ack/clear/reset pending uCode interrupts.
 810          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
 811          */
 812         /* There is a hardware bug in the interrupt mask function that some
 813          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
 814          * they are disabled in the CSR_INT_MASK register. Furthermore the
 815          * ICT interrupt handling mechanism has another bug that might cause
 816          * these unmasked interrupts fail to be detected. We workaround the
 817          * hardware bugs here by ACKing all the possible interrupts so that
 818          * interrupt coalescing can still be achieved.
 819          */
 820         iwl_write32(trans, CSR_INT,
 821                     trans_pcie->inta | ~trans_pcie->inta_mask);
 822
 823         inta = trans_pcie->inta;
 824
 825 #ifdef CONFIG_IWLWIFI_DEBUG
 826         if (iwl_have_debug_level(IWL_DL_ISR)) {
 827                 /* just for debug */
 828                 inta_mask = iwl_read32(trans, CSR_INT_MASK);
 829                 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
 830                               inta, inta_mask);
 831         }
 832 #endif
 833
 834         /* saved interrupt in inta variable now we can reset trans_pcie->inta */
 835         trans_pcie->inta = 0;
 836
 837         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 838
 839         /* Now service all interrupt bits discovered above. */
 840         if (inta & CSR_INT_BIT_HW_ERR) {
 841                 IWL_ERR(trans, "Hardware error detected.  Restarting.\n");
 842
 843                 /* Tell the device to stop sending interrupts */
 844                 iwl_disable_interrupts(trans);
 845
 846                 isr_stats->hw++;
 847                 iwl_pcie_irq_handle_error(trans);
 848
 849                 handled |= CSR_INT_BIT_HW_ERR;
 850
 851                 return;
 852         }
 853
 854 #ifdef CONFIG_IWLWIFI_DEBUG
 855         if (iwl_have_debug_level(IWL_DL_ISR)) {
 856                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
 857                 if (inta & CSR_INT_BIT_SCD) {
 858                         IWL_DEBUG_ISR(trans, "Scheduler finished to transmit "
 859                                       "the frame/frames.\n");
 860                         isr_stats->sch++;
 861                 }
 862
 863                 /* Alive notification via Rx interrupt will do the real work */
 864                 if (inta & CSR_INT_BIT_ALIVE) {
 865                         IWL_DEBUG_ISR(trans, "Alive interrupt\n");
 866                         isr_stats->alive++;
 867                 }
 868         }
 869 #endif
 870         /* Safely ignore these bits for debug checks below */
 871         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
 872
 873         /* HW RF KILL switch toggled */
 874         if (inta & CSR_INT_BIT_RF_KILL) {
 875                 bool hw_rfkill;
 876
 877                 hw_rfkill = iwl_is_rfkill_set(trans);
 878                 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
 879                          hw_rfkill ? "disable radio" : "enable radio");
 880
 881                 isr_stats->rfkill++;
 882
 883                 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 884                 if (hw_rfkill) {
 885                         set_bit(STATUS_RFKILL, &trans_pcie->status);
 886                         if (test_and_clear_bit(STATUS_HCMD_ACTIVE,
 887                                                &trans_pcie->status))
 888                                 IWL_DEBUG_RF_KILL(trans,
 889                                                   "Rfkill while SYNC HCMD in flight\n");
 890                         wake_up(&trans_pcie->wait_command_queue);
 891                 } else {
 892                         clear_bit(STATUS_RFKILL, &trans_pcie->status);
 893                 }
 894
 895                 handled |= CSR_INT_BIT_RF_KILL;
 896         }
 897
 898         /* Chip got too hot and stopped itself */
 899         if (inta & CSR_INT_BIT_CT_KILL) {
 900                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
 901                 isr_stats->ctkill++;
 902                 handled |= CSR_INT_BIT_CT_KILL;
 903         }
 904
 905         /* Error detected by uCode */
 906         if (inta & CSR_INT_BIT_SW_ERR) {
 907                 IWL_ERR(trans, "Microcode SW error detected. "
 908                         " Restarting 0x%X.\n", inta);
 909                 isr_stats->sw++;
 910                 iwl_pcie_irq_handle_error(trans);
 911                 handled |= CSR_INT_BIT_SW_ERR;
 912         }
 913
 914         /* uCode wakes up after power-down sleep */
 915         if (inta & CSR_INT_BIT_WAKEUP) {
 916                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
 917                 iwl_pcie_rxq_inc_wr_ptr(trans, &trans_pcie->rxq);
 918                 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++)
 919                         iwl_pcie_txq_inc_wr_ptr(trans, &trans_pcie->txq[i]);
 920
 921                 isr_stats->wakeup++;
 922
 923                 handled |= CSR_INT_BIT_WAKEUP;
 924         }
 925
 926         /* All uCode command responses, including Tx command responses,
 927          * Rx "responses" (frame-received notification), and other
 928          * notifications from uCode come through here*/
 929         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
 930                     CSR_INT_BIT_RX_PERIODIC)) {
 931                 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
 932                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
 933                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
 934                         iwl_write32(trans, CSR_FH_INT_STATUS,
 935                                         CSR_FH_INT_RX_MASK);
 936                 }
 937                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
 938                         handled |= CSR_INT_BIT_RX_PERIODIC;
 939                         iwl_write32(trans,
 940                                 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
 941                 }
 942                 /* Sending RX interrupt require many steps to be done in the
 943                  * the device:
 944                  * 1- write interrupt to current index in ICT table.
 945                  * 2- dma RX frame.
 946                  * 3- update RX shared data to indicate last write index.
 947                  * 4- send interrupt.
 948                  * This could lead to RX race, driver could receive RX interrupt
 949                  * but the shared data changes does not reflect this;
 950                  * periodic interrupt will detect any dangling Rx activity.
 951                  */
 952
 953                 /* Disable periodic interrupt; we use it as just a one-shot. */
 954                 iwl_write8(trans, CSR_INT_PERIODIC_REG,
 955                             CSR_INT_PERIODIC_DIS);
 956
 957                 iwl_pcie_rx_handle(trans);
 958
 959                 /*
 960                  * Enable periodic interrupt in 8 msec only if we received
 961                  * real RX interrupt (instead of just periodic int), to catch
 962                  * any dangling Rx interrupt.  If it was just the periodic
 963                  * interrupt, there was no dangling Rx activity, and no need
 964                  * to extend the periodic interrupt; one-shot is enough.
 965                  */
 966                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
 967                         iwl_write8(trans, CSR_INT_PERIODIC_REG,
 968                                    CSR_INT_PERIODIC_ENA);
 969
 970                 isr_stats->rx++;
 971         }
 972
 973         /* This "Tx" DMA channel is used only for loading uCode */
 974         if (inta & CSR_INT_BIT_FH_TX) {
 975                 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
 976                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
 977                 isr_stats->tx++;
 978                 handled |= CSR_INT_BIT_FH_TX;
 979                 /* Wake up uCode load routine, now that load is complete */
 980                 trans_pcie->ucode_write_complete = true;
 981                 wake_up(&trans_pcie->ucode_write_waitq);
 982         }
 983
 984         if (inta & ~handled) {
 985                 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
 986                 isr_stats->unhandled++;
 987         }
 988
 989         if (inta & ~(trans_pcie->inta_mask)) {
 990                 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
 991                          inta & ~trans_pcie->inta_mask);
 992         }
 993
 994         /* Re-enable all interrupts */
 995         /* only Re-enable if disabled by irq */
 996         if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status))
 997                 iwl_enable_interrupts(trans);
 998         /* Re-enable RF_KILL if it occurred */
 999         else if (handled & CSR_INT_BIT_RF_KILL)
1000                 iwl_enable_rfkill_int(trans);
1001 }
1002
1003 /******************************************************************************
1004  *
1005  * ICT functions
1006  *
1007  ******************************************************************************/
1008
1009 /* a device (PCI-E) page is 4096 bytes long */
1010 #define ICT_SHIFT       12
1011 #define ICT_SIZE        (1 << ICT_SHIFT)
1012 #define ICT_COUNT       (ICT_SIZE / sizeof(u32))
1013
1014 /* Free dram table */
1015 void iwl_pcie_free_ict(struct iwl_trans *trans)
1016 {
1017         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1018
1019         if (trans_pcie->ict_tbl) {
1020                 dma_free_coherent(trans->dev, ICT_SIZE,
1021                                   trans_pcie->ict_tbl,
1022                                   trans_pcie->ict_tbl_dma);
1023                 trans_pcie->ict_tbl = NULL;
1024                 trans_pcie->ict_tbl_dma = 0;
1025         }
1026 }
1027
1028 /*
1029  * allocate dram shared table, it is an aligned memory
1030  * block of ICT_SIZE.
1031  * also reset all data related to ICT table interrupt.
1032  */
1033 int iwl_pcie_alloc_ict(struct iwl_trans *trans)
1034 {
1035         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1036
1037         trans_pcie->ict_tbl =
1038                 dma_alloc_coherent(trans->dev, ICT_SIZE,
1039                                    &trans_pcie->ict_tbl_dma,
1040                                    GFP_KERNEL);
1041         if (!trans_pcie->ict_tbl)
1042                 return -ENOMEM;
1043
1044         /* just an API sanity check ... it is guaranteed to be aligned */
1045         if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
1046                 iwl_pcie_free_ict(trans);
1047                 return -EINVAL;
1048         }
1049
1050         IWL_DEBUG_ISR(trans, "ict dma addr %Lx\n",
1051                       (unsigned long long)trans_pcie->ict_tbl_dma);
1052
1053         IWL_DEBUG_ISR(trans, "ict vir addr %p\n", trans_pcie->ict_tbl);
1054
1055         /* reset table and index to all 0 */
1056         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1057         trans_pcie->ict_index = 0;
1058
1059         /* add periodic RX interrupt */
1060         trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
1061         return 0;
1062 }
1063
1064 /* Device is going up inform it about using ICT interrupt table,
1065  * also we need to tell the driver to start using ICT interrupt.
1066  */
1067 void iwl_pcie_reset_ict(struct iwl_trans *trans)
1068 {
1069         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1070         u32 val;
1071         unsigned long flags;
1072
1073         if (!trans_pcie->ict_tbl)
1074                 return;
1075
1076         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1077         iwl_disable_interrupts(trans);
1078
1079         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1080
1081         val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
1082
1083         val |= CSR_DRAM_INT_TBL_ENABLE;
1084         val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1085
1086         IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
1087
1088         iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
1089         trans_pcie->use_ict = true;
1090         trans_pcie->ict_index = 0;
1091         iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
1092         iwl_enable_interrupts(trans);
1093         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1094 }
1095
1096 /* Device is going down disable ict interrupt usage */
1097 void iwl_pcie_disable_ict(struct iwl_trans *trans)
1098 {
1099         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1100         unsigned long flags;
1101
1102         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1103         trans_pcie->use_ict = false;
1104         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1105 }
1106
1107 /* legacy (non-ICT) ISR. Assumes that trans_pcie->irq_lock is held */
1108 static irqreturn_t iwl_pcie_isr(int irq, void *data)
1109 {
1110         struct iwl_trans *trans = data;
1111         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1112         u32 inta, inta_mask;
1113 #ifdef CONFIG_IWLWIFI_DEBUG
1114         u32 inta_fh;
1115 #endif
1116
1117         lockdep_assert_held(&trans_pcie->irq_lock);
1118
1119         trace_iwlwifi_dev_irq(trans->dev);
1120
1121         /* Disable (but don't clear!) interrupts here to avoid
1122          *    back-to-back ISRs and sporadic interrupts from our NIC.
1123          * If we have something to service, the tasklet will re-enable ints.
1124          * If we *don't* have something, we'll re-enable before leaving here. */
1125         inta_mask = iwl_read32(trans, CSR_INT_MASK);
1126         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1127
1128         /* Discover which interrupts are active/pending */
1129         inta = iwl_read32(trans, CSR_INT);
1130
1131         if (inta & (~inta_mask)) {
1132                 IWL_DEBUG_ISR(trans,
1133                               "We got a masked interrupt (0x%08x)...Ack and ignore\n",
1134                               inta & (~inta_mask));
1135                 iwl_write32(trans, CSR_INT, inta & (~inta_mask));
1136                 inta &= inta_mask;
1137         }
1138
1139         /* Ignore interrupt if there's nothing in NIC to service.
1140          * This may be due to IRQ shared with another device,
1141          * or due to sporadic interrupts thrown from our NIC. */
1142         if (!inta) {
1143                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1144                 goto none;
1145         }
1146
1147         if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1148                 /* Hardware disappeared. It might have already raised
1149                  * an interrupt */
1150                 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1151                 return IRQ_HANDLED;
1152         }
1153
1154 #ifdef CONFIG_IWLWIFI_DEBUG
1155         if (iwl_have_debug_level(IWL_DL_ISR)) {
1156                 inta_fh = iwl_read32(trans, CSR_FH_INT_STATUS);
1157                 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, "
1158                               "fh 0x%08x\n", inta, inta_mask, inta_fh);
1159         }
1160 #endif
1161
1162         trans_pcie->inta |= inta;
1163         /* iwl_pcie_tasklet() will service interrupts and re-enable them */
1164         if (likely(inta))
1165                 tasklet_schedule(&trans_pcie->irq_tasklet);
1166         else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1167                  !trans_pcie->inta)
1168                 iwl_enable_interrupts(trans);
1169
1170 none:
1171         /* re-enable interrupts here since we don't have anything to service. */
1172         /* only Re-enable if disabled by irq  and no schedules tasklet. */
1173         if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1174             !trans_pcie->inta)
1175                 iwl_enable_interrupts(trans);
1176
1177         return IRQ_NONE;
1178 }
1179
1180 /* interrupt handler using ict table, with this interrupt driver will
1181  * stop using INTA register to get device's interrupt, reading this register
1182  * is expensive, device will write interrupts in ICT dram table, increment
1183  * index then will fire interrupt to driver, driver will OR all ICT table
1184  * entries from current index up to table entry with 0 value. the result is
1185  * the interrupt we need to service, driver will set the entries back to 0 and
1186  * set index.
1187  */
1188 irqreturn_t iwl_pcie_isr_ict(int irq, void *data)
1189 {
1190         struct iwl_trans *trans = data;
1191         struct iwl_trans_pcie *trans_pcie;
1192         u32 inta, inta_mask;
1193         u32 val = 0;
1194         u32 read;
1195         unsigned long flags;
1196
1197         if (!trans)
1198                 return IRQ_NONE;
1199
1200         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1201
1202         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1203
1204         /* dram interrupt table not set yet,
1205          * use legacy interrupt.
1206          */
1207         if (unlikely(!trans_pcie->use_ict)) {
1208                 irqreturn_t ret = iwl_pcie_isr(irq, data);
1209                 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1210                 return ret;
1211         }
1212
1213         trace_iwlwifi_dev_irq(trans->dev);
1214
1215         /* Disable (but don't clear!) interrupts here to avoid
1216          * back-to-back ISRs and sporadic interrupts from our NIC.
1217          * If we have something to service, the tasklet will re-enable ints.
1218          * If we *don't* have something, we'll re-enable before leaving here.
1219          */
1220         inta_mask = iwl_read32(trans, CSR_INT_MASK);
1221         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1222
1223         /* Ignore interrupt if there's nothing in NIC to service.
1224          * This may be due to IRQ shared with another device,
1225          * or due to sporadic interrupts thrown from our NIC. */
1226         read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1227         trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
1228         if (!read) {
1229                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1230                 goto none;
1231         }
1232
1233         /*
1234          * Collect all entries up to the first 0, starting from ict_index;
1235          * note we already read at ict_index.
1236          */
1237         do {
1238                 val |= read;
1239                 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1240                                 trans_pcie->ict_index, read);
1241                 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1242                 trans_pcie->ict_index =
1243                         iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
1244
1245                 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1246                 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
1247                                            read);
1248         } while (read);
1249
1250         /* We should not get this value, just ignore it. */
1251         if (val == 0xffffffff)
1252                 val = 0;
1253
1254         /*
1255          * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1256          * (bit 15 before shifting it to 31) to clear when using interrupt
1257          * coalescing. fortunately, bits 18 and 19 stay set when this happens
1258          * so we use them to decide on the real state of the Rx bit.
1259          * In order words, bit 15 is set if bit 18 or bit 19 are set.
1260          */
1261         if (val & 0xC0000)
1262                 val |= 0x8000;
1263
1264         inta = (0xff & val) | ((0xff00 & val) << 16);
1265         IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1266                       inta, inta_mask, val);
1267
1268         inta &= trans_pcie->inta_mask;
1269         trans_pcie->inta |= inta;
1270
1271         /* iwl_pcie_tasklet() will service interrupts and re-enable them */
1272         if (likely(inta))
1273                 tasklet_schedule(&trans_pcie->irq_tasklet);
1274         else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1275                  !trans_pcie->inta) {
1276                 /* Allow interrupt if was disabled by this handler and
1277                  * no tasklet was schedules, We should not enable interrupt,
1278                  * tasklet will enable it.
1279                  */
1280                 iwl_enable_interrupts(trans);
1281         }
1282
1283         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1284         return IRQ_HANDLED;
1285
1286  none:
1287         /* re-enable interrupts here since we don't have anything to service.
1288          * only Re-enable if disabled by irq.
1289          */
1290         if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1291             !trans_pcie->inta)
1292                 iwl_enable_interrupts(trans);
1293
1294         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1295         return IRQ_NONE;
1296 }