drivers/net/wireless/rtlwifi/rtl8723ae/phy.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../pci.h"
  32 #include "../ps.h"
  33 #include "reg.h"
  34 #include "def.h"
  35 #include "phy.h"
  36 #include "rf.h"
  37 #include "dm.h"
  38 #include "table.h"
  39
  40 /* static forward definitions */
  41 static u32 _phy_fw_rf_serial_read(struct ieee80211_hw *hw,
  42                                   enum radio_path rfpath, u32 offset);
  43 static void _phy_fw_rf_serial_write(struct ieee80211_hw *hw,
  44                                     enum radio_path rfpath,
  45                                     u32 offset, u32 data);
  46 static u32 _phy_rf_serial_read(struct ieee80211_hw *hw,
  47                                enum radio_path rfpath, u32 offset);
  48 static void _phy_rf_serial_write(struct ieee80211_hw *hw,
  49                                  enum radio_path rfpath, u32 offset, u32 data);
  50 static u32 _phy_calculate_bit_shift(u32 bitmask);
  51 static bool _phy_bb8192c_config_parafile(struct ieee80211_hw *hw);
  52 static bool _phy_cfg_mac_w_header(struct ieee80211_hw *hw);
  53 static bool _phy_cfg_bb_w_header(struct ieee80211_hw *hw, u8 configtype);
  54 static bool _phy_cfg_bb_w_pgheader(struct ieee80211_hw *hw, u8 configtype);
  55 static void _phy_init_bb_rf_reg_def(struct ieee80211_hw *hw);
  56 static bool _phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
  57                                       u32 cmdtableidx, u32 cmdtablesz,
  58                                       enum swchnlcmd_id cmdid,
  59                                       u32 para1, u32 para2,
  60                                       u32 msdelay);
  61 static bool _phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, u8 channel,
  62                                       u8 *stage, u8 *step, u32 *delay);
  63 static u8 _phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw,
  64                                 enum wireless_mode wirelessmode,
  65                                 long power_indbm);
  66 static long _phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
  67                                   enum wireless_mode wirelessmode, u8 txpwridx);
  68 static void rtl8723ae_phy_set_io(struct ieee80211_hw *hw);
  69
  70 u32 rtl8723ae_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr,
  71                                u32 bitmask)
  72 {
  73         struct rtl_priv *rtlpriv = rtl_priv(hw);
  74         u32 returnvalue, originalvalue, bitshift;
  75
  76         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  77                  "regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask);
  78         originalvalue = rtl_read_dword(rtlpriv, regaddr);
  79         bitshift = _phy_calculate_bit_shift(bitmask);
  80         returnvalue = (originalvalue & bitmask) >> bitshift;
  81
  82         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  83                  "BBR MASK=0x%x Addr[0x%x]=0x%x\n", bitmask, regaddr,
  84                  originalvalue);
  85
  86         return returnvalue;
  87 }
  88
  89 void rtl8723ae_phy_set_bb_reg(struct ieee80211_hw *hw,
  90                               u32 regaddr, u32 bitmask, u32 data)
  91 {
  92         struct rtl_priv *rtlpriv = rtl_priv(hw);
  93         u32 originalvalue, bitshift;
  94
  95         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  96                  "regaddr(%#x), bitmask(%#x), data(%#x)\n", regaddr,
  97                  bitmask, data);
  98
  99         if (bitmask != MASKDWORD) {
 100                 originalvalue = rtl_read_dword(rtlpriv, regaddr);
 101                 bitshift = _phy_calculate_bit_shift(bitmask);
 102                 data = ((originalvalue & (~bitmask)) | (data << bitshift));
 103         }
 104
 105         rtl_write_dword(rtlpriv, regaddr, data);
 106
 107         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 108                  "regaddr(%#x), bitmask(%#x), data(%#x)\n",
 109                  regaddr, bitmask, data);
 110 }
 111
 112 u32 rtl8723ae_phy_query_rf_reg(struct ieee80211_hw *hw,
 113                                enum radio_path rfpath, u32 regaddr, u32 bitmask)
 114 {
 115         struct rtl_priv *rtlpriv = rtl_priv(hw);
 116         u32 original_value, readback_value, bitshift;
 117         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 118         unsigned long flags;
 119
 120         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 121                  "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
 122                  regaddr, rfpath, bitmask);
 123
 124         spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
 125
 126         if (rtlphy->rf_mode != RF_OP_BY_FW)
 127                 original_value = _phy_rf_serial_read(hw, rfpath, regaddr);
 128         else
 129                 original_value = _phy_fw_rf_serial_read(hw, rfpath, regaddr);
 130
 131         bitshift = _phy_calculate_bit_shift(bitmask);
 132         readback_value = (original_value & bitmask) >> bitshift;
 133
 134         spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
 135
 136         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 137                  "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
 138                  regaddr, rfpath, bitmask, original_value);
 139
 140         return readback_value;
 141 }
 142
 143 void rtl8723ae_phy_set_rf_reg(struct ieee80211_hw *hw,
 144                               enum radio_path rfpath,
 145                               u32 regaddr, u32 bitmask, u32 data)
 146 {
 147         struct rtl_priv *rtlpriv = rtl_priv(hw);
 148         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 149         u32 original_value, bitshift;
 150         unsigned long flags;
 151
 152         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 153                  "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 154                  regaddr, bitmask, data, rfpath);
 155
 156         spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
 157
 158         if (rtlphy->rf_mode != RF_OP_BY_FW) {
 159                 if (bitmask != RFREG_OFFSET_MASK) {
 160                         original_value = _phy_rf_serial_read(hw, rfpath,
 161                                                              regaddr);
 162                         bitshift = _phy_calculate_bit_shift(bitmask);
 163                         data = ((original_value & (~bitmask)) |
 164                                (data << bitshift));
 165                 }
 166
 167                 _phy_rf_serial_write(hw, rfpath, regaddr, data);
 168         } else {
 169                 if (bitmask != RFREG_OFFSET_MASK) {
 170                         original_value = _phy_fw_rf_serial_read(hw, rfpath,
 171                                                                 regaddr);
 172                         bitshift = _phy_calculate_bit_shift(bitmask);
 173                         data = ((original_value & (~bitmask)) |
 174                                (data << bitshift));
 175                 }
 176                 _phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
 177         }
 178
 179         spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
 180
 181         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 182                  "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 183                  regaddr, bitmask, data, rfpath);
 184 }
 185
 186 static u32 _phy_fw_rf_serial_read(struct ieee80211_hw *hw,
 187                                             enum radio_path rfpath, u32 offset)
 188 {
 189         RT_ASSERT(false, "deprecated!\n");
 190         return 0;
 191 }
 192
 193 static void _phy_fw_rf_serial_write(struct ieee80211_hw *hw,
 194                                     enum radio_path rfpath,
 195                                     u32 offset, u32 data)
 196 {
 197         RT_ASSERT(false, "deprecated!\n");
 198 }
 199
 200 static u32 _phy_rf_serial_read(struct ieee80211_hw *hw,
 201                                enum radio_path rfpath, u32 offset)
 202 {
 203         struct rtl_priv *rtlpriv = rtl_priv(hw);
 204         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 205         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
 206         u32 newoffset;
 207         u32 tmplong, tmplong2;
 208         u8 rfpi_enable = 0;
 209         u32 retvalue;
 210
 211         offset &= 0x3f;
 212         newoffset = offset;
 213         if (RT_CANNOT_IO(hw)) {
 214                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "return all one\n");
 215                 return 0xFFFFFFFF;
 216         }
 217         tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
 218         if (rfpath == RF90_PATH_A)
 219                 tmplong2 = tmplong;
 220         else
 221                 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
 222         tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
 223             (newoffset << 23) | BLSSIREADEDGE;
 224         rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
 225                       tmplong & (~BLSSIREADEDGE));
 226         mdelay(1);
 227         rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
 228         mdelay(1);
 229         rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
 230                       tmplong | BLSSIREADEDGE);
 231         mdelay(1);
 232         if (rfpath == RF90_PATH_A)
 233                 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
 234                                                  BIT(8));
 235         else if (rfpath == RF90_PATH_B)
 236                 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
 237                                                  BIT(8));
 238         if (rfpi_enable)
 239                 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
 240                                          BLSSIREADBACKDATA);
 241         else
 242                 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
 243                                          BLSSIREADBACKDATA);
 244         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n",
 245                  rfpath, pphyreg->rf_rb, retvalue);
 246         return retvalue;
 247 }
 248
 249 static void _phy_rf_serial_write(struct ieee80211_hw *hw,
 250                                  enum radio_path rfpath, u32 offset, u32 data)
 251 {
 252         u32 data_and_addr;
 253         u32 newoffset;
 254         struct rtl_priv *rtlpriv = rtl_priv(hw);
 255         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 256         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
 257
 258         if (RT_CANNOT_IO(hw)) {
 259                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "stop\n");
 260                 return;
 261         }
 262         offset &= 0x3f;
 263         newoffset = offset;
 264         data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
 265         rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
 266         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
 267                  rfpath, pphyreg->rf3wire_offset, data_and_addr);
 268 }
 269
 270 static u32 _phy_calculate_bit_shift(u32 bitmask)
 271 {
 272         u32 i;
 273
 274         for (i = 0; i <= 31; i++) {
 275                 if (((bitmask >> i) & 0x1) == 1)
 276                         break;
 277         }
 278         return i;
 279 }
 280
 281 static void _rtl8723ae_phy_bb_config_1t(struct ieee80211_hw *hw)
 282 {
 283         rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2);
 284         rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022);
 285         rtl_set_bbreg(hw, RCCK0_AFESETTING, MASKBYTE3, 0x45);
 286         rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23);
 287         rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, 0x30, 0x1);
 288         rtl_set_bbreg(hw, 0xe74, 0x0c000000, 0x2);
 289         rtl_set_bbreg(hw, 0xe78, 0x0c000000, 0x2);
 290         rtl_set_bbreg(hw, 0xe7c, 0x0c000000, 0x2);
 291         rtl_set_bbreg(hw, 0xe80, 0x0c000000, 0x2);
 292         rtl_set_bbreg(hw, 0xe88, 0x0c000000, 0x2);
 293 }
 294
 295 bool rtl8723ae_phy_mac_config(struct ieee80211_hw *hw)
 296 {
 297         struct rtl_priv *rtlpriv = rtl_priv(hw);
 298         bool rtstatus = _phy_cfg_mac_w_header(hw);
 299         rtl_write_byte(rtlpriv, 0x04CA, 0x0A);
 300         return rtstatus;
 301 }
 302
 303 bool rtl8723ae_phy_bb_config(struct ieee80211_hw *hw)
 304 {
 305         bool rtstatus = true;
 306         struct rtl_priv *rtlpriv = rtl_priv(hw);
 307         u8 tmpu1b;
 308         u8 reg_hwparafile = 1;
 309
 310         _phy_init_bb_rf_reg_def(hw);
 311
 312         /* 1. 0x28[1] = 1 */
 313         tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_PLL_CTRL);
 314         udelay(2);
 315         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, (tmpu1b|BIT(1)));
 316         udelay(2);
 317         /* 2. 0x29[7:0] = 0xFF */
 318         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL+1, 0xff);
 319         udelay(2);
 320
 321         /* 3. 0x02[1:0] = 2b'11 */
 322         tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
 323         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, (tmpu1b |
 324                        FEN_BB_GLB_RSTn | FEN_BBRSTB));
 325
 326         /* 4. 0x25[6] = 0 */
 327         tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+1);
 328         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+1, (tmpu1b&(~BIT(6))));
 329
 330         /* 5. 0x24[20] = 0      Advised by SD3 Alex Wang. 2011.02.09. */
 331         tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2);
 332         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, (tmpu1b&(~BIT(4))));
 333
 334         /* 6. 0x1f[7:0] = 0x07 */
 335         rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x07);
 336
 337         if (reg_hwparafile == 1)
 338                 rtstatus = _phy_bb8192c_config_parafile(hw);
 339         return rtstatus;
 340 }
 341
 342 bool rtl8723ae_phy_rf_config(struct ieee80211_hw *hw)
 343 {
 344         return rtl8723ae_phy_rf6052_config(hw);
 345 }
 346
 347 static bool _phy_bb8192c_config_parafile(struct ieee80211_hw *hw)
 348 {
 349         struct rtl_priv *rtlpriv = rtl_priv(hw);
 350         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 351         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 352         bool rtstatus;
 353
 354         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "==>\n");
 355         rtstatus = _phy_cfg_bb_w_header(hw, BASEBAND_CONFIG_PHY_REG);
 356         if (rtstatus != true) {
 357                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Write BB Reg Fail!!");
 358                 return false;
 359         }
 360
 361         if (rtlphy->rf_type == RF_1T2R) {
 362                 _rtl8723ae_phy_bb_config_1t(hw);
 363                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n");
 364         }
 365         if (rtlefuse->autoload_failflag == false) {
 366                 rtlphy->pwrgroup_cnt = 0;
 367                 rtstatus = _phy_cfg_bb_w_pgheader(hw, BASEBAND_CONFIG_PHY_REG);
 368         }
 369         if (rtstatus != true) {
 370                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!");
 371                 return false;
 372         }
 373         rtstatus = _phy_cfg_bb_w_header(hw, BASEBAND_CONFIG_AGC_TAB);
 374         if (rtstatus != true) {
 375                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n");
 376                 return false;
 377         }
 378         rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
 379                                          RFPGA0_XA_HSSIPARAMETER2, 0x200));
 380         return true;
 381 }
 382
 383 static bool _phy_cfg_mac_w_header(struct ieee80211_hw *hw)
 384 {
 385         struct rtl_priv *rtlpriv = rtl_priv(hw);
 386         u32 i;
 387         u32 arraylength;
 388         u32 *ptrarray;
 389
 390         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl723MACPHY_Array\n");
 391         arraylength = RTL8723E_MACARRAYLENGTH;
 392         ptrarray = RTL8723EMAC_ARRAY;
 393
 394         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 395                  "Img:RTL8192CEMAC_2T_ARRAY\n");
 396         for (i = 0; i < arraylength; i = i + 2)
 397                 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
 398         return true;
 399 }
 400
 401 static bool _phy_cfg_bb_w_header(struct ieee80211_hw *hw, u8 configtype)
 402 {
 403         int i;
 404         u32 *phy_regarray_table;
 405         u32 *agctab_array_table;
 406         u16 phy_reg_arraylen, agctab_arraylen;
 407         struct rtl_priv *rtlpriv = rtl_priv(hw);
 408
 409         agctab_arraylen = RTL8723E_AGCTAB_1TARRAYLENGTH;
 410         agctab_array_table = RTL8723EAGCTAB_1TARRAY;
 411         phy_reg_arraylen = RTL8723E_PHY_REG_1TARRAY_LENGTH;
 412         phy_regarray_table = RTL8723EPHY_REG_1TARRAY;
 413         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 414                 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
 415                         if (phy_regarray_table[i] == 0xfe)
 416                                 mdelay(50);
 417                         else if (phy_regarray_table[i] == 0xfd)
 418                                 mdelay(5);
 419                         else if (phy_regarray_table[i] == 0xfc)
 420                                 mdelay(1);
 421                         else if (phy_regarray_table[i] == 0xfb)
 422                                 udelay(50);
 423                         else if (phy_regarray_table[i] == 0xfa)
 424                                 udelay(5);
 425                         else if (phy_regarray_table[i] == 0xf9)
 426                                 udelay(1);
 427                         rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
 428                                       phy_regarray_table[i + 1]);
 429                         udelay(1);
 430                         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 431                                  "The phy_regarray_table[0] is %x"
 432                                  " Rtl819XPHY_REGArray[1] is %x\n",
 433                                  phy_regarray_table[i],
 434                                  phy_regarray_table[i + 1]);
 435                 }
 436         } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
 437                 for (i = 0; i < agctab_arraylen; i = i + 2) {
 438                         rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
 439                                       agctab_array_table[i + 1]);
 440                         udelay(1);
 441                         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 442                                  "The agctab_array_table[0] is "
 443                                  "%x Rtl819XPHY_REGArray[1] is %x\n",
 444                                  agctab_array_table[i],
 445                                  agctab_array_table[i + 1]);
 446                 }
 447         }
 448         return true;
 449 }
 450
 451 static void _st_pwrIdx_dfrate_off(struct ieee80211_hw *hw, u32 regaddr,
 452                                   u32 bitmask, u32 data)
 453 {
 454         struct rtl_priv *rtlpriv = rtl_priv(hw);
 455         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 456
 457         switch (regaddr) {
 458         case RTXAGC_A_RATE18_06:
 459                 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][0] = data;
 460                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 461                          "MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n",
 462                          rtlphy->pwrgroup_cnt,
 463                 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][0]);
 464                 break;
 465         case RTXAGC_A_RATE54_24:
 466                 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][1] = data;
 467                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 468                          "MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n",
 469                          rtlphy->pwrgroup_cnt,
 470                          rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][1]);
 471                 break;
 472         case RTXAGC_A_CCK1_MCS32:
 473                 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][6] = data;
 474                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 475                          "MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n",
 476                          rtlphy->pwrgroup_cnt,
 477                          rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][6]);
 478                 break;
 479         case RTXAGC_B_CCK11_A_CCK2_11:
 480                 if (bitmask == 0xffffff00) {
 481                         rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][7] = data;
 482                         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 483                                  "MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n",
 484                                  rtlphy->pwrgroup_cnt,
 485                                  rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][7]);
 486                 }
 487                 if (bitmask == 0x000000ff) {
 488                         rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][15] = data;
 489                         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 490                                  "MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n",
 491                                  rtlphy->pwrgroup_cnt,
 492                                  rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][15]);
 493                 }
 494                 break;
 495         case RTXAGC_A_MCS03_MCS00:
 496                 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][2] = data;
 497                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 498                          "MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n",
 499                          rtlphy->pwrgroup_cnt,
 500                          rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][2]);
 501                 break;
 502         case RTXAGC_A_MCS07_MCS04:
 503                 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][3] = data;
 504                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 505                          "MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n",
 506                          rtlphy->pwrgroup_cnt,
 507                          rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][3]);
 508                 break;
 509         case RTXAGC_A_MCS11_MCS08:
 510                 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][4] = data;
 511                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 512                          "MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n",
 513                          rtlphy->pwrgroup_cnt,
 514                          rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][4]);
 515                 break;
 516         case RTXAGC_A_MCS15_MCS12:
 517                 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][5] = data;
 518                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 519                          "MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n",
 520                          rtlphy->pwrgroup_cnt,
 521                          rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][5]);
 522                 break;
 523         case RTXAGC_B_RATE18_06:
 524                 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][8] = data;
 525                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 526                          "MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n",
 527                          rtlphy->pwrgroup_cnt,
 528                          rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][8]);
 529                 break;
 530         case RTXAGC_B_RATE54_24:
 531                 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][9] = data;
 532                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 533                          "MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n",
 534                          rtlphy->pwrgroup_cnt,
 535                          rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][9]);
 536                 break;
 537         case RTXAGC_B_CCK1_55_MCS32:
 538                 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][14] = data;
 539                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 540                          "MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n",
 541                          rtlphy->pwrgroup_cnt,
 542                          rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][14]);
 543                 break;
 544         case RTXAGC_B_MCS03_MCS00:
 545                 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][10] = data;
 546                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 547                          "MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n",
 548                          rtlphy->pwrgroup_cnt,
 549                          rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][10]);
 550                 break;
 551         case RTXAGC_B_MCS07_MCS04:
 552                 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][11] = data;
 553                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 554                          "MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n",
 555                          rtlphy->pwrgroup_cnt,
 556                          rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][11]);
 557                 break;
 558         case RTXAGC_B_MCS11_MCS08:
 559                 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][12] = data;
 560                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 561                          "MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n",
 562                          rtlphy->pwrgroup_cnt,
 563                          rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][12]);
 564                 break;
 565         case RTXAGC_B_MCS15_MCS12:
 566                 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][13] = data;
 567                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 568                          "MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n",
 569                          rtlphy->pwrgroup_cnt,
 570                          rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][13]);
 571                 rtlphy->pwrgroup_cnt++;
 572                 break;
 573         }
 574 }
 575
 576 static bool _phy_cfg_bb_w_pgheader(struct ieee80211_hw *hw, u8 configtype)
 577 {
 578         struct rtl_priv *rtlpriv = rtl_priv(hw);
 579         int i;
 580         u32 *phy_regarray_table_pg;
 581         u16 phy_regarray_pg_len;
 582
 583         phy_regarray_pg_len = RTL8723E_PHY_REG_ARRAY_PGLENGTH;
 584         phy_regarray_table_pg = RTL8723EPHY_REG_ARRAY_PG;
 585
 586         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 587                 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
 588                         if (phy_regarray_table_pg[i] == 0xfe)
 589                                 mdelay(50);
 590                         else if (phy_regarray_table_pg[i] == 0xfd)
 591                                 mdelay(5);
 592                         else if (phy_regarray_table_pg[i] == 0xfc)
 593                                 mdelay(1);
 594                         else if (phy_regarray_table_pg[i] == 0xfb)
 595                                 udelay(50);
 596                         else if (phy_regarray_table_pg[i] == 0xfa)
 597                                 udelay(5);
 598                         else if (phy_regarray_table_pg[i] == 0xf9)
 599                                 udelay(1);
 600
 601                         _st_pwrIdx_dfrate_off(hw, phy_regarray_table_pg[i],
 602                                               phy_regarray_table_pg[i + 1],
 603                                               phy_regarray_table_pg[i + 2]);
 604                 }
 605         } else {
 606                 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
 607                          "configtype != BaseBand_Config_PHY_REG\n");
 608         }
 609         return true;
 610 }
 611
 612 bool rtl8723ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
 613                                              enum radio_path rfpath)
 614 {
 615         struct rtl_priv *rtlpriv = rtl_priv(hw);
 616         int i;
 617         bool rtstatus = true;
 618         u32 *radioa_array_table;
 619         u32 *radiob_array_table;
 620         u16 radioa_arraylen, radiob_arraylen;
 621
 622         radioa_arraylen = Rtl8723ERADIOA_1TARRAYLENGTH;
 623         radioa_array_table = RTL8723E_RADIOA_1TARRAY;
 624         radiob_arraylen = RTL8723E_RADIOB_1TARRAYLENGTH;
 625         radiob_array_table = RTL8723E_RADIOB_1TARRAY;
 626
 627         rtstatus = true;
 628
 629         switch (rfpath) {
 630         case RF90_PATH_A:
 631                 for (i = 0; i < radioa_arraylen; i = i + 2) {
 632                         if (radioa_array_table[i] == 0xfe)
 633                                 mdelay(50);
 634                         else if (radioa_array_table[i] == 0xfd)
 635                                 mdelay(5);
 636                         else if (radioa_array_table[i] == 0xfc)
 637                                 mdelay(1);
 638                         else if (radioa_array_table[i] == 0xfb)
 639                                 udelay(50);
 640                         else if (radioa_array_table[i] == 0xfa)
 641                                 udelay(5);
 642                         else if (radioa_array_table[i] == 0xf9)
 643                                 udelay(1);
 644                         else {
 645                                 rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
 646                                               RFREG_OFFSET_MASK,
 647                                               radioa_array_table[i + 1]);
 648                                 udelay(1);
 649                         }
 650                 }
 651                 break;
 652         case RF90_PATH_B:
 653                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 654                          "switch case not process\n");
 655                 break;
 656         case RF90_PATH_C:
 657                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 658                          "switch case not process\n");
 659                 break;
 660         case RF90_PATH_D:
 661                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 662                          "switch case not process\n");
 663                 break;
 664         }
 665         return true;
 666 }
 667
 668 void rtl8723ae_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
 669 {
 670         struct rtl_priv *rtlpriv = rtl_priv(hw);
 671         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 672
 673         rtlphy->default_initialgain[0] =
 674             (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
 675         rtlphy->default_initialgain[1] =
 676             (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
 677         rtlphy->default_initialgain[2] =
 678             (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
 679         rtlphy->default_initialgain[3] =
 680             (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
 681
 682         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 683                  "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
 684                   rtlphy->default_initialgain[0],
 685                   rtlphy->default_initialgain[1],
 686                   rtlphy->default_initialgain[2],
 687                   rtlphy->default_initialgain[3]);
 688
 689         rtlphy->framesync = (u8) rtl_get_bbreg(hw,
 690                                                ROFDM0_RXDETECTOR3, MASKBYTE0);
 691         rtlphy->framesync_c34 = rtl_get_bbreg(hw,
 692                                               ROFDM0_RXDETECTOR2, MASKDWORD);
 693
 694         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 695                  "Default framesync (0x%x) = 0x%x\n",
 696                  ROFDM0_RXDETECTOR3, rtlphy->framesync);
 697 }
 698
 699 static void _phy_init_bb_rf_reg_def(struct ieee80211_hw *hw)
 700 {
 701         struct rtl_priv *rtlpriv = rtl_priv(hw);
 702         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 703
 704         rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
 705         rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
 706         rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
 707         rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
 708
 709         rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
 710         rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
 711         rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
 712         rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
 713
 714         rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
 715         rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
 716
 717         rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
 718         rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
 719
 720         rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
 721                             RFPGA0_XA_LSSIPARAMETER;
 722         rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
 723                             RFPGA0_XB_LSSIPARAMETER;
 724
 725         rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = rFPGA0_XAB_RFPARAMETER;
 726         rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = rFPGA0_XAB_RFPARAMETER;
 727         rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = rFPGA0_XCD_RFPARAMETER;
 728         rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = rFPGA0_XCD_RFPARAMETER;
 729
 730         rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 731         rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 732         rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 733         rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 734
 735         rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
 736         rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
 737
 738         rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
 739         rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
 740
 741         rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
 742         rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
 743         rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
 744         rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
 745
 746         rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
 747         rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
 748         rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
 749         rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
 750
 751         rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
 752         rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
 753         rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
 754         rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
 755
 756         rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
 757         rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
 758         rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE;
 759         rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
 760
 761         rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
 762         rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
 763         rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
 764         rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
 765
 766         rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
 767         rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
 768         rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
 769         rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
 770
 771         rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
 772         rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
 773         rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
 774         rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
 775
 776         rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
 777         rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
 778         rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
 779         rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
 780
 781         rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;
 782         rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;
 783 }
 784
 785 void rtl8723ae_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
 786 {
 787         struct rtl_priv *rtlpriv = rtl_priv(hw);
 788         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 789         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 790         u8 txpwr_level;
 791         long txpwr_dbm;
 792
 793         txpwr_level = rtlphy->cur_cck_txpwridx;
 794         txpwr_dbm = _phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_B, txpwr_level);
 795         txpwr_level = rtlphy->cur_ofdm24g_txpwridx +
 796             rtlefuse->legacy_ht_txpowerdiff;
 797         if (_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, txpwr_level) > txpwr_dbm)
 798                 txpwr_dbm = _phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
 799                                                   txpwr_level);
 800         txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
 801         if (_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G, txpwr_level) >
 802             txpwr_dbm)
 803                 txpwr_dbm = _phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
 804                                                   txpwr_level);
 805         *powerlevel = txpwr_dbm;
 806 }
 807
 808 static void _rtl8723ae_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
 809                                          u8 *cckpowerlevel, u8 *ofdmpowerlevel)
 810 {
 811         struct rtl_priv *rtlpriv = rtl_priv(hw);
 812         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 813         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 814         u8 index = (channel - 1);
 815
 816         cckpowerlevel[RF90_PATH_A] =
 817             rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
 818         cckpowerlevel[RF90_PATH_B] =
 819             rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
 820         if (get_rf_type(rtlphy) == RF_1T2R || get_rf_type(rtlphy) == RF_1T1R) {
 821                 ofdmpowerlevel[RF90_PATH_A] =
 822                     rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
 823                 ofdmpowerlevel[RF90_PATH_B] =
 824                     rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
 825         } else if (get_rf_type(rtlphy) == RF_2T2R) {
 826                 ofdmpowerlevel[RF90_PATH_A] =
 827                     rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
 828                 ofdmpowerlevel[RF90_PATH_B] =
 829                     rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
 830         }
 831 }
 832
 833 static void _rtl8723ae_ccxpower_index_check(struct ieee80211_hw *hw,
 834                                             u8 channel, u8 *cckpowerlevel,
 835                                             u8 *ofdmpowerlevel)
 836 {
 837         struct rtl_priv *rtlpriv = rtl_priv(hw);
 838         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 839
 840         rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
 841         rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
 842 }
 843
 844 void rtl8723ae_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
 845 {
 846         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 847         u8 cckpowerlevel[2], ofdmpowerlevel[2];
 848
 849         if (rtlefuse->txpwr_fromeprom == false)
 850                 return;
 851         _rtl8723ae_get_txpower_index(hw, channel, &cckpowerlevel[0],
 852                                      &ofdmpowerlevel[0]);
 853         _rtl8723ae_ccxpower_index_check(hw, channel, &cckpowerlevel[0],
 854                                         &ofdmpowerlevel[0]);
 855         rtl8723ae_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
 856         rtl8723ae_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel);
 857 }
 858
 859 bool rtl8723ae_phy_update_txpower_dbm(struct ieee80211_hw *hw, long power_indbm)
 860 {
 861         struct rtl_priv *rtlpriv = rtl_priv(hw);
 862         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 863         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 864         u8 idx;
 865         u8 rf_path;
 866         u8 ccktxpwridx = _phy_dbm_to_txpwr_Idx(hw, WIRELESS_MODE_B,
 867                                                power_indbm);
 868         u8 ofdmtxpwridx = _phy_dbm_to_txpwr_Idx(hw, WIRELESS_MODE_N_24G,
 869                                                 power_indbm);
 870         if (ofdmtxpwridx - rtlefuse->legacy_ht_txpowerdiff > 0)
 871                 ofdmtxpwridx -= rtlefuse->legacy_ht_txpowerdiff;
 872         else
 873                 ofdmtxpwridx = 0;
 874         RT_TRACE(rtlpriv, COMP_TXAGC, DBG_TRACE,
 875                  "%lx dBm, ccktxpwridx = %d, ofdmtxpwridx = %d\n",
 876                  power_indbm, ccktxpwridx, ofdmtxpwridx);
 877         for (idx = 0; idx < 14; idx++) {
 878                 for (rf_path = 0; rf_path < 2; rf_path++) {
 879                         rtlefuse->txpwrlevel_cck[rf_path][idx] = ccktxpwridx;
 880                         rtlefuse->txpwrlevel_ht40_1s[rf_path][idx] =
 881                                                             ofdmtxpwridx;
 882                         rtlefuse->txpwrlevel_ht40_2s[rf_path][idx] =
 883                                                             ofdmtxpwridx;
 884                 }
 885         }
 886         rtl8723ae_phy_set_txpower_level(hw, rtlphy->current_channel);
 887         return true;
 888 }
 889
 890 static u8 _phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw,
 891                                 enum wireless_mode wirelessmode,
 892                                 long power_indbm)
 893 {
 894         u8 txpwridx;
 895         long offset;
 896
 897         switch (wirelessmode) {
 898         case WIRELESS_MODE_B:
 899                 offset = -7;
 900                 break;
 901         case WIRELESS_MODE_G:
 902         case WIRELESS_MODE_N_24G:
 903                 offset = -8;
 904                 break;
 905         default:
 906                 offset = -8;
 907                 break;
 908         }
 909
 910         if ((power_indbm - offset) > 0)
 911                 txpwridx = (u8) ((power_indbm - offset) * 2);
 912         else
 913                 txpwridx = 0;
 914
 915         if (txpwridx > MAX_TXPWR_IDX_NMODE_92S)
 916                 txpwridx = MAX_TXPWR_IDX_NMODE_92S;
 917
 918         return txpwridx;
 919 }
 920
 921 static long _phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
 922                                   enum wireless_mode wirelessmode, u8 txpwridx)
 923 {
 924         long offset;
 925         long pwrout_dbm;
 926
 927         switch (wirelessmode) {
 928         case WIRELESS_MODE_B:
 929                 offset = -7;
 930                 break;
 931         case WIRELESS_MODE_G:
 932         case WIRELESS_MODE_N_24G:
 933                 offset = -8;
 934                 break;
 935         default:
 936                 offset = -8;
 937                 break;
 938         }
 939         pwrout_dbm = txpwridx / 2 + offset;
 940         return pwrout_dbm;
 941 }
 942
 943 void rtl8723ae_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
 944 {
 945         struct rtl_priv *rtlpriv = rtl_priv(hw);
 946         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 947         enum io_type iotype;
 948
 949         if (!is_hal_stop(rtlhal)) {
 950                 switch (operation) {
 951                 case SCAN_OPT_BACKUP:
 952                         iotype = IO_CMD_PAUSE_DM_BY_SCAN;
 953                         rtlpriv->cfg->ops->set_hw_reg(hw,
 954                                                       HW_VAR_IO_CMD,
 955                                                       (u8 *)&iotype);
 956
 957                         break;
 958                 case SCAN_OPT_RESTORE:
 959                         iotype = IO_CMD_RESUME_DM_BY_SCAN;
 960                         rtlpriv->cfg->ops->set_hw_reg(hw,
 961                                                       HW_VAR_IO_CMD,
 962                                                       (u8 *)&iotype);
 963                         break;
 964                 default:
 965                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 966                                  "Unknown Scan Backup operation.\n");
 967                         break;
 968                 }
 969         }
 970 }
 971
 972 void rtl8723ae_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
 973 {
 974         struct rtl_priv *rtlpriv = rtl_priv(hw);
 975         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 976         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 977         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 978         u8 reg_bw_opmode;
 979         u8 reg_prsr_rsc;
 980
 981         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
 982                  "Switch to %s bandwidth\n",
 983                  rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
 984                  "20MHz" : "40MHz");
 985
 986         if (is_hal_stop(rtlhal)) {
 987                 rtlphy->set_bwmode_inprogress = false;
 988                 return;
 989         }
 990
 991         reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
 992         reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
 993
 994         switch (rtlphy->current_chan_bw) {
 995         case HT_CHANNEL_WIDTH_20:
 996                 reg_bw_opmode |= BW_OPMODE_20MHZ;
 997                 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 998                 break;
 999         case HT_CHANNEL_WIDTH_20_40:
1000                 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
1001                 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1002                 reg_prsr_rsc =
1003                     (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
1004                 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
1005                 break;
1006         default:
1007                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1008                          "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
1009                 break;
1010         }
1011
1012         switch (rtlphy->current_chan_bw) {
1013         case HT_CHANNEL_WIDTH_20:
1014                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
1015                 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
1016                 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
1017                 break;
1018         case HT_CHANNEL_WIDTH_20_40:
1019                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
1020                 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
1021
1022                 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
1023                               (mac->cur_40_prime_sc >> 1));
1024                 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
1025                 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
1026
1027                 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
1028                               (mac->cur_40_prime_sc ==
1029                                HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
1030                 break;
1031         default:
1032                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1033                          "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
1034                 break;
1035         }
1036         rtl8723ae_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1037         rtlphy->set_bwmode_inprogress = false;
1038         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
1039 }
1040
1041 void rtl8723ae_phy_set_bw_mode(struct ieee80211_hw *hw,
1042                                enum nl80211_channel_type ch_type)
1043 {
1044         struct rtl_priv *rtlpriv = rtl_priv(hw);
1045         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1046         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1047         u8 tmp_bw = rtlphy->current_chan_bw;
1048
1049         if (rtlphy->set_bwmode_inprogress)
1050                 return;
1051         rtlphy->set_bwmode_inprogress = true;
1052         if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1053                 rtl8723ae_phy_set_bw_mode_callback(hw);
1054         } else {
1055                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1056                          "FALSE driver sleep or unload\n");
1057                 rtlphy->set_bwmode_inprogress = false;
1058                 rtlphy->current_chan_bw = tmp_bw;
1059         }
1060 }
1061
1062 void rtl8723ae_phy_sw_chnl_callback(struct ieee80211_hw *hw)
1063 {
1064         struct rtl_priv *rtlpriv = rtl_priv(hw);
1065         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1066         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1067         u32 delay;
1068
1069         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
1070                  "switch to channel%d\n", rtlphy->current_channel);
1071         if (is_hal_stop(rtlhal))
1072                 return;
1073         do {
1074                 if (!rtlphy->sw_chnl_inprogress)
1075                         break;
1076                 if (!_phy_sw_chnl_step_by_step
1077                     (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
1078                      &rtlphy->sw_chnl_step, &delay)) {
1079                         if (delay > 0)
1080                                 mdelay(delay);
1081                         else
1082                                 continue;
1083                 } else {
1084                         rtlphy->sw_chnl_inprogress = false;
1085                 }
1086                 break;
1087         } while (true);
1088         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
1089 }
1090
1091 u8 rtl8723ae_phy_sw_chnl(struct ieee80211_hw *hw)
1092 {
1093         struct rtl_priv *rtlpriv = rtl_priv(hw);
1094         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1095         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1096
1097         if (rtlphy->sw_chnl_inprogress)
1098                 return 0;
1099         if (rtlphy->set_bwmode_inprogress)
1100                 return 0;
1101         RT_ASSERT((rtlphy->current_channel <= 14),
1102                   "WIRELESS_MODE_G but channel>14");
1103         rtlphy->sw_chnl_inprogress = true;
1104         rtlphy->sw_chnl_stage = 0;
1105         rtlphy->sw_chnl_step = 0;
1106         if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1107                 rtl8723ae_phy_sw_chnl_callback(hw);
1108                 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
1109                          "sw_chnl_inprogress false schedule workitem\n");
1110                 rtlphy->sw_chnl_inprogress = false;
1111         } else {
1112                 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
1113                          "sw_chnl_inprogress false driver sleep or unload\n");
1114                 rtlphy->sw_chnl_inprogress = false;
1115         }
1116         return 1;
1117 }
1118
1119 static void _rtl8723ae_phy_sw_rf_seting(struct ieee80211_hw *hw, u8 channel)
1120 {
1121         struct rtl_priv *rtlpriv = rtl_priv(hw);
1122         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1123         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1124
1125         if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) {
1126                 if (channel == 6 && rtlphy->current_chan_bw ==
1127                     HT_CHANNEL_WIDTH_20)
1128                         rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD,
1129                                       0x00255);
1130                 else{
1131                         u32 backupRF0x1A = (u32)rtl_get_rfreg(hw, RF90_PATH_A,
1132                                            RF_RX_G1, RFREG_OFFSET_MASK);
1133                         rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD,
1134                                       backupRF0x1A);
1135                 }
1136         }
1137 }
1138
1139 static bool _phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, u8 channel,
1140                                       u8 *stage, u8 *step, u32 *delay)
1141 {
1142         struct rtl_priv *rtlpriv = rtl_priv(hw);
1143         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1144         struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
1145         u32 precommoncmdcnt;
1146         struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
1147         u32 postcommoncmdcnt;
1148         struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
1149         u32 rfdependcmdcnt;
1150         struct swchnlcmd *currentcmd = NULL;
1151         u8 rfpath;
1152         u8 num_total_rfpath = rtlphy->num_total_rfpath;
1153
1154         precommoncmdcnt = 0;
1155         _phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
1156                                   MAX_PRECMD_CNT, CMDID_SET_TXPOWEROWER_LEVEL,
1157                                   0, 0, 0);
1158         _phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
1159                                   MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
1160         postcommoncmdcnt = 0;
1161
1162         _phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
1163                                   MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
1164         rfdependcmdcnt = 0;
1165
1166         RT_ASSERT((channel >= 1 && channel <= 14),
1167                   "illegal channel for Zebra: %d\n", channel);
1168
1169         _phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
1170                                   MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
1171                                   RF_CHNLBW, channel, 10);
1172
1173         _phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
1174                                   MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, 0);
1175
1176         do {
1177                 switch (*stage) {
1178                 case 0:
1179                         currentcmd = &precommoncmd[*step];
1180                         break;
1181                 case 1:
1182                         currentcmd = &rfdependcmd[*step];
1183                         break;
1184                 case 2:
1185                         currentcmd = &postcommoncmd[*step];
1186                         break;
1187                 }
1188
1189                 if (currentcmd->cmdid == CMDID_END) {
1190                         if ((*stage) == 2) {
1191                                 return true;
1192                         } else {
1193                                 (*stage)++;
1194                                 (*step) = 0;
1195                                 continue;
1196                         }
1197                 }
1198
1199                 switch (currentcmd->cmdid) {
1200                 case CMDID_SET_TXPOWEROWER_LEVEL:
1201                         rtl8723ae_phy_set_txpower_level(hw, channel);
1202                         break;
1203                 case CMDID_WRITEPORT_ULONG:
1204                         rtl_write_dword(rtlpriv, currentcmd->para1,
1205                                         currentcmd->para2);
1206                         break;
1207                 case CMDID_WRITEPORT_USHORT:
1208                         rtl_write_word(rtlpriv, currentcmd->para1,
1209                                        (u16) currentcmd->para2);
1210                         break;
1211                 case CMDID_WRITEPORT_UCHAR:
1212                         rtl_write_byte(rtlpriv, currentcmd->para1,
1213                                        (u8) currentcmd->para2);
1214                         break;
1215                 case CMDID_RF_WRITEREG:
1216                         for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
1217                                 rtlphy->rfreg_chnlval[rfpath] =
1218                                     ((rtlphy->rfreg_chnlval[rfpath] &
1219                                       0xfffffc00) | currentcmd->para2);
1220
1221                                 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1222                                               currentcmd->para1,
1223                                               RFREG_OFFSET_MASK,
1224                                               rtlphy->rfreg_chnlval[rfpath]);
1225                         }
1226                         _rtl8723ae_phy_sw_rf_seting(hw, channel);
1227                         break;
1228                 default:
1229                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1230                                  "switch case not process\n");
1231                         break;
1232                 }
1233
1234                 break;
1235         } while (true);
1236
1237         (*delay) = currentcmd->msdelay;
1238         (*step)++;
1239         return false;
1240 }
1241
1242 static bool _phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
1243                                       u32 cmdtableidx, u32 cmdtablesz,
1244                                       enum swchnlcmd_id cmdid, u32 para1,
1245                                       u32 para2, u32 msdelay)
1246 {
1247         struct swchnlcmd *pcmd;
1248
1249         if (cmdtable == NULL) {
1250                 RT_ASSERT(false, "cmdtable cannot be NULL.\n");
1251                 return false;
1252         }
1253
1254         if (cmdtableidx >= cmdtablesz)
1255                 return false;
1256
1257         pcmd = cmdtable + cmdtableidx;
1258         pcmd->cmdid = cmdid;
1259         pcmd->para1 = para1;
1260         pcmd->para2 = para2;
1261         pcmd->msdelay = msdelay;
1262         return true;
1263 }
1264
1265 static u8 _rtl8723ae_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
1266 {
1267         u32 reg_eac, reg_e94, reg_e9c, reg_ea4;
1268         u8 result = 0x00;
1269
1270         rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
1271         rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
1272         rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
1273         rtl_set_bbreg(hw, 0xe3c, MASKDWORD,
1274                       config_pathb ? 0x28160202 : 0x28160502);
1275
1276         if (config_pathb) {
1277                 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
1278                 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
1279                 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
1280                 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160202);
1281         }
1282
1283         rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x001028d1);
1284         rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1285         rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1286
1287         mdelay(IQK_DELAY_TIME);
1288
1289         reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1290         reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1291         reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1292         reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1293
1294         if (!(reg_eac & BIT(28)) &&
1295             (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1296             (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1297                 result |= 0x01;
1298         else
1299                 return result;
1300
1301         if (!(reg_eac & BIT(27)) &&
1302             (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
1303             (((reg_eac & 0x03FF0000) >> 16) != 0x36))
1304                 result |= 0x02;
1305         return result;
1306 }
1307
1308 static u8 _rtl8723ae_phy_path_b_iqk(struct ieee80211_hw *hw)
1309 {
1310         u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
1311         u8 result = 0x00;
1312
1313         rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
1314         rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
1315         mdelay(IQK_DELAY_TIME);
1316         reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1317         reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1318         reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1319         reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1320         reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1321
1322         if (!(reg_eac & BIT(31)) &&
1323             (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
1324             (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
1325                 result |= 0x01;
1326         else
1327                 return result;
1328         if (!(reg_eac & BIT(30)) &&
1329             (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
1330             (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
1331                 result |= 0x02;
1332         return result;
1333 }
1334
1335 static void phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw, bool iqk_ok,
1336                                        long result[][8], u8 final_candidate,
1337                                        bool btxonly)
1338 {
1339         u32 oldval_0, x, tx0_a, reg;
1340         long y, tx0_c;
1341
1342         if (final_candidate == 0xFF) {
1343                 return;
1344         } else if (iqk_ok) {
1345                 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
1346                                           MASKDWORD) >> 22) & 0x3FF;
1347                 x = result[final_candidate][0];
1348                 if ((x & 0x00000200) != 0)
1349                         x = x | 0xFFFFFC00;
1350                 tx0_a = (x * oldval_0) >> 8;
1351                 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
1352                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
1353                               ((x * oldval_0 >> 7) & 0x1));
1354                 y = result[final_candidate][1];
1355                 if ((y & 0x00000200) != 0)
1356                         y = y | 0xFFFFFC00;
1357                 tx0_c = (y * oldval_0) >> 8;
1358                 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
1359                               ((tx0_c & 0x3C0) >> 6));
1360                 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
1361                               (tx0_c & 0x3F));
1362                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
1363                               ((y * oldval_0 >> 7) & 0x1));
1364                 if (btxonly)
1365                         return;
1366                 reg = result[final_candidate][2];
1367                 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
1368                 reg = result[final_candidate][3] & 0x3F;
1369                 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
1370                 reg = (result[final_candidate][3] >> 6) & 0xF;
1371                 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
1372         }
1373 }
1374
1375 static void phy_save_adda_regs(struct ieee80211_hw *hw,
1376                                                u32 *addareg, u32 *addabackup,
1377                                                u32 registernum)
1378 {
1379         u32 i;
1380
1381         for (i = 0; i < registernum; i++)
1382                 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
1383 }
1384
1385 static void phy_save_mac_regs(struct ieee80211_hw *hw, u32 *macreg,
1386                               u32 *macbackup)
1387 {
1388         struct rtl_priv *rtlpriv = rtl_priv(hw);
1389         u32 i;
1390
1391         for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1392                 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1393         macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1394 }
1395
1396 static void phy_reload_adda_regs(struct ieee80211_hw *hw, u32 *addareg,
1397                                  u32 *addabackup, u32 regiesternum)
1398 {
1399         u32 i;
1400
1401         for (i = 0; i < regiesternum; i++)
1402                 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
1403 }
1404
1405 static void phy_reload_mac_regs(struct ieee80211_hw *hw, u32 *macreg,
1406                                 u32 *macbackup)
1407 {
1408         struct rtl_priv *rtlpriv = rtl_priv(hw);
1409         u32 i;
1410
1411         for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1412                 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1413         rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
1414 }
1415
1416 static void _rtl8723ae_phy_path_adda_on(struct ieee80211_hw *hw,
1417                                         u32 *addareg, bool is_patha_on,
1418                                         bool is2t)
1419 {
1420         u32 pathOn;
1421         u32 i;
1422
1423         pathOn = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
1424         if (false == is2t) {
1425                 pathOn = 0x0bdb25a0;
1426                 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
1427         } else {
1428                 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathOn);
1429         }
1430
1431         for (i = 1; i < IQK_ADDA_REG_NUM; i++)
1432                 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathOn);
1433 }
1434
1435 static void _rtl8723ae_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1436                                                    u32 *macreg, u32 *macbackup)
1437 {
1438         struct rtl_priv *rtlpriv = rtl_priv(hw);
1439         u32 i = 0;
1440
1441         rtl_write_byte(rtlpriv, macreg[i], 0x3F);
1442
1443         for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1444                 rtl_write_byte(rtlpriv, macreg[i],
1445                                (u8) (macbackup[i] & (~BIT(3))));
1446         rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1447 }
1448
1449 static void _rtl8723ae_phy_path_a_standby(struct ieee80211_hw *hw)
1450 {
1451         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1452         rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1453         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1454 }
1455
1456 static void _rtl8723ae_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode)
1457 {
1458         u32 mode;
1459
1460         mode = pi_mode ? 0x01000100 : 0x01000000;
1461         rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1462         rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1463 }
1464
1465 static bool phy_simularity_comp(struct ieee80211_hw *hw, long result[][8],
1466                                 u8 c1, u8 c2)
1467 {
1468         u32 i, j, diff, simularity_bitmap, bound;
1469
1470         u8 final_candidate[2] = { 0xFF, 0xFF };
1471         bool bresult = true;
1472
1473         bound = 4;
1474
1475         simularity_bitmap = 0;
1476
1477         for (i = 0; i < bound; i++) {
1478                 diff = (result[c1][i] > result[c2][i]) ?
1479                     (result[c1][i] - result[c2][i]) :
1480                     (result[c2][i] - result[c1][i]);
1481
1482                 if (diff > MAX_TOLERANCE) {
1483                         if ((i == 2 || i == 6) && !simularity_bitmap) {
1484                                 if (result[c1][i] + result[c1][i + 1] == 0)
1485                                         final_candidate[(i / 4)] = c2;
1486                                 else if (result[c2][i] + result[c2][i + 1] == 0)
1487                                         final_candidate[(i / 4)] = c1;
1488                                 else
1489                                         simularity_bitmap = simularity_bitmap |
1490                                             (1 << i);
1491                         } else
1492                                 simularity_bitmap =
1493                                     simularity_bitmap | (1 << i);
1494                 }
1495         }
1496
1497         if (simularity_bitmap == 0) {
1498                 for (i = 0; i < (bound / 4); i++) {
1499                         if (final_candidate[i] != 0xFF) {
1500                                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
1501                                         result[3][j] =
1502                                             result[final_candidate[i]][j];
1503                                 bresult = false;
1504                         }
1505                 }
1506                 return bresult;
1507         } else if (!(simularity_bitmap & 0x0F)) {
1508                 for (i = 0; i < 4; i++)
1509                         result[3][i] = result[c1][i];
1510                 return false;
1511         } else {
1512                 return false;
1513         }
1514
1515 }
1516
1517 static void _rtl8723ae_phy_iq_calibrate(struct ieee80211_hw *hw,
1518                                         long result[][8], u8 t, bool is2t)
1519 {
1520         struct rtl_priv *rtlpriv = rtl_priv(hw);
1521         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1522         u32 i;
1523         u8 patha_ok, pathb_ok;
1524         u32 adda_reg[IQK_ADDA_REG_NUM] = {
1525                 0x85c, 0xe6c, 0xe70, 0xe74,
1526                 0xe78, 0xe7c, 0xe80, 0xe84,
1527                 0xe88, 0xe8c, 0xed0, 0xed4,
1528                 0xed8, 0xedc, 0xee0, 0xeec
1529         };
1530         u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1531                 0x522, 0x550, 0x551, 0x040
1532         };
1533         const u32 retrycount = 2;
1534         u32 bbvalue;
1535
1536         if (t == 0) {
1537                 bbvalue = rtl_get_bbreg(hw, 0x800, MASKDWORD);
1538
1539                 phy_save_adda_regs(hw, adda_reg, rtlphy->adda_backup, 16);
1540                 phy_save_mac_regs(hw, iqk_mac_reg, rtlphy->iqk_mac_backup);
1541         }
1542         _rtl8723ae_phy_path_adda_on(hw, adda_reg, true, is2t);
1543         if (t == 0) {
1544                 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1545                                                  RFPGA0_XA_HSSIPARAMETER1,
1546                                                  BIT(8));
1547         }
1548
1549         if (!rtlphy->rfpi_enable)
1550                 _rtl8723ae_phy_pi_mode_switch(hw, true);
1551         if (t == 0) {
1552                 rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD);
1553                 rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD);
1554                 rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD);
1555         }
1556         rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
1557         rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
1558         rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
1559         if (is2t) {
1560                 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1561                 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000);
1562         }
1563         _rtl8723ae_phy_mac_setting_calibration(hw, iqk_mac_reg,
1564                                             rtlphy->iqk_mac_backup);
1565         rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000);
1566         if (is2t)
1567                 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x00080000);
1568         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1569         rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1570         rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1571         for (i = 0; i < retrycount; i++) {
1572                 patha_ok = _rtl8723ae_phy_path_a_iqk(hw, is2t);
1573                 if (patha_ok == 0x03) {
1574                         result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1575                                         0x3FF0000) >> 16;
1576                         result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1577                                         0x3FF0000) >> 16;
1578                         result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1579                                         0x3FF0000) >> 16;
1580                         result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1581                                         0x3FF0000) >> 16;
1582                         break;
1583                 } else if (i == (retrycount - 1) && patha_ok == 0x01)
1584
1585                         result[t][0] = (rtl_get_bbreg(hw, 0xe94,
1586                                         MASKDWORD) & 0x3FF0000) >> 16;
1587                 result[t][1] =
1588                     (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16;
1589
1590         }
1591
1592         if (is2t) {
1593                 _rtl8723ae_phy_path_a_standby(hw);
1594                 _rtl8723ae_phy_path_adda_on(hw, adda_reg, false, is2t);
1595                 for (i = 0; i < retrycount; i++) {
1596                         pathb_ok = _rtl8723ae_phy_path_b_iqk(hw);
1597                         if (pathb_ok == 0x03) {
1598                                 result[t][4] =
1599                                     (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) &
1600                                      0x3FF0000) >> 16;
1601                                 result[t][5] =
1602                                     (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1603                                      0x3FF0000) >> 16;
1604                                 result[t][6] =
1605                                     (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
1606                                      0x3FF0000) >> 16;
1607                                 result[t][7] =
1608                                     (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
1609                                      0x3FF0000) >> 16;
1610                                 break;
1611                         } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1612                                 result[t][4] =
1613                                     (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) &
1614                                      0x3FF0000) >> 16;
1615                         }
1616                         result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1617                                         0x3FF0000) >> 16;
1618                 }
1619         }
1620         rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04);
1621         rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874);
1622         rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08);
1623         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1624         rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3);
1625         if (is2t)
1626                 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3);
1627         if (t != 0) {
1628                 if (!rtlphy->rfpi_enable)
1629                         _rtl8723ae_phy_pi_mode_switch(hw, false);
1630                 phy_reload_adda_regs(hw, adda_reg, rtlphy->adda_backup, 16);
1631                 phy_reload_mac_regs(hw, iqk_mac_reg, rtlphy->iqk_mac_backup);
1632         }
1633 }
1634
1635 static void _rtl8723ae_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
1636 {
1637         struct rtl_priv *rtlpriv = rtl_priv(hw);
1638         u8 tmpreg;
1639         u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
1640
1641         tmpreg = rtl_read_byte(rtlpriv, 0xd03);
1642
1643         if ((tmpreg & 0x70) != 0)
1644                 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
1645         else
1646                 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1647
1648         if ((tmpreg & 0x70) != 0) {
1649                 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
1650
1651                 if (is2t)
1652                         rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
1653                                                   MASK12BITS);
1654
1655                 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
1656                               (rf_a_mode & 0x8FFFF) | 0x10000);
1657
1658                 if (is2t)
1659                         rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
1660                                       (rf_b_mode & 0x8FFFF) | 0x10000);
1661         }
1662         lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
1663
1664         rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
1665
1666         mdelay(100);
1667
1668         if ((tmpreg & 0x70) != 0) {
1669                 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
1670                 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
1671
1672                 if (is2t)
1673                         rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
1674                                       rf_b_mode);
1675         } else {
1676                 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1677         }
1678 }
1679
1680 static void _rtl8723ae_phy_set_rfpath_switch(struct ieee80211_hw *hw,
1681                                              bool bmain, bool is2t)
1682 {
1683         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1684
1685         if (is_hal_stop(rtlhal)) {
1686                 rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01);
1687                 rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1688         }
1689         if (is2t) {
1690                 if (bmain)
1691                         rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1692                                       BIT(5) | BIT(6), 0x1);
1693                 else
1694                         rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1695                                       BIT(5) | BIT(6), 0x2);
1696         } else {
1697                 if (bmain)
1698                         rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x2);
1699                 else
1700                         rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1);
1701
1702         }
1703 }
1704
1705 #undef IQK_ADDA_REG_NUM
1706 #undef IQK_DELAY_TIME
1707
1708 void rtl8723ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery)
1709 {
1710         struct rtl_priv *rtlpriv = rtl_priv(hw);
1711         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1712         long result[4][8];
1713         u8 i, final_candidate;
1714         bool patha_ok, pathb_ok;
1715         long reg_e94, reg_e9c, reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4,
1716             reg_ecc, reg_tmp = 0;
1717         bool is12simular, is13simular, is23simular;
1718         bool start_conttx = false, singletone = false;
1719         u32 iqk_bb_reg[10] = {
1720                 ROFDM0_XARXIQIMBALANCE,
1721                 ROFDM0_XBRXIQIMBALANCE,
1722                 ROFDM0_ECCATHRESHOLD,
1723                 ROFDM0_AGCRSSITABLE,
1724                 ROFDM0_XATXIQIMBALANCE,
1725                 ROFDM0_XBTXIQIMBALANCE,
1726                 ROFDM0_XCTXIQIMBALANCE,
1727                 ROFDM0_XCTXAFE,
1728                 ROFDM0_XDTXAFE,
1729                 ROFDM0_RXIQEXTANTA
1730         };
1731
1732         if (recovery) {
1733                 phy_reload_adda_regs(hw, iqk_bb_reg, rtlphy->iqk_bb_backup, 10);
1734                 return;
1735         }
1736         if (start_conttx || singletone)
1737                 return;
1738         for (i = 0; i < 8; i++) {
1739                 result[0][i] = 0;
1740                 result[1][i] = 0;
1741                 result[2][i] = 0;
1742                 result[3][i] = 0;
1743         }
1744         final_candidate = 0xff;
1745         patha_ok = false;
1746         pathb_ok = false;
1747         is12simular = false;
1748         is23simular = false;
1749         is13simular = false;
1750         for (i = 0; i < 3; i++) {
1751                 _rtl8723ae_phy_iq_calibrate(hw, result, i, false);
1752                 if (i == 1) {
1753                         is12simular = phy_simularity_comp(hw, result, 0, 1);
1754                         if (is12simular) {
1755                                 final_candidate = 0;
1756                                 break;
1757                         }
1758                 }
1759                 if (i == 2) {
1760                         is13simular = phy_simularity_comp(hw, result, 0, 2);
1761                         if (is13simular) {
1762                                 final_candidate = 0;
1763                                 break;
1764                         }
1765                         is23simular = phy_simularity_comp(hw, result, 1, 2);
1766                         if (is23simular) {
1767                                 final_candidate = 1;
1768                         } else {
1769                                 for (i = 0; i < 8; i++)
1770                                         reg_tmp += result[3][i];
1771
1772                                 if (reg_tmp != 0)
1773                                         final_candidate = 3;
1774                                 else
1775                                         final_candidate = 0xFF;
1776                         }
1777                 }
1778         }
1779         for (i = 0; i < 4; i++) {
1780                 reg_e94 = result[i][0];
1781                 reg_e9c = result[i][1];
1782                 reg_ea4 = result[i][2];
1783                 reg_eac = result[i][3];
1784                 reg_eb4 = result[i][4];
1785                 reg_ebc = result[i][5];
1786                 reg_ec4 = result[i][6];
1787                 reg_ecc = result[i][7];
1788         }
1789         if (final_candidate != 0xff) {
1790                 rtlphy->reg_e94 = reg_e94 = result[final_candidate][0];
1791                 rtlphy->reg_e9c = reg_e9c = result[final_candidate][1];
1792                 reg_ea4 = result[final_candidate][2];
1793                 reg_eac = result[final_candidate][3];
1794                 rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4];
1795                 rtlphy->reg_ebc = reg_ebc = result[final_candidate][5];
1796                 reg_ec4 = result[final_candidate][6];
1797                 reg_ecc = result[final_candidate][7];
1798                 patha_ok = pathb_ok = true;
1799         } else {
1800                 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100;
1801                 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;
1802         }
1803         if (reg_e94 != 0) /*&&(reg_ea4 != 0) */
1804                 phy_path_a_fill_iqk_matrix(hw, patha_ok, result,
1805                                            final_candidate, (reg_ea4 == 0));
1806         phy_save_adda_regs(hw, iqk_bb_reg, rtlphy->iqk_bb_backup, 10);
1807 }
1808
1809 void rtl8723ae_phy_lc_calibrate(struct ieee80211_hw *hw)
1810 {
1811         bool start_conttx = false, singletone = false;
1812
1813         if (start_conttx || singletone)
1814                 return;
1815         _rtl8723ae_phy_lc_calibrate(hw, false);
1816 }
1817
1818 void rtl8723ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
1819 {
1820         _rtl8723ae_phy_set_rfpath_switch(hw, bmain, false);
1821 }
1822
1823 bool rtl8723ae_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
1824 {
1825         struct rtl_priv *rtlpriv = rtl_priv(hw);
1826         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1827         bool postprocessing = false;
1828
1829         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1830                  "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
1831                  iotype, rtlphy->set_io_inprogress);
1832         do {
1833                 switch (iotype) {
1834                 case IO_CMD_RESUME_DM_BY_SCAN:
1835                         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1836                                  "[IO CMD] Resume DM after scan.\n");
1837                         postprocessing = true;
1838                         break;
1839                 case IO_CMD_PAUSE_DM_BY_SCAN:
1840                         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1841                                  "[IO CMD] Pause DM before scan.\n");
1842                         postprocessing = true;
1843                         break;
1844                 default:
1845                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1846                                  "switch case not process\n");
1847                         break;
1848                 }
1849         } while (false);
1850         if (postprocessing && !rtlphy->set_io_inprogress) {
1851                 rtlphy->set_io_inprogress = true;
1852                 rtlphy->current_io_type = iotype;
1853         } else {
1854                 return false;
1855         }
1856         rtl8723ae_phy_set_io(hw);
1857         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype);
1858         return true;
1859 }
1860
1861 static void rtl8723ae_phy_set_io(struct ieee80211_hw *hw)
1862 {
1863         struct rtl_priv *rtlpriv = rtl_priv(hw);
1864         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1865         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
1866
1867         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1868                  "--->Cmd(%#x), set_io_inprogress(%d)\n",
1869                  rtlphy->current_io_type, rtlphy->set_io_inprogress);
1870         switch (rtlphy->current_io_type) {
1871         case IO_CMD_RESUME_DM_BY_SCAN:
1872                 dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
1873                 rtl8723ae_dm_write_dig(hw);
1874                 rtl8723ae_phy_set_txpower_level(hw, rtlphy->current_channel);
1875                 break;
1876         case IO_CMD_PAUSE_DM_BY_SCAN:
1877                 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue;
1878                 dm_digtable->cur_igvalue = 0x17;
1879                 rtl8723ae_dm_write_dig(hw);
1880                 break;
1881         default:
1882                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1883                          "switch case not process\n");
1884                 break;
1885         }
1886         rtlphy->set_io_inprogress = false;
1887         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1888                  "<---(%#x)\n", rtlphy->current_io_type);
1889 }
1890
1891 static void rtl8723ae_phy_set_rf_on(struct ieee80211_hw *hw)
1892 {
1893         struct rtl_priv *rtlpriv = rtl_priv(hw);
1894
1895         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
1896         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1897         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
1898         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1899         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1900         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1901 }
1902
1903 static void _rtl8723ae_phy_set_rf_sleep(struct ieee80211_hw *hw)
1904 {
1905         struct rtl_priv *rtlpriv = rtl_priv(hw);
1906         u32 u4b_tmp;
1907         u8 delay = 5;
1908
1909         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1910         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1911         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1912         u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
1913         while (u4b_tmp != 0 && delay > 0) {
1914                 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
1915                 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1916                 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1917                 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
1918                 delay--;
1919         }
1920         if (delay == 0) {
1921                 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
1922                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1923                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1924                 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1925                 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
1926                          "Switch RF timeout !!!.\n");
1927                 return;
1928         }
1929         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1930         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
1931 }
1932
1933 static bool _rtl8723ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
1934                                               enum rf_pwrstate rfpwr_state)
1935 {
1936         struct rtl_priv *rtlpriv = rtl_priv(hw);
1937         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1938         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1939         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1940         struct rtl8192_tx_ring *ring = NULL;
1941         bool bresult = true;
1942         u8 i, queue_id;
1943
1944         switch (rfpwr_state) {
1945         case ERFON:
1946                 if ((ppsc->rfpwr_state == ERFOFF) &&
1947                     RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
1948                         bool rtstatus;
1949                         u32 InitializeCount = 0;
1950                         do {
1951                                 InitializeCount++;
1952                                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1953                                          "IPS Set eRf nic enable\n");
1954                                 rtstatus = rtl_ps_enable_nic(hw);
1955                         } while ((rtstatus != true) && (InitializeCount < 10));
1956                         RT_CLEAR_PS_LEVEL(ppsc,
1957                                           RT_RF_OFF_LEVL_HALT_NIC);
1958                 } else {
1959                         RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1960                                  "Set ERFON sleeped:%d ms\n",
1961                                  jiffies_to_msecs(jiffies -
1962                                  ppsc->last_sleep_jiffies));
1963                         ppsc->last_awake_jiffies = jiffies;
1964                         rtl8723ae_phy_set_rf_on(hw);
1965                 }
1966                 if (mac->link_state == MAC80211_LINKED) {
1967                         rtlpriv->cfg->ops->led_control(hw,
1968                                         LED_CTL_LINK);
1969                 } else {
1970                         rtlpriv->cfg->ops->led_control(hw,
1971                                         LED_CTL_NO_LINK);
1972                 }
1973                 break;
1974         case ERFOFF:
1975                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
1976                         RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1977                                  "IPS Set eRf nic disable\n");
1978                         rtl_ps_disable_nic(hw);
1979                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1980                 } else {
1981                         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
1982                                 rtlpriv->cfg->ops->led_control(hw,
1983                                         LED_CTL_NO_LINK);
1984                         } else {
1985                                 rtlpriv->cfg->ops->led_control(hw,
1986                                         LED_CTL_POWER_OFF);
1987                         }
1988                 }
1989                 break;
1990         case ERFSLEEP:
1991                 if (ppsc->rfpwr_state == ERFOFF)
1992                         break;
1993                 for (queue_id = 0, i = 0;
1994                      queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
1995                         ring = &pcipriv->dev.tx_ring[queue_id];
1996                         if (skb_queue_len(&ring->queue) == 0) {
1997                                 queue_id++;
1998                                 continue;
1999                         } else {
2000                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2001                                          "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
2002                                          (i + 1), queue_id,
2003                                          skb_queue_len(&ring->queue));
2004
2005                                 udelay(10);
2006                                 i++;
2007                         }
2008                         if (i >= MAX_DOZE_WAITING_TIMES_9x) {
2009                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2010                                          "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
2011                                          MAX_DOZE_WAITING_TIMES_9x,
2012                                          queue_id,
2013                                          skb_queue_len(&ring->queue));
2014                                 break;
2015                         }
2016                 }
2017                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2018                          "Set ERFSLEEP awaked:%d ms\n",
2019                          jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies));
2020                 ppsc->last_sleep_jiffies = jiffies;
2021                 _rtl8723ae_phy_set_rf_sleep(hw);
2022                 break;
2023         default:
2024                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2025                          "switch case not processed\n");
2026                 bresult = false;
2027                 break;
2028         }
2029         if (bresult)
2030                 ppsc->rfpwr_state = rfpwr_state;
2031         return bresult;
2032 }
2033
2034 bool rtl8723ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
2035                                       enum rf_pwrstate rfpwr_state)
2036 {
2037         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2038         bool bresult = false;
2039
2040         if (rfpwr_state == ppsc->rfpwr_state)
2041                 return bresult;
2042         bresult = _rtl8723ae_phy_set_rf_power_state(hw, rfpwr_state);
2043         return bresult;
2044 }