drivers/nvme/host/pci.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/aer.h>
  16 #include <linux/bitops.h>
  17 #include <linux/blkdev.h>
  18 #include <linux/blk-mq.h>
  19 #include <linux/blk-mq-pci.h>
  20 #include <linux/dmi.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/io.h>
  24 #include <linux/mm.h>
  25 #include <linux/module.h>
  26 #include <linux/mutex.h>
  27 #include <linux/pci.h>
  28 #include <linux/poison.h>
  29 #include <linux/t10-pi.h>
  30 #include <linux/timer.h>
  31 #include <linux/types.h>
  32 #include <linux/io-64-nonatomic-lo-hi.h>
  33 #include <asm/unaligned.h>
  34 #include <linux/sed-opal.h>
  35
  36 #include "nvme.h"
  37
  38 #define NVME_Q_DEPTH            1024
  39 #define NVME_AQ_DEPTH           256
  40 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  41 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  42
  43 /*
  44  * We handle AEN commands ourselves and don't even let the
  45  * block layer know about them.
  46  */
  47 #define NVME_AQ_BLKMQ_DEPTH     (NVME_AQ_DEPTH - NVME_NR_AERS)
  48
  49 static int use_threaded_interrupts;
  50 module_param(use_threaded_interrupts, int, 0);
  51
  52 static bool use_cmb_sqes = true;
  53 module_param(use_cmb_sqes, bool, 0644);
  54 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  55
  56 static unsigned int max_host_mem_size_mb = 128;
  57 module_param(max_host_mem_size_mb, uint, 0444);
  58 MODULE_PARM_DESC(max_host_mem_size_mb,
  59         "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
  60
  61 struct nvme_dev;
  62 struct nvme_queue;
  63
  64 static void nvme_process_cq(struct nvme_queue *nvmeq);
  65 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
  66
  67 /*
  68  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  69  */
  70 struct nvme_dev {
  71         struct nvme_queue **queues;
  72         struct blk_mq_tag_set tagset;
  73         struct blk_mq_tag_set admin_tagset;
  74         u32 __iomem *dbs;
  75         struct device *dev;
  76         struct dma_pool *prp_page_pool;
  77         struct dma_pool *prp_small_pool;
  78         unsigned queue_count;
  79         unsigned online_queues;
  80         unsigned max_qid;
  81         int q_depth;
  82         u32 db_stride;
  83         void __iomem *bar;
  84         unsigned long bar_mapped_size;
  85         struct work_struct remove_work;
  86         struct mutex shutdown_lock;
  87         bool subsystem;
  88         void __iomem *cmb;
  89         dma_addr_t cmb_dma_addr;
  90         u64 cmb_size;
  91         u32 cmbsz;
  92         u32 cmbloc;
  93         struct nvme_ctrl ctrl;
  94         struct completion ioq_wait;
  95
  96         /* shadow doorbell buffer support: */
  97         u32 *dbbuf_dbs;
  98         dma_addr_t dbbuf_dbs_dma_addr;
  99         u32 *dbbuf_eis;
 100         dma_addr_t dbbuf_eis_dma_addr;
 101
 102         /* host memory buffer support: */
 103         u64 host_mem_size;
 104         u32 nr_host_mem_descs;
 105         struct nvme_host_mem_buf_desc *host_mem_descs;
 106         void **host_mem_desc_bufs;
 107 };
 108
 109 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
 110 {
 111         return qid * 2 * stride;
 112 }
 113
 114 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
 115 {
 116         return (qid * 2 + 1) * stride;
 117 }
 118
 119 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 120 {
 121         return container_of(ctrl, struct nvme_dev, ctrl);
 122 }
 123
 124 /*
 125  * An NVM Express queue.  Each device has at least two (one for admin
 126  * commands and one for I/O commands).
 127  */
 128 struct nvme_queue {
 129         struct device *q_dmadev;
 130         struct nvme_dev *dev;
 131         spinlock_t q_lock;
 132         struct nvme_command *sq_cmds;
 133         struct nvme_command __iomem *sq_cmds_io;
 134         volatile struct nvme_completion *cqes;
 135         struct blk_mq_tags **tags;
 136         dma_addr_t sq_dma_addr;
 137         dma_addr_t cq_dma_addr;
 138         u32 __iomem *q_db;
 139         u16 q_depth;
 140         s16 cq_vector;
 141         u16 sq_tail;
 142         u16 cq_head;
 143         u16 qid;
 144         u8 cq_phase;
 145         u8 cqe_seen;
 146         u32 *dbbuf_sq_db;
 147         u32 *dbbuf_cq_db;
 148         u32 *dbbuf_sq_ei;
 149         u32 *dbbuf_cq_ei;
 150 };
 151
 152 /*
 153  * The nvme_iod describes the data in an I/O, including the list of PRP
 154  * entries.  You can't see it in this data structure because C doesn't let
 155  * me express that.  Use nvme_init_iod to ensure there's enough space
 156  * allocated to store the PRP list.
 157  */
 158 struct nvme_iod {
 159         struct nvme_request req;
 160         struct nvme_queue *nvmeq;
 161         int aborted;
 162         int npages;             /* In the PRP list. 0 means small pool in use */
 163         int nents;              /* Used in scatterlist */
 164         int length;             /* Of data, in bytes */
 165         dma_addr_t first_dma;
 166         struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
 167         struct scatterlist *sg;
 168         struct scatterlist inline_sg[0];
 169 };
 170
 171 /*
 172  * Check we didin't inadvertently grow the command struct
 173  */
 174 static inline void _nvme_check_size(void)
 175 {
 176         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 177         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 178         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 179         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 180         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 181         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 182         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 183         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 184         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
 185         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
 186         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 187         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 188         BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
 189 }
 190
 191 static inline unsigned int nvme_dbbuf_size(u32 stride)
 192 {
 193         return ((num_possible_cpus() + 1) * 8 * stride);
 194 }
 195
 196 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
 197 {
 198         unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
 199
 200         if (dev->dbbuf_dbs)
 201                 return 0;
 202
 203         dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
 204                                             &dev->dbbuf_dbs_dma_addr,
 205                                             GFP_KERNEL);
 206         if (!dev->dbbuf_dbs)
 207                 return -ENOMEM;
 208         dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
 209                                             &dev->dbbuf_eis_dma_addr,
 210                                             GFP_KERNEL);
 211         if (!dev->dbbuf_eis) {
 212                 dma_free_coherent(dev->dev, mem_size,
 213                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 214                 dev->dbbuf_dbs = NULL;
 215                 return -ENOMEM;
 216         }
 217
 218         return 0;
 219 }
 220
 221 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
 222 {
 223         unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
 224
 225         if (dev->dbbuf_dbs) {
 226                 dma_free_coherent(dev->dev, mem_size,
 227                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 228                 dev->dbbuf_dbs = NULL;
 229         }
 230         if (dev->dbbuf_eis) {
 231                 dma_free_coherent(dev->dev, mem_size,
 232                                   dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
 233                 dev->dbbuf_eis = NULL;
 234         }
 235 }
 236
 237 static void nvme_dbbuf_init(struct nvme_dev *dev,
 238                             struct nvme_queue *nvmeq, int qid)
 239 {
 240         if (!dev->dbbuf_dbs || !qid)
 241                 return;
 242
 243         nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
 244         nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
 245         nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
 246         nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
 247 }
 248
 249 static void nvme_dbbuf_set(struct nvme_dev *dev)
 250 {
 251         struct nvme_command c;
 252
 253         if (!dev->dbbuf_dbs)
 254                 return;
 255
 256         memset(&c, 0, sizeof(c));
 257         c.dbbuf.opcode = nvme_admin_dbbuf;
 258         c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
 259         c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
 260
 261         if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
 262                 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
 263                 /* Free memory and continue on */
 264                 nvme_dbbuf_dma_free(dev);
 265         }
 266 }
 267
 268 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
 269 {
 270         return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
 271 }
 272
 273 /* Update dbbuf and return true if an MMIO is required */
 274 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
 275                                               volatile u32 *dbbuf_ei)
 276 {
 277         if (dbbuf_db) {
 278                 u16 old_value;
 279
 280                 /*
 281                  * Ensure that the queue is written before updating
 282                  * the doorbell in memory
 283                  */
 284                 wmb();
 285
 286                 old_value = *dbbuf_db;
 287                 *dbbuf_db = value;
 288
 289                 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
 290                         return false;
 291         }
 292
 293         return true;
 294 }
 295
 296 /*
 297  * Max size of iod being embedded in the request payload
 298  */
 299 #define NVME_INT_PAGES          2
 300 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 301
 302 /*
 303  * Will slightly overestimate the number of pages needed.  This is OK
 304  * as it only leads to a small amount of wasted memory for the lifetime of
 305  * the I/O.
 306  */
 307 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 308 {
 309         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 310                                       dev->ctrl.page_size);
 311         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 312 }
 313
 314 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
 315                 unsigned int size, unsigned int nseg)
 316 {
 317         return sizeof(__le64 *) * nvme_npages(size, dev) +
 318                         sizeof(struct scatterlist) * nseg;
 319 }
 320
 321 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
 322 {
 323         return sizeof(struct nvme_iod) +
 324                 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
 325 }
 326
 327 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 328                                 unsigned int hctx_idx)
 329 {
 330         struct nvme_dev *dev = data;
 331         struct nvme_queue *nvmeq = dev->queues[0];
 332
 333         WARN_ON(hctx_idx != 0);
 334         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 335         WARN_ON(nvmeq->tags);
 336
 337         hctx->driver_data = nvmeq;
 338         nvmeq->tags = &dev->admin_tagset.tags[0];
 339         return 0;
 340 }
 341
 342 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 343 {
 344         struct nvme_queue *nvmeq = hctx->driver_data;
 345
 346         nvmeq->tags = NULL;
 347 }
 348
 349 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 350                           unsigned int hctx_idx)
 351 {
 352         struct nvme_dev *dev = data;
 353         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 354
 355         if (!nvmeq->tags)
 356                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 357
 358         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 359         hctx->driver_data = nvmeq;
 360         return 0;
 361 }
 362
 363 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
 364                 unsigned int hctx_idx, unsigned int numa_node)
 365 {
 366         struct nvme_dev *dev = set->driver_data;
 367         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 368         int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
 369         struct nvme_queue *nvmeq = dev->queues[queue_idx];
 370
 371         BUG_ON(!nvmeq);
 372         iod->nvmeq = nvmeq;
 373         return 0;
 374 }
 375
 376 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
 377 {
 378         struct nvme_dev *dev = set->driver_data;
 379
 380         return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev));
 381 }
 382
 383 /**
 384  * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 385  * @nvmeq: The queue to use
 386  * @cmd: The command to send
 387  *
 388  * Safe to use from interrupt context
 389  */
 390 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
 391                                                 struct nvme_command *cmd)
 392 {
 393         u16 tail = nvmeq->sq_tail;
 394
 395         if (nvmeq->sq_cmds_io)
 396                 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
 397         else
 398                 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 399
 400         if (++tail == nvmeq->q_depth)
 401                 tail = 0;
 402         if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db,
 403                                               nvmeq->dbbuf_sq_ei))
 404                 writel(tail, nvmeq->q_db);
 405         nvmeq->sq_tail = tail;
 406 }
 407
 408 static __le64 **iod_list(struct request *req)
 409 {
 410         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 411         return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req));
 412 }
 413
 414 static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
 415 {
 416         struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
 417         int nseg = blk_rq_nr_phys_segments(rq);
 418         unsigned int size = blk_rq_payload_bytes(rq);
 419
 420         if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
 421                 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
 422                 if (!iod->sg)
 423                         return BLK_STS_RESOURCE;
 424         } else {
 425                 iod->sg = iod->inline_sg;
 426         }
 427
 428         iod->aborted = 0;
 429         iod->npages = -1;
 430         iod->nents = 0;
 431         iod->length = size;
 432
 433         return BLK_STS_OK;
 434 }
 435
 436 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
 437 {
 438         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 439         const int last_prp = dev->ctrl.page_size / 8 - 1;
 440         int i;
 441         __le64 **list = iod_list(req);
 442         dma_addr_t prp_dma = iod->first_dma;
 443
 444         if (iod->npages == 0)
 445                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 446         for (i = 0; i < iod->npages; i++) {
 447                 __le64 *prp_list = list[i];
 448                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 449                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 450                 prp_dma = next_prp_dma;
 451         }
 452
 453         if (iod->sg != iod->inline_sg)
 454                 kfree(iod->sg);
 455 }
 456
 457 #ifdef CONFIG_BLK_DEV_INTEGRITY
 458 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 459 {
 460         if (be32_to_cpu(pi->ref_tag) == v)
 461                 pi->ref_tag = cpu_to_be32(p);
 462 }
 463
 464 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 465 {
 466         if (be32_to_cpu(pi->ref_tag) == p)
 467                 pi->ref_tag = cpu_to_be32(v);
 468 }
 469
 470 /**
 471  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 472  *
 473  * The virtual start sector is the one that was originally submitted by the
 474  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 475  * start sector may be different. Remap protection information to match the
 476  * physical LBA on writes, and back to the original seed on reads.
 477  *
 478  * Type 0 and 3 do not have a ref tag, so no remapping required.
 479  */
 480 static void nvme_dif_remap(struct request *req,
 481                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 482 {
 483         struct nvme_ns *ns = req->rq_disk->private_data;
 484         struct bio_integrity_payload *bip;
 485         struct t10_pi_tuple *pi;
 486         void *p, *pmap;
 487         u32 i, nlb, ts, phys, virt;
 488
 489         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 490                 return;
 491
 492         bip = bio_integrity(req->bio);
 493         if (!bip)
 494                 return;
 495
 496         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 497
 498         p = pmap;
 499         virt = bip_get_seed(bip);
 500         phys = nvme_block_nr(ns, blk_rq_pos(req));
 501         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 502         ts = ns->disk->queue->integrity.tuple_size;
 503
 504         for (i = 0; i < nlb; i++, virt++, phys++) {
 505                 pi = (struct t10_pi_tuple *)p;
 506                 dif_swap(phys, virt, pi);
 507                 p += ts;
 508         }
 509         kunmap_atomic(pmap);
 510 }
 511 #else /* CONFIG_BLK_DEV_INTEGRITY */
 512 static void nvme_dif_remap(struct request *req,
 513                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 514 {
 515 }
 516 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 517 {
 518 }
 519 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 520 {
 521 }
 522 #endif
 523
 524 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req)
 525 {
 526         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 527         struct dma_pool *pool;
 528         int length = blk_rq_payload_bytes(req);
 529         struct scatterlist *sg = iod->sg;
 530         int dma_len = sg_dma_len(sg);
 531         u64 dma_addr = sg_dma_address(sg);
 532         u32 page_size = dev->ctrl.page_size;
 533         int offset = dma_addr & (page_size - 1);
 534         __le64 *prp_list;
 535         __le64 **list = iod_list(req);
 536         dma_addr_t prp_dma;
 537         int nprps, i;
 538
 539         length -= (page_size - offset);
 540         if (length <= 0)
 541                 return true;
 542
 543         dma_len -= (page_size - offset);
 544         if (dma_len) {
 545                 dma_addr += (page_size - offset);
 546         } else {
 547                 sg = sg_next(sg);
 548                 dma_addr = sg_dma_address(sg);
 549                 dma_len = sg_dma_len(sg);
 550         }
 551
 552         if (length <= page_size) {
 553                 iod->first_dma = dma_addr;
 554                 return true;
 555         }
 556
 557         nprps = DIV_ROUND_UP(length, page_size);
 558         if (nprps <= (256 / 8)) {
 559                 pool = dev->prp_small_pool;
 560                 iod->npages = 0;
 561         } else {
 562                 pool = dev->prp_page_pool;
 563                 iod->npages = 1;
 564         }
 565
 566         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 567         if (!prp_list) {
 568                 iod->first_dma = dma_addr;
 569                 iod->npages = -1;
 570                 return false;
 571         }
 572         list[0] = prp_list;
 573         iod->first_dma = prp_dma;
 574         i = 0;
 575         for (;;) {
 576                 if (i == page_size >> 3) {
 577                         __le64 *old_prp_list = prp_list;
 578                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 579                         if (!prp_list)
 580                                 return false;
 581                         list[iod->npages++] = prp_list;
 582                         prp_list[0] = old_prp_list[i - 1];
 583                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 584                         i = 1;
 585                 }
 586                 prp_list[i++] = cpu_to_le64(dma_addr);
 587                 dma_len -= page_size;
 588                 dma_addr += page_size;
 589                 length -= page_size;
 590                 if (length <= 0)
 591                         break;
 592                 if (dma_len > 0)
 593                         continue;
 594                 BUG_ON(dma_len < 0);
 595                 sg = sg_next(sg);
 596                 dma_addr = sg_dma_address(sg);
 597                 dma_len = sg_dma_len(sg);
 598         }
 599
 600         return true;
 601 }
 602
 603 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
 604                 struct nvme_command *cmnd)
 605 {
 606         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 607         struct request_queue *q = req->q;
 608         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 609                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 610         blk_status_t ret = BLK_STS_IOERR;
 611
 612         sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
 613         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 614         if (!iod->nents)
 615                 goto out;
 616
 617         ret = BLK_STS_RESOURCE;
 618         if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
 619                                 DMA_ATTR_NO_WARN))
 620                 goto out;
 621
 622         if (!nvme_setup_prps(dev, req))
 623                 goto out_unmap;
 624
 625         ret = BLK_STS_IOERR;
 626         if (blk_integrity_rq(req)) {
 627                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 628                         goto out_unmap;
 629
 630                 sg_init_table(&iod->meta_sg, 1);
 631                 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
 632                         goto out_unmap;
 633
 634                 if (rq_data_dir(req))
 635                         nvme_dif_remap(req, nvme_dif_prep);
 636
 637                 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
 638                         goto out_unmap;
 639         }
 640
 641         cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 642         cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma);
 643         if (blk_integrity_rq(req))
 644                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
 645         return BLK_STS_OK;
 646
 647 out_unmap:
 648         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 649 out:
 650         return ret;
 651 }
 652
 653 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 654 {
 655         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 656         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 657                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 658
 659         if (iod->nents) {
 660                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 661                 if (blk_integrity_rq(req)) {
 662                         if (!rq_data_dir(req))
 663                                 nvme_dif_remap(req, nvme_dif_complete);
 664                         dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
 665                 }
 666         }
 667
 668         nvme_cleanup_cmd(req);
 669         nvme_free_iod(dev, req);
 670 }
 671
 672 /*
 673  * NOTE: ns is NULL when called on the admin queue.
 674  */
 675 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 676                          const struct blk_mq_queue_data *bd)
 677 {
 678         struct nvme_ns *ns = hctx->queue->queuedata;
 679         struct nvme_queue *nvmeq = hctx->driver_data;
 680         struct nvme_dev *dev = nvmeq->dev;
 681         struct request *req = bd->rq;
 682         struct nvme_command cmnd;
 683         blk_status_t ret;
 684
 685         ret = nvme_setup_cmd(ns, req, &cmnd);
 686         if (ret)
 687                 return ret;
 688
 689         ret = nvme_init_iod(req, dev);
 690         if (ret)
 691                 goto out_free_cmd;
 692
 693         if (blk_rq_nr_phys_segments(req)) {
 694                 ret = nvme_map_data(dev, req, &cmnd);
 695                 if (ret)
 696                         goto out_cleanup_iod;
 697         }
 698
 699         blk_mq_start_request(req);
 700
 701         spin_lock_irq(&nvmeq->q_lock);
 702         if (unlikely(nvmeq->cq_vector < 0)) {
 703                 ret = BLK_STS_IOERR;
 704                 spin_unlock_irq(&nvmeq->q_lock);
 705                 goto out_cleanup_iod;
 706         }
 707         __nvme_submit_cmd(nvmeq, &cmnd);
 708         nvme_process_cq(nvmeq);
 709         spin_unlock_irq(&nvmeq->q_lock);
 710         return BLK_STS_OK;
 711 out_cleanup_iod:
 712         nvme_free_iod(dev, req);
 713 out_free_cmd:
 714         nvme_cleanup_cmd(req);
 715         return ret;
 716 }
 717
 718 static void nvme_pci_complete_rq(struct request *req)
 719 {
 720         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 721
 722         nvme_unmap_data(iod->nvmeq->dev, req);
 723         nvme_complete_rq(req);
 724 }
 725
 726 /* We read the CQE phase first to check if the rest of the entry is valid */
 727 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
 728                 u16 phase)
 729 {
 730         return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
 731 }
 732
 733 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
 734 {
 735         u16 head = nvmeq->cq_head;
 736
 737         if (likely(nvmeq->cq_vector >= 0)) {
 738                 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
 739                                                       nvmeq->dbbuf_cq_ei))
 740                         writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 741         }
 742 }
 743
 744 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
 745                 struct nvme_completion *cqe)
 746 {
 747         struct request *req;
 748
 749         if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
 750                 dev_warn(nvmeq->dev->ctrl.device,
 751                         "invalid id %d completed on queue %d\n",
 752                         cqe->command_id, le16_to_cpu(cqe->sq_id));
 753                 return;
 754         }
 755
 756         /*
 757          * AEN requests are special as they don't time out and can
 758          * survive any kind of queue freeze and often don't respond to
 759          * aborts.  We don't even bother to allocate a struct request
 760          * for them but rather special case them here.
 761          */
 762         if (unlikely(nvmeq->qid == 0 &&
 763                         cqe->command_id >= NVME_AQ_BLKMQ_DEPTH)) {
 764                 nvme_complete_async_event(&nvmeq->dev->ctrl,
 765                                 cqe->status, &cqe->result);
 766                 return;
 767         }
 768
 769         req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
 770         nvme_end_request(req, cqe->status, cqe->result);
 771 }
 772
 773 static inline bool nvme_read_cqe(struct nvme_queue *nvmeq,
 774                 struct nvme_completion *cqe)
 775 {
 776         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
 777                 *cqe = nvmeq->cqes[nvmeq->cq_head];
 778
 779                 if (++nvmeq->cq_head == nvmeq->q_depth) {
 780                         nvmeq->cq_head = 0;
 781                         nvmeq->cq_phase = !nvmeq->cq_phase;
 782                 }
 783                 return true;
 784         }
 785         return false;
 786 }
 787
 788 static void nvme_process_cq(struct nvme_queue *nvmeq)
 789 {
 790         struct nvme_completion cqe;
 791         int consumed = 0;
 792
 793         while (nvme_read_cqe(nvmeq, &cqe)) {
 794                 nvme_handle_cqe(nvmeq, &cqe);
 795                 consumed++;
 796         }
 797
 798         if (consumed) {
 799                 nvme_ring_cq_doorbell(nvmeq);
 800                 nvmeq->cqe_seen = 1;
 801         }
 802 }
 803
 804 static irqreturn_t nvme_irq(int irq, void *data)
 805 {
 806         irqreturn_t result;
 807         struct nvme_queue *nvmeq = data;
 808         spin_lock(&nvmeq->q_lock);
 809         nvme_process_cq(nvmeq);
 810         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
 811         nvmeq->cqe_seen = 0;
 812         spin_unlock(&nvmeq->q_lock);
 813         return result;
 814 }
 815
 816 static irqreturn_t nvme_irq_check(int irq, void *data)
 817 {
 818         struct nvme_queue *nvmeq = data;
 819         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
 820                 return IRQ_WAKE_THREAD;
 821         return IRQ_NONE;
 822 }
 823
 824 static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
 825 {
 826         struct nvme_completion cqe;
 827         int found = 0, consumed = 0;
 828
 829         if (!nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
 830                 return 0;
 831
 832         spin_lock_irq(&nvmeq->q_lock);
 833         while (nvme_read_cqe(nvmeq, &cqe)) {
 834                 nvme_handle_cqe(nvmeq, &cqe);
 835                 consumed++;
 836
 837                 if (tag == cqe.command_id) {
 838                         found = 1;
 839                         break;
 840                 }
 841        }
 842
 843         if (consumed)
 844                 nvme_ring_cq_doorbell(nvmeq);
 845         spin_unlock_irq(&nvmeq->q_lock);
 846
 847         return found;
 848 }
 849
 850 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
 851 {
 852         struct nvme_queue *nvmeq = hctx->driver_data;
 853
 854         return __nvme_poll(nvmeq, tag);
 855 }
 856
 857 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx)
 858 {
 859         struct nvme_dev *dev = to_nvme_dev(ctrl);
 860         struct nvme_queue *nvmeq = dev->queues[0];
 861         struct nvme_command c;
 862
 863         memset(&c, 0, sizeof(c));
 864         c.common.opcode = nvme_admin_async_event;
 865         c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx;
 866
 867         spin_lock_irq(&nvmeq->q_lock);
 868         __nvme_submit_cmd(nvmeq, &c);
 869         spin_unlock_irq(&nvmeq->q_lock);
 870 }
 871
 872 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 873 {
 874         struct nvme_command c;
 875
 876         memset(&c, 0, sizeof(c));
 877         c.delete_queue.opcode = opcode;
 878         c.delete_queue.qid = cpu_to_le16(id);
 879
 880         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 881 }
 882
 883 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 884                                                 struct nvme_queue *nvmeq)
 885 {
 886         struct nvme_command c;
 887         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 888
 889         /*
 890          * Note: we (ab)use the fact the the prp fields survive if no data
 891          * is attached to the request.
 892          */
 893         memset(&c, 0, sizeof(c));
 894         c.create_cq.opcode = nvme_admin_create_cq;
 895         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 896         c.create_cq.cqid = cpu_to_le16(qid);
 897         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 898         c.create_cq.cq_flags = cpu_to_le16(flags);
 899         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 900
 901         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 902 }
 903
 904 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 905                                                 struct nvme_queue *nvmeq)
 906 {
 907         struct nvme_command c;
 908         int flags = NVME_QUEUE_PHYS_CONTIG;
 909
 910         /*
 911          * Note: we (ab)use the fact the the prp fields survive if no data
 912          * is attached to the request.
 913          */
 914         memset(&c, 0, sizeof(c));
 915         c.create_sq.opcode = nvme_admin_create_sq;
 916         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 917         c.create_sq.sqid = cpu_to_le16(qid);
 918         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 919         c.create_sq.sq_flags = cpu_to_le16(flags);
 920         c.create_sq.cqid = cpu_to_le16(qid);
 921
 922         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 923 }
 924
 925 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 926 {
 927         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 928 }
 929
 930 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 931 {
 932         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 933 }
 934
 935 static void abort_endio(struct request *req, blk_status_t error)
 936 {
 937         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 938         struct nvme_queue *nvmeq = iod->nvmeq;
 939
 940         dev_warn(nvmeq->dev->ctrl.device,
 941                  "Abort status: 0x%x", nvme_req(req)->status);
 942         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
 943         blk_mq_free_request(req);
 944 }
 945
 946 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
 947 {
 948
 949         /* If true, indicates loss of adapter communication, possibly by a
 950          * NVMe Subsystem reset.
 951          */
 952         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
 953
 954         /* If there is a reset ongoing, we shouldn't reset again. */
 955         if (dev->ctrl.state == NVME_CTRL_RESETTING)
 956                 return false;
 957
 958         /* We shouldn't reset unless the controller is on fatal error state
 959          * _or_ if we lost the communication with it.
 960          */
 961         if (!(csts & NVME_CSTS_CFS) && !nssro)
 962                 return false;
 963
 964         /* If PCI error recovery process is happening, we cannot reset or
 965          * the recovery mechanism will surely fail.
 966          */
 967         if (pci_channel_offline(to_pci_dev(dev->dev)))
 968                 return false;
 969
 970         return true;
 971 }
 972
 973 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
 974 {
 975         /* Read a config register to help see what died. */
 976         u16 pci_status;
 977         int result;
 978
 979         result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
 980                                       &pci_status);
 981         if (result == PCIBIOS_SUCCESSFUL)
 982                 dev_warn(dev->ctrl.device,
 983                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
 984                          csts, pci_status);
 985         else
 986                 dev_warn(dev->ctrl.device,
 987                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
 988                          csts, result);
 989 }
 990
 991 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
 992 {
 993         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 994         struct nvme_queue *nvmeq = iod->nvmeq;
 995         struct nvme_dev *dev = nvmeq->dev;
 996         struct request *abort_req;
 997         struct nvme_command cmd;
 998         u32 csts = readl(dev->bar + NVME_REG_CSTS);
 999
1000         /*
1001          * Reset immediately if the controller is failed
1002          */
1003         if (nvme_should_reset(dev, csts)) {
1004                 nvme_warn_reset(dev, csts);
1005                 nvme_dev_disable(dev, false);
1006                 nvme_reset_ctrl(&dev->ctrl);
1007                 return BLK_EH_HANDLED;
1008         }
1009
1010         /*
1011          * Did we miss an interrupt?
1012          */
1013         if (__nvme_poll(nvmeq, req->tag)) {
1014                 dev_warn(dev->ctrl.device,
1015                          "I/O %d QID %d timeout, completion polled\n",
1016                          req->tag, nvmeq->qid);
1017                 return BLK_EH_HANDLED;
1018         }
1019
1020         /*
1021          * Shutdown immediately if controller times out while starting. The
1022          * reset work will see the pci device disabled when it gets the forced
1023          * cancellation error. All outstanding requests are completed on
1024          * shutdown, so we return BLK_EH_HANDLED.
1025          */
1026         if (dev->ctrl.state == NVME_CTRL_RESETTING) {
1027                 dev_warn(dev->ctrl.device,
1028                          "I/O %d QID %d timeout, disable controller\n",
1029                          req->tag, nvmeq->qid);
1030                 nvme_dev_disable(dev, false);
1031                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1032                 return BLK_EH_HANDLED;
1033         }
1034
1035         /*
1036          * Shutdown the controller immediately and schedule a reset if the
1037          * command was already aborted once before and still hasn't been
1038          * returned to the driver, or if this is the admin queue.
1039          */
1040         if (!nvmeq->qid || iod->aborted) {
1041                 dev_warn(dev->ctrl.device,
1042                          "I/O %d QID %d timeout, reset controller\n",
1043                          req->tag, nvmeq->qid);
1044                 nvme_dev_disable(dev, false);
1045                 nvme_reset_ctrl(&dev->ctrl);
1046
1047                 /*
1048                  * Mark the request as handled, since the inline shutdown
1049                  * forces all outstanding requests to complete.
1050                  */
1051                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1052                 return BLK_EH_HANDLED;
1053         }
1054
1055         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1056                 atomic_inc(&dev->ctrl.abort_limit);
1057                 return BLK_EH_RESET_TIMER;
1058         }
1059         iod->aborted = 1;
1060
1061         memset(&cmd, 0, sizeof(cmd));
1062         cmd.abort.opcode = nvme_admin_abort_cmd;
1063         cmd.abort.cid = req->tag;
1064         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1065
1066         dev_warn(nvmeq->dev->ctrl.device,
1067                 "I/O %d QID %d timeout, aborting\n",
1068                  req->tag, nvmeq->qid);
1069
1070         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1071                         BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1072         if (IS_ERR(abort_req)) {
1073                 atomic_inc(&dev->ctrl.abort_limit);
1074                 return BLK_EH_RESET_TIMER;
1075         }
1076
1077         abort_req->timeout = ADMIN_TIMEOUT;
1078         abort_req->end_io_data = NULL;
1079         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1080
1081         /*
1082          * The aborted req will be completed on receiving the abort req.
1083          * We enable the timer again. If hit twice, it'll cause a device reset,
1084          * as the device then is in a faulty state.
1085          */
1086         return BLK_EH_RESET_TIMER;
1087 }
1088
1089 static void nvme_free_queue(struct nvme_queue *nvmeq)
1090 {
1091         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1092                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1093         if (nvmeq->sq_cmds)
1094                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1095                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1096         kfree(nvmeq);
1097 }
1098
1099 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1100 {
1101         int i;
1102
1103         for (i = dev->queue_count - 1; i >= lowest; i--) {
1104                 struct nvme_queue *nvmeq = dev->queues[i];
1105                 dev->queue_count--;
1106                 dev->queues[i] = NULL;
1107                 nvme_free_queue(nvmeq);
1108         }
1109 }
1110
1111 /**
1112  * nvme_suspend_queue - put queue into suspended state
1113  * @nvmeq - queue to suspend
1114  */
1115 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1116 {
1117         int vector;
1118
1119         spin_lock_irq(&nvmeq->q_lock);
1120         if (nvmeq->cq_vector == -1) {
1121                 spin_unlock_irq(&nvmeq->q_lock);
1122                 return 1;
1123         }
1124         vector = nvmeq->cq_vector;
1125         nvmeq->dev->online_queues--;
1126         nvmeq->cq_vector = -1;
1127         spin_unlock_irq(&nvmeq->q_lock);
1128
1129         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1130                 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
1131
1132         pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
1133
1134         return 0;
1135 }
1136
1137 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1138 {
1139         struct nvme_queue *nvmeq = dev->queues[0];
1140
1141         if (!nvmeq)
1142                 return;
1143         if (nvme_suspend_queue(nvmeq))
1144                 return;
1145
1146         if (shutdown)
1147                 nvme_shutdown_ctrl(&dev->ctrl);
1148         else
1149                 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
1150                                                 dev->bar + NVME_REG_CAP));
1151
1152         spin_lock_irq(&nvmeq->q_lock);
1153         nvme_process_cq(nvmeq);
1154         spin_unlock_irq(&nvmeq->q_lock);
1155 }
1156
1157 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1158                                 int entry_size)
1159 {
1160         int q_depth = dev->q_depth;
1161         unsigned q_size_aligned = roundup(q_depth * entry_size,
1162                                           dev->ctrl.page_size);
1163
1164         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1165                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1166                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1167                 q_depth = div_u64(mem_per_q, entry_size);
1168
1169                 /*
1170                  * Ensure the reduced q_depth is above some threshold where it
1171                  * would be better to map queues in system memory with the
1172                  * original depth
1173                  */
1174                 if (q_depth < 64)
1175                         return -ENOMEM;
1176         }
1177
1178         return q_depth;
1179 }
1180
1181 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1182                                 int qid, int depth)
1183 {
1184         if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1185                 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1186                                                       dev->ctrl.page_size);
1187                 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1188                 nvmeq->sq_cmds_io = dev->cmb + offset;
1189         } else {
1190                 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1191                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1192                 if (!nvmeq->sq_cmds)
1193                         return -ENOMEM;
1194         }
1195
1196         return 0;
1197 }
1198
1199 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1200                                                         int depth, int node)
1201 {
1202         struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL,
1203                                                         node);
1204         if (!nvmeq)
1205                 return NULL;
1206
1207         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1208                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1209         if (!nvmeq->cqes)
1210                 goto free_nvmeq;
1211
1212         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1213                 goto free_cqdma;
1214
1215         nvmeq->q_dmadev = dev->dev;
1216         nvmeq->dev = dev;
1217         spin_lock_init(&nvmeq->q_lock);
1218         nvmeq->cq_head = 0;
1219         nvmeq->cq_phase = 1;
1220         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1221         nvmeq->q_depth = depth;
1222         nvmeq->qid = qid;
1223         nvmeq->cq_vector = -1;
1224         dev->queues[qid] = nvmeq;
1225         dev->queue_count++;
1226
1227         return nvmeq;
1228
1229  free_cqdma:
1230         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1231                                                         nvmeq->cq_dma_addr);
1232  free_nvmeq:
1233         kfree(nvmeq);
1234         return NULL;
1235 }
1236
1237 static int queue_request_irq(struct nvme_queue *nvmeq)
1238 {
1239         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1240         int nr = nvmeq->dev->ctrl.instance;
1241
1242         if (use_threaded_interrupts) {
1243                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1244                                 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1245         } else {
1246                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1247                                 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1248         }
1249 }
1250
1251 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1252 {
1253         struct nvme_dev *dev = nvmeq->dev;
1254
1255         spin_lock_irq(&nvmeq->q_lock);
1256         nvmeq->sq_tail = 0;
1257         nvmeq->cq_head = 0;
1258         nvmeq->cq_phase = 1;
1259         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1260         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1261         nvme_dbbuf_init(dev, nvmeq, qid);
1262         dev->online_queues++;
1263         spin_unlock_irq(&nvmeq->q_lock);
1264 }
1265
1266 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1267 {
1268         struct nvme_dev *dev = nvmeq->dev;
1269         int result;
1270
1271         nvmeq->cq_vector = qid - 1;
1272         result = adapter_alloc_cq(dev, qid, nvmeq);
1273         if (result < 0)
1274                 return result;
1275
1276         result = adapter_alloc_sq(dev, qid, nvmeq);
1277         if (result < 0)
1278                 goto release_cq;
1279
1280         result = queue_request_irq(nvmeq);
1281         if (result < 0)
1282                 goto release_sq;
1283
1284         nvme_init_queue(nvmeq, qid);
1285         return result;
1286
1287  release_sq:
1288         adapter_delete_sq(dev, qid);
1289  release_cq:
1290         adapter_delete_cq(dev, qid);
1291         return result;
1292 }
1293
1294 static const struct blk_mq_ops nvme_mq_admin_ops = {
1295         .queue_rq       = nvme_queue_rq,
1296         .complete       = nvme_pci_complete_rq,
1297         .init_hctx      = nvme_admin_init_hctx,
1298         .exit_hctx      = nvme_admin_exit_hctx,
1299         .init_request   = nvme_init_request,
1300         .timeout        = nvme_timeout,
1301 };
1302
1303 static const struct blk_mq_ops nvme_mq_ops = {
1304         .queue_rq       = nvme_queue_rq,
1305         .complete       = nvme_pci_complete_rq,
1306         .init_hctx      = nvme_init_hctx,
1307         .init_request   = nvme_init_request,
1308         .map_queues     = nvme_pci_map_queues,
1309         .timeout        = nvme_timeout,
1310         .poll           = nvme_poll,
1311 };
1312
1313 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1314 {
1315         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1316                 /*
1317                  * If the controller was reset during removal, it's possible
1318                  * user requests may be waiting on a stopped queue. Start the
1319                  * queue to flush these to completion.
1320                  */
1321                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1322                 blk_cleanup_queue(dev->ctrl.admin_q);
1323                 blk_mq_free_tag_set(&dev->admin_tagset);
1324         }
1325 }
1326
1327 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1328 {
1329         if (!dev->ctrl.admin_q) {
1330                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1331                 dev->admin_tagset.nr_hw_queues = 1;
1332
1333                 /*
1334                  * Subtract one to leave an empty queue entry for 'Full Queue'
1335                  * condition. See NVM-Express 1.2 specification, section 4.1.2.
1336                  */
1337                 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1338                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1339                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1340                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1341                 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1342                 dev->admin_tagset.driver_data = dev;
1343
1344                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1345                         return -ENOMEM;
1346
1347                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1348                 if (IS_ERR(dev->ctrl.admin_q)) {
1349                         blk_mq_free_tag_set(&dev->admin_tagset);
1350                         return -ENOMEM;
1351                 }
1352                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1353                         nvme_dev_remove_admin(dev);
1354                         dev->ctrl.admin_q = NULL;
1355                         return -ENODEV;
1356                 }
1357         } else
1358                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1359
1360         return 0;
1361 }
1362
1363 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1364 {
1365         return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1366 }
1367
1368 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1369 {
1370         struct pci_dev *pdev = to_pci_dev(dev->dev);
1371
1372         if (size <= dev->bar_mapped_size)
1373                 return 0;
1374         if (size > pci_resource_len(pdev, 0))
1375                 return -ENOMEM;
1376         if (dev->bar)
1377                 iounmap(dev->bar);
1378         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1379         if (!dev->bar) {
1380                 dev->bar_mapped_size = 0;
1381                 return -ENOMEM;
1382         }
1383         dev->bar_mapped_size = size;
1384         dev->dbs = dev->bar + NVME_REG_DBS;
1385
1386         return 0;
1387 }
1388
1389 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1390 {
1391         int result;
1392         u32 aqa;
1393         u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1394         struct nvme_queue *nvmeq;
1395
1396         result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1397         if (result < 0)
1398                 return result;
1399
1400         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1401                                                 NVME_CAP_NSSRC(cap) : 0;
1402
1403         if (dev->subsystem &&
1404             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1405                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1406
1407         result = nvme_disable_ctrl(&dev->ctrl, cap);
1408         if (result < 0)
1409                 return result;
1410
1411         nvmeq = dev->queues[0];
1412         if (!nvmeq) {
1413                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH,
1414                                         dev_to_node(dev->dev));
1415                 if (!nvmeq)
1416                         return -ENOMEM;
1417         }
1418
1419         aqa = nvmeq->q_depth - 1;
1420         aqa |= aqa << 16;
1421
1422         writel(aqa, dev->bar + NVME_REG_AQA);
1423         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1424         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1425
1426         result = nvme_enable_ctrl(&dev->ctrl, cap);
1427         if (result)
1428                 return result;
1429
1430         nvmeq->cq_vector = 0;
1431         result = queue_request_irq(nvmeq);
1432         if (result) {
1433                 nvmeq->cq_vector = -1;
1434                 return result;
1435         }
1436
1437         return result;
1438 }
1439
1440 static int nvme_create_io_queues(struct nvme_dev *dev)
1441 {
1442         unsigned i, max;
1443         int ret = 0;
1444
1445         for (i = dev->queue_count; i <= dev->max_qid; i++) {
1446                 /* vector == qid - 1, match nvme_create_queue */
1447                 if (!nvme_alloc_queue(dev, i, dev->q_depth,
1448                      pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) {
1449                         ret = -ENOMEM;
1450                         break;
1451                 }
1452         }
1453
1454         max = min(dev->max_qid, dev->queue_count - 1);
1455         for (i = dev->online_queues; i <= max; i++) {
1456                 ret = nvme_create_queue(dev->queues[i], i);
1457                 if (ret)
1458                         break;
1459         }
1460
1461         /*
1462          * Ignore failing Create SQ/CQ commands, we can continue with less
1463          * than the desired aount of queues, and even a controller without
1464          * I/O queues an still be used to issue admin commands.  This might
1465          * be useful to upgrade a buggy firmware for example.
1466          */
1467         return ret >= 0 ? 0 : ret;
1468 }
1469
1470 static ssize_t nvme_cmb_show(struct device *dev,
1471                              struct device_attribute *attr,
1472                              char *buf)
1473 {
1474         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1475
1476         return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz  : x%08x\n",
1477                        ndev->cmbloc, ndev->cmbsz);
1478 }
1479 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1480
1481 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1482 {
1483         u64 szu, size, offset;
1484         resource_size_t bar_size;
1485         struct pci_dev *pdev = to_pci_dev(dev->dev);
1486         void __iomem *cmb;
1487         dma_addr_t dma_addr;
1488
1489         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1490         if (!(NVME_CMB_SZ(dev->cmbsz)))
1491                 return NULL;
1492         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1493
1494         if (!use_cmb_sqes)
1495                 return NULL;
1496
1497         szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1498         size = szu * NVME_CMB_SZ(dev->cmbsz);
1499         offset = szu * NVME_CMB_OFST(dev->cmbloc);
1500         bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc));
1501
1502         if (offset > bar_size)
1503                 return NULL;
1504
1505         /*
1506          * Controllers may support a CMB size larger than their BAR,
1507          * for example, due to being behind a bridge. Reduce the CMB to
1508          * the reported size of the BAR
1509          */
1510         if (size > bar_size - offset)
1511                 size = bar_size - offset;
1512
1513         dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset;
1514         cmb = ioremap_wc(dma_addr, size);
1515         if (!cmb)
1516                 return NULL;
1517
1518         dev->cmb_dma_addr = dma_addr;
1519         dev->cmb_size = size;
1520         return cmb;
1521 }
1522
1523 static inline void nvme_release_cmb(struct nvme_dev *dev)
1524 {
1525         if (dev->cmb) {
1526                 iounmap(dev->cmb);
1527                 dev->cmb = NULL;
1528                 if (dev->cmbsz) {
1529                         sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1530                                                      &dev_attr_cmb.attr, NULL);
1531                         dev->cmbsz = 0;
1532                 }
1533         }
1534 }
1535
1536 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1537 {
1538         size_t len = dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs);
1539         struct nvme_command c;
1540         u64 dma_addr;
1541         int ret;
1542
1543         dma_addr = dma_map_single(dev->dev, dev->host_mem_descs, len,
1544                         DMA_TO_DEVICE);
1545         if (dma_mapping_error(dev->dev, dma_addr))
1546                 return -ENOMEM;
1547
1548         memset(&c, 0, sizeof(c));
1549         c.features.opcode       = nvme_admin_set_features;
1550         c.features.fid          = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1551         c.features.dword11      = cpu_to_le32(bits);
1552         c.features.dword12      = cpu_to_le32(dev->host_mem_size >>
1553                                               ilog2(dev->ctrl.page_size));
1554         c.features.dword13      = cpu_to_le32(lower_32_bits(dma_addr));
1555         c.features.dword14      = cpu_to_le32(upper_32_bits(dma_addr));
1556         c.features.dword15      = cpu_to_le32(dev->nr_host_mem_descs);
1557
1558         ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1559         if (ret) {
1560                 dev_warn(dev->ctrl.device,
1561                          "failed to set host mem (err %d, flags %#x).\n",
1562                          ret, bits);
1563         }
1564         dma_unmap_single(dev->dev, dma_addr, len, DMA_TO_DEVICE);
1565         return ret;
1566 }
1567
1568 static void nvme_free_host_mem(struct nvme_dev *dev)
1569 {
1570         int i;
1571
1572         for (i = 0; i < dev->nr_host_mem_descs; i++) {
1573                 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1574                 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1575
1576                 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1577                                 le64_to_cpu(desc->addr));
1578         }
1579
1580         kfree(dev->host_mem_desc_bufs);
1581         dev->host_mem_desc_bufs = NULL;
1582         kfree(dev->host_mem_descs);
1583         dev->host_mem_descs = NULL;
1584 }
1585
1586 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1587 {
1588         struct nvme_host_mem_buf_desc *descs;
1589         u32 chunk_size, max_entries, i = 0;
1590         void **bufs;
1591         u64 size, tmp;
1592
1593         /* start big and work our way down */
1594         chunk_size = min(preferred, (u64)PAGE_SIZE << MAX_ORDER);
1595 retry:
1596         tmp = (preferred + chunk_size - 1);
1597         do_div(tmp, chunk_size);
1598         max_entries = tmp;
1599         descs = kcalloc(max_entries, sizeof(*descs), GFP_KERNEL);
1600         if (!descs)
1601                 goto out;
1602
1603         bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1604         if (!bufs)
1605                 goto out_free_descs;
1606
1607         for (size = 0; size < preferred; size += chunk_size) {
1608                 u32 len = min_t(u64, chunk_size, preferred - size);
1609                 dma_addr_t dma_addr;
1610
1611                 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1612                                 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1613                 if (!bufs[i])
1614                         break;
1615
1616                 descs[i].addr = cpu_to_le64(dma_addr);
1617                 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1618                 i++;
1619         }
1620
1621         if (!size || (min && size < min)) {
1622                 dev_warn(dev->ctrl.device,
1623                         "failed to allocate host memory buffer.\n");
1624                 goto out_free_bufs;
1625         }
1626
1627         dev_info(dev->ctrl.device,
1628                 "allocated %lld MiB host memory buffer.\n",
1629                 size >> ilog2(SZ_1M));
1630         dev->nr_host_mem_descs = i;
1631         dev->host_mem_size = size;
1632         dev->host_mem_descs = descs;
1633         dev->host_mem_desc_bufs = bufs;
1634         return 0;
1635
1636 out_free_bufs:
1637         while (--i >= 0) {
1638                 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1639
1640                 dma_free_coherent(dev->dev, size, bufs[i],
1641                                 le64_to_cpu(descs[i].addr));
1642         }
1643
1644         kfree(bufs);
1645 out_free_descs:
1646         kfree(descs);
1647 out:
1648         /* try a smaller chunk size if we failed early */
1649         if (chunk_size >= PAGE_SIZE * 2 && (i == 0 || size < min)) {
1650                 chunk_size /= 2;
1651                 goto retry;
1652         }
1653         dev->host_mem_descs = NULL;
1654         return -ENOMEM;
1655 }
1656
1657 static void nvme_setup_host_mem(struct nvme_dev *dev)
1658 {
1659         u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1660         u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1661         u64 min = (u64)dev->ctrl.hmmin * 4096;
1662         u32 enable_bits = NVME_HOST_MEM_ENABLE;
1663
1664         preferred = min(preferred, max);
1665         if (min > max) {
1666                 dev_warn(dev->ctrl.device,
1667                         "min host memory (%lld MiB) above limit (%d MiB).\n",
1668                         min >> ilog2(SZ_1M), max_host_mem_size_mb);
1669                 nvme_free_host_mem(dev);
1670                 return;
1671         }
1672
1673         /*
1674          * If we already have a buffer allocated check if we can reuse it.
1675          */
1676         if (dev->host_mem_descs) {
1677                 if (dev->host_mem_size >= min)
1678                         enable_bits |= NVME_HOST_MEM_RETURN;
1679                 else
1680                         nvme_free_host_mem(dev);
1681         }
1682
1683         if (!dev->host_mem_descs) {
1684                 if (nvme_alloc_host_mem(dev, min, preferred))
1685                         return;
1686         }
1687
1688         if (nvme_set_host_mem(dev, enable_bits))
1689                 nvme_free_host_mem(dev);
1690 }
1691
1692 static int nvme_setup_io_queues(struct nvme_dev *dev)
1693 {
1694         struct nvme_queue *adminq = dev->queues[0];
1695         struct pci_dev *pdev = to_pci_dev(dev->dev);
1696         int result, nr_io_queues;
1697         unsigned long size;
1698
1699         nr_io_queues = num_online_cpus();
1700         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1701         if (result < 0)
1702                 return result;
1703
1704         if (nr_io_queues == 0)
1705                 return 0;
1706
1707         if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1708                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1709                                 sizeof(struct nvme_command));
1710                 if (result > 0)
1711                         dev->q_depth = result;
1712                 else
1713                         nvme_release_cmb(dev);
1714         }
1715
1716         do {
1717                 size = db_bar_size(dev, nr_io_queues);
1718                 result = nvme_remap_bar(dev, size);
1719                 if (!result)
1720                         break;
1721                 if (!--nr_io_queues)
1722                         return -ENOMEM;
1723         } while (1);
1724         adminq->q_db = dev->dbs;
1725
1726         /* Deregister the admin queue's interrupt */
1727         pci_free_irq(pdev, 0, adminq);
1728
1729         /*
1730          * If we enable msix early due to not intx, disable it again before
1731          * setting up the full range we need.
1732          */
1733         pci_free_irq_vectors(pdev);
1734         nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues,
1735                         PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY);
1736         if (nr_io_queues <= 0)
1737                 return -EIO;
1738         dev->max_qid = nr_io_queues;
1739
1740         /*
1741          * Should investigate if there's a performance win from allocating
1742          * more queues than interrupt vectors; it might allow the submission
1743          * path to scale better, even if the receive path is limited by the
1744          * number of interrupts.
1745          */
1746
1747         result = queue_request_irq(adminq);
1748         if (result) {
1749                 adminq->cq_vector = -1;
1750                 return result;
1751         }
1752         return nvme_create_io_queues(dev);
1753 }
1754
1755 static void nvme_del_queue_end(struct request *req, blk_status_t error)
1756 {
1757         struct nvme_queue *nvmeq = req->end_io_data;
1758
1759         blk_mq_free_request(req);
1760         complete(&nvmeq->dev->ioq_wait);
1761 }
1762
1763 static void nvme_del_cq_end(struct request *req, blk_status_t error)
1764 {
1765         struct nvme_queue *nvmeq = req->end_io_data;
1766
1767         if (!error) {
1768                 unsigned long flags;
1769
1770                 /*
1771                  * We might be called with the AQ q_lock held
1772                  * and the I/O queue q_lock should always
1773                  * nest inside the AQ one.
1774                  */
1775                 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1776                                         SINGLE_DEPTH_NESTING);
1777                 nvme_process_cq(nvmeq);
1778                 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1779         }
1780
1781         nvme_del_queue_end(req, error);
1782 }
1783
1784 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1785 {
1786         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1787         struct request *req;
1788         struct nvme_command cmd;
1789
1790         memset(&cmd, 0, sizeof(cmd));
1791         cmd.delete_queue.opcode = opcode;
1792         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1793
1794         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1795         if (IS_ERR(req))
1796                 return PTR_ERR(req);
1797
1798         req->timeout = ADMIN_TIMEOUT;
1799         req->end_io_data = nvmeq;
1800
1801         blk_execute_rq_nowait(q, NULL, req, false,
1802                         opcode == nvme_admin_delete_cq ?
1803                                 nvme_del_cq_end : nvme_del_queue_end);
1804         return 0;
1805 }
1806
1807 static void nvme_disable_io_queues(struct nvme_dev *dev, int queues)
1808 {
1809         int pass;
1810         unsigned long timeout;
1811         u8 opcode = nvme_admin_delete_sq;
1812
1813         for (pass = 0; pass < 2; pass++) {
1814                 int sent = 0, i = queues;
1815
1816                 reinit_completion(&dev->ioq_wait);
1817  retry:
1818                 timeout = ADMIN_TIMEOUT;
1819                 for (; i > 0; i--, sent++)
1820                         if (nvme_delete_queue(dev->queues[i], opcode))
1821                                 break;
1822
1823                 while (sent--) {
1824                         timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1825                         if (timeout == 0)
1826                                 return;
1827                         if (i)
1828                                 goto retry;
1829                 }
1830                 opcode = nvme_admin_delete_cq;
1831         }
1832 }
1833
1834 /*
1835  * Return: error value if an error occurred setting up the queues or calling
1836  * Identify Device.  0 if these succeeded, even if adding some of the
1837  * namespaces failed.  At the moment, these failures are silent.  TBD which
1838  * failures should be reported.
1839  */
1840 static int nvme_dev_add(struct nvme_dev *dev)
1841 {
1842         if (!dev->ctrl.tagset) {
1843                 dev->tagset.ops = &nvme_mq_ops;
1844                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1845                 dev->tagset.timeout = NVME_IO_TIMEOUT;
1846                 dev->tagset.numa_node = dev_to_node(dev->dev);
1847                 dev->tagset.queue_depth =
1848                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1849                 dev->tagset.cmd_size = nvme_cmd_size(dev);
1850                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1851                 dev->tagset.driver_data = dev;
1852
1853                 if (blk_mq_alloc_tag_set(&dev->tagset))
1854                         return 0;
1855                 dev->ctrl.tagset = &dev->tagset;
1856
1857                 nvme_dbbuf_set(dev);
1858         } else {
1859                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1860
1861                 /* Free previously allocated queues that are no longer usable */
1862                 nvme_free_queues(dev, dev->online_queues);
1863         }
1864
1865         return 0;
1866 }
1867
1868 static int nvme_pci_enable(struct nvme_dev *dev)
1869 {
1870         u64 cap;
1871         int result = -ENOMEM;
1872         struct pci_dev *pdev = to_pci_dev(dev->dev);
1873
1874         if (pci_enable_device_mem(pdev))
1875                 return result;
1876
1877         pci_set_master(pdev);
1878
1879         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1880             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1881                 goto disable;
1882
1883         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1884                 result = -ENODEV;
1885                 goto disable;
1886         }
1887
1888         /*
1889          * Some devices and/or platforms don't advertise or work with INTx
1890          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1891          * adjust this later.
1892          */
1893         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1894         if (result < 0)
1895                 return result;
1896
1897         cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1898
1899         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1900         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1901         dev->dbs = dev->bar + 4096;
1902
1903         /*
1904          * Temporary fix for the Apple controller found in the MacBook8,1 and
1905          * some MacBook7,1 to avoid controller resets and data loss.
1906          */
1907         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1908                 dev->q_depth = 2;
1909                 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
1910                         "set queue depth=%u to work around controller resets\n",
1911                         dev->q_depth);
1912         }
1913
1914         /*
1915          * CMBs can currently only exist on >=1.2 PCIe devices. We only
1916          * populate sysfs if a CMB is implemented. Note that we add the
1917          * CMB attribute to the nvme_ctrl kobj which removes the need to remove
1918          * it on exit. Since nvme_dev_attrs_group has no name we can pass
1919          * NULL as final argument to sysfs_add_file_to_group.
1920          */
1921
1922         if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) {
1923                 dev->cmb = nvme_map_cmb(dev);
1924
1925                 if (dev->cmbsz) {
1926                         if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1927                                                     &dev_attr_cmb.attr, NULL))
1928                                 dev_warn(dev->ctrl.device,
1929                                          "failed to add sysfs attribute for CMB\n");
1930                 }
1931         }
1932
1933         pci_enable_pcie_error_reporting(pdev);
1934         pci_save_state(pdev);
1935         return 0;
1936
1937  disable:
1938         pci_disable_device(pdev);
1939         return result;
1940 }
1941
1942 static void nvme_dev_unmap(struct nvme_dev *dev)
1943 {
1944         if (dev->bar)
1945                 iounmap(dev->bar);
1946         pci_release_mem_regions(to_pci_dev(dev->dev));
1947 }
1948
1949 static void nvme_pci_disable(struct nvme_dev *dev)
1950 {
1951         struct pci_dev *pdev = to_pci_dev(dev->dev);
1952
1953         nvme_release_cmb(dev);
1954         pci_free_irq_vectors(pdev);
1955
1956         if (pci_is_enabled(pdev)) {
1957                 pci_disable_pcie_error_reporting(pdev);
1958                 pci_disable_device(pdev);
1959         }
1960 }
1961
1962 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1963 {
1964         int i, queues;
1965         bool dead = true;
1966         struct pci_dev *pdev = to_pci_dev(dev->dev);
1967
1968         mutex_lock(&dev->shutdown_lock);
1969         if (pci_is_enabled(pdev)) {
1970                 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1971
1972                 if (dev->ctrl.state == NVME_CTRL_LIVE)
1973                         nvme_start_freeze(&dev->ctrl);
1974                 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
1975                         pdev->error_state  != pci_channel_io_normal);
1976         }
1977
1978         /*
1979          * Give the controller a chance to complete all entered requests if
1980          * doing a safe shutdown.
1981          */
1982         if (!dead) {
1983                 if (shutdown)
1984                         nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
1985
1986                 /*
1987                  * If the controller is still alive tell it to stop using the
1988                  * host memory buffer.  In theory the shutdown / reset should
1989                  * make sure that it doesn't access the host memoery anymore,
1990                  * but I'd rather be safe than sorry..
1991                  */
1992                 if (dev->host_mem_descs)
1993                         nvme_set_host_mem(dev, 0);
1994
1995         }
1996         nvme_stop_queues(&dev->ctrl);
1997
1998         queues = dev->online_queues - 1;
1999         for (i = dev->queue_count - 1; i > 0; i--)
2000                 nvme_suspend_queue(dev->queues[i]);
2001
2002         if (dead) {
2003                 /* A device might become IO incapable very soon during
2004                  * probe, before the admin queue is configured. Thus,
2005                  * queue_count can be 0 here.
2006                  */
2007                 if (dev->queue_count)
2008                         nvme_suspend_queue(dev->queues[0]);
2009         } else {
2010                 nvme_disable_io_queues(dev, queues);
2011                 nvme_disable_admin_queue(dev, shutdown);
2012         }
2013         nvme_pci_disable(dev);
2014
2015         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2016         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2017
2018         /*
2019          * The driver will not be starting up queues again if shutting down so
2020          * must flush all entered requests to their failed completion to avoid
2021          * deadlocking blk-mq hot-cpu notifier.
2022          */
2023         if (shutdown)
2024                 nvme_start_queues(&dev->ctrl);
2025         mutex_unlock(&dev->shutdown_lock);
2026 }
2027
2028 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2029 {
2030         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2031                                                 PAGE_SIZE, PAGE_SIZE, 0);
2032         if (!dev->prp_page_pool)
2033                 return -ENOMEM;
2034
2035         /* Optimisation for I/Os between 4k and 128k */
2036         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2037                                                 256, 256, 0);
2038         if (!dev->prp_small_pool) {
2039                 dma_pool_destroy(dev->prp_page_pool);
2040                 return -ENOMEM;
2041         }
2042         return 0;
2043 }
2044
2045 static void nvme_release_prp_pools(struct nvme_dev *dev)
2046 {
2047         dma_pool_destroy(dev->prp_page_pool);
2048         dma_pool_destroy(dev->prp_small_pool);
2049 }
2050
2051 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2052 {
2053         struct nvme_dev *dev = to_nvme_dev(ctrl);
2054
2055         nvme_dbbuf_dma_free(dev);
2056         put_device(dev->dev);
2057         if (dev->tagset.tags)
2058                 blk_mq_free_tag_set(&dev->tagset);
2059         if (dev->ctrl.admin_q)
2060                 blk_put_queue(dev->ctrl.admin_q);
2061         kfree(dev->queues);
2062         free_opal_dev(dev->ctrl.opal_dev);
2063         kfree(dev);
2064 }
2065
2066 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2067 {
2068         dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
2069
2070         kref_get(&dev->ctrl.kref);
2071         nvme_dev_disable(dev, false);
2072         if (!schedule_work(&dev->remove_work))
2073                 nvme_put_ctrl(&dev->ctrl);
2074 }
2075
2076 static void nvme_reset_work(struct work_struct *work)
2077 {
2078         struct nvme_dev *dev =
2079                 container_of(work, struct nvme_dev, ctrl.reset_work);
2080         bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2081         int result = -ENODEV;
2082
2083         if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
2084                 goto out;
2085
2086         /*
2087          * If we're called to reset a live controller first shut it down before
2088          * moving on.
2089          */
2090         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2091                 nvme_dev_disable(dev, false);
2092
2093         result = nvme_pci_enable(dev);
2094         if (result)
2095                 goto out;
2096
2097         result = nvme_configure_admin_queue(dev);
2098         if (result)
2099                 goto out;
2100
2101         nvme_init_queue(dev->queues[0], 0);
2102         result = nvme_alloc_admin_tags(dev);
2103         if (result)
2104                 goto out;
2105
2106         result = nvme_init_identify(&dev->ctrl);
2107         if (result)
2108                 goto out;
2109
2110         if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2111                 if (!dev->ctrl.opal_dev)
2112                         dev->ctrl.opal_dev =
2113                                 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2114                 else if (was_suspend)
2115                         opal_unlock_from_suspend(dev->ctrl.opal_dev);
2116         } else {
2117                 free_opal_dev(dev->ctrl.opal_dev);
2118                 dev->ctrl.opal_dev = NULL;
2119         }
2120
2121         if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2122                 result = nvme_dbbuf_dma_alloc(dev);
2123                 if (result)
2124                         dev_warn(dev->dev,
2125                                  "unable to allocate dma for dbbuf\n");
2126         }
2127
2128         if (dev->ctrl.hmpre)
2129                 nvme_setup_host_mem(dev);
2130
2131         result = nvme_setup_io_queues(dev);
2132         if (result)
2133                 goto out;
2134
2135         /*
2136          * A controller that can not execute IO typically requires user
2137          * intervention to correct. For such degraded controllers, the driver
2138          * should not submit commands the user did not request, so skip
2139          * registering for asynchronous event notification on this condition.
2140          */
2141         if (dev->online_queues > 1)
2142                 nvme_queue_async_events(&dev->ctrl);
2143
2144         /*
2145          * Keep the controller around but remove all namespaces if we don't have
2146          * any working I/O queue.
2147          */
2148         if (dev->online_queues < 2) {
2149                 dev_warn(dev->ctrl.device, "IO queues not created\n");
2150                 nvme_kill_queues(&dev->ctrl);
2151                 nvme_remove_namespaces(&dev->ctrl);
2152         } else {
2153                 nvme_start_queues(&dev->ctrl);
2154                 nvme_wait_freeze(&dev->ctrl);
2155                 nvme_dev_add(dev);
2156                 nvme_unfreeze(&dev->ctrl);
2157         }
2158
2159         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2160                 dev_warn(dev->ctrl.device, "failed to mark controller live\n");
2161                 goto out;
2162         }
2163
2164         if (dev->online_queues > 1)
2165                 nvme_queue_scan(&dev->ctrl);
2166         return;
2167
2168  out:
2169         nvme_remove_dead_ctrl(dev, result);
2170 }
2171
2172 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2173 {
2174         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2175         struct pci_dev *pdev = to_pci_dev(dev->dev);
2176
2177         nvme_kill_queues(&dev->ctrl);
2178         if (pci_get_drvdata(pdev))
2179                 device_release_driver(&pdev->dev);
2180         nvme_put_ctrl(&dev->ctrl);
2181 }
2182
2183 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2184 {
2185         *val = readl(to_nvme_dev(ctrl)->bar + off);
2186         return 0;
2187 }
2188
2189 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2190 {
2191         writel(val, to_nvme_dev(ctrl)->bar + off);
2192         return 0;
2193 }
2194
2195 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2196 {
2197         *val = readq(to_nvme_dev(ctrl)->bar + off);
2198         return 0;
2199 }
2200
2201 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2202         .name                   = "pcie",
2203         .module                 = THIS_MODULE,
2204         .flags                  = NVME_F_METADATA_SUPPORTED,
2205         .reg_read32             = nvme_pci_reg_read32,
2206         .reg_write32            = nvme_pci_reg_write32,
2207         .reg_read64             = nvme_pci_reg_read64,
2208         .free_ctrl              = nvme_pci_free_ctrl,
2209         .submit_async_event     = nvme_pci_submit_async_event,
2210 };
2211
2212 static int nvme_dev_map(struct nvme_dev *dev)
2213 {
2214         struct pci_dev *pdev = to_pci_dev(dev->dev);
2215
2216         if (pci_request_mem_regions(pdev, "nvme"))
2217                 return -ENODEV;
2218
2219         if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2220                 goto release;
2221
2222         return 0;
2223   release:
2224         pci_release_mem_regions(pdev);
2225         return -ENODEV;
2226 }
2227
2228 static unsigned long check_dell_samsung_bug(struct pci_dev *pdev)
2229 {
2230         if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2231                 /*
2232                  * Several Samsung devices seem to drop off the PCIe bus
2233                  * randomly when APST is on and uses the deepest sleep state.
2234                  * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2235                  * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2236                  * 950 PRO 256GB", but it seems to be restricted to two Dell
2237                  * laptops.
2238                  */
2239                 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2240                     (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2241                      dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2242                         return NVME_QUIRK_NO_DEEPEST_PS;
2243         }
2244
2245         return 0;
2246 }
2247
2248 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2249 {
2250         int node, result = -ENOMEM;
2251         struct nvme_dev *dev;
2252         unsigned long quirks = id->driver_data;
2253
2254         node = dev_to_node(&pdev->dev);
2255         if (node == NUMA_NO_NODE)
2256                 set_dev_node(&pdev->dev, first_memory_node);
2257
2258         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2259         if (!dev)
2260                 return -ENOMEM;
2261         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2262                                                         GFP_KERNEL, node);
2263         if (!dev->queues)
2264                 goto free;
2265
2266         dev->dev = get_device(&pdev->dev);
2267         pci_set_drvdata(pdev, dev);
2268
2269         result = nvme_dev_map(dev);
2270         if (result)
2271                 goto free;
2272
2273         INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2274         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2275         mutex_init(&dev->shutdown_lock);
2276         init_completion(&dev->ioq_wait);
2277
2278         result = nvme_setup_prp_pools(dev);
2279         if (result)
2280                 goto put_pci;
2281
2282         quirks |= check_dell_samsung_bug(pdev);
2283
2284         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2285                         quirks);
2286         if (result)
2287                 goto release_pools;
2288
2289         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING);
2290         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2291
2292         queue_work(nvme_wq, &dev->ctrl.reset_work);
2293         return 0;
2294
2295  release_pools:
2296         nvme_release_prp_pools(dev);
2297  put_pci:
2298         put_device(dev->dev);
2299         nvme_dev_unmap(dev);
2300  free:
2301         kfree(dev->queues);
2302         kfree(dev);
2303         return result;
2304 }
2305
2306 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2307 {
2308         struct nvme_dev *dev = pci_get_drvdata(pdev);
2309
2310         if (prepare)
2311                 nvme_dev_disable(dev, false);
2312         else
2313                 nvme_reset_ctrl(&dev->ctrl);
2314 }
2315
2316 static void nvme_shutdown(struct pci_dev *pdev)
2317 {
2318         struct nvme_dev *dev = pci_get_drvdata(pdev);
2319         nvme_dev_disable(dev, true);
2320 }
2321
2322 /*
2323  * The driver's remove may be called on a device in a partially initialized
2324  * state. This function must not have any dependencies on the device state in
2325  * order to proceed.
2326  */
2327 static void nvme_remove(struct pci_dev *pdev)
2328 {
2329         struct nvme_dev *dev = pci_get_drvdata(pdev);
2330
2331         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2332
2333         cancel_work_sync(&dev->ctrl.reset_work);
2334         pci_set_drvdata(pdev, NULL);
2335
2336         if (!pci_device_is_present(pdev)) {
2337                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2338                 nvme_dev_disable(dev, false);
2339         }
2340
2341         flush_work(&dev->ctrl.reset_work);
2342         nvme_uninit_ctrl(&dev->ctrl);
2343         nvme_dev_disable(dev, true);
2344         nvme_free_host_mem(dev);
2345         nvme_dev_remove_admin(dev);
2346         nvme_free_queues(dev, 0);
2347         nvme_release_prp_pools(dev);
2348         nvme_dev_unmap(dev);
2349         nvme_put_ctrl(&dev->ctrl);
2350 }
2351
2352 static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2353 {
2354         int ret = 0;
2355
2356         if (numvfs == 0) {
2357                 if (pci_vfs_assigned(pdev)) {
2358                         dev_warn(&pdev->dev,
2359                                 "Cannot disable SR-IOV VFs while assigned\n");
2360                         return -EPERM;
2361                 }
2362                 pci_disable_sriov(pdev);
2363                 return 0;
2364         }
2365
2366         ret = pci_enable_sriov(pdev, numvfs);
2367         return ret ? ret : numvfs;
2368 }
2369
2370 #ifdef CONFIG_PM_SLEEP
2371 static int nvme_suspend(struct device *dev)
2372 {
2373         struct pci_dev *pdev = to_pci_dev(dev);
2374         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2375
2376         nvme_dev_disable(ndev, true);
2377         return 0;
2378 }
2379
2380 static int nvme_resume(struct device *dev)
2381 {
2382         struct pci_dev *pdev = to_pci_dev(dev);
2383         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2384
2385         nvme_reset_ctrl(&ndev->ctrl);
2386         return 0;
2387 }
2388 #endif
2389
2390 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2391
2392 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2393                                                 pci_channel_state_t state)
2394 {
2395         struct nvme_dev *dev = pci_get_drvdata(pdev);
2396
2397         /*
2398          * A frozen channel requires a reset. When detected, this method will
2399          * shutdown the controller to quiesce. The controller will be restarted
2400          * after the slot reset through driver's slot_reset callback.
2401          */
2402         switch (state) {
2403         case pci_channel_io_normal:
2404                 return PCI_ERS_RESULT_CAN_RECOVER;
2405         case pci_channel_io_frozen:
2406                 dev_warn(dev->ctrl.device,
2407                         "frozen state error detected, reset controller\n");
2408                 nvme_dev_disable(dev, false);
2409                 return PCI_ERS_RESULT_NEED_RESET;
2410         case pci_channel_io_perm_failure:
2411                 dev_warn(dev->ctrl.device,
2412                         "failure state error detected, request disconnect\n");
2413                 return PCI_ERS_RESULT_DISCONNECT;
2414         }
2415         return PCI_ERS_RESULT_NEED_RESET;
2416 }
2417
2418 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2419 {
2420         struct nvme_dev *dev = pci_get_drvdata(pdev);
2421
2422         dev_info(dev->ctrl.device, "restart after slot reset\n");
2423         pci_restore_state(pdev);
2424         nvme_reset_ctrl(&dev->ctrl);
2425         return PCI_ERS_RESULT_RECOVERED;
2426 }
2427
2428 static void nvme_error_resume(struct pci_dev *pdev)
2429 {
2430         pci_cleanup_aer_uncorrect_error_status(pdev);
2431 }
2432
2433 static const struct pci_error_handlers nvme_err_handler = {
2434         .error_detected = nvme_error_detected,
2435         .slot_reset     = nvme_slot_reset,
2436         .resume         = nvme_error_resume,
2437         .reset_notify   = nvme_reset_notify,
2438 };
2439
2440 static const struct pci_device_id nvme_id_table[] = {
2441         { PCI_VDEVICE(INTEL, 0x0953),
2442                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2443                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2444         { PCI_VDEVICE(INTEL, 0x0a53),
2445                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2446                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2447         { PCI_VDEVICE(INTEL, 0x0a54),
2448                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2449                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2450         { PCI_VDEVICE(INTEL, 0xf1a5),   /* Intel 600P/P3100 */
2451                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS },
2452         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2453                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2454         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
2455                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2456         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
2457                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2458         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2459         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2460         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
2461         { 0, }
2462 };
2463 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2464
2465 static struct pci_driver nvme_driver = {
2466         .name           = "nvme",
2467         .id_table       = nvme_id_table,
2468         .probe          = nvme_probe,
2469         .remove         = nvme_remove,
2470         .shutdown       = nvme_shutdown,
2471         .driver         = {
2472                 .pm     = &nvme_dev_pm_ops,
2473         },
2474         .sriov_configure = nvme_pci_sriov_configure,
2475         .err_handler    = &nvme_err_handler,
2476 };
2477
2478 static int __init nvme_init(void)
2479 {
2480         return pci_register_driver(&nvme_driver);
2481 }
2482
2483 static void __exit nvme_exit(void)
2484 {
2485         pci_unregister_driver(&nvme_driver);
2486         _nvme_check_size();
2487 }
2488
2489 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2490 MODULE_LICENSE("GPL");
2491 MODULE_VERSION("1.0");
2492 module_init(nvme_init);
2493 module_exit(nvme_exit);